12sim_insts 1538759602 # Number of instructions simulated 13sim_ops 1658228915 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.inst_hits 0 # ITB inst hits 136system.cpu.itb.inst_misses 0 # ITB inst misses 137system.cpu.itb.read_hits 0 # DTB read hits 138system.cpu.itb.read_misses 0 # DTB read misses 139system.cpu.itb.write_hits 0 # DTB write hits 140system.cpu.itb.write_misses 0 # DTB write misses 141system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 142system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 143system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 144system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 146system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 147system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 148system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 46 # Number of system calls 157system.cpu.numCycles 4754059341 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 1538759602 # Number of instructions committed 161system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 164system.cpu.num_func_calls 27330256 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls 166system.cpu.num_int_insts 1477900422 # number of integer instructions 167system.cpu.num_fp_insts 36 # number of float instructions
| 12sim_insts 1538759602 # Number of instructions simulated 13sim_ops 1658228915 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 124870272 # Number of bytes read from this memory 18system.physmem.bytes_read::total 124909696 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65352128 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65352128 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1951098 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1951714 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1021127 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1021127 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 16585 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 52532063 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 52548648 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 16585 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 16585 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 27493190 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 27493190 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 27493190 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 16585 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 52532063 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 80041838 # Total bandwidth to/from this memory (bytes/s) 39system.cpu_clk_domain.clock 500 # Clock period in ticks 40system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 49system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 50system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 51system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 52system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 53system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 55system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 58system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 59system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 60system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 61system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 62system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 63system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 64system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 65system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 66system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 67system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 68system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 69system.cpu.dtb.walker.walks 0 # Table walker walks requested 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu.itb.walker.walks 0 # Table walker walks requested 128system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.inst_hits 0 # ITB inst hits 136system.cpu.itb.inst_misses 0 # ITB inst misses 137system.cpu.itb.read_hits 0 # DTB read hits 138system.cpu.itb.read_misses 0 # DTB read misses 139system.cpu.itb.write_hits 0 # DTB write hits 140system.cpu.itb.write_misses 0 # DTB write misses 141system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 142system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 143system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 144system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 145system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 146system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 147system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 148system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 149system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 150system.cpu.itb.read_accesses 0 # DTB read accesses 151system.cpu.itb.write_accesses 0 # DTB write accesses 152system.cpu.itb.inst_accesses 0 # ITB inst accesses 153system.cpu.itb.hits 0 # DTB hits 154system.cpu.itb.misses 0 # DTB misses 155system.cpu.itb.accesses 0 # DTB accesses 156system.cpu.workload.num_syscalls 46 # Number of system calls 157system.cpu.numCycles 4754059341 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 1538759602 # Number of instructions committed 161system.cpu.committedOps 1658228915 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 164system.cpu.num_func_calls 27330256 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls 166system.cpu.num_int_insts 1477900422 # number of integer instructions 167system.cpu.num_fp_insts 36 # number of float instructions
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