Cross Reference: /gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt

stats.txt (10352:5f1f92bf76ee)	stats.txt (10409:8c80b91944c5)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.363671 # Number of seconds simulated 4sim_ticks 2363670998000 # Number of ticks simulated 5final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.363671 # Number of seconds simulated 4sim_ticks 2363670998000 # Number of ticks simulated 5final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1066052 # Simulator instruction rate (inst/s) 8host_op_rate 1148821 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1637550718 # Simulator tick rate (ticks/s) 10host_mem_usage 316024 # Number of bytes of host memory used 11host_seconds 1443.42 # Real time elapsed on the host	7host_inst_rate 1205605 # Simulator instruction rate (inst/s) 8host_op_rate 1299208 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1851916301 # Simulator tick rate (ticks/s) 10host_mem_usage 306192 # Number of bytes of host memory used 11host_seconds 1276.34 # Real time elapsed on the host
12sim_insts 1538759601 # Number of instructions simulated 13sim_ops 1658228914 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory 18system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)	12sim_insts 1538759601 # Number of instructions simulated 13sim_ops 1658228914 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory 18system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)
39system.membus.throughput 80578984 # Throughput (bytes/s)
40system.membus.trans_dist::ReadReq 1177898 # Transaction distribution 41system.membus.trans_dist::ReadResp 1177898 # Transaction distribution 42system.membus.trans_dist::Writeback 1017198 # Transaction distribution 43system.membus.trans_dist::ReadExReq 780876 # Transaction distribution 44system.membus.trans_dist::ReadExResp 780876 # Transaction distribution 45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)	39system.membus.trans_dist::ReadReq 1177898 # Transaction distribution 40system.membus.trans_dist::ReadResp 1177898 # Transaction distribution 41system.membus.trans_dist::Writeback 1017198 # Transaction distribution 42system.membus.trans_dist::ReadExReq 780876 # Transaction distribution 43system.membus.trans_dist::ReadExResp 780876 # Transaction distribution 44system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) 45system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)
47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) 48system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) 49system.membus.data_through_bus 190462208 # Total data (bytes) 50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)	46system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) 47system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) 48system.membus.snoops 0 # Total snoops (count) 49system.membus.snoop_fanout::samples 2975972 # Request fanout histogram 50system.membus.snoop_fanout::mean 0 # Request fanout histogram 51system.membus.snoop_fanout::stdev 0 # Request fanout histogram 52system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 53system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram 54system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 55system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 56system.membus.snoop_fanout::min_value 0 # Request fanout histogram 57system.membus.snoop_fanout::max_value 0 # Request fanout histogram 58system.membus.snoop_fanout::total 2975972 # Request fanout histogram
51system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 53system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 67system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 68system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 109system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 110system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 119system.cpu.itb.inst_hits 0 # ITB inst hits 120system.cpu.itb.inst_misses 0 # ITB inst misses 121system.cpu.itb.read_hits 0 # DTB read hits 122system.cpu.itb.read_misses 0 # DTB read misses 123system.cpu.itb.write_hits 0 # DTB write hits 124system.cpu.itb.write_misses 0 # DTB write misses 125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 127system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 128system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 129system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 130system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 131system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 132system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 133system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 134system.cpu.itb.read_accesses 0 # DTB read accesses 135system.cpu.itb.write_accesses 0 # DTB write accesses 136system.cpu.itb.inst_accesses 0 # ITB inst accesses 137system.cpu.itb.hits 0 # DTB hits 138system.cpu.itb.misses 0 # DTB misses 139system.cpu.itb.accesses 0 # DTB accesses 140system.cpu.workload.num_syscalls 46 # Number of system calls 141system.cpu.numCycles 4727341996 # number of cpu cycles simulated 142system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 143system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 144system.cpu.committedInsts 1538759601 # Number of instructions committed 145system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed 146system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses 147system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 148system.cpu.num_func_calls 27330256 # number of times a function call or return occured 149system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls 150system.cpu.num_int_insts 1477900422 # number of integer instructions 151system.cpu.num_fp_insts 36 # number of float instructions 152system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read 153system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written 154system.cpu.num_fp_register_reads 24 # number of times the floating registers were read 155system.cpu.num_fp_register_writes 16 # number of times the floating registers were written 156system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read 157system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written 158system.cpu.num_mem_refs 633153380 # number of memory refs 159system.cpu.num_load_insts 458306334 # Number of load instructions 160system.cpu.num_store_insts 174847046 # Number of store instructions 161system.cpu.num_idle_cycles 0 # Number of idle cycles 162system.cpu.num_busy_cycles 4727341996 # Number of busy cycles 163system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 164system.cpu.idle_fraction 0 # Percentage of idle cycles 165system.cpu.Branches 213462426 # Number of branches fetched 166system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 167system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction 168system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction 169system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction 170system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction 171system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction 172system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction 173system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction 174system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction 175system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction 176system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction 177system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction 178system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction 179system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction 180system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction 181system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction 182system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction 183system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction 184system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction 185system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction 186system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction 187system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction 188system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction 189system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction 190system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction 191system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction 192system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction 193system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction 194system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction 195system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction 196system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction 197system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction 198system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 199system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 200system.cpu.op_class::total 1664032480 # Class of executed instruction 201system.cpu.icache.tags.replacements 7 # number of replacements 202system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use 203system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. 204system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. 205system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. 206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 207system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor 208system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy 209system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy 210system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id 211system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 212system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 213system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id 214system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id 215system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses 216system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses 217system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits 218system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits 219system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits 220system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits 221system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits 222system.cpu.icache.overall_hits::total 1544564952 # number of overall hits 223system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses 224system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses 225system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses 226system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses 227system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses 228system.cpu.icache.overall_misses::total 638 # number of overall misses 229system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles 230system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles 231system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles 232system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles 233system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles 234system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles 235system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) 236system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) 237system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses 238system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses 239system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses 240system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses 241system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 242system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 243system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 244system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 245system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 246system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 247system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency 248system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency 249system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency 250system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency 251system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency 252system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency 253system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 254system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 255system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 256system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 257system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 258system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 259system.cpu.icache.fast_writes 0 # number of fast writes performed 260system.cpu.icache.cache_copies 0 # number of cache copies performed 261system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 262system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 263system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 264system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 265system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 266system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses 267system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles 268system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles 269system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles 270system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles 271system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles 272system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles 273system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 274system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 275system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 276system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 277system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 278system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 279system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency 280system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency 281system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency 282system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency 283system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency 284system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency 285system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 286system.cpu.l2cache.tags.replacements 1926075 # number of replacements 287system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use 288system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. 289system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. 290system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. 291system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit. 292system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor 293system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor 294system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor 295system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy 296system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy 297system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy 298system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy 299system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id 300system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 301system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 302system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id 303system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id 304system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26841 # Occupied blocks per task id 305system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id 306system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses 307system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses 308system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits 309system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits 310system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits 311system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits 312system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits 313system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits 314system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits 315system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits 316system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits 317system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits 318system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits 319system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits 320system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits 321system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses 322system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses 323system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses 324system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses 325system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses 326system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses 327system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses 328system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses 329system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses 330system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses 331system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses 332system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles 333system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles 334system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles 335system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles 336system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles 337system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles 338system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles 339system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles 340system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles 341system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles 342system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles 343system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) 344system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) 345system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) 346system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses) 347system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses) 348system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) 349system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) 350system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses 351system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses 352system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses 353system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses 354system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses 355system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses 356system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses 357system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses 358system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses 359system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses 360system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses 361system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses 362system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses 363system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses 364system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses 365system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses 366system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses 367system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency 368system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency 369system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency 370system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency 371system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency 372system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency 373system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency 374system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency 375system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency 376system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency 377system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency 378system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 379system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 380system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 381system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 382system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 383system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 384system.cpu.l2cache.fast_writes 0 # number of fast writes performed 385system.cpu.l2cache.cache_copies 0 # number of cache copies performed 386system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks 387system.cpu.l2cache.writebacks::total 1017198 # number of writebacks 388system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses 389system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses 390system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses 391system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses 392system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses 393system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses 394system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses 395system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses 396system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses 397system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses 398system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses 399system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles 400system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles 401system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles 402system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles 403system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles 404system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles 405system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles 406system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles 407system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles 408system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles 409system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles 410system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses 411system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses 412system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses 413system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses 414system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses 415system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses 416system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses 417system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses 418system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses 419system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses 420system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses 421system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency 422system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency 423system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency 424system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency 425system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency 426system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency 427system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency 428system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency 429system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency 430system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency 431system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency 432system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 433system.cpu.dcache.tags.replacements 9111140 # number of replacements 434system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use 435system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. 436system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. 437system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. 438system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. 439system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor 440system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy 441system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy 442system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id 445system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id 446system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id 447system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 448system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 449system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses 450system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses 451system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits 452system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits 453system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits 454system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits 455system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 456system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 457system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 458system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 459system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits 460system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits 461system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits 462system.cpu.dcache.overall_hits::total 618379947 # number of overall hits 463system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses 464system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses 465system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses 466system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses 467system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 468system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 469system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses 470system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses 471system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses 472system.cpu.dcache.overall_misses::total 9115236 # number of overall misses 473system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles 474system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles 475system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles 476system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles 477system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles 478system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles 479system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles 480system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles 481system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) 482system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) 483system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 484system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 485system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) 486system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) 487system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 488system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 489system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 490system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 491system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses 492system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses 493system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses 494system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses 495system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses 496system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses 497system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses 498system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses 499system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 500system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 501system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses 502system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses 503system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses 504system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses 505system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency 506system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency 507system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency 508system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency 509system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency 510system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency 511system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency 512system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency 513system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 514system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 515system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 516system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 517system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 518system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 519system.cpu.dcache.fast_writes 0 # number of fast writes performed 520system.cpu.dcache.cache_copies 0 # number of cache copies performed 521system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks 522system.cpu.dcache.writebacks::total 3697418 # number of writebacks 523system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses 524system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses 525system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 526system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses 527system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 528system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 529system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses 530system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses 531system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses 532system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses 533system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles 534system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles 538system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles 539system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles 540system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles 541system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles 542system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles 543system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses 544system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses 545system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses 546system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses 547system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses 548system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses 549system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses 550system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses 551system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses 552system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses 553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency 554system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency 555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency 556system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency 557system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency 558system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency 559system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency 560system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency 561system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency 562system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency 563system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate	59system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks) 60system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 61system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks) 62system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 63system.cpu_clk_domain.clock 500 # Clock period in ticks 64system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 65system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 66system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 67system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 68system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 69system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 70system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 71system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 72system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 73system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 74system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 75system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 76system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 77system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 78system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 79system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 80system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 81system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 82system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 83system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 84system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 85system.cpu.dtb.inst_hits 0 # ITB inst hits 86system.cpu.dtb.inst_misses 0 # ITB inst misses 87system.cpu.dtb.read_hits 0 # DTB read hits 88system.cpu.dtb.read_misses 0 # DTB read misses 89system.cpu.dtb.write_hits 0 # DTB write hits 90system.cpu.dtb.write_misses 0 # DTB write misses 91system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 92system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 93system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 94system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 95system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 96system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 97system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 98system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 99system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 100system.cpu.dtb.read_accesses 0 # DTB read accesses 101system.cpu.dtb.write_accesses 0 # DTB write accesses 102system.cpu.dtb.inst_accesses 0 # ITB inst accesses 103system.cpu.dtb.hits 0 # DTB hits 104system.cpu.dtb.misses 0 # DTB misses 105system.cpu.dtb.accesses 0 # DTB accesses 106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 127system.cpu.itb.inst_hits 0 # ITB inst hits 128system.cpu.itb.inst_misses 0 # ITB inst misses 129system.cpu.itb.read_hits 0 # DTB read hits 130system.cpu.itb.read_misses 0 # DTB read misses 131system.cpu.itb.write_hits 0 # DTB write hits 132system.cpu.itb.write_misses 0 # DTB write misses 133system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 134system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 135system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 136system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 137system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 138system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 139system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 140system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 141system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 142system.cpu.itb.read_accesses 0 # DTB read accesses 143system.cpu.itb.write_accesses 0 # DTB write accesses 144system.cpu.itb.inst_accesses 0 # ITB inst accesses 145system.cpu.itb.hits 0 # DTB hits 146system.cpu.itb.misses 0 # DTB misses 147system.cpu.itb.accesses 0 # DTB accesses 148system.cpu.workload.num_syscalls 46 # Number of system calls 149system.cpu.numCycles 4727341996 # number of cpu cycles simulated 150system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 151system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 152system.cpu.committedInsts 1538759601 # Number of instructions committed 153system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed 154system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses 155system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 156system.cpu.num_func_calls 27330256 # number of times a function call or return occured 157system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls 158system.cpu.num_int_insts 1477900422 # number of integer instructions 159system.cpu.num_fp_insts 36 # number of float instructions 160system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read 161system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written 162system.cpu.num_fp_register_reads 24 # number of times the floating registers were read 163system.cpu.num_fp_register_writes 16 # number of times the floating registers were written 164system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read 165system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written 166system.cpu.num_mem_refs 633153380 # number of memory refs 167system.cpu.num_load_insts 458306334 # Number of load instructions 168system.cpu.num_store_insts 174847046 # Number of store instructions 169system.cpu.num_idle_cycles 0 # Number of idle cycles 170system.cpu.num_busy_cycles 4727341996 # Number of busy cycles 171system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 172system.cpu.idle_fraction 0 # Percentage of idle cycles 173system.cpu.Branches 213462426 # Number of branches fetched 174system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 175system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction 176system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction 177system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction 178system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction 179system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction 180system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction 181system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction 182system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction 183system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction 184system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction 185system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction 186system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction 187system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction 188system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction 189system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction 190system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction 191system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction 192system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction 193system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction 194system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction 195system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction 196system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction 197system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction 198system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction 199system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction 200system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction 201system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction 202system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction 203system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction 204system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction 205system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction 206system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 207system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::total 1664032480 # Class of executed instruction 209system.cpu.icache.tags.replacements 7 # number of replacements 210system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use 211system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. 212system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. 213system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. 214system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 215system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor 216system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy 217system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy 218system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id 219system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 220system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id 222system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id 223system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses 224system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses 225system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits 226system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits 227system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits 228system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits 229system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits 230system.cpu.icache.overall_hits::total 1544564952 # number of overall hits 231system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses 232system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses 233system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses 234system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses 235system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses 236system.cpu.icache.overall_misses::total 638 # number of overall misses 237system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles 238system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles 239system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles 240system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles 241system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles 242system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles 243system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) 244system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) 245system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses 246system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses 247system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses 248system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses 249system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 250system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 251system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 252system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 253system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 254system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 255system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency 256system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency 257system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency 258system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency 259system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency 260system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency 261system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 262system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 263system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 264system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 265system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 266system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 267system.cpu.icache.fast_writes 0 # number of fast writes performed 268system.cpu.icache.cache_copies 0 # number of cache copies performed 269system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 270system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 271system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 272system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 273system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 274system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses 275system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles 276system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles 277system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles 278system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles 279system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles 280system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles 281system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 282system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 283system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 284system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 285system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 286system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 287system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency 289system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency 291system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency 293system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 294system.cpu.l2cache.tags.replacements 1926075 # number of replacements 295system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use 296system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. 297system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. 298system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. 299system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit. 300system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor 301system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor 302system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor 303system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy 304system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy 305system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy 306system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id 308system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 309system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id 312system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26841 # Occupied blocks per task id 313system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id 314system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses 315system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses 316system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits 317system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits 318system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits 319system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits 320system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits 321system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits 322system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits 323system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits 324system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits 325system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits 326system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits 327system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits 328system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits 329system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses 330system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses 331system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses 332system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses 333system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses 334system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses 335system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses 336system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses 337system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses 338system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses 339system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses 340system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles 341system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles 342system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles 343system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles 344system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles 345system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles 346system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles 347system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles 348system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles 349system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles 350system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles 351system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) 352system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) 353system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) 354system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses) 355system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses) 356system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) 357system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) 358system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses 359system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses 360system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses 361system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses 362system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses 363system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses 364system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses 365system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses 366system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses 367system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses 368system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses 369system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses 370system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses 371system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses 372system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses 373system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses 374system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses 375system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency 376system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency 377system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency 378system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency 379system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency 380system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency 381system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency 382system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency 383system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency 384system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency 385system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency 386system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 387system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 388system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 389system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 390system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 391system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 392system.cpu.l2cache.fast_writes 0 # number of fast writes performed 393system.cpu.l2cache.cache_copies 0 # number of cache copies performed 394system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks 395system.cpu.l2cache.writebacks::total 1017198 # number of writebacks 396system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses 397system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses 398system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses 399system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses 400system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses 401system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses 402system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses 403system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses 404system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses 405system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses 406system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses 407system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles 408system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles 409system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles 410system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles 411system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles 412system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles 413system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles 414system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles 415system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles 416system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles 418system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses 419system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses 420system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses 421system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses 422system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses 423system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses 424system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses 425system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses 426system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses 427system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses 428system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses 429system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency 430system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency 431system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency 432system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency 433system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency 434system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency 435system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency 436system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency 437system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency 438system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency 439system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency 440system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 441system.cpu.dcache.tags.replacements 9111140 # number of replacements 442system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use 443system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks. 444system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. 445system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks. 446system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit. 447system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor 448system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy 449system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy 450system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 451system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id 452system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id 453system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id 454system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id 455system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 456system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 457system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses 458system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses 459system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits 460system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits 461system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits 462system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits 463system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 464system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 465system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 466system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 467system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits 468system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits 469system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits 470system.cpu.dcache.overall_hits::total 618379947 # number of overall hits 471system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses 472system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses 473system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses 474system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses 475system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses 476system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses 477system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses 478system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses 479system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses 480system.cpu.dcache.overall_misses::total 9115236 # number of overall misses 481system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles 482system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles 483system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles 484system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles 485system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles 486system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles 487system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles 488system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles 489system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses) 490system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses) 491system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 492system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 493system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses) 494system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses) 495system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 496system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 497system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 498system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 499system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses 500system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses 501system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses 502system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses 503system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses 504system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses 505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses 506system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses 507system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 508system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 509system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses 510system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses 511system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses 512system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses 513system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency 514system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency 515system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency 516system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency 517system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency 518system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency 519system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency 520system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency 521system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 522system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 523system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 524system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 525system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 526system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 527system.cpu.dcache.fast_writes 0 # number of fast writes performed 528system.cpu.dcache.cache_copies 0 # number of cache copies performed 529system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks 530system.cpu.dcache.writebacks::total 3697418 # number of writebacks 531system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses 532system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses 533system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 534system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses 535system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 536system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 537system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses 538system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses 539system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses 540system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses 541system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles 542system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles 543system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles 544system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles 545system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles 546system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles 547system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles 548system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles 549system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles 550system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles 551system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses 552system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses 553system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses 554system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses 555system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses 556system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses 557system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses 558system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses 559system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses 560system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses 561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency 562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency 563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency 564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency 565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency 566system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency 567system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency 568system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency 569system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency 570system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency 571system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
564system.cpu.toL2Bus.throughput 346939438 # Throughput (bytes/s)
565system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution 566system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution 567system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution 568system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution 569system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution 570system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) 571system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes) 572system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)	572system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution 573system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution 577system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) 578system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes) 579system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)
573system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) 574system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) 575system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) 576system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes) 577system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)	580system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) 582system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) 583system.cpu.toL2Bus.snoops 0 # Total snoops (count) 584system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram 585system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 586system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 587system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 588system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 589system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 590system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 591system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 592system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 593system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram 594system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 595system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 596system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 597system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 598system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram
578system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) 579system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) 580system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) 581system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 582system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) 583system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 584 585---------- End Simulation Statistics ----------	599system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) 600system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) 601system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) 602system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 603system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) 604system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 605 606---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 2.363671 # Number of seconds simulated
4sim_ticks 2363670998000 # Number of ticks simulated
5final_tick 2363670998000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 1066052 # Simulator instruction rate (inst/s)
8host_op_rate 1148821 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1637550718 # Simulator tick rate (ticks/s)
10host_mem_usage 316024 # Number of bytes of host memory used
11host_seconds 1443.42 # Real time elapsed on the host

7host_inst_rate 1205605 # Simulator instruction rate (inst/s)
8host_op_rate 1299208 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1851916301 # Simulator tick rate (ticks/s)
10host_mem_usage 306192 # Number of bytes of host memory used
11host_seconds 1276.34 # Real time elapsed on the host

12sim_insts 1538759601 # Number of instructions simulated
13sim_ops 1658228914 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory
18system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory
22system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 16679 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 53020117 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 53036796 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 16679 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 16679 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 27542188 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 27542188 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 27542188 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 16679 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 53020117 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 80578984 # Total bandwidth to/from this memory (bytes/s)

39system.membus.throughput 80578984 # Throughput (bytes/s)

40system.membus.trans_dist::ReadReq 1177898 # Transaction distribution
41system.membus.trans_dist::ReadResp 1177898 # Transaction distribution
42system.membus.trans_dist::Writeback 1017198 # Transaction distribution
43system.membus.trans_dist::ReadExReq 780876 # Transaction distribution
44system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes)
46system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)

39system.membus.trans_dist::ReadReq 1177898 # Transaction distribution
40system.membus.trans_dist::ReadResp 1177898 # Transaction distribution
41system.membus.trans_dist::Writeback 1017198 # Transaction distribution
42system.membus.trans_dist::ReadExReq 780876 # Transaction distribution
43system.membus.trans_dist::ReadExResp 780876 # Transaction distribution
44system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes)
45system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes)

47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
48system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
49system.membus.data_through_bus 190462208 # Total data (bytes)
50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)

46system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes)
47system.membus.pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes)
48system.membus.snoops 0 # Total snoops (count)
49system.membus.snoop_fanout::samples 2975972 # Request fanout histogram
50system.membus.snoop_fanout::mean 0 # Request fanout histogram
51system.membus.snoop_fanout::stdev 0 # Request fanout histogram
52system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
53system.membus.snoop_fanout::0 2975972 100.00% 100.00% # Request fanout histogram
54system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
55system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
56system.membus.snoop_fanout::min_value 0 # Request fanout histogram
57system.membus.snoop_fanout::max_value 0 # Request fanout histogram
58system.membus.snoop_fanout::total 2975972 # Request fanout histogram

51system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks)
52system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
53system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks)
54system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
55system.cpu_clk_domain.clock 500 # Clock period in ticks
56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
64system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
65system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
66system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
67system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
68system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
77system.cpu.dtb.inst_hits 0 # ITB inst hits
78system.cpu.dtb.inst_misses 0 # ITB inst misses
79system.cpu.dtb.read_hits 0 # DTB read hits
80system.cpu.dtb.read_misses 0 # DTB read misses
81system.cpu.dtb.write_hits 0 # DTB write hits
82system.cpu.dtb.write_misses 0 # DTB write misses
83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
92system.cpu.dtb.read_accesses 0 # DTB read accesses
93system.cpu.dtb.write_accesses 0 # DTB write accesses
94system.cpu.dtb.inst_accesses 0 # ITB inst accesses
95system.cpu.dtb.hits 0 # DTB hits
96system.cpu.dtb.misses 0 # DTB misses
97system.cpu.dtb.accesses 0 # DTB accesses
98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
108system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
109system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
110system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
119system.cpu.itb.inst_hits 0 # ITB inst hits
120system.cpu.itb.inst_misses 0 # ITB inst misses
121system.cpu.itb.read_hits 0 # DTB read hits
122system.cpu.itb.read_misses 0 # DTB read misses
123system.cpu.itb.write_hits 0 # DTB write hits
124system.cpu.itb.write_misses 0 # DTB write misses
125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
127system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
128system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
129system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
130system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
131system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
132system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
133system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
134system.cpu.itb.read_accesses 0 # DTB read accesses
135system.cpu.itb.write_accesses 0 # DTB write accesses
136system.cpu.itb.inst_accesses 0 # ITB inst accesses
137system.cpu.itb.hits 0 # DTB hits
138system.cpu.itb.misses 0 # DTB misses
139system.cpu.itb.accesses 0 # DTB accesses
140system.cpu.workload.num_syscalls 46 # Number of system calls
141system.cpu.numCycles 4727341996 # number of cpu cycles simulated
142system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
143system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
144system.cpu.committedInsts 1538759601 # Number of instructions committed
145system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed
146system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
147system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
148system.cpu.num_func_calls 27330256 # number of times a function call or return occured
149system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
150system.cpu.num_int_insts 1477900422 # number of integer instructions
151system.cpu.num_fp_insts 36 # number of float instructions
152system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read
153system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
154system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
155system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
156system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read
157system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
158system.cpu.num_mem_refs 633153380 # number of memory refs
159system.cpu.num_load_insts 458306334 # Number of load instructions
160system.cpu.num_store_insts 174847046 # Number of store instructions
161system.cpu.num_idle_cycles 0 # Number of idle cycles
162system.cpu.num_busy_cycles 4727341996 # Number of busy cycles
163system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
164system.cpu.idle_fraction 0 # Percentage of idle cycles
165system.cpu.Branches 213462426 # Number of branches fetched
166system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
167system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction
168system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
169system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
170system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
171system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
172system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
173system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
174system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
175system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
176system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
177system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
178system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
179system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
180system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
181system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
182system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
183system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
184system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
185system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
186system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
187system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
188system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
189system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
190system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
191system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
192system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
193system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
194system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
195system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
196system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
197system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
198system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
199system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
200system.cpu.op_class::total 1664032480 # Class of executed instruction
201system.cpu.icache.tags.replacements 7 # number of replacements
202system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use
203system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
204system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
205system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks.
206system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
207system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor
208system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy
209system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy
210system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
211system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
212system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
213system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
214system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
215system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses
216system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses
217system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
218system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
219system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
220system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits
221system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits
222system.cpu.icache.overall_hits::total 1544564952 # number of overall hits
223system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
224system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
225system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
226system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
227system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
228system.cpu.icache.overall_misses::total 638 # number of overall misses
229system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles
230system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles
231system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles
232system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles
233system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles
234system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles
235system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
236system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
237system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
238system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses
239system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses
240system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses
241system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
242system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
243system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
244system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
245system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
246system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
247system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency
248system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency
249system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
250system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency
251system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
252system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency
253system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
254system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
255system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
256system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
257system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
258system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
259system.cpu.icache.fast_writes 0 # number of fast writes performed
260system.cpu.icache.cache_copies 0 # number of cache copies performed
261system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
262system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
263system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
264system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
265system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
266system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
267system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles
268system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles
269system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles
270system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles
271system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles
272system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles
273system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
274system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
275system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
276system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
277system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
278system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
279system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency
280system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency
281system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
282system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
283system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
284system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
285system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
286system.cpu.l2cache.tags.replacements 1926075 # number of replacements
287system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use
288system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks.
289system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks.
290system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks.
291system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit.
292system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor
293system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor
294system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor
295system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy
296system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy
297system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy
298system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy
299system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
300system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
301system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
302system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id
303system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id
304system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26841 # Occupied blocks per task id
305system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
306system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses
307system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses
308system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
309system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits
310system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits
311system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits
312system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits
313system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits
314system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits
315system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
316system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits
317system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits
318system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
319system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits
320system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits
321system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
322system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses
323system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses
324system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses
325system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses
326system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
327system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses
328system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses
329system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
330system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses
331system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses
332system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles
333system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles
334system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles
335system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles
336system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles
337system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles
338system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles
339system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles
340system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles
341system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles
342system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles
343system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
344system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
345system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
346system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses)
347system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses)
348system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
349system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
350system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
351system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
352system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
353system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
354system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
355system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
356system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses
357system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
358system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses
359system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses
360system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses
361system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
362system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses
363system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses
364system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
365system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses
366system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses
367system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency
368system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency
369system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency
370system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency
371system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency
372system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
373system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
374system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency
375system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
376system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
377system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency
378system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
379system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
380system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
381system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
382system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
383system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
384system.cpu.l2cache.fast_writes 0 # number of fast writes performed
385system.cpu.l2cache.cache_copies 0 # number of cache copies performed
386system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks
387system.cpu.l2cache.writebacks::total 1017198 # number of writebacks
388system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
389system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses
390system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses
391system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses
392system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses
393system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
394system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses
395system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses
396system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
397system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses
398system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses
399system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles
400system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles
401system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles
402system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles
403system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles
404system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles
405system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles
406system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles
407system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles
408system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles
409system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles
410system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
411system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
412system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses
413system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses
414system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses
415system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
416system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses
417system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses
418system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
419system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses
420system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses
421system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency
422system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency
423system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency
424system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
425system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
426system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
427system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
428system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
429system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
430system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
431system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
432system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
433system.cpu.dcache.tags.replacements 9111140 # number of replacements
434system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use
435system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
436system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
437system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
438system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit.
439system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor
440system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy
441system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy
442system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
443system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
444system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id
445system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id
446system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id
447system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
448system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
449system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
450system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses
451system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits
452system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits
453system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
454system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
455system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
456system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
457system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
458system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
459system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits
460system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits
461system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits
462system.cpu.dcache.overall_hits::total 618379947 # number of overall hits
463system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses
464system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses
465system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
466system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
467system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
468system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
469system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses
470system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
471system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
472system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
473system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles
474system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles
475system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles
476system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles
477system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles
478system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles
479system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles
480system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles
481system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
482system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
483system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
484system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
485system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses)
486system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses)
487system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
488system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
489system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
490system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
491system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses
492system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses
493system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses
494system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses
495system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses
496system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses
497system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
498system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
499system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
500system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
501system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses
502system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
503system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
504system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
505system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency
506system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency
507system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency
508system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency
509system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency
510system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency
511system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency
512system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency
513system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
514system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
515system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
516system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
517system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
518system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
519system.cpu.dcache.fast_writes 0 # number of fast writes performed
520system.cpu.dcache.cache_copies 0 # number of cache copies performed
521system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks
522system.cpu.dcache.writebacks::total 3697418 # number of writebacks
523system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses
524system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses
525system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
526system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
527system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
528system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
529system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses
530system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
531system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
532system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
533system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles
534system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles
535system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles
536system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles
537system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
538system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
539system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles
540system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles
541system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles
542system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles
543system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
544system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
545system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
546system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
547system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses
548system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses
549system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses
550system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
551system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
552system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency
554system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency
555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency
556system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency
557system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
558system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
559system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency
560system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency
561system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency
562system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency
563system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

59system.membus.reqLayer0.occupancy 11138507500 # Layer occupancy (ticks)
60system.membus.reqLayer0.utilization 0.5 # Layer utilization (%)
61system.membus.respLayer1.occupancy 17642613000 # Layer occupancy (ticks)
62system.membus.respLayer1.utilization 0.7 # Layer utilization (%)
63system.cpu_clk_domain.clock 500 # Clock period in ticks
64system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
65system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
66system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
67system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
68system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
69system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
70system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
71system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
72system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
73system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
74system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
75system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
76system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
77system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
78system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
79system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
80system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
81system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
82system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
83system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
84system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
85system.cpu.dtb.inst_hits 0 # ITB inst hits
86system.cpu.dtb.inst_misses 0 # ITB inst misses
87system.cpu.dtb.read_hits 0 # DTB read hits
88system.cpu.dtb.read_misses 0 # DTB read misses
89system.cpu.dtb.write_hits 0 # DTB write hits
90system.cpu.dtb.write_misses 0 # DTB write misses
91system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
92system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
93system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
94system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
95system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
96system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
97system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
98system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
99system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
100system.cpu.dtb.read_accesses 0 # DTB read accesses
101system.cpu.dtb.write_accesses 0 # DTB write accesses
102system.cpu.dtb.inst_accesses 0 # ITB inst accesses
103system.cpu.dtb.hits 0 # DTB hits
104system.cpu.dtb.misses 0 # DTB misses
105system.cpu.dtb.accesses 0 # DTB accesses
106system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
107system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
108system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
109system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
110system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
111system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
112system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
114system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
115system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
116system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
117system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
118system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
119system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
120system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
121system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
122system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
123system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
124system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
125system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
126system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
127system.cpu.itb.inst_hits 0 # ITB inst hits
128system.cpu.itb.inst_misses 0 # ITB inst misses
129system.cpu.itb.read_hits 0 # DTB read hits
130system.cpu.itb.read_misses 0 # DTB read misses
131system.cpu.itb.write_hits 0 # DTB write hits
132system.cpu.itb.write_misses 0 # DTB write misses
133system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
134system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
135system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
136system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
137system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
138system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
139system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
140system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
141system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
142system.cpu.itb.read_accesses 0 # DTB read accesses
143system.cpu.itb.write_accesses 0 # DTB write accesses
144system.cpu.itb.inst_accesses 0 # ITB inst accesses
145system.cpu.itb.hits 0 # DTB hits
146system.cpu.itb.misses 0 # DTB misses
147system.cpu.itb.accesses 0 # DTB accesses
148system.cpu.workload.num_syscalls 46 # Number of system calls
149system.cpu.numCycles 4727341996 # number of cpu cycles simulated
150system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
151system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
152system.cpu.committedInsts 1538759601 # Number of instructions committed
153system.cpu.committedOps 1658228914 # Number of ops (including micro ops) committed
154system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses
155system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
156system.cpu.num_func_calls 27330256 # number of times a function call or return occured
157system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls
158system.cpu.num_int_insts 1477900422 # number of integer instructions
159system.cpu.num_fp_insts 36 # number of float instructions
160system.cpu.num_int_register_reads 2601860372 # number of times the integer registers were read
161system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written
162system.cpu.num_fp_register_reads 24 # number of times the floating registers were read
163system.cpu.num_fp_register_writes 16 # number of times the floating registers were written
164system.cpu.num_cc_register_reads 6356387675 # number of times the CC registers were read
165system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written
166system.cpu.num_mem_refs 633153380 # number of memory refs
167system.cpu.num_load_insts 458306334 # Number of load instructions
168system.cpu.num_store_insts 174847046 # Number of store instructions
169system.cpu.num_idle_cycles 0 # Number of idle cycles
170system.cpu.num_busy_cycles 4727341996 # Number of busy cycles
171system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
172system.cpu.idle_fraction 0 # Percentage of idle cycles
173system.cpu.Branches 213462426 # Number of branches fetched
174system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
175system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction
176system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction
177system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction
178system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction
179system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction
180system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction
181system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction
182system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction
183system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction
184system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction
185system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction
186system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction
187system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction
188system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction
189system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction
190system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction
191system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction
192system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction
193system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction
194system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction
195system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction
196system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction
197system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction
198system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction
199system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction
200system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction
201system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction
202system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction
203system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction
204system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction
205system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction
206system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
207system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::total 1664032480 # Class of executed instruction
209system.cpu.icache.tags.replacements 7 # number of replacements
210system.cpu.icache.tags.tagsinuse 515.012865 # Cycle average of tags in use
211system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks.
212system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks.
213system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks.
214system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
215system.cpu.icache.tags.occ_blocks::cpu.inst 515.012865 # Average occupied blocks per requestor
216system.cpu.icache.tags.occ_percent::cpu.inst 0.251471 # Average percentage of cache occupancy
217system.cpu.icache.tags.occ_percent::total 0.251471 # Average percentage of cache occupancy
218system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id
219system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
220system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id
221system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id
222system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id
223system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses
224system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses
225system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits
226system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits
227system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits
228system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits
229system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits
230system.cpu.icache.overall_hits::total 1544564952 # number of overall hits
231system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
232system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
233system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
234system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
235system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
236system.cpu.icache.overall_misses::total 638 # number of overall misses
237system.cpu.icache.ReadReq_miss_latency::cpu.inst 34244500 # number of ReadReq miss cycles
238system.cpu.icache.ReadReq_miss_latency::total 34244500 # number of ReadReq miss cycles
239system.cpu.icache.demand_miss_latency::cpu.inst 34244500 # number of demand (read+write) miss cycles
240system.cpu.icache.demand_miss_latency::total 34244500 # number of demand (read+write) miss cycles
241system.cpu.icache.overall_miss_latency::cpu.inst 34244500 # number of overall miss cycles
242system.cpu.icache.overall_miss_latency::total 34244500 # number of overall miss cycles
243system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses)
244system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses)
245system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses
246system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses
247system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses
248system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses
249system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
250system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses
251system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
252system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses
253system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
254system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses
255system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53674.764890 # average ReadReq miss latency
256system.cpu.icache.ReadReq_avg_miss_latency::total 53674.764890 # average ReadReq miss latency
257system.cpu.icache.demand_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
258system.cpu.icache.demand_avg_miss_latency::total 53674.764890 # average overall miss latency
259system.cpu.icache.overall_avg_miss_latency::cpu.inst 53674.764890 # average overall miss latency
260system.cpu.icache.overall_avg_miss_latency::total 53674.764890 # average overall miss latency
261system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
262system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
263system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
264system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
265system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
266system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
267system.cpu.icache.fast_writes 0 # number of fast writes performed
268system.cpu.icache.cache_copies 0 # number of cache copies performed
269system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
270system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
271system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
272system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
273system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
274system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
275system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32968500 # number of ReadReq MSHR miss cycles
276system.cpu.icache.ReadReq_mshr_miss_latency::total 32968500 # number of ReadReq MSHR miss cycles
277system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32968500 # number of demand (read+write) MSHR miss cycles
278system.cpu.icache.demand_mshr_miss_latency::total 32968500 # number of demand (read+write) MSHR miss cycles
279system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32968500 # number of overall MSHR miss cycles
280system.cpu.icache.overall_mshr_miss_latency::total 32968500 # number of overall MSHR miss cycles
281system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
282system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses
283system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
284system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses
285system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
286system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses
287system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51674.764890 # average ReadReq mshr miss latency
288system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51674.764890 # average ReadReq mshr miss latency
289system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
290system.cpu.icache.demand_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
291system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51674.764890 # average overall mshr miss latency
292system.cpu.icache.overall_avg_mshr_miss_latency::total 51674.764890 # average overall mshr miss latency
293system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
294system.cpu.l2cache.tags.replacements 1926075 # number of replacements
295system.cpu.l2cache.tags.tagsinuse 31008.537310 # Cycle average of tags in use
296system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks.
297system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks.
298system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks.
299system.cpu.l2cache.tags.warmup_cycle 150067859000 # Cycle when the warmup percentage was hit.
300system.cpu.l2cache.tags.occ_blocks::writebacks 15658.172881 # Average occupied blocks per requestor
301system.cpu.l2cache.tags.occ_blocks::cpu.inst 23.876038 # Average occupied blocks per requestor
302system.cpu.l2cache.tags.occ_blocks::cpu.data 15326.488392 # Average occupied blocks per requestor
303system.cpu.l2cache.tags.occ_percent::writebacks 0.477850 # Average percentage of cache occupancy
304system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000729 # Average percentage of cache occupancy
305system.cpu.l2cache.tags.occ_percent::cpu.data 0.467727 # Average percentage of cache occupancy
306system.cpu.l2cache.tags.occ_percent::total 0.946305 # Average percentage of cache occupancy
307system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id
308system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id
309system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id
310system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id
311system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1732 # Occupied blocks per task id
312system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26841 # Occupied blocks per task id
313system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id
314system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses
315system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses
316system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits
317system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits
318system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits
319system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits
320system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits
321system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits
322system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits
323system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits
324system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits
325system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits
326system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits
327system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits
328system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits
329system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
330system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses
331system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses
332system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses
333system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses
334system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
335system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses
336system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses
337system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
338system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses
339system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses
340system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32110500 # number of ReadReq miss cycles
341system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61239144500 # number of ReadReq miss cycles
342system.cpu.l2cache.ReadReq_miss_latency::total 61271255000 # number of ReadReq miss cycles
343system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608894000 # number of ReadExReq miss cycles
344system.cpu.l2cache.ReadExReq_miss_latency::total 40608894000 # number of ReadExReq miss cycles
345system.cpu.l2cache.demand_miss_latency::cpu.inst 32110500 # number of demand (read+write) miss cycles
346system.cpu.l2cache.demand_miss_latency::cpu.data 101848038500 # number of demand (read+write) miss cycles
347system.cpu.l2cache.demand_miss_latency::total 101880149000 # number of demand (read+write) miss cycles
348system.cpu.l2cache.overall_miss_latency::cpu.inst 32110500 # number of overall miss cycles
349system.cpu.l2cache.overall_miss_latency::cpu.data 101848038500 # number of overall miss cycles
350system.cpu.l2cache.overall_miss_latency::total 101880149000 # number of overall miss cycles
351system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses)
352system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses)
353system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses)
354system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses)
355system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses)
356system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses)
357system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses)
358system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses
359system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses
360system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses
361system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses
362system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses
363system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses
364system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses
365system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
366system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses
367system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses
368system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses
369system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses
370system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses
371system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses
372system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses
373system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses
374system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses
375system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52127.435065 # average ReadReq miss latency
376system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52017.396427 # average ReadReq miss latency
377system.cpu.l2cache.ReadReq_avg_miss_latency::total 52017.453973 # average ReadReq miss latency
378system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.279809 # average ReadExReq miss latency
379system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.279809 # average ReadExReq miss latency
380system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
381system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
382system.cpu.l2cache.demand_avg_miss_latency::total 52012.202020 # average overall miss latency
383system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52127.435065 # average overall miss latency
384system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52012.165770 # average overall miss latency
385system.cpu.l2cache.overall_avg_miss_latency::total 52012.202020 # average overall miss latency
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387system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
388system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
389system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
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391system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
392system.cpu.l2cache.fast_writes 0 # number of fast writes performed
393system.cpu.l2cache.cache_copies 0 # number of cache copies performed
394system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks
395system.cpu.l2cache.writebacks::total 1017198 # number of writebacks
396system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
397system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses
398system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses
399system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses
400system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses
401system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
402system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses
403system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses
404system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
405system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses
406system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses
407system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24708000 # number of ReadReq MSHR miss cycles
408system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098189000 # number of ReadReq MSHR miss cycles
409system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122897000 # number of ReadReq MSHR miss cycles
410system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles
411system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles
412system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24708000 # number of demand (read+write) MSHR miss cycles
413system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336506000 # number of demand (read+write) MSHR miss cycles
414system.cpu.l2cache.demand_mshr_miss_latency::total 78361214000 # number of demand (read+write) MSHR miss cycles
415system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24708000 # number of overall MSHR miss cycles
416system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336506000 # number of overall MSHR miss cycles
417system.cpu.l2cache.overall_mshr_miss_latency::total 78361214000 # number of overall MSHR miss cycles
418system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
419system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
420system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses
421system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses
422system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses
423system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
424system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses
425system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses
426system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
427system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses
428system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses
429system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40110.389610 # average ReadReq mshr miss latency
430system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.868602 # average ReadReq mshr miss latency
431system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.923263 # average ReadReq mshr miss latency
432system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency
433system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency
434system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
435system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
436system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
437system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40110.389610 # average overall mshr miss latency
438system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.201827 # average overall mshr miss latency
439system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.234907 # average overall mshr miss latency
440system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
441system.cpu.dcache.tags.replacements 9111140 # number of replacements
442system.cpu.dcache.tags.tagsinuse 4083.733705 # Cycle average of tags in use
443system.cpu.dcache.tags.total_refs 618380069 # Total number of references to valid blocks.
444system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks.
445system.cpu.dcache.tags.avg_refs 67.840270 # Average number of references to valid blocks.
446system.cpu.dcache.tags.warmup_cycle 25164666000 # Cycle when the warmup percentage was hit.
447system.cpu.dcache.tags.occ_blocks::cpu.data 4083.733705 # Average occupied blocks per requestor
448system.cpu.dcache.tags.occ_percent::cpu.data 0.997005 # Average percentage of cache occupancy
449system.cpu.dcache.tags.occ_percent::total 0.997005 # Average percentage of cache occupancy
450system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
451system.cpu.dcache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
452system.cpu.dcache.tags.age_task_id_blocks_1024::1 1213 # Occupied blocks per task id
453system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id
454system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id
455system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id
456system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
457system.cpu.dcache.tags.tag_accesses 1264105846 # Number of tag accesses
458system.cpu.dcache.tags.data_accesses 1264105846 # Number of data accesses
459system.cpu.dcache.ReadReq_hits::cpu.data 447683049 # number of ReadReq hits
460system.cpu.dcache.ReadReq_hits::total 447683049 # number of ReadReq hits
461system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits
462system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits
463system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
464system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
465system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
466system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
467system.cpu.dcache.demand_hits::cpu.data 618379947 # number of demand (read+write) hits
468system.cpu.dcache.demand_hits::total 618379947 # number of demand (read+write) hits
469system.cpu.dcache.overall_hits::cpu.data 618379947 # number of overall hits
470system.cpu.dcache.overall_hits::total 618379947 # number of overall hits
471system.cpu.dcache.ReadReq_misses::cpu.data 7226086 # number of ReadReq misses
472system.cpu.dcache.ReadReq_misses::total 7226086 # number of ReadReq misses
473system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses
474system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses
475system.cpu.dcache.SoftPFReq_misses::cpu.data 1 # number of SoftPFReq misses
476system.cpu.dcache.SoftPFReq_misses::total 1 # number of SoftPFReq misses
477system.cpu.dcache.demand_misses::cpu.data 9115235 # number of demand (read+write) misses
478system.cpu.dcache.demand_misses::total 9115235 # number of demand (read+write) misses
479system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses
480system.cpu.dcache.overall_misses::total 9115236 # number of overall misses
481system.cpu.dcache.ReadReq_miss_latency::cpu.data 143405400500 # number of ReadReq miss cycles
482system.cpu.dcache.ReadReq_miss_latency::total 143405400500 # number of ReadReq miss cycles
483system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359071000 # number of WriteReq miss cycles
484system.cpu.dcache.WriteReq_miss_latency::total 57359071000 # number of WriteReq miss cycles
485system.cpu.dcache.demand_miss_latency::cpu.data 200764471500 # number of demand (read+write) miss cycles
486system.cpu.dcache.demand_miss_latency::total 200764471500 # number of demand (read+write) miss cycles
487system.cpu.dcache.overall_miss_latency::cpu.data 200764471500 # number of overall miss cycles
488system.cpu.dcache.overall_miss_latency::total 200764471500 # number of overall miss cycles
489system.cpu.dcache.ReadReq_accesses::cpu.data 454909135 # number of ReadReq accesses(hits+misses)
490system.cpu.dcache.ReadReq_accesses::total 454909135 # number of ReadReq accesses(hits+misses)
491system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
492system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
493system.cpu.dcache.SoftPFReq_accesses::cpu.data 1 # number of SoftPFReq accesses(hits+misses)
494system.cpu.dcache.SoftPFReq_accesses::total 1 # number of SoftPFReq accesses(hits+misses)
495system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
496system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
497system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
498system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
499system.cpu.dcache.demand_accesses::cpu.data 627495182 # number of demand (read+write) accesses
500system.cpu.dcache.demand_accesses::total 627495182 # number of demand (read+write) accesses
501system.cpu.dcache.overall_accesses::cpu.data 627495183 # number of overall (read+write) accesses
502system.cpu.dcache.overall_accesses::total 627495183 # number of overall (read+write) accesses
503system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015885 # miss rate for ReadReq accesses
504system.cpu.dcache.ReadReq_miss_rate::total 0.015885 # miss rate for ReadReq accesses
505system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses
506system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses
507system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
508system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
509system.cpu.dcache.demand_miss_rate::cpu.data 0.014526 # miss rate for demand accesses
510system.cpu.dcache.demand_miss_rate::total 0.014526 # miss rate for demand accesses
511system.cpu.dcache.overall_miss_rate::cpu.data 0.014526 # miss rate for overall accesses
512system.cpu.dcache.overall_miss_rate::total 0.014526 # miss rate for overall accesses
513system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19845.515332 # average ReadReq miss latency
514system.cpu.dcache.ReadReq_avg_miss_latency::total 19845.515332 # average ReadReq miss latency
515system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.385921 # average WriteReq miss latency
516system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.385921 # average WriteReq miss latency
517system.cpu.dcache.demand_avg_miss_latency::cpu.data 22025.155852 # average overall miss latency
518system.cpu.dcache.demand_avg_miss_latency::total 22025.155852 # average overall miss latency
519system.cpu.dcache.overall_avg_miss_latency::cpu.data 22025.153435 # average overall miss latency
520system.cpu.dcache.overall_avg_miss_latency::total 22025.153435 # average overall miss latency
521system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
522system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
523system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
524system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
525system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
526system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
527system.cpu.dcache.fast_writes 0 # number of fast writes performed
528system.cpu.dcache.cache_copies 0 # number of cache copies performed
529system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks
530system.cpu.dcache.writebacks::total 3697418 # number of writebacks
531system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226086 # number of ReadReq MSHR misses
532system.cpu.dcache.ReadReq_mshr_misses::total 7226086 # number of ReadReq MSHR misses
533system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses
534system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses
535system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
536system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
537system.cpu.dcache.demand_mshr_misses::cpu.data 9115235 # number of demand (read+write) MSHR misses
538system.cpu.dcache.demand_mshr_misses::total 9115235 # number of demand (read+write) MSHR misses
539system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses
540system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses
541system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128953228500 # number of ReadReq MSHR miss cycles
542system.cpu.dcache.ReadReq_mshr_miss_latency::total 128953228500 # number of ReadReq MSHR miss cycles
543system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580773000 # number of WriteReq MSHR miss cycles
544system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580773000 # number of WriteReq MSHR miss cycles
545system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 53000 # number of SoftPFReq MSHR miss cycles
546system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 53000 # number of SoftPFReq MSHR miss cycles
547system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182534001500 # number of demand (read+write) MSHR miss cycles
548system.cpu.dcache.demand_mshr_miss_latency::total 182534001500 # number of demand (read+write) MSHR miss cycles
549system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182534054500 # number of overall MSHR miss cycles
550system.cpu.dcache.overall_mshr_miss_latency::total 182534054500 # number of overall MSHR miss cycles
551system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015885 # mshr miss rate for ReadReq accesses
552system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015885 # mshr miss rate for ReadReq accesses
553system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses
554system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses
555system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SoftPFReq accesses
556system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 1 # mshr miss rate for SoftPFReq accesses
557system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for demand accesses
558system.cpu.dcache.demand_mshr_miss_rate::total 0.014526 # mshr miss rate for demand accesses
559system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014526 # mshr miss rate for overall accesses
560system.cpu.dcache.overall_mshr_miss_rate::total 0.014526 # mshr miss rate for overall accesses
561system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17845.515332 # average ReadReq mshr miss latency
562system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17845.515332 # average ReadReq mshr miss latency
563system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.385921 # average WriteReq mshr miss latency
564system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.385921 # average WriteReq mshr miss latency
565system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 53000 # average SoftPFReq mshr miss latency
566system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 53000 # average SoftPFReq mshr miss latency
567system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20025.155852 # average overall mshr miss latency
568system.cpu.dcache.demand_avg_mshr_miss_latency::total 20025.155852 # average overall mshr miss latency
569system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20025.159469 # average overall mshr miss latency
570system.cpu.dcache.overall_avg_mshr_miss_latency::total 20025.159469 # average overall mshr miss latency
571system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

564system.cpu.toL2Bus.throughput 346939438 # Throughput (bytes/s)

565system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
566system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
567system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
568system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
569system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
570system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
571system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes)
572system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)

572system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution
573system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution
574system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution
575system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution
576system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution
577system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes)
578system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes)
579system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes)

573system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
574system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
575system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
576system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes)
577system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)

580system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes)
581system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes)
582system.cpu.toL2Bus.pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes)
583system.cpu.toL2Bus.snoops 0 # Total snoops (count)
584system.cpu.toL2Bus.snoop_fanout::samples 12813292 # Request fanout histogram
585system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
586system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
587system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
588system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
589system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
590system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
591system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
592system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
593system.cpu.toL2Bus.snoop_fanout::5 12813292 100.00% 100.00% # Request fanout histogram
594system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
595system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
596system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
597system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
598system.cpu.toL2Bus.snoop_fanout::total 12813292 # Request fanout histogram