Cross Reference: /gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt

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1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.391205 # Number of seconds simulated 4sim_ticks 2391205115000 # Number of ticks simulated 5final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 2.391205 # Number of seconds simulated 4sim_ticks 2391205115000 # Number of ticks simulated 5final_tick 2391205115000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1176543 # Simulator instruction rate (inst/s) 8host_op_rate 1313033 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1828326739 # Simulator tick rate (ticks/s) 10host_mem_usage 268744 # Number of bytes of host memory used 11host_seconds 1307.87 # Real time elapsed on the host	7host_inst_rate 867002 # Simulator instruction rate (inst/s) 8host_op_rate 967582 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1347305237 # Simulator tick rate (ticks/s) 10host_mem_usage 310408 # Number of bytes of host memory used 11host_seconds 1774.81 # Real time elapsed on the host
12sim_insts 1538759601 # Number of instructions simulated 13sim_ops 1717270334 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory 18system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) 39system.membus.throughput 79651138 # Throughput (bytes/s) 40system.membus.trans_dist::ReadReq 1177898 # Transaction distribution 41system.membus.trans_dist::ReadResp 1177898 # Transaction distribution 42system.membus.trans_dist::Writeback 1017198 # Transaction distribution 43system.membus.trans_dist::ReadExReq 780876 # Transaction distribution 44system.membus.trans_dist::ReadExResp 780876 # Transaction distribution 45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) 47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) 48system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) 49system.membus.data_through_bus 190462208 # Total data (bytes) 50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 51system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 53system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 67system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 68system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 109system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 110system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 119system.cpu.itb.inst_hits 0 # ITB inst hits 120system.cpu.itb.inst_misses 0 # ITB inst misses 121system.cpu.itb.read_hits 0 # DTB read hits 122system.cpu.itb.read_misses 0 # DTB read misses 123system.cpu.itb.write_hits 0 # DTB write hits 124system.cpu.itb.write_misses 0 # DTB write misses 125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 127system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 128system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 129system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 130system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 131system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 132system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 133system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 134system.cpu.itb.read_accesses 0 # DTB read accesses 135system.cpu.itb.write_accesses 0 # DTB write accesses 136system.cpu.itb.inst_accesses 0 # ITB inst accesses 137system.cpu.itb.hits 0 # DTB hits 138system.cpu.itb.misses 0 # DTB misses 139system.cpu.itb.accesses 0 # DTB accesses 140system.cpu.workload.num_syscalls 46 # Number of system calls 141system.cpu.numCycles 4782410230 # number of cpu cycles simulated 142system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 143system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 144system.cpu.committedInsts 1538759601 # Number of instructions committed 145system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed 146system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses 147system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 148system.cpu.num_func_calls 27330256 # number of times a function call or return occured 149system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls 150system.cpu.num_int_insts 1536941842 # number of integer instructions 151system.cpu.num_fp_insts 36 # number of float instructions 152system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read 153system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written 154system.cpu.num_fp_register_reads 24 # number of times the floating registers were read 155system.cpu.num_fp_register_writes 16 # number of times the floating registers were written 156system.cpu.num_mem_refs 660773815 # number of memory refs 157system.cpu.num_load_insts 485926769 # Number of load instructions 158system.cpu.num_store_insts 174847046 # Number of store instructions 159system.cpu.num_idle_cycles 0 # Number of idle cycles 160system.cpu.num_busy_cycles 4782410230 # Number of busy cycles 161system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 162system.cpu.idle_fraction 0 # Percentage of idle cycles 163system.cpu.Branches 213462426 # Number of branches fetched	12sim_insts 1538759601 # Number of instructions simulated 13sim_ops 1717270334 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 39424 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 125322112 # Number of bytes read from this memory 18system.physmem.bytes_read::total 125361536 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 39424 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 39424 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 65100672 # Number of bytes written to this memory 22system.physmem.bytes_written::total 65100672 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 616 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1958158 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1958774 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1017198 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1017198 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 16487 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 52409604 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 52426091 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 16487 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 16487 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 27225047 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 27225047 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 27225047 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 16487 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 52409604 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 79651138 # Total bandwidth to/from this memory (bytes/s) 39system.membus.throughput 79651138 # Throughput (bytes/s) 40system.membus.trans_dist::ReadReq 1177898 # Transaction distribution 41system.membus.trans_dist::ReadResp 1177898 # Transaction distribution 42system.membus.trans_dist::Writeback 1017198 # Transaction distribution 43system.membus.trans_dist::ReadExReq 780876 # Transaction distribution 44system.membus.trans_dist::ReadExResp 780876 # Transaction distribution 45system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4934746 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count::total 4934746 # Packet count per connected master and slave (bytes) 47system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190462208 # Cumulative packet size per connected master and slave (bytes) 48system.membus.tot_pkt_size::total 190462208 # Cumulative packet size per connected master and slave (bytes) 49system.membus.data_through_bus 190462208 # Total data (bytes) 50system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 51system.membus.reqLayer0.occupancy 11113556000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 0.5 # Layer utilization (%) 53system.membus.respLayer1.occupancy 17628966000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 0.7 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 57system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 58system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 59system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 60system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 61system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 62system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 63system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 64system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 65system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 66system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 67system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 68system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 69system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 70system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 71system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 72system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 73system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 74system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 75system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 76system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 77system.cpu.dtb.inst_hits 0 # ITB inst hits 78system.cpu.dtb.inst_misses 0 # ITB inst misses 79system.cpu.dtb.read_hits 0 # DTB read hits 80system.cpu.dtb.read_misses 0 # DTB read misses 81system.cpu.dtb.write_hits 0 # DTB write hits 82system.cpu.dtb.write_misses 0 # DTB write misses 83system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 84system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 85system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 86system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 87system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 88system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 89system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 90system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 91system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 92system.cpu.dtb.read_accesses 0 # DTB read accesses 93system.cpu.dtb.write_accesses 0 # DTB write accesses 94system.cpu.dtb.inst_accesses 0 # ITB inst accesses 95system.cpu.dtb.hits 0 # DTB hits 96system.cpu.dtb.misses 0 # DTB misses 97system.cpu.dtb.accesses 0 # DTB accesses 98system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 99system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 100system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 101system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 102system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 103system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 104system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 109system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 110system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 111system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 112system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 113system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 114system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 115system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 116system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 117system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 118system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 119system.cpu.itb.inst_hits 0 # ITB inst hits 120system.cpu.itb.inst_misses 0 # ITB inst misses 121system.cpu.itb.read_hits 0 # DTB read hits 122system.cpu.itb.read_misses 0 # DTB read misses 123system.cpu.itb.write_hits 0 # DTB write hits 124system.cpu.itb.write_misses 0 # DTB write misses 125system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 126system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 127system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 128system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 129system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 130system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 131system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 132system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 133system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 134system.cpu.itb.read_accesses 0 # DTB read accesses 135system.cpu.itb.write_accesses 0 # DTB write accesses 136system.cpu.itb.inst_accesses 0 # ITB inst accesses 137system.cpu.itb.hits 0 # DTB hits 138system.cpu.itb.misses 0 # DTB misses 139system.cpu.itb.accesses 0 # DTB accesses 140system.cpu.workload.num_syscalls 46 # Number of system calls 141system.cpu.numCycles 4782410230 # number of cpu cycles simulated 142system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 143system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 144system.cpu.committedInsts 1538759601 # Number of instructions committed 145system.cpu.committedOps 1717270334 # Number of ops (including micro ops) committed 146system.cpu.num_int_alu_accesses 1536941842 # Number of integer alu accesses 147system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 148system.cpu.num_func_calls 27330256 # number of times a function call or return occured 149system.cpu.num_conditional_control_insts 177498328 # number of instructions that are conditional controls 150system.cpu.num_int_insts 1536941842 # number of integer instructions 151system.cpu.num_fp_insts 36 # number of float instructions 152system.cpu.num_int_register_reads 9304895467 # number of times the integer registers were read 153system.cpu.num_int_register_writes 1675132405 # number of times the integer registers were written 154system.cpu.num_fp_register_reads 24 # number of times the floating registers were read 155system.cpu.num_fp_register_writes 16 # number of times the floating registers were written 156system.cpu.num_mem_refs 660773815 # number of memory refs 157system.cpu.num_load_insts 485926769 # Number of load instructions 158system.cpu.num_store_insts 174847046 # Number of store instructions 159system.cpu.num_idle_cycles 0 # Number of idle cycles 160system.cpu.num_busy_cycles 4782410230 # Number of busy cycles 161system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 162system.cpu.idle_fraction 0 # Percentage of idle cycles 163system.cpu.Branches 213462426 # Number of branches fetched
	164system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 165system.cpu.op_class::IntAlu 1061599760 61.61% 61.61% # Class of executed instruction 166system.cpu.op_class::IntMult 700322 0.04% 61.65% # Class of executed instruction 167system.cpu.op_class::IntDiv 0 0.00% 61.65% # Class of executed instruction 168system.cpu.op_class::FloatAdd 0 0.00% 61.65% # Class of executed instruction 169system.cpu.op_class::FloatCmp 0 0.00% 61.65% # Class of executed instruction 170system.cpu.op_class::FloatCvt 0 0.00% 61.65% # Class of executed instruction 171system.cpu.op_class::FloatMult 0 0.00% 61.65% # Class of executed instruction 172system.cpu.op_class::FloatDiv 0 0.00% 61.65% # Class of executed instruction 173system.cpu.op_class::FloatSqrt 0 0.00% 61.65% # Class of executed instruction 174system.cpu.op_class::SimdAdd 0 0.00% 61.65% # Class of executed instruction 175system.cpu.op_class::SimdAddAcc 0 0.00% 61.65% # Class of executed instruction 176system.cpu.op_class::SimdAlu 0 0.00% 61.65% # Class of executed instruction 177system.cpu.op_class::SimdCmp 0 0.00% 61.65% # Class of executed instruction 178system.cpu.op_class::SimdCvt 0 0.00% 61.65% # Class of executed instruction 179system.cpu.op_class::SimdMisc 0 0.00% 61.65% # Class of executed instruction 180system.cpu.op_class::SimdMult 0 0.00% 61.65% # Class of executed instruction 181system.cpu.op_class::SimdMultAcc 0 0.00% 61.65% # Class of executed instruction 182system.cpu.op_class::SimdShift 0 0.00% 61.65% # Class of executed instruction 183system.cpu.op_class::SimdShiftAcc 0 0.00% 61.65% # Class of executed instruction 184system.cpu.op_class::SimdSqrt 0 0.00% 61.65% # Class of executed instruction 185system.cpu.op_class::SimdFloatAdd 0 0.00% 61.65% # Class of executed instruction 186system.cpu.op_class::SimdFloatAlu 0 0.00% 61.65% # Class of executed instruction 187system.cpu.op_class::SimdFloatCmp 0 0.00% 61.65% # Class of executed instruction 188system.cpu.op_class::SimdFloatCvt 0 0.00% 61.65% # Class of executed instruction 189system.cpu.op_class::SimdFloatDiv 0 0.00% 61.65% # Class of executed instruction 190system.cpu.op_class::SimdFloatMisc 3 0.00% 61.65% # Class of executed instruction 191system.cpu.op_class::SimdFloatMult 0 0.00% 61.65% # Class of executed instruction 192system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.65% # Class of executed instruction 193system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.65% # Class of executed instruction 194system.cpu.op_class::MemRead 485926769 28.20% 89.85% # Class of executed instruction 195system.cpu.op_class::MemWrite 174847046 10.15% 100.00% # Class of executed instruction 196system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 197system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 198system.cpu.op_class::total 1723073900 # Class of executed instruction
164system.cpu.icache.tags.replacements 7 # number of replacements 165system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use 166system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. 167system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. 168system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. 169system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 170system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor 171system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy 172system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy 173system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id 174system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 175system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 176system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id 177system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id 178system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses 179system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses 180system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits 181system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits 182system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits 183system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits 184system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits 185system.cpu.icache.overall_hits::total 1544564952 # number of overall hits 186system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses 187system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses 188system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses 189system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses 190system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses 191system.cpu.icache.overall_misses::total 638 # number of overall misses 192system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles 193system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles 194system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles 195system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles 196system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles 197system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles 198system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) 199system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) 200system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses 201system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses 202system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses 203system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses 204system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 205system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 206system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 207system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 208system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 209system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 210system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency 211system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency 212system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency 213system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency 214system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency 215system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency 216system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 217system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 218system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 219system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 220system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 221system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 222system.cpu.icache.fast_writes 0 # number of fast writes performed 223system.cpu.icache.cache_copies 0 # number of cache copies performed 224system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 225system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 226system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 227system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 228system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 229system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses 230system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles 231system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles 232system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles 233system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles 234system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles 235system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles 236system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 237system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 238system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 239system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 240system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 241system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 242system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency 243system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency 244system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency 245system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency 246system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency 247system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency 248system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 249system.cpu.l2cache.tags.replacements 1926075 # number of replacements 250system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use 251system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. 252system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. 253system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. 254system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. 255system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor 256system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor 257system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor 258system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy 259system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy 260system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy 261system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy 262system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id 263system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 264system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 265system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id 266system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id 267system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26880 # Occupied blocks per task id 268system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id 269system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses 270system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses 271system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits 272system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits 273system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits 274system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits 275system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits 276system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits 277system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits 278system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits 279system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits 280system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits 281system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits 282system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits 283system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits 284system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses 285system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses 286system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses 287system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses 288system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses 289system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses 290system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses 291system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses 292system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses 293system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses 294system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses 295system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles 296system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles 297system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles 298system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles 299system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles 300system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles 301system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles 302system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles 303system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles 304system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles 305system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles 306system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) 307system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) 308system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) 309system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses) 310system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses) 311system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) 312system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) 313system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses 314system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses 315system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses 316system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses 317system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses 318system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses 319system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses 320system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses 321system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses 322system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses 323system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses 324system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses 325system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses 326system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses 327system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses 328system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses 329system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses 330system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency 331system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency 332system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency 333system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency 334system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency 335system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency 336system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency 337system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency 338system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency 339system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency 340system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency 341system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 342system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 343system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 344system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 345system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 346system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 347system.cpu.l2cache.fast_writes 0 # number of fast writes performed 348system.cpu.l2cache.cache_copies 0 # number of cache copies performed 349system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks 350system.cpu.l2cache.writebacks::total 1017198 # number of writebacks 351system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses 352system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses 353system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses 354system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses 355system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses 356system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses 357system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses 358system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses 359system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses 360system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses 361system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses 362system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles 363system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles 364system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles 365system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles 366system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles 367system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles 368system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles 369system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles 370system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles 371system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles 372system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles 373system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses 374system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses 375system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses 376system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses 377system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses 378system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses 379system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses 380system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses 381system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses 382system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses 383system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses 384system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency 385system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency 386system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency 387system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency 388system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency 389system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency 390system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency 391system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency 392system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency 393system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency 394system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency 395system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 396system.cpu.dcache.tags.replacements 9111140 # number of replacements 397system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use 398system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks. 399system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. 400system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks. 401system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. 402system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor 403system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy 404system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy 405system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 406system.cpu.dcache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id 407system.cpu.dcache.tags.age_task_id_blocks_1024::1 1214 # Occupied blocks per task id 408system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id 409system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id 410system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 411system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 412system.cpu.dcache.tags.tag_accesses 1319055826 # Number of tag accesses 413system.cpu.dcache.tags.data_accesses 1319055826 # Number of data accesses 414system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits 415system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits 416system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits 417system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits 418system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 419system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 420system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 421system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 422system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits 423system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits 424system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits 425system.cpu.dcache.overall_hits::total 645854937 # number of overall hits 426system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses 427system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses 428system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses 429system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses 430system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses 431system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses 432system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses 433system.cpu.dcache.overall_misses::total 9115236 # number of overall misses 434system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles 435system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles 436system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles 437system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles 438system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles 439system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles 440system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles 441system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles 442system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) 443system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) 444system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 445system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 446system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 447system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 448system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 449system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 450system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses 451system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses 452system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses 453system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses 454system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses 455system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses 456system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses 457system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses 458system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses 459system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses 460system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses 461system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses 462system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency 463system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency 464system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency 465system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency 466system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency 467system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency 468system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency 469system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency 470system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 471system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 472system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 473system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 474system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 475system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 476system.cpu.dcache.fast_writes 0 # number of fast writes performed 477system.cpu.dcache.cache_copies 0 # number of cache copies performed 478system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks 479system.cpu.dcache.writebacks::total 3697418 # number of writebacks 480system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses 481system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses 482system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 483system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses 484system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses 485system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses 486system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses 487system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses 488system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles 489system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles 490system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles 491system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles 492system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles 493system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles 494system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles 495system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles 496system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses 497system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses 498system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses 499system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses 500system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses 501system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses 502system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses 503system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses 504system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency 505system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency 506system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency 507system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency 508system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency 509system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency 510system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency 511system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency 512system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 513system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s) 514system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution 515system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution 516system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution 517system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution 518system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution 519system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) 520system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes) 521system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes) 522system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) 523system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) 524system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) 525system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes) 526system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 527system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) 528system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) 529system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) 530system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 531system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) 532system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 533 534---------- End Simulation Statistics ----------	199system.cpu.icache.tags.replacements 7 # number of replacements 200system.cpu.icache.tags.tagsinuse 514.976015 # Cycle average of tags in use 201system.cpu.icache.tags.total_refs 1544564952 # Total number of references to valid blocks. 202system.cpu.icache.tags.sampled_refs 638 # Sample count of references to valid blocks. 203system.cpu.icache.tags.avg_refs 2420948.200627 # Average number of references to valid blocks. 204system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 205system.cpu.icache.tags.occ_blocks::cpu.inst 514.976015 # Average occupied blocks per requestor 206system.cpu.icache.tags.occ_percent::cpu.inst 0.251453 # Average percentage of cache occupancy 207system.cpu.icache.tags.occ_percent::total 0.251453 # Average percentage of cache occupancy 208system.cpu.icache.tags.occ_task_id_blocks::1024 631 # Occupied blocks per task id 209system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id 210system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id 211system.cpu.icache.tags.age_task_id_blocks_1024::4 606 # Occupied blocks per task id 212system.cpu.icache.tags.occ_task_id_percent::1024 0.308105 # Percentage of cache occupancy per task id 213system.cpu.icache.tags.tag_accesses 3089131818 # Number of tag accesses 214system.cpu.icache.tags.data_accesses 3089131818 # Number of data accesses 215system.cpu.icache.ReadReq_hits::cpu.inst 1544564952 # number of ReadReq hits 216system.cpu.icache.ReadReq_hits::total 1544564952 # number of ReadReq hits 217system.cpu.icache.demand_hits::cpu.inst 1544564952 # number of demand (read+write) hits 218system.cpu.icache.demand_hits::total 1544564952 # number of demand (read+write) hits 219system.cpu.icache.overall_hits::cpu.inst 1544564952 # number of overall hits 220system.cpu.icache.overall_hits::total 1544564952 # number of overall hits 221system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses 222system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses 223system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses 224system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses 225system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses 226system.cpu.icache.overall_misses::total 638 # number of overall misses 227system.cpu.icache.ReadReq_miss_latency::cpu.inst 34233000 # number of ReadReq miss cycles 228system.cpu.icache.ReadReq_miss_latency::total 34233000 # number of ReadReq miss cycles 229system.cpu.icache.demand_miss_latency::cpu.inst 34233000 # number of demand (read+write) miss cycles 230system.cpu.icache.demand_miss_latency::total 34233000 # number of demand (read+write) miss cycles 231system.cpu.icache.overall_miss_latency::cpu.inst 34233000 # number of overall miss cycles 232system.cpu.icache.overall_miss_latency::total 34233000 # number of overall miss cycles 233system.cpu.icache.ReadReq_accesses::cpu.inst 1544565590 # number of ReadReq accesses(hits+misses) 234system.cpu.icache.ReadReq_accesses::total 1544565590 # number of ReadReq accesses(hits+misses) 235system.cpu.icache.demand_accesses::cpu.inst 1544565590 # number of demand (read+write) accesses 236system.cpu.icache.demand_accesses::total 1544565590 # number of demand (read+write) accesses 237system.cpu.icache.overall_accesses::cpu.inst 1544565590 # number of overall (read+write) accesses 238system.cpu.icache.overall_accesses::total 1544565590 # number of overall (read+write) accesses 239system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses 240system.cpu.icache.ReadReq_miss_rate::total 0.000000 # miss rate for ReadReq accesses 241system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses 242system.cpu.icache.demand_miss_rate::total 0.000000 # miss rate for demand accesses 243system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses 244system.cpu.icache.overall_miss_rate::total 0.000000 # miss rate for overall accesses 245system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53656.739812 # average ReadReq miss latency 246system.cpu.icache.ReadReq_avg_miss_latency::total 53656.739812 # average ReadReq miss latency 247system.cpu.icache.demand_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency 248system.cpu.icache.demand_avg_miss_latency::total 53656.739812 # average overall miss latency 249system.cpu.icache.overall_avg_miss_latency::cpu.inst 53656.739812 # average overall miss latency 250system.cpu.icache.overall_avg_miss_latency::total 53656.739812 # average overall miss latency 251system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 252system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 253system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 254system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 255system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 256system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 257system.cpu.icache.fast_writes 0 # number of fast writes performed 258system.cpu.icache.cache_copies 0 # number of cache copies performed 259system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses 260system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses 261system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses 262system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses 263system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses 264system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses 265system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32957000 # number of ReadReq MSHR miss cycles 266system.cpu.icache.ReadReq_mshr_miss_latency::total 32957000 # number of ReadReq MSHR miss cycles 267system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32957000 # number of demand (read+write) MSHR miss cycles 268system.cpu.icache.demand_mshr_miss_latency::total 32957000 # number of demand (read+write) MSHR miss cycles 269system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32957000 # number of overall MSHR miss cycles 270system.cpu.icache.overall_mshr_miss_latency::total 32957000 # number of overall MSHR miss cycles 271system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses 272system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000000 # mshr miss rate for ReadReq accesses 273system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses 274system.cpu.icache.demand_mshr_miss_rate::total 0.000000 # mshr miss rate for demand accesses 275system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses 276system.cpu.icache.overall_mshr_miss_rate::total 0.000000 # mshr miss rate for overall accesses 277system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51656.739812 # average ReadReq mshr miss latency 278system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51656.739812 # average ReadReq mshr miss latency 279system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency 280system.cpu.icache.demand_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency 281system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51656.739812 # average overall mshr miss latency 282system.cpu.icache.overall_avg_mshr_miss_latency::total 51656.739812 # average overall mshr miss latency 283system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 284system.cpu.l2cache.tags.replacements 1926075 # number of replacements 285system.cpu.l2cache.tags.tagsinuse 30987.094489 # Cycle average of tags in use 286system.cpu.l2cache.tags.total_refs 8967572 # Total number of references to valid blocks. 287system.cpu.l2cache.tags.sampled_refs 1955843 # Sample count of references to valid blocks. 288system.cpu.l2cache.tags.avg_refs 4.585016 # Average number of references to valid blocks. 289system.cpu.l2cache.tags.warmup_cycle 154026636000 # Cycle when the warmup percentage was hit. 290system.cpu.l2cache.tags.occ_blocks::writebacks 15648.493745 # Average occupied blocks per requestor 291system.cpu.l2cache.tags.occ_blocks::cpu.inst 24.153175 # Average occupied blocks per requestor 292system.cpu.l2cache.tags.occ_blocks::cpu.data 15314.447570 # Average occupied blocks per requestor 293system.cpu.l2cache.tags.occ_percent::writebacks 0.477554 # Average percentage of cache occupancy 294system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000737 # Average percentage of cache occupancy 295system.cpu.l2cache.tags.occ_percent::cpu.data 0.467360 # Average percentage of cache occupancy 296system.cpu.l2cache.tags.occ_percent::total 0.945651 # Average percentage of cache occupancy 297system.cpu.l2cache.tags.occ_task_id_blocks::1024 29768 # Occupied blocks per task id 298system.cpu.l2cache.tags.age_task_id_blocks_1024::0 83 # Occupied blocks per task id 299system.cpu.l2cache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 300system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1082 # Occupied blocks per task id 301system.cpu.l2cache.tags.age_task_id_blocks_1024::3 1693 # Occupied blocks per task id 302system.cpu.l2cache.tags.age_task_id_blocks_1024::4 26880 # Occupied blocks per task id 303system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908447 # Percentage of cache occupancy per task id 304system.cpu.l2cache.tags.tag_accesses 106351328 # Number of tag accesses 305system.cpu.l2cache.tags.data_accesses 106351328 # Number of data accesses 306system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits 307system.cpu.l2cache.ReadReq_hits::cpu.data 6048805 # number of ReadReq hits 308system.cpu.l2cache.ReadReq_hits::total 6048827 # number of ReadReq hits 309system.cpu.l2cache.Writeback_hits::writebacks 3697418 # number of Writeback hits 310system.cpu.l2cache.Writeback_hits::total 3697418 # number of Writeback hits 311system.cpu.l2cache.ReadExReq_hits::cpu.data 1108273 # number of ReadExReq hits 312system.cpu.l2cache.ReadExReq_hits::total 1108273 # number of ReadExReq hits 313system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits 314system.cpu.l2cache.demand_hits::cpu.data 7157078 # number of demand (read+write) hits 315system.cpu.l2cache.demand_hits::total 7157100 # number of demand (read+write) hits 316system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits 317system.cpu.l2cache.overall_hits::cpu.data 7157078 # number of overall hits 318system.cpu.l2cache.overall_hits::total 7157100 # number of overall hits 319system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses 320system.cpu.l2cache.ReadReq_misses::cpu.data 1177282 # number of ReadReq misses 321system.cpu.l2cache.ReadReq_misses::total 1177898 # number of ReadReq misses 322system.cpu.l2cache.ReadExReq_misses::cpu.data 780876 # number of ReadExReq misses 323system.cpu.l2cache.ReadExReq_misses::total 780876 # number of ReadExReq misses 324system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses 325system.cpu.l2cache.demand_misses::cpu.data 1958158 # number of demand (read+write) misses 326system.cpu.l2cache.demand_misses::total 1958774 # number of demand (read+write) misses 327system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses 328system.cpu.l2cache.overall_misses::cpu.data 1958158 # number of overall misses 329system.cpu.l2cache.overall_misses::total 1958774 # number of overall misses 330system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32099000 # number of ReadReq miss cycles 331system.cpu.l2cache.ReadReq_miss_latency::cpu.data 61225555000 # number of ReadReq miss cycles 332system.cpu.l2cache.ReadReq_miss_latency::total 61257654000 # number of ReadReq miss cycles 333system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 40608829000 # number of ReadExReq miss cycles 334system.cpu.l2cache.ReadExReq_miss_latency::total 40608829000 # number of ReadExReq miss cycles 335system.cpu.l2cache.demand_miss_latency::cpu.inst 32099000 # number of demand (read+write) miss cycles 336system.cpu.l2cache.demand_miss_latency::cpu.data 101834384000 # number of demand (read+write) miss cycles 337system.cpu.l2cache.demand_miss_latency::total 101866483000 # number of demand (read+write) miss cycles 338system.cpu.l2cache.overall_miss_latency::cpu.inst 32099000 # number of overall miss cycles 339system.cpu.l2cache.overall_miss_latency::cpu.data 101834384000 # number of overall miss cycles 340system.cpu.l2cache.overall_miss_latency::total 101866483000 # number of overall miss cycles 341system.cpu.l2cache.ReadReq_accesses::cpu.inst 638 # number of ReadReq accesses(hits+misses) 342system.cpu.l2cache.ReadReq_accesses::cpu.data 7226087 # number of ReadReq accesses(hits+misses) 343system.cpu.l2cache.ReadReq_accesses::total 7226725 # number of ReadReq accesses(hits+misses) 344system.cpu.l2cache.Writeback_accesses::writebacks 3697418 # number of Writeback accesses(hits+misses) 345system.cpu.l2cache.Writeback_accesses::total 3697418 # number of Writeback accesses(hits+misses) 346system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889149 # number of ReadExReq accesses(hits+misses) 347system.cpu.l2cache.ReadExReq_accesses::total 1889149 # number of ReadExReq accesses(hits+misses) 348system.cpu.l2cache.demand_accesses::cpu.inst 638 # number of demand (read+write) accesses 349system.cpu.l2cache.demand_accesses::cpu.data 9115236 # number of demand (read+write) accesses 350system.cpu.l2cache.demand_accesses::total 9115874 # number of demand (read+write) accesses 351system.cpu.l2cache.overall_accesses::cpu.inst 638 # number of overall (read+write) accesses 352system.cpu.l2cache.overall_accesses::cpu.data 9115236 # number of overall (read+write) accesses 353system.cpu.l2cache.overall_accesses::total 9115874 # number of overall (read+write) accesses 354system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965517 # miss rate for ReadReq accesses 355system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses 356system.cpu.l2cache.ReadReq_miss_rate::total 0.162992 # miss rate for ReadReq accesses 357system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413348 # miss rate for ReadExReq accesses 358system.cpu.l2cache.ReadExReq_miss_rate::total 0.413348 # miss rate for ReadExReq accesses 359system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965517 # miss rate for demand accesses 360system.cpu.l2cache.demand_miss_rate::cpu.data 0.214823 # miss rate for demand accesses 361system.cpu.l2cache.demand_miss_rate::total 0.214875 # miss rate for demand accesses 362system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965517 # miss rate for overall accesses 363system.cpu.l2cache.overall_miss_rate::cpu.data 0.214823 # miss rate for overall accesses 364system.cpu.l2cache.overall_miss_rate::total 0.214875 # miss rate for overall accesses 365system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52108.766234 # average ReadReq miss latency 366system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52005.853313 # average ReadReq miss latency 367system.cpu.l2cache.ReadReq_avg_miss_latency::total 52005.907133 # average ReadReq miss latency 368system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52004.196569 # average ReadExReq miss latency 369system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52004.196569 # average ReadExReq miss latency 370system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency 371system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency 372system.cpu.l2cache.demand_avg_miss_latency::total 52005.225207 # average overall miss latency 373system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52108.766234 # average overall miss latency 374system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52005.192635 # average overall miss latency 375system.cpu.l2cache.overall_avg_miss_latency::total 52005.225207 # average overall miss latency 376system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 380system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 381system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 382system.cpu.l2cache.fast_writes 0 # number of fast writes performed 383system.cpu.l2cache.cache_copies 0 # number of cache copies performed 384system.cpu.l2cache.writebacks::writebacks 1017198 # number of writebacks 385system.cpu.l2cache.writebacks::total 1017198 # number of writebacks 386system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses 387system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177282 # number of ReadReq MSHR misses 388system.cpu.l2cache.ReadReq_mshr_misses::total 1177898 # number of ReadReq MSHR misses 389system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 780876 # number of ReadExReq MSHR misses 390system.cpu.l2cache.ReadExReq_mshr_misses::total 780876 # number of ReadExReq MSHR misses 391system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses 392system.cpu.l2cache.demand_mshr_misses::cpu.data 1958158 # number of demand (read+write) MSHR misses 393system.cpu.l2cache.demand_mshr_misses::total 1958774 # number of demand (read+write) MSHR misses 394system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses 395system.cpu.l2cache.overall_mshr_misses::cpu.data 1958158 # number of overall MSHR misses 396system.cpu.l2cache.overall_mshr_misses::total 1958774 # number of overall MSHR misses 397system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24707000 # number of ReadReq MSHR miss cycles 398system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 47098171000 # number of ReadReq MSHR miss cycles 399system.cpu.l2cache.ReadReq_mshr_miss_latency::total 47122878000 # number of ReadReq MSHR miss cycles 400system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 31238317000 # number of ReadExReq MSHR miss cycles 401system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 31238317000 # number of ReadExReq MSHR miss cycles 402system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24707000 # number of demand (read+write) MSHR miss cycles 403system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 78336488000 # number of demand (read+write) MSHR miss cycles 404system.cpu.l2cache.demand_mshr_miss_latency::total 78361195000 # number of demand (read+write) MSHR miss cycles 405system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24707000 # number of overall MSHR miss cycles 406system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 78336488000 # number of overall MSHR miss cycles 407system.cpu.l2cache.overall_mshr_miss_latency::total 78361195000 # number of overall MSHR miss cycles 408system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses 409system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses 410system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.162992 # mshr miss rate for ReadReq accesses 411system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413348 # mshr miss rate for ReadExReq accesses 412system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413348 # mshr miss rate for ReadExReq accesses 413system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses 414system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for demand accesses 415system.cpu.l2cache.demand_mshr_miss_rate::total 0.214875 # mshr miss rate for demand accesses 416system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses 417system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214823 # mshr miss rate for overall accesses 418system.cpu.l2cache.overall_mshr_miss_rate::total 0.214875 # mshr miss rate for overall accesses 419system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40108.766234 # average ReadReq mshr miss latency 420system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40005.853313 # average ReadReq mshr miss latency 421system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40005.907133 # average ReadReq mshr miss latency 422system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.196569 # average ReadExReq mshr miss latency 423system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40004.196569 # average ReadExReq mshr miss latency 424system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency 425system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency 426system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency 427system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40108.766234 # average overall mshr miss latency 428system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40005.192635 # average overall mshr miss latency 429system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40005.225207 # average overall mshr miss latency 430system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 431system.cpu.dcache.tags.replacements 9111140 # number of replacements 432system.cpu.dcache.tags.tagsinuse 4083.522356 # Cycle average of tags in use 433system.cpu.dcache.tags.total_refs 645855059 # Total number of references to valid blocks. 434system.cpu.dcache.tags.sampled_refs 9115236 # Sample count of references to valid blocks. 435system.cpu.dcache.tags.avg_refs 70.854453 # Average number of references to valid blocks. 436system.cpu.dcache.tags.warmup_cycle 25914401000 # Cycle when the warmup percentage was hit. 437system.cpu.dcache.tags.occ_blocks::cpu.data 4083.522356 # Average occupied blocks per requestor 438system.cpu.dcache.tags.occ_percent::cpu.data 0.996954 # Average percentage of cache occupancy 439system.cpu.dcache.tags.occ_percent::total 0.996954 # Average percentage of cache occupancy 440system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 441system.cpu.dcache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id 442system.cpu.dcache.tags.age_task_id_blocks_1024::1 1214 # Occupied blocks per task id 443system.cpu.dcache.tags.age_task_id_blocks_1024::2 2578 # Occupied blocks per task id 444system.cpu.dcache.tags.age_task_id_blocks_1024::3 146 # Occupied blocks per task id 445system.cpu.dcache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id 446system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 447system.cpu.dcache.tags.tag_accesses 1319055826 # Number of tag accesses 448system.cpu.dcache.tags.data_accesses 1319055826 # Number of data accesses 449system.cpu.dcache.ReadReq_hits::cpu.data 475158039 # number of ReadReq hits 450system.cpu.dcache.ReadReq_hits::total 475158039 # number of ReadReq hits 451system.cpu.dcache.WriteReq_hits::cpu.data 170696898 # number of WriteReq hits 452system.cpu.dcache.WriteReq_hits::total 170696898 # number of WriteReq hits 453system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 454system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 455system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 456system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 457system.cpu.dcache.demand_hits::cpu.data 645854937 # number of demand (read+write) hits 458system.cpu.dcache.demand_hits::total 645854937 # number of demand (read+write) hits 459system.cpu.dcache.overall_hits::cpu.data 645854937 # number of overall hits 460system.cpu.dcache.overall_hits::total 645854937 # number of overall hits 461system.cpu.dcache.ReadReq_misses::cpu.data 7226087 # number of ReadReq misses 462system.cpu.dcache.ReadReq_misses::total 7226087 # number of ReadReq misses 463system.cpu.dcache.WriteReq_misses::cpu.data 1889149 # number of WriteReq misses 464system.cpu.dcache.WriteReq_misses::total 1889149 # number of WriteReq misses 465system.cpu.dcache.demand_misses::cpu.data 9115236 # number of demand (read+write) misses 466system.cpu.dcache.demand_misses::total 9115236 # number of demand (read+write) misses 467system.cpu.dcache.overall_misses::cpu.data 9115236 # number of overall misses 468system.cpu.dcache.overall_misses::total 9115236 # number of overall misses 469system.cpu.dcache.ReadReq_miss_latency::cpu.data 143391866000 # number of ReadReq miss cycles 470system.cpu.dcache.ReadReq_miss_latency::total 143391866000 # number of ReadReq miss cycles 471system.cpu.dcache.WriteReq_miss_latency::cpu.data 57359006000 # number of WriteReq miss cycles 472system.cpu.dcache.WriteReq_miss_latency::total 57359006000 # number of WriteReq miss cycles 473system.cpu.dcache.demand_miss_latency::cpu.data 200750872000 # number of demand (read+write) miss cycles 474system.cpu.dcache.demand_miss_latency::total 200750872000 # number of demand (read+write) miss cycles 475system.cpu.dcache.overall_miss_latency::cpu.data 200750872000 # number of overall miss cycles 476system.cpu.dcache.overall_miss_latency::total 200750872000 # number of overall miss cycles 477system.cpu.dcache.ReadReq_accesses::cpu.data 482384126 # number of ReadReq accesses(hits+misses) 478system.cpu.dcache.ReadReq_accesses::total 482384126 # number of ReadReq accesses(hits+misses) 479system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 480system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 481system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 485system.cpu.dcache.demand_accesses::cpu.data 654970173 # number of demand (read+write) accesses 486system.cpu.dcache.demand_accesses::total 654970173 # number of demand (read+write) accesses 487system.cpu.dcache.overall_accesses::cpu.data 654970173 # number of overall (read+write) accesses 488system.cpu.dcache.overall_accesses::total 654970173 # number of overall (read+write) accesses 489system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.014980 # miss rate for ReadReq accesses 490system.cpu.dcache.ReadReq_miss_rate::total 0.014980 # miss rate for ReadReq accesses 491system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010946 # miss rate for WriteReq accesses 492system.cpu.dcache.WriteReq_miss_rate::total 0.010946 # miss rate for WriteReq accesses 493system.cpu.dcache.demand_miss_rate::cpu.data 0.013917 # miss rate for demand accesses 494system.cpu.dcache.demand_miss_rate::total 0.013917 # miss rate for demand accesses 495system.cpu.dcache.overall_miss_rate::cpu.data 0.013917 # miss rate for overall accesses 496system.cpu.dcache.overall_miss_rate::total 0.013917 # miss rate for overall accesses 497system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19843.639580 # average ReadReq miss latency 498system.cpu.dcache.ReadReq_avg_miss_latency::total 19843.639580 # average ReadReq miss latency 499system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30362.351514 # average WriteReq miss latency 500system.cpu.dcache.WriteReq_avg_miss_latency::total 30362.351514 # average WriteReq miss latency 501system.cpu.dcache.demand_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency 502system.cpu.dcache.demand_avg_miss_latency::total 22023.661483 # average overall miss latency 503system.cpu.dcache.overall_avg_miss_latency::cpu.data 22023.661483 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::total 22023.661483 # average overall miss latency 505system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 506system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 507system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 508system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 509system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 510system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 511system.cpu.dcache.fast_writes 0 # number of fast writes performed 512system.cpu.dcache.cache_copies 0 # number of cache copies performed 513system.cpu.dcache.writebacks::writebacks 3697418 # number of writebacks 514system.cpu.dcache.writebacks::total 3697418 # number of writebacks 515system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7226087 # number of ReadReq MSHR misses 516system.cpu.dcache.ReadReq_mshr_misses::total 7226087 # number of ReadReq MSHR misses 517system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889149 # number of WriteReq MSHR misses 518system.cpu.dcache.WriteReq_mshr_misses::total 1889149 # number of WriteReq MSHR misses 519system.cpu.dcache.demand_mshr_misses::cpu.data 9115236 # number of demand (read+write) MSHR misses 520system.cpu.dcache.demand_mshr_misses::total 9115236 # number of demand (read+write) MSHR misses 521system.cpu.dcache.overall_mshr_misses::cpu.data 9115236 # number of overall MSHR misses 522system.cpu.dcache.overall_mshr_misses::total 9115236 # number of overall MSHR misses 523system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 128939692000 # number of ReadReq MSHR miss cycles 524system.cpu.dcache.ReadReq_mshr_miss_latency::total 128939692000 # number of ReadReq MSHR miss cycles 525system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 53580708000 # number of WriteReq MSHR miss cycles 526system.cpu.dcache.WriteReq_mshr_miss_latency::total 53580708000 # number of WriteReq MSHR miss cycles 527system.cpu.dcache.demand_mshr_miss_latency::cpu.data 182520400000 # number of demand (read+write) MSHR miss cycles 528system.cpu.dcache.demand_mshr_miss_latency::total 182520400000 # number of demand (read+write) MSHR miss cycles 529system.cpu.dcache.overall_mshr_miss_latency::cpu.data 182520400000 # number of overall MSHR miss cycles 530system.cpu.dcache.overall_mshr_miss_latency::total 182520400000 # number of overall MSHR miss cycles 531system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014980 # mshr miss rate for ReadReq accesses 532system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014980 # mshr miss rate for ReadReq accesses 533system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010946 # mshr miss rate for WriteReq accesses 534system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010946 # mshr miss rate for WriteReq accesses 535system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for demand accesses 536system.cpu.dcache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses 537system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013917 # mshr miss rate for overall accesses 538system.cpu.dcache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses 539system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17843.639580 # average ReadReq mshr miss latency 540system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 17843.639580 # average ReadReq mshr miss latency 541system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28362.351514 # average WriteReq mshr miss latency 542system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 28362.351514 # average WriteReq mshr miss latency 543system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency 544system.cpu.dcache.demand_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency 545system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20023.661483 # average overall mshr miss latency 546system.cpu.dcache.overall_avg_mshr_miss_latency::total 20023.661483 # average overall mshr miss latency 547system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 548system.cpu.toL2Bus.throughput 342944519 # Throughput (bytes/s) 549system.cpu.toL2Bus.trans_dist::ReadReq 7226725 # Transaction distribution 550system.cpu.toL2Bus.trans_dist::ReadResp 7226725 # Transaction distribution 551system.cpu.toL2Bus.trans_dist::Writeback 3697418 # Transaction distribution 552system.cpu.toL2Bus.trans_dist::ReadExReq 1889149 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::ReadExResp 1889149 # Transaction distribution 554system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1276 # Packet count per connected master and slave (bytes) 555system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21927890 # Packet count per connected master and slave (bytes) 556system.cpu.toL2Bus.pkt_count::total 21929166 # Packet count per connected master and slave (bytes) 557system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 40832 # Cumulative packet size per connected master and slave (bytes) 558system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 820009856 # Cumulative packet size per connected master and slave (bytes) 559system.cpu.toL2Bus.tot_pkt_size::total 820050688 # Cumulative packet size per connected master and slave (bytes) 560system.cpu.toL2Bus.data_through_bus 820050688 # Total data (bytes) 561system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 562system.cpu.toL2Bus.reqLayer0.occupancy 10104064000 # Layer occupancy (ticks) 563system.cpu.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) 564system.cpu.toL2Bus.respLayer0.occupancy 957000 # Layer occupancy (ticks) 565system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 566system.cpu.toL2Bus.respLayer1.occupancy 13672854000 # Layer occupancy (ticks) 567system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) 568 569---------- End Simulation Statistics ----------