| config.ini (10038:7eccd14e2610) | config.ini (10315:9e02c14446bb) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System |
| 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain | 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain |
| 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= | 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= |
| 20kernel_addr_check=true |
|
| 20load_addr_mask=1099511627775 21load_offset=0 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= --- 4 unchanged lines hidden (view full) --- 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 | 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem 26num_work_ids=16 27readfile= 28symbolfile= --- 4 unchanged lines hidden (view full) --- 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 |
| 41domain_id=-1 |
|
| 40eventq_index=0 | 42eventq_index=0 |
| 43init_perf_level=0 |
|
| 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=TimingSimpleCPU 45children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload | 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=TimingSimpleCPU 48children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload |
| 49branchPred=Null |
|
| 46checker=Null 47clk_domain=system.cpu_clk_domain 48cpu_id=0 49do_checkpoint_insts=true 50do_quiesce=true 51do_statistics_insts=true 52dstage2_mmu=system.cpu.dstage2_mmu 53dtb=system.cpu.dtb --- 7 unchanged lines hidden (view full) --- 61max_insts_all_threads=0 62max_insts_any_thread=0 63max_loads_all_threads=0 64max_loads_any_thread=0 65numThreads=1 66profile=0 67progress_interval=0 68simpoint_start_insts= | 50checker=Null 51clk_domain=system.cpu_clk_domain 52cpu_id=0 53do_checkpoint_insts=true 54do_quiesce=true 55do_statistics_insts=true 56dstage2_mmu=system.cpu.dstage2_mmu 57dtb=system.cpu.dtb --- 7 unchanged lines hidden (view full) --- 65max_insts_all_threads=0 66max_insts_any_thread=0 67max_loads_all_threads=0 68max_loads_any_thread=0 69numThreads=1 70profile=0 71progress_interval=0 72simpoint_start_insts= |
| 73socket_id=0 |
|
| 69switched_out=false 70system=system 71tracer=system.cpu.tracer 72workload=system.cpu.workload 73dcache_port=system.cpu.dcache.cpu_side 74icache_port=system.cpu.icache.cpu_side 75 76[system.cpu.dcache] --- 235 unchanged lines hidden (view full) --- 312type=LiveProcess 313cmd=bzip2 input.source 1 314cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing 315egid=100 316env= 317errout=cerr 318euid=100 319eventq_index=0 | 74switched_out=false 75system=system 76tracer=system.cpu.tracer 77workload=system.cpu.workload 78dcache_port=system.cpu.dcache.cpu_side 79icache_port=system.cpu.icache.cpu_side 80 81[system.cpu.dcache] --- 235 unchanged lines hidden (view full) --- 317type=LiveProcess 318cmd=bzip2 input.source 1 319cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing 320egid=100 321env= 322errout=cerr 323euid=100 324eventq_index=0 |
| 320executable=/dist/cpu2000/binaries/arm/linux/bzip2 | 325executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2 |
| 321gid=100 322input=cin 323max_stack_size=67108864 324output=cout 325pid=100 326ppid=99 327simpoint=0 328system=system 329uid=100 330 331[system.cpu_clk_domain] 332type=SrcClockDomain 333clock=500 | 326gid=100 327input=cin 328max_stack_size=67108864 329output=cout 330pid=100 331ppid=99 332simpoint=0 333system=system 334uid=100 335 336[system.cpu_clk_domain] 337type=SrcClockDomain 338clock=500 |
| 339domain_id=-1 |
|
| 334eventq_index=0 | 340eventq_index=0 |
| 341init_perf_level=0 |
|
| 335voltage_domain=system.voltage_domain 336 | 342voltage_domain=system.voltage_domain 343 |
| 344[system.dvfs_handler] 345type=DVFSHandler 346domains= 347enable=false 348eventq_index=0 349sys_clk_domain=system.clk_domain 350transition_latency=100000000 351 |
|
| 337[system.membus] 338type=CoherentBus 339clk_domain=system.clk_domain 340eventq_index=0 341header_cycles=1 342system=system 343use_default_range=false 344width=8 --- 21 unchanged lines hidden --- | 352[system.membus] 353type=CoherentBus 354clk_domain=system.clk_domain 355eventq_index=0 356header_cycles=1 357system=system 358use_default_range=false 359width=8 --- 21 unchanged lines hidden --- |