1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.832017 # Number of seconds simulated 4sim_ticks 832017490500 # Number of ticks simulated 5final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2178592 # Simulator instruction rate (inst/s) 8host_op_rate 2347103 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1173553065 # Simulator tick rate (ticks/s) 10host_mem_usage 260024 # Number of bytes of host memory used 11host_seconds 708.97 # Real time elapsed on the host 12sim_insts 1544563042 # Number of instructions simulated 13sim_ops 1664032434 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory 19system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory 23system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory 27system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s) 39system.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 40system.cpu_clk_domain.clock 500 # Clock period in ticks 41system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 42system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 53system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 54system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 55system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 62system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 63system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 67system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 71system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 72system.cpu.dtb.walker.walks 0 # Table walker walks requested 73system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.inst_hits 0 # ITB inst hits 81system.cpu.dtb.inst_misses 0 # ITB inst misses 82system.cpu.dtb.read_hits 0 # DTB read hits 83system.cpu.dtb.read_misses 0 # DTB read misses 84system.cpu.dtb.write_hits 0 # DTB write hits 85system.cpu.dtb.write_misses 0 # DTB write misses 86system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 87system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 88system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 89system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 90system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 91system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 92system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 93system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 94system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95system.cpu.dtb.read_accesses 0 # DTB read accesses 96system.cpu.dtb.write_accesses 0 # DTB write accesses 97system.cpu.dtb.inst_accesses 0 # ITB inst accesses 98system.cpu.dtb.hits 0 # DTB hits 99system.cpu.dtb.misses 0 # DTB misses 100system.cpu.dtb.accesses 0 # DTB accesses 101system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 102system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 111system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 112system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 113system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 114system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 115system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 116system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 121system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 122system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 123system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 131system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 132system.cpu.itb.walker.walks 0 # Table walker walks requested 133system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.inst_hits 0 # ITB inst hits 141system.cpu.itb.inst_misses 0 # ITB inst misses 142system.cpu.itb.read_hits 0 # DTB read hits 143system.cpu.itb.read_misses 0 # DTB read misses 144system.cpu.itb.write_hits 0 # DTB write hits 145system.cpu.itb.write_misses 0 # DTB write misses 146system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 147system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 149system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 150system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 151system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.itb.read_accesses 0 # DTB read accesses 156system.cpu.itb.write_accesses 0 # DTB write accesses 157system.cpu.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.itb.hits 0 # DTB hits 159system.cpu.itb.misses 0 # DTB misses 160system.cpu.itb.accesses 0 # DTB accesses
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.832017 # Number of seconds simulated 4sim_ticks 832017490500 # Number of ticks simulated 5final_tick 832017490500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 2178592 # Simulator instruction rate (inst/s) 8host_op_rate 2347103 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1173553065 # Simulator tick rate (ticks/s) 10host_mem_usage 260024 # Number of bytes of host memory used 11host_seconds 708.97 # Real time elapsed on the host 12sim_insts 1544563042 # Number of instructions simulated 13sim_ops 1664032434 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 6178262360 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory 19system.physmem.bytes_read::total 7759650031 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 6178262360 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 6178262360 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory 23system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1544565590 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 1999474787 # Number of read requests responded to by this memory 27system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 1900666379 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 9326306381 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 2650840984 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 10076480986 # Total bandwidth to/from this memory (bytes/s) 39system.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 40system.cpu_clk_domain.clock 500 # Clock period in ticks 41system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 42system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 53system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 54system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 55system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 56system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 57system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 59system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 60system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 62system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 63system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 67system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 71system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 72system.cpu.dtb.walker.walks 0 # Table walker walks requested 73system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 76system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 77system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 78system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 79system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 80system.cpu.dtb.inst_hits 0 # ITB inst hits 81system.cpu.dtb.inst_misses 0 # ITB inst misses 82system.cpu.dtb.read_hits 0 # DTB read hits 83system.cpu.dtb.read_misses 0 # DTB read misses 84system.cpu.dtb.write_hits 0 # DTB write hits 85system.cpu.dtb.write_misses 0 # DTB write misses 86system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 87system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 88system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 89system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 90system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 91system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 92system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 93system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 94system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95system.cpu.dtb.read_accesses 0 # DTB read accesses 96system.cpu.dtb.write_accesses 0 # DTB write accesses 97system.cpu.dtb.inst_accesses 0 # ITB inst accesses 98system.cpu.dtb.hits 0 # DTB hits 99system.cpu.dtb.misses 0 # DTB misses 100system.cpu.dtb.accesses 0 # DTB accesses 101system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 102system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 110system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 111system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 112system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 113system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 114system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 115system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 116system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 121system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 122system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 123system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 131system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 832017490500 # Cumulative time (in ticks) in various power states 132system.cpu.itb.walker.walks 0 # Table walker walks requested 133system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 140system.cpu.itb.inst_hits 0 # ITB inst hits 141system.cpu.itb.inst_misses 0 # ITB inst misses 142system.cpu.itb.read_hits 0 # DTB read hits 143system.cpu.itb.read_misses 0 # DTB read misses 144system.cpu.itb.write_hits 0 # DTB write hits 145system.cpu.itb.write_misses 0 # DTB write misses 146system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 147system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 149system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 150system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 151system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.itb.read_accesses 0 # DTB read accesses 156system.cpu.itb.write_accesses 0 # DTB write accesses 157system.cpu.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.itb.hits 0 # DTB hits 159system.cpu.itb.misses 0 # DTB misses 160system.cpu.itb.accesses 0 # DTB accesses
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