Cross Reference: /gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt

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stats.txt (10352:5f1f92bf76ee)	stats.txt (10409:8c80b91944c5)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.832017 # Number of seconds simulated 4sim_ticks 832017490000 # Number of ticks simulated 5final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.832017 # Number of seconds simulated 4sim_ticks 832017490000 # Number of ticks simulated 5final_tick 832017490000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 1782051 # Simulator instruction rate (inst/s) 8host_op_rate 1919890 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 959946236 # Simulator tick rate (ticks/s) 10host_mem_usage 306272 # Number of bytes of host memory used 11host_seconds 866.73 # Real time elapsed on the host	7host_inst_rate 2048371 # Simulator instruction rate (inst/s) 8host_op_rate 2206809 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1103406177 # Simulator tick rate (ticks/s) 10host_mem_usage 296712 # Number of bytes of host memory used 11host_seconds 754.04 # Real time elapsed on the host
12sim_insts 1544563041 # Number of instructions simulated 13sim_ops 1664032433 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory 18system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 6178262356 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 6178262356 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory 22system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1999474786 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1900666380 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 9326306382 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s)	12sim_insts 1544563041 # Number of instructions simulated 13sim_ops 1664032433 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 6178262356 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 1581387671 # Number of bytes read from this memory 18system.physmem.bytes_read::total 7759650027 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 6178262356 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 6178262356 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 624158392 # Number of bytes written to this memory 22system.physmem.bytes_written::total 624158392 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 1544565589 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 454909197 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 1999474786 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 172586108 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 172586108 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 7425640002 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1900666380 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 9326306382 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 7425640002 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 7425640002 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 750174605 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 750174605 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 7425640002 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 2650840985 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 10076480987 # Total bandwidth to/from this memory (bytes/s)
38system.membus.throughput 10076480987 # Throughput (bytes/s) 39system.membus.data_through_bus 8383808419 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)	38system.membus.trans_dist::ReadReq 1999474724 # Transaction distribution 39system.membus.trans_dist::ReadResp 1999474785 # Transaction distribution 40system.membus.trans_dist::WriteReq 172586047 # Transaction distribution 41system.membus.trans_dist::WriteResp 172586047 # Transaction distribution 42system.membus.trans_dist::SoftPFReq 1 # Transaction distribution 43system.membus.trans_dist::SoftPFResp 1 # Transaction distribution 44system.membus.trans_dist::LoadLockedReq 61 # Transaction distribution 45system.membus.trans_dist::StoreCondReq 61 # Transaction distribution 46system.membus.trans_dist::StoreCondResp 61 # Transaction distribution 47system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 3089131178 # Packet count per connected master and slave (bytes) 48system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 1254990610 # Packet count per connected master and slave (bytes) 49system.membus.pkt_count::total 4344121788 # Packet count per connected master and slave (bytes) 50system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 6178262356 # Cumulative packet size per connected master and slave (bytes) 51system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 2205546063 # Cumulative packet size per connected master and slave (bytes) 52system.membus.pkt_size::total 8383808419 # Cumulative packet size per connected master and slave (bytes) 53system.membus.snoops 0 # Total snoops (count) 54system.membus.snoop_fanout::samples 2172060894 # Request fanout histogram 55system.membus.snoop_fanout::mean 4.711106 # Request fanout histogram 56system.membus.snoop_fanout::stdev 0.453249 # Request fanout histogram 57system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 58system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 59system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 60system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 61system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 62system.membus.snoop_fanout::4 627495305 28.89% 28.89% # Request fanout histogram 63system.membus.snoop_fanout::5 1544565589 71.11% 100.00% # Request fanout histogram 64system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 65system.membus.snoop_fanout::min_value 4 # Request fanout histogram 66system.membus.snoop_fanout::max_value 5 # Request fanout histogram 67system.membus.snoop_fanout::total 2172060894 # Request fanout histogram
41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 43system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 44system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 45system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 46system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 47system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 53system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 54system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 55system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 56system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 58system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 59system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 60system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 61system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 62system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 63system.cpu.dtb.inst_hits 0 # ITB inst hits 64system.cpu.dtb.inst_misses 0 # ITB inst misses 65system.cpu.dtb.read_hits 0 # DTB read hits 66system.cpu.dtb.read_misses 0 # DTB read misses 67system.cpu.dtb.write_hits 0 # DTB write hits 68system.cpu.dtb.write_misses 0 # DTB write misses 69system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 70system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 71system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 73system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 74system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 75system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 76system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 77system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 78system.cpu.dtb.read_accesses 0 # DTB read accesses 79system.cpu.dtb.write_accesses 0 # DTB write accesses 80system.cpu.dtb.inst_accesses 0 # ITB inst accesses 81system.cpu.dtb.hits 0 # DTB hits 82system.cpu.dtb.misses 0 # DTB misses 83system.cpu.dtb.accesses 0 # DTB accesses 84system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 85system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 86system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 87system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 88system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 89system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 90system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 91system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 92system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 93system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 94system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 95system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 96system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 97system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 98system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 99system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 100system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 101system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 102system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 103system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 104system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 105system.cpu.itb.inst_hits 0 # ITB inst hits 106system.cpu.itb.inst_misses 0 # ITB inst misses 107system.cpu.itb.read_hits 0 # DTB read hits 108system.cpu.itb.read_misses 0 # DTB read misses 109system.cpu.itb.write_hits 0 # DTB write hits 110system.cpu.itb.write_misses 0 # DTB write misses 111system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 113system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 114system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 115system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 116system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 117system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 118system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.itb.read_accesses 0 # DTB read accesses 121system.cpu.itb.write_accesses 0 # DTB write accesses 122system.cpu.itb.inst_accesses 0 # ITB inst accesses 123system.cpu.itb.hits 0 # DTB hits 124system.cpu.itb.misses 0 # DTB misses 125system.cpu.itb.accesses 0 # DTB accesses 126system.cpu.workload.num_syscalls 46 # Number of system calls 127system.cpu.numCycles 1664034981 # number of cpu cycles simulated 128system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 129system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 130system.cpu.committedInsts 1544563041 # Number of instructions committed 131system.cpu.committedOps 1664032433 # Number of ops (including micro ops) committed 132system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses 133system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 134system.cpu.num_func_calls 27330256 # number of times a function call or return occured 135system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls 136system.cpu.num_int_insts 1477900422 # number of integer instructions 137system.cpu.num_fp_insts 36 # number of float instructions 138system.cpu.num_int_register_reads 2605402942 # number of times the integer registers were read 139system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written 140system.cpu.num_fp_register_reads 24 # number of times the floating registers were read 141system.cpu.num_fp_register_writes 16 # number of times the floating registers were written 142system.cpu.num_cc_register_reads 4992096236 # number of times the CC registers were read 143system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written 144system.cpu.num_mem_refs 633153380 # number of memory refs 145system.cpu.num_load_insts 458306334 # Number of load instructions 146system.cpu.num_store_insts 174847046 # Number of store instructions 147system.cpu.num_idle_cycles 0 # Number of idle cycles 148system.cpu.num_busy_cycles 1664034981 # Number of busy cycles 149system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 150system.cpu.idle_fraction 0 # Percentage of idle cycles 151system.cpu.Branches 213462426 # Number of branches fetched 152system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 153system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction 154system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction 155system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction 156system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction 157system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction 158system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction 159system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction 160system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction 161system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction 162system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction 163system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction 164system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction 165system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction 166system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction 167system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction 168system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction 169system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction 170system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction 171system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction 172system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction 173system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction 174system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction 175system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction 176system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction 177system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction 178system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction 179system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction 180system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction 181system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction 182system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction 183system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction 184system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 185system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 186system.cpu.op_class::total 1664032480 # Class of executed instruction 187 188---------- End Simulation Statistics ----------	68system.cpu_clk_domain.clock 500 # Clock period in ticks 69system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 70system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 71system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 72system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 73system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 74system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 75system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 76system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 77system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 78system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 79system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 80system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 81system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 82system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 83system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 84system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 85system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 86system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 87system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 88system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 89system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 90system.cpu.dtb.inst_hits 0 # ITB inst hits 91system.cpu.dtb.inst_misses 0 # ITB inst misses 92system.cpu.dtb.read_hits 0 # DTB read hits 93system.cpu.dtb.read_misses 0 # DTB read misses 94system.cpu.dtb.write_hits 0 # DTB write hits 95system.cpu.dtb.write_misses 0 # DTB write misses 96system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 97system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 98system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 99system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 100system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 101system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 102system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 103system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 104system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 105system.cpu.dtb.read_accesses 0 # DTB read accesses 106system.cpu.dtb.write_accesses 0 # DTB write accesses 107system.cpu.dtb.inst_accesses 0 # ITB inst accesses 108system.cpu.dtb.hits 0 # DTB hits 109system.cpu.dtb.misses 0 # DTB misses 110system.cpu.dtb.accesses 0 # DTB accesses 111system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 112system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 113system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 114system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 115system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 116system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 117system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 118system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 119system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 120system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 121system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 122system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 123system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 124system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 125system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 126system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 127system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 128system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 129system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 130system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 131system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 132system.cpu.itb.inst_hits 0 # ITB inst hits 133system.cpu.itb.inst_misses 0 # ITB inst misses 134system.cpu.itb.read_hits 0 # DTB read hits 135system.cpu.itb.read_misses 0 # DTB read misses 136system.cpu.itb.write_hits 0 # DTB write hits 137system.cpu.itb.write_misses 0 # DTB write misses 138system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 139system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 140system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 141system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 142system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 143system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 144system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 145system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 146system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 147system.cpu.itb.read_accesses 0 # DTB read accesses 148system.cpu.itb.write_accesses 0 # DTB write accesses 149system.cpu.itb.inst_accesses 0 # ITB inst accesses 150system.cpu.itb.hits 0 # DTB hits 151system.cpu.itb.misses 0 # DTB misses 152system.cpu.itb.accesses 0 # DTB accesses 153system.cpu.workload.num_syscalls 46 # Number of system calls 154system.cpu.numCycles 1664034981 # number of cpu cycles simulated 155system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 156system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 157system.cpu.committedInsts 1544563041 # Number of instructions committed 158system.cpu.committedOps 1664032433 # Number of ops (including micro ops) committed 159system.cpu.num_int_alu_accesses 1477900422 # Number of integer alu accesses 160system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses 161system.cpu.num_func_calls 27330256 # number of times a function call or return occured 162system.cpu.num_conditional_control_insts 167612489 # number of instructions that are conditional controls 163system.cpu.num_int_insts 1477900422 # number of integer instructions 164system.cpu.num_fp_insts 36 # number of float instructions 165system.cpu.num_int_register_reads 2605402942 # number of times the integer registers were read 166system.cpu.num_int_register_writes 1125475224 # number of times the integer registers were written 167system.cpu.num_fp_register_reads 24 # number of times the floating registers were read 168system.cpu.num_fp_register_writes 16 # number of times the floating registers were written 169system.cpu.num_cc_register_reads 4992096236 # number of times the CC registers were read 170system.cpu.num_cc_register_writes 518236214 # number of times the CC registers were written 171system.cpu.num_mem_refs 633153380 # number of memory refs 172system.cpu.num_load_insts 458306334 # Number of load instructions 173system.cpu.num_store_insts 174847046 # Number of store instructions 174system.cpu.num_idle_cycles 0 # Number of idle cycles 175system.cpu.num_busy_cycles 1664034981 # Number of busy cycles 176system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 177system.cpu.idle_fraction 0 # Percentage of idle cycles 178system.cpu.Branches 213462426 # Number of branches fetched 179system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 180system.cpu.op_class::IntAlu 1030178775 61.91% 61.91% # Class of executed instruction 181system.cpu.op_class::IntMult 700322 0.04% 61.95% # Class of executed instruction 182system.cpu.op_class::IntDiv 0 0.00% 61.95% # Class of executed instruction 183system.cpu.op_class::FloatAdd 0 0.00% 61.95% # Class of executed instruction 184system.cpu.op_class::FloatCmp 0 0.00% 61.95% # Class of executed instruction 185system.cpu.op_class::FloatCvt 0 0.00% 61.95% # Class of executed instruction 186system.cpu.op_class::FloatMult 0 0.00% 61.95% # Class of executed instruction 187system.cpu.op_class::FloatDiv 0 0.00% 61.95% # Class of executed instruction 188system.cpu.op_class::FloatSqrt 0 0.00% 61.95% # Class of executed instruction 189system.cpu.op_class::SimdAdd 0 0.00% 61.95% # Class of executed instruction 190system.cpu.op_class::SimdAddAcc 0 0.00% 61.95% # Class of executed instruction 191system.cpu.op_class::SimdAlu 0 0.00% 61.95% # Class of executed instruction 192system.cpu.op_class::SimdCmp 0 0.00% 61.95% # Class of executed instruction 193system.cpu.op_class::SimdCvt 0 0.00% 61.95% # Class of executed instruction 194system.cpu.op_class::SimdMisc 0 0.00% 61.95% # Class of executed instruction 195system.cpu.op_class::SimdMult 0 0.00% 61.95% # Class of executed instruction 196system.cpu.op_class::SimdMultAcc 0 0.00% 61.95% # Class of executed instruction 197system.cpu.op_class::SimdShift 0 0.00% 61.95% # Class of executed instruction 198system.cpu.op_class::SimdShiftAcc 0 0.00% 61.95% # Class of executed instruction 199system.cpu.op_class::SimdSqrt 0 0.00% 61.95% # Class of executed instruction 200system.cpu.op_class::SimdFloatAdd 0 0.00% 61.95% # Class of executed instruction 201system.cpu.op_class::SimdFloatAlu 0 0.00% 61.95% # Class of executed instruction 202system.cpu.op_class::SimdFloatCmp 0 0.00% 61.95% # Class of executed instruction 203system.cpu.op_class::SimdFloatCvt 0 0.00% 61.95% # Class of executed instruction 204system.cpu.op_class::SimdFloatDiv 0 0.00% 61.95% # Class of executed instruction 205system.cpu.op_class::SimdFloatMisc 3 0.00% 61.95% # Class of executed instruction 206system.cpu.op_class::SimdFloatMult 0 0.00% 61.95% # Class of executed instruction 207system.cpu.op_class::SimdFloatMultAcc 0 0.00% 61.95% # Class of executed instruction 208system.cpu.op_class::SimdFloatSqrt 0 0.00% 61.95% # Class of executed instruction 209system.cpu.op_class::MemRead 458306334 27.54% 89.49% # Class of executed instruction 210system.cpu.op_class::MemWrite 174847046 10.51% 100.00% # Class of executed instruction 211system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 212system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 213system.cpu.op_class::total 1664032480 # Class of executed instruction 214 215---------- End Simulation Statistics ----------