| stats.txt (9978:81d7551dd3be) | stats.txt (9988:0b2e590c85be) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.533691 # Number of seconds simulated 4sim_ticks 533690503000 # Number of ticks simulated 5final_tick 533690503000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.533797 # Number of seconds simulated 4sim_ticks 533797009000 # Number of ticks simulated 5final_tick 533797009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 128085 # Simulator instruction rate (inst/s) 8host_op_rate 142888 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44256929 # Simulator tick rate (ticks/s) 10host_mem_usage 275676 # Number of bytes of host memory used 11host_seconds 12058.91 # Real time elapsed on the host | 7host_inst_rate 102910 # Simulator instruction rate (inst/s) 8host_op_rate 114803 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 35565366 # Simulator tick rate (ticks/s) 10host_mem_usage 295220 # Number of bytes of host memory used 11host_seconds 15008.90 # Real time elapsed on the host |
| 12sim_insts 1544563023 # Number of instructions simulated 13sim_ops 1723073835 # Number of ops (including micro ops) simulated | 12sim_insts 1544563023 # Number of instructions simulated 13sim_ops 1723073835 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 143713600 # Number of bytes read from this memory 16system.physmem.bytes_read::total 143761344 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 70434112 # Number of bytes written to this memory 20system.physmem.bytes_written::total 70434112 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2245525 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2246271 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1100533 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1100533 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 89460 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 269282663 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 269372123 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 89460 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 89460 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 131975577 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 131975577 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 131975577 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 89460 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 269282663 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 401347700 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 2246271 # Number of read requests accepted 38system.physmem.writeReqs 1100533 # Number of write requests accepted 39system.physmem.readBursts 2246271 # Number of DRAM read bursts, including those serviced by the write queue 40system.physmem.writeBursts 1100533 # Number of DRAM write bursts, including those merged in the write queue 41system.physmem.bytesReadDRAM 143722048 # Total number of bytes read from DRAM 42system.physmem.bytesReadWrQ 39296 # Total number of bytes read from write queue 43system.physmem.bytesWritten 70432960 # Total number of bytes written to DRAM 44system.physmem.bytesReadSys 143761344 # Total read bytes from the system interface side 45system.physmem.bytesWrittenSys 70434112 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 614 # Number of DRAM read bursts serviced by the write queue | 14system.physmem.bytes_read::cpu.inst 47680 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 143743296 # Number of bytes read from this memory 16system.physmem.bytes_read::total 143790976 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 47680 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 47680 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 70431872 # Number of bytes written to this memory 20system.physmem.bytes_written::total 70431872 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 745 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2245989 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2246734 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1100498 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1100498 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 89322 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 269284566 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 269373889 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 89322 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 89322 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 131945048 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 131945048 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 131945048 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 89322 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 269284566 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 401318937 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 2246734 # Number of read requests accepted 38system.physmem.writeReqs 1100498 # Number of write requests accepted 39system.physmem.readBursts 2246734 # Number of DRAM read bursts, including those serviced by the write queue 40system.physmem.writeBursts 1100498 # Number of DRAM write bursts, including those merged in the write queue 41system.physmem.bytesReadDRAM 143754112 # Total number of bytes read from DRAM 42system.physmem.bytesReadWrQ 36864 # Total number of bytes read from write queue 43system.physmem.bytesWritten 70430784 # Total number of bytes written to DRAM 44system.physmem.bytesReadSys 143790976 # Total read bytes from the system interface side 45system.physmem.bytesWrittenSys 70431872 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by the write queue |
| 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 49system.physmem.perBankRdBursts::0 139609 # Per bank write bursts 50system.physmem.perBankRdBursts::1 136206 # Per bank write bursts 51system.physmem.perBankRdBursts::2 133832 # Per bank write bursts 52system.physmem.perBankRdBursts::3 136344 # Per bank write bursts 53system.physmem.perBankRdBursts::4 135019 # Per bank write bursts 54system.physmem.perBankRdBursts::5 135288 # Per bank write bursts 55system.physmem.perBankRdBursts::6 136231 # Per bank write bursts 56system.physmem.perBankRdBursts::7 136121 # Per bank write bursts 57system.physmem.perBankRdBursts::8 143692 # Per bank write bursts 58system.physmem.perBankRdBursts::9 146373 # Per bank write bursts 59system.physmem.perBankRdBursts::10 144432 # Per bank write bursts 60system.physmem.perBankRdBursts::11 146294 # Per bank write bursts 61system.physmem.perBankRdBursts::12 145666 # Per bank write bursts 62system.physmem.perBankRdBursts::13 146070 # Per bank write bursts 63system.physmem.perBankRdBursts::14 142065 # Per bank write bursts 64system.physmem.perBankRdBursts::15 142415 # Per bank write bursts 65system.physmem.perBankWrBursts::0 69121 # Per bank write bursts 66system.physmem.perBankWrBursts::1 67439 # Per bank write bursts 67system.physmem.perBankWrBursts::2 65729 # Per bank write bursts 68system.physmem.perBankWrBursts::3 66294 # Per bank write bursts 69system.physmem.perBankWrBursts::4 66241 # Per bank write bursts 70system.physmem.perBankWrBursts::5 66403 # Per bank write bursts 71system.physmem.perBankWrBursts::6 67965 # Per bank write bursts 72system.physmem.perBankWrBursts::7 68773 # Per bank write bursts 73system.physmem.perBankWrBursts::8 70328 # Per bank write bursts 74system.physmem.perBankWrBursts::9 70962 # Per bank write bursts 75system.physmem.perBankWrBursts::10 70540 # Per bank write bursts 76system.physmem.perBankWrBursts::11 70927 # Per bank write bursts 77system.physmem.perBankWrBursts::12 70302 # Per bank write bursts 78system.physmem.perBankWrBursts::13 70806 # Per bank write bursts 79system.physmem.perBankWrBursts::14 69598 # Per bank write bursts 80system.physmem.perBankWrBursts::15 69087 # Per bank write bursts | 49system.physmem.perBankRdBursts::0 139750 # Per bank write bursts 50system.physmem.perBankRdBursts::1 136273 # Per bank write bursts 51system.physmem.perBankRdBursts::2 133708 # Per bank write bursts 52system.physmem.perBankRdBursts::3 136246 # Per bank write bursts 53system.physmem.perBankRdBursts::4 134906 # Per bank write bursts 54system.physmem.perBankRdBursts::5 135253 # Per bank write bursts 55system.physmem.perBankRdBursts::6 136175 # Per bank write bursts 56system.physmem.perBankRdBursts::7 136295 # Per bank write bursts 57system.physmem.perBankRdBursts::8 143732 # Per bank write bursts 58system.physmem.perBankRdBursts::9 146555 # Per bank write bursts 59system.physmem.perBankRdBursts::10 144302 # Per bank write bursts 60system.physmem.perBankRdBursts::11 146237 # Per bank write bursts 61system.physmem.perBankRdBursts::12 145788 # Per bank write bursts 62system.physmem.perBankRdBursts::13 146277 # Per bank write bursts 63system.physmem.perBankRdBursts::14 142119 # Per bank write bursts 64system.physmem.perBankRdBursts::15 142542 # Per bank write bursts 65system.physmem.perBankWrBursts::0 69128 # Per bank write bursts 66system.physmem.perBankWrBursts::1 67452 # Per bank write bursts 67system.physmem.perBankWrBursts::2 65650 # Per bank write bursts 68system.physmem.perBankWrBursts::3 66298 # Per bank write bursts 69system.physmem.perBankWrBursts::4 66182 # Per bank write bursts 70system.physmem.perBankWrBursts::5 66379 # Per bank write bursts 71system.physmem.perBankWrBursts::6 67939 # Per bank write bursts 72system.physmem.perBankWrBursts::7 68869 # Per bank write bursts 73system.physmem.perBankWrBursts::8 70353 # Per bank write bursts 74system.physmem.perBankWrBursts::9 70986 # Per bank write bursts 75system.physmem.perBankWrBursts::10 70505 # Per bank write bursts 76system.physmem.perBankWrBursts::11 70955 # Per bank write bursts 77system.physmem.perBankWrBursts::12 70250 # Per bank write bursts 78system.physmem.perBankWrBursts::13 70819 # Per bank write bursts 79system.physmem.perBankWrBursts::14 69624 # Per bank write bursts 80system.physmem.perBankWrBursts::15 69092 # Per bank write bursts |
| 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry | 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| 82system.physmem.numWrRetry 1 # Number of times write queue was full causing retry 83system.physmem.totGap 533690432500 # Total gap between requests | 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 83system.physmem.totGap 533796944500 # Total gap between requests |
| 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) | 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 90system.physmem.readPktSize::6 2246271 # Read request sizes (log2) | 90system.physmem.readPktSize::6 2246734 # Read request sizes (log2) |
| 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) | 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 97system.physmem.writePktSize::6 1100533 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 1620463 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 446151 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 135620 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 43412 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 10 # What read queue length does an incoming req see | 97system.physmem.writePktSize::6 1100498 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 1621551 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::1 445207 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 135727 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 43660 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 122system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 103system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 122system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 130system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::1 49049 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::2 49091 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::3 49066 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::4 49073 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::5 49089 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::6 49084 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::7 49051 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::8 49094 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::9 49119 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::10 49113 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::11 49182 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::12 49203 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::13 49260 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::14 49489 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::15 49964 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::16 50324 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::17 52085 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::18 51901 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::19 51517 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::20 52884 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::21 52174 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::22 2402 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::23 373 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::24 43 # What write queue length does an incoming req see | 130system.physmem.wrQLenPdf::0 48879 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::1 49064 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::2 49063 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::3 49078 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::4 49086 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::5 49106 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::6 49070 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::7 49088 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::8 49113 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::9 49112 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::10 49119 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::11 49167 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::12 49186 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::13 49268 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::14 49533 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::15 49888 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::16 50325 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::17 52053 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::18 51988 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::19 51535 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::20 52936 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::21 52147 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::22 2310 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::23 336 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see |
| 155system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see | 155system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see |
| 156system.physmem.wrQLenPdf::26 4 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::27 3 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::28 2 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::31 3 # What write queue length does an incoming req see 162system.physmem.bytesPerActivate::samples 2077885 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::mean 103.053834 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::gmean 79.951836 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::stdev 184.653120 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::64-65 1660855 79.93% 79.93% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::128-129 226890 10.92% 90.85% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::192-193 69105 3.33% 94.18% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::256-257 37676 1.81% 95.99% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::320-321 25011 1.20% 97.19% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::384-385 12112 0.58% 97.77% # Bytes accessed per row activation | 156system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 162system.physmem.bytesPerActivate::samples 2077673 # Bytes accessed per row activation 163system.physmem.bytesPerActivate::mean 103.074669 # Bytes accessed per row activation 164system.physmem.bytesPerActivate::gmean 79.977753 # Bytes accessed per row activation 165system.physmem.bytesPerActivate::stdev 184.400722 # Bytes accessed per row activation 166system.physmem.bytesPerActivate::64-65 1659880 79.89% 79.89% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::128-129 227444 10.95% 90.84% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::192-193 69322 3.34% 94.17% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::256-257 37684 1.81% 95.99% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::320-321 24960 1.20% 97.19% # Bytes accessed per row activation 171system.physmem.bytesPerActivate::384-385 12074 0.58% 97.77% # Bytes accessed per row activation |
| 172system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation | 172system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation |
| 173system.physmem.bytesPerActivate::512-513 8103 0.39% 98.56% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::576-577 4494 0.22% 98.78% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::640-641 3425 0.16% 98.94% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::704-705 2747 0.13% 99.08% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::768-769 2032 0.10% 99.17% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::832-833 1669 0.08% 99.25% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::896-897 1441 0.07% 99.32% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::960-961 1240 0.06% 99.38% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1024-1025 1051 0.05% 99.43% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1088-1089 987 0.05% 99.48% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1152-1153 902 0.04% 99.52% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1216-1217 711 0.03% 99.56% # Bytes accessed per row activation | 173system.physmem.bytesPerActivate::512-513 8168 0.39% 98.56% # Bytes accessed per row activation 174system.physmem.bytesPerActivate::576-577 4452 0.21% 98.78% # Bytes accessed per row activation 175system.physmem.bytesPerActivate::640-641 3374 0.16% 98.94% # Bytes accessed per row activation 176system.physmem.bytesPerActivate::704-705 2842 0.14% 99.08% # Bytes accessed per row activation 177system.physmem.bytesPerActivate::768-769 2038 0.10% 99.17% # Bytes accessed per row activation 178system.physmem.bytesPerActivate::832-833 1716 0.08% 99.26% # Bytes accessed per row activation 179system.physmem.bytesPerActivate::896-897 1451 0.07% 99.33% # Bytes accessed per row activation 180system.physmem.bytesPerActivate::960-961 1190 0.06% 99.38% # Bytes accessed per row activation 181system.physmem.bytesPerActivate::1024-1025 1071 0.05% 99.44% # Bytes accessed per row activation 182system.physmem.bytesPerActivate::1088-1089 949 0.05% 99.48% # Bytes accessed per row activation 183system.physmem.bytesPerActivate::1152-1153 909 0.04% 99.52% # Bytes accessed per row activation 184system.physmem.bytesPerActivate::1216-1217 717 0.03% 99.56% # Bytes accessed per row activation |
| 185system.physmem.bytesPerActivate::1280-1281 682 0.03% 99.59% # Bytes accessed per row activation | 185system.physmem.bytesPerActivate::1280-1281 682 0.03% 99.59% # Bytes accessed per row activation |
| 186system.physmem.bytesPerActivate::1344-1345 694 0.03% 99.63% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1408-1409 3096 0.15% 99.77% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1472-1473 406 0.02% 99.79% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1536-1537 291 0.01% 99.81% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1600-1601 190 0.01% 99.82% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1664-1665 185 0.01% 99.83% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1728-1729 205 0.01% 99.84% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1792-1793 473 0.02% 99.86% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1856-1857 132 0.01% 99.86% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1920-1921 131 0.01% 99.87% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1984-1985 122 0.01% 99.88% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2048-2049 122 0.01% 99.88% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2112-2113 103 0.00% 99.89% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2176-2177 129 0.01% 99.89% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2240-2241 71 0.00% 99.90% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2304-2305 83 0.00% 99.90% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2368-2369 90 0.00% 99.91% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2432-2433 83 0.00% 99.91% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2496-2497 94 0.00% 99.91% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2560-2561 68 0.00% 99.92% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2624-2625 57 0.00% 99.92% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2688-2689 64 0.00% 99.92% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2752-2753 70 0.00% 99.93% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2816-2817 60 0.00% 99.93% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2880-2881 55 0.00% 99.93% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2944-2945 48 0.00% 99.93% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3008-3009 43 0.00% 99.94% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3072-3073 58 0.00% 99.94% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3136-3137 55 0.00% 99.94% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3200-3201 43 0.00% 99.94% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3264-3265 33 0.00% 99.95% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3328-3329 30 0.00% 99.95% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3392-3393 32 0.00% 99.95% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3456-3457 24 0.00% 99.95% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3520-3521 28 0.00% 99.95% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3584-3585 19 0.00% 99.95% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3648-3649 34 0.00% 99.95% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3712-3713 24 0.00% 99.96% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3776-3777 26 0.00% 99.96% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3840-3841 14 0.00% 99.96% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3904-3905 19 0.00% 99.96% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3968-3969 24 0.00% 99.96% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4032-4033 24 0.00% 99.96% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4096-4097 17 0.00% 99.96% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4160-4161 19 0.00% 99.96% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4224-4225 19 0.00% 99.96% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4288-4289 21 0.00% 99.96% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4352-4353 13 0.00% 99.96% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4416-4417 17 0.00% 99.97% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4544-4545 21 0.00% 99.97% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4608-4609 12 0.00% 99.97% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4672-4673 20 0.00% 99.97% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4736-4737 12 0.00% 99.97% # Bytes accessed per row activation | 186system.physmem.bytesPerActivate::1344-1345 676 0.03% 99.62% # Bytes accessed per row activation 187system.physmem.bytesPerActivate::1408-1409 3081 0.15% 99.77% # Bytes accessed per row activation 188system.physmem.bytesPerActivate::1472-1473 420 0.02% 99.79% # Bytes accessed per row activation 189system.physmem.bytesPerActivate::1536-1537 289 0.01% 99.81% # Bytes accessed per row activation 190system.physmem.bytesPerActivate::1600-1601 203 0.01% 99.82% # Bytes accessed per row activation 191system.physmem.bytesPerActivate::1664-1665 186 0.01% 99.83% # Bytes accessed per row activation 192system.physmem.bytesPerActivate::1728-1729 219 0.01% 99.84% # Bytes accessed per row activation 193system.physmem.bytesPerActivate::1792-1793 499 0.02% 99.86% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.87% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::1920-1921 143 0.01% 99.87% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::1984-1985 125 0.01% 99.88% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::2048-2049 127 0.01% 99.89% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::2112-2113 94 0.00% 99.89% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::2176-2177 128 0.01% 99.90% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::2240-2241 92 0.00% 99.90% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::2304-2305 97 0.00% 99.91% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::2368-2369 82 0.00% 99.91% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::2432-2433 82 0.00% 99.91% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::2496-2497 62 0.00% 99.92% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::2560-2561 59 0.00% 99.92% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::2624-2625 52 0.00% 99.92% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::2688-2689 72 0.00% 99.93% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::2752-2753 47 0.00% 99.93% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::2816-2817 62 0.00% 99.93% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::2880-2881 51 0.00% 99.93% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::2944-2945 51 0.00% 99.94% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::3008-3009 39 0.00% 99.94% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::3072-3073 48 0.00% 99.94% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::3136-3137 40 0.00% 99.94% # Bytes accessed per row activation 215system.physmem.bytesPerActivate::3200-3201 42 0.00% 99.94% # Bytes accessed per row activation 216system.physmem.bytesPerActivate::3264-3265 28 0.00% 99.94% # Bytes accessed per row activation 217system.physmem.bytesPerActivate::3328-3329 34 0.00% 99.95% # Bytes accessed per row activation 218system.physmem.bytesPerActivate::3392-3393 28 0.00% 99.95% # Bytes accessed per row activation 219system.physmem.bytesPerActivate::3456-3457 44 0.00% 99.95% # Bytes accessed per row activation 220system.physmem.bytesPerActivate::3520-3521 23 0.00% 99.95% # Bytes accessed per row activation 221system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation 222system.physmem.bytesPerActivate::3648-3649 29 0.00% 99.95% # Bytes accessed per row activation 223system.physmem.bytesPerActivate::3712-3713 27 0.00% 99.96% # Bytes accessed per row activation 224system.physmem.bytesPerActivate::3776-3777 28 0.00% 99.96% # Bytes accessed per row activation 225system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.96% # Bytes accessed per row activation 226system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation 227system.physmem.bytesPerActivate::3968-3969 28 0.00% 99.96% # Bytes accessed per row activation 228system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.96% # Bytes accessed per row activation 229system.physmem.bytesPerActivate::4096-4097 19 0.00% 99.96% # Bytes accessed per row activation 230system.physmem.bytesPerActivate::4160-4161 9 0.00% 99.96% # Bytes accessed per row activation 231system.physmem.bytesPerActivate::4224-4225 25 0.00% 99.96% # Bytes accessed per row activation 232system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation 233system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation 234system.physmem.bytesPerActivate::4416-4417 18 0.00% 99.96% # Bytes accessed per row activation 235system.physmem.bytesPerActivate::4480-4481 18 0.00% 99.97% # Bytes accessed per row activation 236system.physmem.bytesPerActivate::4544-4545 19 0.00% 99.97% # Bytes accessed per row activation 237system.physmem.bytesPerActivate::4608-4609 22 0.00% 99.97% # Bytes accessed per row activation 238system.physmem.bytesPerActivate::4672-4673 11 0.00% 99.97% # Bytes accessed per row activation 239system.physmem.bytesPerActivate::4736-4737 34 0.00% 99.97% # Bytes accessed per row activation |
| 240system.physmem.bytesPerActivate::4800-4801 14 0.00% 99.97% # Bytes accessed per row activation | 240system.physmem.bytesPerActivate::4800-4801 14 0.00% 99.97% # Bytes accessed per row activation |
| 241system.physmem.bytesPerActivate::4864-4865 13 0.00% 99.97% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4928-4929 16 0.00% 99.97% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4992-4993 16 0.00% 99.97% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5056-5057 27 0.00% 99.97% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5120-5121 36 0.00% 99.97% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5184-5185 17 0.00% 99.98% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5248-5249 14 0.00% 99.98% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5312-5313 16 0.00% 99.98% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5376-5377 187 0.01% 99.99% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5440-5441 3 0.00% 99.99% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5568-5569 8 0.00% 99.99% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5632-5633 2 0.00% 99.99% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5696-5697 12 0.00% 99.99% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5760-5761 7 0.00% 99.99% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation 257system.physmem.bytesPerActivate::5888-5889 1 0.00% 99.99% # Bytes accessed per row activation | 241system.physmem.bytesPerActivate::4864-4865 17 0.00% 99.97% # Bytes accessed per row activation 242system.physmem.bytesPerActivate::4928-4929 11 0.00% 99.97% # Bytes accessed per row activation 243system.physmem.bytesPerActivate::4992-4993 23 0.00% 99.97% # Bytes accessed per row activation 244system.physmem.bytesPerActivate::5056-5057 14 0.00% 99.97% # Bytes accessed per row activation 245system.physmem.bytesPerActivate::5120-5121 20 0.00% 99.97% # Bytes accessed per row activation 246system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.98% # Bytes accessed per row activation 247system.physmem.bytesPerActivate::5248-5249 17 0.00% 99.98% # Bytes accessed per row activation 248system.physmem.bytesPerActivate::5312-5313 15 0.00% 99.98% # Bytes accessed per row activation 249system.physmem.bytesPerActivate::5376-5377 185 0.01% 99.99% # Bytes accessed per row activation 250system.physmem.bytesPerActivate::5440-5441 4 0.00% 99.99% # Bytes accessed per row activation 251system.physmem.bytesPerActivate::5504-5505 13 0.00% 99.99% # Bytes accessed per row activation 252system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.99% # Bytes accessed per row activation 253system.physmem.bytesPerActivate::5696-5697 3 0.00% 99.99% # Bytes accessed per row activation 254system.physmem.bytesPerActivate::5760-5761 17 0.00% 99.99% # Bytes accessed per row activation 255system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.99% # Bytes accessed per row activation 256system.physmem.bytesPerActivate::5888-5889 2 0.00% 99.99% # Bytes accessed per row activation |
| 258system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation | 257system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation |
| 259system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6080-6081 9 0.00% 99.99% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6144-6145 3 0.00% 99.99% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6208-6209 13 0.00% 99.99% # Bytes accessed per row activation 263system.physmem.bytesPerActivate::6272-6273 6 0.00% 99.99% # Bytes accessed per row activation | 258system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.99% # Bytes accessed per row activation 259system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.99% # Bytes accessed per row activation 260system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.99% # Bytes accessed per row activation 261system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.99% # Bytes accessed per row activation 262system.physmem.bytesPerActivate::6272-6273 12 0.00% 99.99% # Bytes accessed per row activation |
| 264system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation | 263system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation |
| 265system.physmem.bytesPerActivate::6400-6401 5 0.00% 99.99% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6464-6465 1 0.00% 99.99% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6528-6529 4 0.00% 99.99% # Bytes accessed per row activation 268system.physmem.bytesPerActivate::6592-6593 9 0.00% 99.99% # Bytes accessed per row activation 269system.physmem.bytesPerActivate::6656-6657 34 0.00% 99.99% # Bytes accessed per row activation | 264system.physmem.bytesPerActivate::6400-6401 7 0.00% 99.99% # Bytes accessed per row activation 265system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.99% # Bytes accessed per row activation 266system.physmem.bytesPerActivate::6528-6529 16 0.00% 99.99% # Bytes accessed per row activation 267system.physmem.bytesPerActivate::6656-6657 38 0.00% 99.99% # Bytes accessed per row activation |
| 270system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation | 268system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation |
| 271system.physmem.bytesPerActivate::6784-6785 5 0.00% 99.99% # Bytes accessed per row activation 272system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation | 269system.physmem.bytesPerActivate::6784-6785 8 0.00% 99.99% # Bytes accessed per row activation 270system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.99% # Bytes accessed per row activation 271system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation |
| 273system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation 274system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation | 272system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation 273system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation |
| 275system.physmem.bytesPerActivate::7104-7105 1 0.00% 99.99% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7168-7169 26 0.00% 99.99% # Bytes accessed per row activation | 274system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.99% # Bytes accessed per row activation 275system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation 276system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.99% # Bytes accessed per row activation |
| 277system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation | 277system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation |
| 278system.physmem.bytesPerActivate::7424-7425 4 0.00% 99.99% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7552-7553 4 0.00% 100.00% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7616-7617 2 0.00% 100.00% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7680-7681 1 0.00% 100.00% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7808-7809 4 0.00% 100.00% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7872-7873 3 0.00% 100.00% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7936-7937 3 0.00% 100.00% # Bytes accessed per row activation 286system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation 287system.physmem.bytesPerActivate::8064-8065 2 0.00% 100.00% # Bytes accessed per row activation | 278system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation 279system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation 280system.physmem.bytesPerActivate::7552-7553 13 0.00% 100.00% # Bytes accessed per row activation 281system.physmem.bytesPerActivate::7680-7681 3 0.00% 100.00% # Bytes accessed per row activation 282system.physmem.bytesPerActivate::7744-7745 1 0.00% 100.00% # Bytes accessed per row activation 283system.physmem.bytesPerActivate::7808-7809 3 0.00% 100.00% # Bytes accessed per row activation 284system.physmem.bytesPerActivate::7872-7873 2 0.00% 100.00% # Bytes accessed per row activation 285system.physmem.bytesPerActivate::7936-7937 2 0.00% 100.00% # Bytes accessed per row activation |
| 288system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation | 286system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation |
| 289system.physmem.bytesPerActivate::8192-8193 83 0.00% 100.00% # Bytes accessed per row activation 290system.physmem.bytesPerActivate::total 2077885 # Bytes accessed per row activation 291system.physmem.totQLat 32824703500 # Total ticks spent queuing 292system.physmem.totMemAccLat 104040704750 # Total ticks spent from burst creation until serviced by the DRAM 293system.physmem.totBusLat 11228285000 # Total ticks spent in databus transfers 294system.physmem.totBankLat 59987716250 # Total ticks spent accessing banks 295system.physmem.avgQLat 14616.97 # Average queueing delay per DRAM burst 296system.physmem.avgBankLat 26712.77 # Average bank access latency per DRAM burst | 287system.physmem.bytesPerActivate::8192-8193 82 0.00% 100.00% # Bytes accessed per row activation 288system.physmem.bytesPerActivate::total 2077673 # Bytes accessed per row activation 289system.physmem.totQLat 32821468000 # Total ticks spent queuing 290system.physmem.totMemAccLat 104059554250 # Total ticks spent from burst creation until serviced by the DRAM 291system.physmem.totBusLat 11230790000 # Total ticks spent in databus transfers 292system.physmem.totBankLat 60007296250 # Total ticks spent accessing banks 293system.physmem.avgQLat 14612.27 # Average queueing delay per DRAM burst 294system.physmem.avgBankLat 26715.53 # Average bank access latency per DRAM burst |
| 297system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 295system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 298system.physmem.avgMemAccLat 46329.74 # Average memory access latency per DRAM burst | 296system.physmem.avgMemAccLat 46327.80 # Average memory access latency per DRAM burst |
| 299system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s | 297system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s |
| 300system.physmem.avgWrBW 131.97 # Average achieved write bandwidth in MiByte/s | 298system.physmem.avgWrBW 131.94 # Average achieved write bandwidth in MiByte/s |
| 301system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s | 299system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s |
| 302system.physmem.avgWrBWSys 131.98 # Average system write bandwidth in MiByte/s | 300system.physmem.avgWrBWSys 131.95 # Average system write bandwidth in MiByte/s |
| 303system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 304system.physmem.busUtil 3.13 # Data bus utilization in percentage 305system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads 306system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes 307system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing | 301system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 302system.physmem.busUtil 3.13 # Data bus utilization in percentage 303system.physmem.busUtilRead 2.10 # Data bus utilization in percentage for reads 304system.physmem.busUtilWrite 1.03 # Data bus utilization in percentage for writes 305system.physmem.avgRdQLen 0.19 # Average read queue length when enqueuing |
| 308system.physmem.avgWrQLen 10.08 # Average write queue length when enqueuing 309system.physmem.readRowHits 931610 # Number of row buffer hits during reads 310system.physmem.writeRowHits 336677 # Number of row buffer hits during writes 311system.physmem.readRowHitRate 41.48 # Row buffer hit rate for reads 312system.physmem.writeRowHitRate 30.59 # Row buffer hit rate for writes 313system.physmem.avgGap 159462.71 # Average gap between requests 314system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined 315system.physmem.prechargeAllPercent 5.89 # Percentage of time for which DRAM has all the banks in precharge state 316system.membus.throughput 401347580 # Throughput (bytes/s) 317system.membus.trans_dist::ReadReq 1419678 # Transaction distribution 318system.membus.trans_dist::ReadResp 1419677 # Transaction distribution 319system.membus.trans_dist::Writeback 1100533 # Transaction distribution 320system.membus.trans_dist::ReadExReq 826593 # Transaction distribution 321system.membus.trans_dist::ReadExResp 826593 # Transaction distribution 322system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593074 # Packet count per connected master and slave (bytes) 323system.membus.pkt_count::total 5593074 # Packet count per connected master and slave (bytes) 324system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214195392 # Cumulative packet size per connected master and slave (bytes) 325system.membus.tot_pkt_size::total 214195392 # Cumulative packet size per connected master and slave (bytes) 326system.membus.data_through_bus 214195392 # Total data (bytes) | 306system.physmem.avgWrQLen 10.35 # Average write queue length when enqueuing 307system.physmem.readRowHits 932509 # Number of row buffer hits during reads 308system.physmem.writeRowHits 336457 # Number of row buffer hits during writes 309system.physmem.readRowHitRate 41.52 # Row buffer hit rate for reads 310system.physmem.writeRowHitRate 30.57 # Row buffer hit rate for writes 311system.physmem.avgGap 159474.14 # Average gap between requests 312system.physmem.pageHitRate 37.92 # Row buffer hit rate, read and write combined 313system.physmem.prechargeAllPercent 5.98 # Percentage of time for which DRAM has all the banks in precharge state 314system.membus.throughput 401318817 # Throughput (bytes/s) 315system.membus.trans_dist::ReadReq 1420235 # Transaction distribution 316system.membus.trans_dist::ReadResp 1420234 # Transaction distribution 317system.membus.trans_dist::Writeback 1100498 # Transaction distribution 318system.membus.trans_dist::ReadExReq 826499 # Transaction distribution 319system.membus.trans_dist::ReadExResp 826499 # Transaction distribution 320system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593965 # Packet count per connected master and slave (bytes) 321system.membus.pkt_count::total 5593965 # Packet count per connected master and slave (bytes) 322system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214222784 # Cumulative packet size per connected master and slave (bytes) 323system.membus.tot_pkt_size::total 214222784 # Cumulative packet size per connected master and slave (bytes) 324system.membus.data_through_bus 214222784 # Total data (bytes) |
| 327system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 325system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 328system.membus.reqLayer0.occupancy 12924294750 # Layer occupancy (ticks) | 326system.membus.reqLayer0.occupancy 12926153000 # Layer occupancy (ticks) |
| 329system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) | 327system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) |
| 330system.membus.respLayer1.occupancy 21079818750 # Layer occupancy (ticks) 331system.membus.respLayer1.utilization 3.9 # Layer utilization (%) 332system.cpu.branchPred.lookups 303467870 # Number of BP lookups 333system.cpu.branchPred.condPredicted 249715061 # Number of conditional branches predicted 334system.cpu.branchPred.condIncorrect 15195903 # Number of conditional branches incorrect 335system.cpu.branchPred.BTBLookups 175178105 # Number of BTB lookups 336system.cpu.branchPred.BTBHits 161776963 # Number of BTB hits | 328system.membus.respLayer1.occupancy 21085487000 # Layer occupancy (ticks) 329system.membus.respLayer1.utilization 4.0 # Layer utilization (%) 330system.cpu.branchPred.lookups 303451211 # Number of BP lookups 331system.cpu.branchPred.condPredicted 249690817 # Number of conditional branches predicted 332system.cpu.branchPred.condIncorrect 15200865 # Number of conditional branches incorrect 333system.cpu.branchPred.BTBLookups 174297258 # Number of BTB lookups 334system.cpu.branchPred.BTBHits 161770128 # Number of BTB hits |
| 337system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 335system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 338system.cpu.branchPred.BTBHitPct 92.349990 # BTB Hit Percentage 339system.cpu.branchPred.usedRAS 17540871 # Number of times the RAS was used to get a target. 340system.cpu.branchPred.RASInCorrect 204 # Number of incorrect RAS predictions. | 336system.cpu.branchPred.BTBHitPct 92.812779 # BTB Hit Percentage 337system.cpu.branchPred.usedRAS 17550277 # Number of times the RAS was used to get a target. 338system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions. |
| 341system.cpu.dtb.inst_hits 0 # ITB inst hits 342system.cpu.dtb.inst_misses 0 # ITB inst misses 343system.cpu.dtb.read_hits 0 # DTB read hits 344system.cpu.dtb.read_misses 0 # DTB read misses 345system.cpu.dtb.write_hits 0 # DTB write hits 346system.cpu.dtb.write_misses 0 # DTB write misses 347system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 348system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 46 # Number of system calls | 339system.cpu.dtb.inst_hits 0 # ITB inst hits 340system.cpu.dtb.inst_misses 0 # ITB inst misses 341system.cpu.dtb.read_hits 0 # DTB read hits 342system.cpu.dtb.read_misses 0 # DTB read misses 343system.cpu.dtb.write_hits 0 # DTB write hits 344system.cpu.dtb.write_misses 0 # DTB write misses 345system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 346system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 374system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 375system.cpu.itb.read_accesses 0 # DTB read accesses 376system.cpu.itb.write_accesses 0 # DTB write accesses 377system.cpu.itb.inst_accesses 0 # ITB inst accesses 378system.cpu.itb.hits 0 # DTB hits 379system.cpu.itb.misses 0 # DTB misses 380system.cpu.itb.accesses 0 # DTB accesses 381system.cpu.workload.num_syscalls 46 # Number of system calls |
| 384system.cpu.numCycles 1067381007 # number of cpu cycles simulated | 382system.cpu.numCycles 1067594019 # number of cpu cycles simulated |
| 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 383system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 384system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 387system.cpu.fetch.icacheStallCycles 299148062 # Number of cycles fetch is stalled on an Icache miss 388system.cpu.fetch.Insts 2189533318 # Number of instructions fetch has processed 389system.cpu.fetch.Branches 303467870 # Number of branches that fetch encountered 390system.cpu.fetch.predictedBranches 179317834 # Number of branches that fetch has predicted taken 391system.cpu.fetch.Cycles 435752088 # Number of cycles fetch has run and was not squashing or blocked 392system.cpu.fetch.SquashCycles 88086251 # Number of cycles fetch has spent squashing 393system.cpu.fetch.BlockedCycles 164106751 # Number of cycles fetch has spent blocked 394system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 395system.cpu.fetch.PendingTrapStallCycles 339 # Number of stall cycles due to pending traps 396system.cpu.fetch.CacheLines 289566494 # Number of cache lines fetched 397system.cpu.fetch.IcacheSquashes 5997594 # Number of outstanding Icache misses that were squashed 398system.cpu.fetch.rateDist::samples 968963067 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::mean 2.499628 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::stdev 3.206367 # Number of instructions fetched each cycle (Total) | 385system.cpu.fetch.icacheStallCycles 299164557 # Number of cycles fetch is stalled on an Icache miss 386system.cpu.fetch.Insts 2189663567 # Number of instructions fetch has processed 387system.cpu.fetch.Branches 303451211 # Number of branches that fetch encountered 388system.cpu.fetch.predictedBranches 179320405 # Number of branches that fetch has predicted taken 389system.cpu.fetch.Cycles 435777521 # Number of cycles fetch has run and was not squashing or blocked 390system.cpu.fetch.SquashCycles 88106670 # Number of cycles fetch has spent squashing 391system.cpu.fetch.BlockedCycles 164181608 # Number of cycles fetch has spent blocked 392system.cpu.fetch.PendingTrapStallCycles 55 # Number of stall cycles due to pending traps 393system.cpu.fetch.CacheLines 289571528 # Number of cache lines fetched 394system.cpu.fetch.IcacheSquashes 5986152 # Number of outstanding Icache misses that were squashed 395system.cpu.fetch.rateDist::samples 969098859 # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.rateDist::mean 2.499353 # Number of instructions fetched each cycle (Total) 397system.cpu.fetch.rateDist::stdev 3.206220 # Number of instructions fetched each cycle (Total) |
| 401system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 398system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 402system.cpu.fetch.rateDist::0 533211067 55.03% 55.03% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::1 25485631 2.63% 57.66% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::2 39032754 4.03% 61.69% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::3 48282665 4.98% 66.67% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::4 43767932 4.52% 71.19% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::5 46382840 4.79% 75.97% # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::6 38389210 3.96% 79.94% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::7 18960850 1.96% 81.89% # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::8 175450118 18.11% 100.00% # Number of instructions fetched each cycle (Total) | 399system.cpu.fetch.rateDist::0 533321418 55.03% 55.03% # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::1 25465587 2.63% 57.66% # Number of instructions fetched each cycle (Total) 401system.cpu.fetch.rateDist::2 39057125 4.03% 61.69% # Number of instructions fetched each cycle (Total) 402system.cpu.fetch.rateDist::3 48306210 4.98% 66.68% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::4 43759030 4.52% 71.19% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::5 46389880 4.79% 75.98% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::6 38408230 3.96% 79.94% # Number of instructions fetched each cycle (Total) 406system.cpu.fetch.rateDist::7 18944401 1.95% 81.90% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::8 175446978 18.10% 100.00% # Number of instructions fetched each cycle (Total) |
| 411system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 413system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 408system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 409system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 414system.cpu.fetch.rateDist::total 968963067 # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.branchRate 0.284311 # Number of branch fetches per cycle 416system.cpu.fetch.rate 2.051314 # Number of inst fetches per cycle 417system.cpu.decode.IdleCycles 331377153 # Number of cycles decode is idle 418system.cpu.decode.BlockedCycles 141962670 # Number of cycles decode is blocked 419system.cpu.decode.RunCycles 405350137 # Number of cycles decode is running 420system.cpu.decode.UnblockCycles 20317948 # Number of cycles decode is unblocking 421system.cpu.decode.SquashCycles 69955159 # Number of cycles decode is squashing 422system.cpu.decode.BranchResolved 46017147 # Number of times decode resolved a branch 423system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction 424system.cpu.decode.DecodedInsts 2369104960 # Number of instructions handled by decode 425system.cpu.decode.SquashedInsts 2426 # Number of squashed instructions handled by decode 426system.cpu.rename.SquashCycles 69955159 # Number of cycles rename is squashing 427system.cpu.rename.IdleCycles 354884990 # Number of cycles rename is idle 428system.cpu.rename.BlockCycles 70530339 # Number of cycles rename is blocking 429system.cpu.rename.serializeStallCycles 17935 # count of cycles rename stalled for serializing inst 430system.cpu.rename.RunCycles 400511119 # Number of cycles rename is running 431system.cpu.rename.UnblockCycles 73063525 # Number of cycles rename is unblocking 432system.cpu.rename.RenamedInsts 2306250708 # Number of instructions processed by rename 433system.cpu.rename.ROBFullEvents 150920 # Number of times rename has blocked due to ROB full 434system.cpu.rename.IQFullEvents 5011927 # Number of times rename has blocked due to IQ full 435system.cpu.rename.LSQFullEvents 60136403 # Number of times rename has blocked due to LSQ full 436system.cpu.rename.FullRegisterEvents 4 # Number of times there has been no free registers 437system.cpu.rename.RenamedOperands 2282159345 # Number of destination operands rename has renamed 438system.cpu.rename.RenameLookups 10649371145 # Number of register rename lookups that rename has made 439system.cpu.rename.int_rename_lookups 9763416611 # Number of integer rename lookups 440system.cpu.rename.fp_rename_lookups 460 # Number of floating rename lookups | 411system.cpu.fetch.rateDist::total 969098859 # Number of instructions fetched each cycle (Total) 412system.cpu.fetch.branchRate 0.284238 # Number of branch fetches per cycle 413system.cpu.fetch.rate 2.051026 # Number of inst fetches per cycle 414system.cpu.decode.IdleCycles 331405346 # Number of cycles decode is idle 415system.cpu.decode.BlockedCycles 142029656 # Number of cycles decode is blocked 416system.cpu.decode.RunCycles 405372937 # Number of cycles decode is running 417system.cpu.decode.UnblockCycles 20316462 # Number of cycles decode is unblocking 418system.cpu.decode.SquashCycles 69974458 # Number of cycles decode is squashing 419system.cpu.decode.BranchResolved 46022119 # Number of times decode resolved a branch 420system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction 421system.cpu.decode.DecodedInsts 2369134638 # Number of instructions handled by decode 422system.cpu.decode.SquashedInsts 2461 # Number of squashed instructions handled by decode 423system.cpu.rename.SquashCycles 69974458 # Number of cycles rename is squashing 424system.cpu.rename.IdleCycles 354905741 # Number of cycles rename is idle 425system.cpu.rename.BlockCycles 70599540 # Number of cycles rename is blocking 426system.cpu.rename.serializeStallCycles 20110 # count of cycles rename stalled for serializing inst 427system.cpu.rename.RunCycles 400539970 # Number of cycles rename is running 428system.cpu.rename.UnblockCycles 73059040 # Number of cycles rename is unblocking 429system.cpu.rename.RenamedInsts 2306329085 # Number of instructions processed by rename 430system.cpu.rename.ROBFullEvents 151792 # Number of times rename has blocked due to ROB full 431system.cpu.rename.IQFullEvents 5017639 # Number of times rename has blocked due to IQ full 432system.cpu.rename.LSQFullEvents 60125136 # Number of times rename has blocked due to LSQ full 433system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers 434system.cpu.rename.RenamedOperands 2282204226 # Number of destination operands rename has renamed 435system.cpu.rename.RenameLookups 10649650977 # Number of register rename lookups that rename has made 436system.cpu.rename.int_rename_lookups 9763673843 # Number of integer rename lookups 437system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups |
| 441system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed | 438system.cpu.rename.CommittedMaps 1706319930 # Number of HB maps that are committed |
| 442system.cpu.rename.UndoneMaps 575839415 # Number of HB maps that are undone due to squashing 443system.cpu.rename.serializingInsts 404 # count of serializing insts renamed 444system.cpu.rename.tempSerializingInsts 401 # count of temporary serializing insts renamed 445system.cpu.rename.skidInsts 160989021 # count of insts added to the skid buffer 446system.cpu.memDep0.insertedLoads 624749088 # Number of loads inserted to the mem dependence unit. 447system.cpu.memDep0.insertedStores 220784728 # Number of stores inserted to the mem dependence unit. 448system.cpu.memDep0.conflictingLoads 85932352 # Number of conflicting loads. 449system.cpu.memDep0.conflictingStores 70842412 # Number of conflicting stores. 450system.cpu.iq.iqInstsAdded 2202316968 # Number of instructions added to the IQ (excludes non-spec) 451system.cpu.iq.iqNonSpecInstsAdded 440 # Number of non-speculative instructions added to the IQ 452system.cpu.iq.iqInstsIssued 2018777354 # Number of instructions issued 453system.cpu.iq.iqSquashedInstsIssued 4015619 # Number of squashed instructions issued 454system.cpu.iq.iqSquashedInstsExamined 474672323 # Number of squashed instructions iterated over during squash; mainly for profiling 455system.cpu.iq.iqSquashedOperandsExamined 1127531541 # Number of squashed operands that are examined and possibly removed from graph 456system.cpu.iq.iqSquashedNonSpecRemoved 270 # Number of squashed non-spec instructions that were removed 457system.cpu.iq.issued_per_cycle::samples 968963067 # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::mean 2.083441 # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::stdev 1.906294 # Number of insts issued each cycle | 439system.cpu.rename.UndoneMaps 575884296 # Number of HB maps that are undone due to squashing 440system.cpu.rename.serializingInsts 843 # count of serializing insts renamed 441system.cpu.rename.tempSerializingInsts 840 # count of temporary serializing insts renamed 442system.cpu.rename.skidInsts 160951749 # count of insts added to the skid buffer 443system.cpu.memDep0.insertedLoads 624757210 # Number of loads inserted to the mem dependence unit. 444system.cpu.memDep0.insertedStores 220789926 # Number of stores inserted to the mem dependence unit. 445system.cpu.memDep0.conflictingLoads 85935761 # Number of conflicting loads. 446system.cpu.memDep0.conflictingStores 70812981 # Number of conflicting stores. 447system.cpu.iq.iqInstsAdded 2202388527 # Number of instructions added to the IQ (excludes non-spec) 448system.cpu.iq.iqNonSpecInstsAdded 863 # Number of non-speculative instructions added to the IQ 449system.cpu.iq.iqInstsIssued 2018815703 # Number of instructions issued 450system.cpu.iq.iqSquashedInstsIssued 4014611 # Number of squashed instructions issued 451system.cpu.iq.iqSquashedInstsExamined 474721541 # Number of squashed instructions iterated over during squash; mainly for profiling 452system.cpu.iq.iqSquashedOperandsExamined 1127548434 # Number of squashed operands that are examined and possibly removed from graph 453system.cpu.iq.iqSquashedNonSpecRemoved 693 # Number of squashed non-spec instructions that were removed 454system.cpu.iq.issued_per_cycle::samples 969098859 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::mean 2.083189 # Number of insts issued each cycle 456system.cpu.iq.issued_per_cycle::stdev 1.906427 # Number of insts issued each cycle |
| 460system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 457system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 461system.cpu.iq.issued_per_cycle::0 286087063 29.53% 29.53% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::1 153648666 15.86% 45.38% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::2 160841319 16.60% 61.98% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::3 120316001 12.42% 74.40% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::4 123517924 12.75% 87.15% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::5 73816539 7.62% 94.76% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::6 38325528 3.96% 98.72% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::7 9889728 1.02% 99.74% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::8 2520299 0.26% 100.00% # Number of insts issued each cycle | 458system.cpu.iq.issued_per_cycle::0 286260209 29.54% 29.54% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::1 153575867 15.85% 45.39% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::2 160890539 16.60% 61.99% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::3 120276383 12.41% 74.40% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::4 123547545 12.75% 87.15% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::5 73803065 7.62% 94.76% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::6 38319485 3.95% 98.72% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::7 9898934 1.02% 99.74% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::8 2526832 0.26% 100.00% # Number of insts issued each cycle |
| 470system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 467system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 473system.cpu.iq.issued_per_cycle::total 968963067 # Number of insts issued each cycle | 470system.cpu.iq.issued_per_cycle::total 969098859 # Number of insts issued each cycle |
| 474system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 471system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 475system.cpu.iq.fu_full::IntAlu 895423 3.74% 3.74% # attempts to use FU when none available 476system.cpu.iq.fu_full::IntMult 5601 0.02% 3.76% # attempts to use FU when none available 477system.cpu.iq.fu_full::IntDiv 0 0.00% 3.76% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.76% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.76% # attempts to use FU when none available 480system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.76% # attempts to use FU when none available 481system.cpu.iq.fu_full::FloatMult 0 0.00% 3.76% # attempts to use FU when none available 482system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.76% # attempts to use FU when none available 483system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.76% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.76% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.76% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.76% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.76% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.76% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.76% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdMult 0 0.00% 3.76% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.76% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdShift 0 0.00% 3.76% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.76% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.76% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.76% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.76% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.76% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.76% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.76% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.76% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.76% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.76% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.76% # attempts to use FU when none available 504system.cpu.iq.fu_full::MemRead 18274862 76.27% 80.03% # attempts to use FU when none available 505system.cpu.iq.fu_full::MemWrite 4786167 19.97% 100.00% # attempts to use FU when none available | 472system.cpu.iq.fu_full::IntAlu 899836 3.76% 3.76% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntMult 5555 0.02% 3.78% # attempts to use FU when none available 474system.cpu.iq.fu_full::IntDiv 0 0.00% 3.78% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.78% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.78% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.78% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatMult 0 0.00% 3.78% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.78% # attempts to use FU when none available 480system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.78% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.78% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.78% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.78% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.78% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.78% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.78% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMult 0 0.00% 3.78% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.78% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShift 0 0.00% 3.78% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.78% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.78% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.78% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.78% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.78% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.78% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.78% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.78% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.78% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.78% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.78% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemRead 18259038 76.22% 80.00% # attempts to use FU when none available 502system.cpu.iq.fu_full::MemWrite 4790984 20.00% 100.00% # attempts to use FU when none available |
| 506system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 507system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 508system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 503system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 505system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 509system.cpu.iq.FU_type_0::IntAlu 1236899038 61.27% 61.27% # Type of FU issued 510system.cpu.iq.FU_type_0::IntMult 924736 0.05% 61.32% # Type of FU issued | 506system.cpu.iq.FU_type_0::IntAlu 1236944304 61.27% 61.27% # Type of FU issued 507system.cpu.iq.FU_type_0::IntMult 924745 0.05% 61.32% # Type of FU issued |
| 511system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 515system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 516system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 517system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 524system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued | 508system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.32% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 514system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 521system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued |
| 532system.cpu.iq.FU_type_0::SimdFloatCvt 48 0.00% 61.32% # Type of FU issued | 529system.cpu.iq.FU_type_0::SimdFloatCvt 39 0.00% 61.32% # Type of FU issued |
| 533system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued | 530system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.32% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued |
| 535system.cpu.iq.FU_type_0::SimdFloatMult 8 0.00% 61.32% # Type of FU issued | 532system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued |
| 536system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued | 533system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued |
| 538system.cpu.iq.FU_type_0::MemRead 587872837 29.12% 90.44% # Type of FU issued 539system.cpu.iq.FU_type_0::MemWrite 193080663 9.56% 100.00% # Type of FU issued | 535system.cpu.iq.FU_type_0::MemRead 587884247 29.12% 90.44% # Type of FU issued 536system.cpu.iq.FU_type_0::MemWrite 193062337 9.56% 100.00% # Type of FU issued |
| 540system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 541system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 537system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 538system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 542system.cpu.iq.FU_type_0::total 2018777354 # Type of FU issued 543system.cpu.iq.rate 1.891337 # Inst issue rate 544system.cpu.iq.fu_busy_cnt 23962053 # FU busy when requested 545system.cpu.iq.fu_busy_rate 0.011870 # FU busy rate (busy events/executed inst) 546system.cpu.iq.int_inst_queue_reads 5034495136 # Number of integer instruction queue reads 547system.cpu.iq.int_inst_queue_writes 2677178912 # Number of integer instruction queue writes 548system.cpu.iq.int_inst_queue_wakeup_accesses 1957310102 # Number of integer instruction queue wakeup accesses 549system.cpu.iq.fp_inst_queue_reads 311 # Number of floating instruction queue reads 550system.cpu.iq.fp_inst_queue_writes 694 # Number of floating instruction queue writes 551system.cpu.iq.fp_inst_queue_wakeup_accesses 129 # Number of floating instruction queue wakeup accesses 552system.cpu.iq.int_alu_accesses 2042739250 # Number of integer alu accesses 553system.cpu.iq.fp_alu_accesses 157 # Number of floating point alu accesses 554system.cpu.iew.lsq.thread0.forwLoads 64569425 # Number of loads that had data forwarded from stores | 539system.cpu.iq.FU_type_0::total 2018815703 # Type of FU issued 540system.cpu.iq.rate 1.890996 # Inst issue rate 541system.cpu.iq.fu_busy_cnt 23955413 # FU busy when requested 542system.cpu.iq.fu_busy_rate 0.011866 # FU busy rate (busy events/executed inst) 543system.cpu.iq.int_inst_queue_reads 5034700006 # Number of integer instruction queue reads 544system.cpu.iq.int_inst_queue_writes 2677299944 # Number of integer instruction queue writes 545system.cpu.iq.int_inst_queue_wakeup_accesses 1957368325 # Number of integer instruction queue wakeup accesses 546system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads 547system.cpu.iq.fp_inst_queue_writes 522 # Number of floating instruction queue writes 548system.cpu.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses 549system.cpu.iq.int_alu_accesses 2042770975 # Number of integer alu accesses 550system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses 551system.cpu.iew.lsq.thread0.forwLoads 64606441 # Number of loads that had data forwarded from stores |
| 555system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 552system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 556system.cpu.iew.lsq.thread0.squashedLoads 138822319 # Number of loads squashed 557system.cpu.iew.lsq.thread0.ignoredResponses 268987 # Number of memory responses ignored because the instruction is squashed 558system.cpu.iew.lsq.thread0.memOrderViolation 192391 # Number of memory ordering violations 559system.cpu.iew.lsq.thread0.squashedStores 45937683 # Number of stores squashed | 553system.cpu.iew.lsq.thread0.squashedLoads 138830441 # Number of loads squashed 554system.cpu.iew.lsq.thread0.ignoredResponses 271664 # Number of memory responses ignored because the instruction is squashed 555system.cpu.iew.lsq.thread0.memOrderViolation 192064 # Number of memory ordering violations 556system.cpu.iew.lsq.thread0.squashedStores 45942881 # Number of stores squashed |
| 560system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 561system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 562system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled | 557system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 558system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 559system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled |
| 563system.cpu.iew.lsq.thread0.cacheBlocked 4778132 # Number of times an access to memory failed due to the cache being blocked | 560system.cpu.iew.lsq.thread0.cacheBlocked 4771033 # Number of times an access to memory failed due to the cache being blocked |
| 564system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 561system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 565system.cpu.iew.iewSquashCycles 69955159 # Number of cycles IEW is squashing 566system.cpu.iew.iewBlockCycles 33483642 # Number of cycles IEW is blocking 567system.cpu.iew.iewUnblockCycles 1603224 # Number of cycles IEW is unblocking 568system.cpu.iew.iewDispatchedInsts 2202317539 # Number of instructions dispatched to IQ 569system.cpu.iew.iewDispSquashedInsts 7879544 # Number of squashed instructions skipped by dispatch 570system.cpu.iew.iewDispLoadInsts 624749088 # Number of dispatched load instructions 571system.cpu.iew.iewDispStoreInsts 220784728 # Number of dispatched store instructions 572system.cpu.iew.iewDispNonSpecInsts 378 # Number of dispatched non-speculative instructions 573system.cpu.iew.iewIQFullEvents 478707 # Number of times the IQ has become full, causing a stall 574system.cpu.iew.iewLSQFullEvents 97428 # Number of times the LSQ has become full, causing a stall 575system.cpu.iew.memOrderViolationEvents 192391 # Number of memory order violations 576system.cpu.iew.predictedTakenIncorrect 8138332 # Number of branches that were predicted taken incorrectly 577system.cpu.iew.predictedNotTakenIncorrect 9600465 # Number of branches that were predicted not taken incorrectly 578system.cpu.iew.branchMispredicts 17738797 # Number of branch mispredicts detected at execute 579system.cpu.iew.iewExecutedInsts 1988042975 # Number of executed instructions 580system.cpu.iew.iewExecLoadInsts 574015030 # Number of load instructions executed 581system.cpu.iew.iewExecSquashedInsts 30734379 # Number of squashed instructions skipped in execute | 562system.cpu.iew.iewSquashCycles 69974458 # Number of cycles IEW is squashing 563system.cpu.iew.iewBlockCycles 33522833 # Number of cycles IEW is blocking 564system.cpu.iew.iewUnblockCycles 1603829 # Number of cycles IEW is unblocking 565system.cpu.iew.iewDispatchedInsts 2202389482 # Number of instructions dispatched to IQ 566system.cpu.iew.iewDispSquashedInsts 7882723 # Number of squashed instructions skipped by dispatch 567system.cpu.iew.iewDispLoadInsts 624757210 # Number of dispatched load instructions 568system.cpu.iew.iewDispStoreInsts 220789926 # Number of dispatched store instructions 569system.cpu.iew.iewDispNonSpecInsts 801 # Number of dispatched non-speculative instructions 570system.cpu.iew.iewIQFullEvents 479284 # Number of times the IQ has become full, causing a stall 571system.cpu.iew.iewLSQFullEvents 97151 # Number of times the LSQ has become full, causing a stall 572system.cpu.iew.memOrderViolationEvents 192064 # Number of memory order violations 573system.cpu.iew.predictedTakenIncorrect 8143428 # Number of branches that were predicted taken incorrectly 574system.cpu.iew.predictedNotTakenIncorrect 9602990 # Number of branches that were predicted not taken incorrectly 575system.cpu.iew.branchMispredicts 17746418 # Number of branch mispredicts detected at execute 576system.cpu.iew.iewExecutedInsts 1988074209 # Number of executed instructions 577system.cpu.iew.iewExecLoadInsts 574028107 # Number of load instructions executed 578system.cpu.iew.iewExecSquashedInsts 30741494 # Number of squashed instructions skipped in execute |
| 582system.cpu.iew.exec_swp 0 # number of swp insts executed | 579system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 583system.cpu.iew.exec_nop 131 # number of nop insts executed 584system.cpu.iew.exec_refs 764217607 # number of memory reference insts executed 585system.cpu.iew.exec_branches 238311346 # Number of branches executed 586system.cpu.iew.exec_stores 190202577 # Number of stores executed 587system.cpu.iew.exec_rate 1.862543 # Inst execution rate 588system.cpu.iew.wb_sent 1965731650 # cumulative count of insts sent to commit 589system.cpu.iew.wb_count 1957310231 # cumulative count of insts written-back 590system.cpu.iew.wb_producers 1295404026 # num instructions producing a value 591system.cpu.iew.wb_consumers 2059270839 # num instructions consuming a value | 580system.cpu.iew.exec_nop 92 # number of nop insts executed 581system.cpu.iew.exec_refs 764206037 # number of memory reference insts executed 582system.cpu.iew.exec_branches 238324356 # Number of branches executed 583system.cpu.iew.exec_stores 190177930 # Number of stores executed 584system.cpu.iew.exec_rate 1.862201 # Inst execution rate 585system.cpu.iew.wb_sent 1965784253 # cumulative count of insts sent to commit 586system.cpu.iew.wb_count 1957368435 # cumulative count of insts written-back 587system.cpu.iew.wb_producers 1295422958 # num instructions producing a value 588system.cpu.iew.wb_consumers 2059236430 # num instructions consuming a value |
| 592system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 589system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 593system.cpu.iew.wb_rate 1.833750 # insts written-back per cycle 594system.cpu.iew.wb_fanout 0.629060 # average fanout of values written-back | 590system.cpu.iew.wb_rate 1.833439 # insts written-back per cycle 591system.cpu.iew.wb_fanout 0.629079 # average fanout of values written-back |
| 595system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 592system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 596system.cpu.commit.commitSquashedInsts 479343339 # The number of squashed insts skipped by commit | 593system.cpu.commit.commitSquashedInsts 479415060 # The number of squashed insts skipped by commit |
| 597system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards | 594system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards |
| 598system.cpu.commit.branchMispredicts 15195240 # The number of times a branch was mispredicted 599system.cpu.commit.committed_per_cycle::samples 899007908 # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::mean 1.916639 # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::stdev 2.718451 # Number of insts commited each cycle | 595system.cpu.commit.branchMispredicts 15200205 # The number of times a branch was mispredicted 596system.cpu.commit.committed_per_cycle::samples 899124401 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::mean 1.916391 # Number of insts commited each cycle 598system.cpu.commit.committed_per_cycle::stdev 2.718302 # Number of insts commited each cycle |
| 602system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 599system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 603system.cpu.commit.committed_per_cycle::0 410513863 45.66% 45.66% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::1 193235979 21.49% 67.16% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::2 72768373 8.09% 75.25% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::3 35278706 3.92% 79.18% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::4 18862057 2.10% 81.27% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::5 30820454 3.43% 84.70% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::6 19957331 2.22% 86.92% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::7 11398634 1.27% 88.19% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::8 106172511 11.81% 100.00% # Number of insts commited each cycle | 600system.cpu.commit.committed_per_cycle::0 410581675 45.66% 45.66% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::1 193287424 21.50% 67.16% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::2 72783200 8.09% 75.26% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::3 35268105 3.92% 79.18% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::4 18874620 2.10% 81.28% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::5 30803459 3.43% 84.70% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::6 19949403 2.22% 86.92% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::7 11408599 1.27% 88.19% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::8 106167916 11.81% 100.00% # Number of insts commited each cycle |
| 612system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 609system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 615system.cpu.commit.committed_per_cycle::total 899007908 # Number of insts commited each cycle | 612system.cpu.commit.committed_per_cycle::total 899124401 # Number of insts commited each cycle |
| 616system.cpu.commit.committedInsts 1544563041 # Number of instructions committed 617system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed 618system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 619system.cpu.commit.refs 660773814 # Number of memory references committed 620system.cpu.commit.loads 485926769 # Number of loads committed 621system.cpu.commit.membars 62 # Number of memory barriers committed 622system.cpu.commit.branches 213462426 # Number of branches committed 623system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 624system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. 625system.cpu.commit.function_calls 13665177 # Number of function calls committed. | 613system.cpu.commit.committedInsts 1544563041 # Number of instructions committed 614system.cpu.commit.committedOps 1723073853 # Number of ops (including micro ops) committed 615system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 616system.cpu.commit.refs 660773814 # Number of memory references committed 617system.cpu.commit.loads 485926769 # Number of loads committed 618system.cpu.commit.membars 62 # Number of memory barriers committed 619system.cpu.commit.branches 213462426 # Number of branches committed 620system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 621system.cpu.commit.int_insts 1536941841 # Number of committed integer instructions. 622system.cpu.commit.function_calls 13665177 # Number of function calls committed. |
| 626system.cpu.commit.bw_lim_events 106172511 # number cycles where commit BW limit reached | 623system.cpu.commit.bw_lim_events 106167916 # number cycles where commit BW limit reached |
| 627system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 624system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 628system.cpu.rob.rob_reads 2995251990 # The number of ROB reads 629system.cpu.rob.rob_writes 4474939624 # The number of ROB writes 630system.cpu.timesIdled 1152982 # Number of times that the entire CPU went into an idle state and unscheduled itself 631system.cpu.idleCycles 98417940 # Total number of cycles that the CPU has spent unscheduled due to idling | 625system.cpu.rob.rob_reads 2995444799 # The number of ROB reads 626system.cpu.rob.rob_writes 4475102834 # The number of ROB writes 627system.cpu.timesIdled 1153332 # Number of times that the entire CPU went into an idle state and unscheduled itself 628system.cpu.idleCycles 98495160 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 632system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 633system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated 634system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated | 629system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 630system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated 631system.cpu.committedInsts_total 1544563023 # Number of Instructions Simulated |
| 635system.cpu.cpi 0.691057 # CPI: Cycles Per Instruction 636system.cpu.cpi_total 0.691057 # CPI: Total CPI of All Threads 637system.cpu.ipc 1.447059 # IPC: Instructions Per Cycle 638system.cpu.ipc_total 1.447059 # IPC: Total IPC of All Threads 639system.cpu.int_regfile_reads 9956212388 # number of integer regfile reads 640system.cpu.int_regfile_writes 1937181821 # number of integer regfile writes 641system.cpu.fp_regfile_reads 130 # number of floating regfile reads 642system.cpu.fp_regfile_writes 139 # number of floating regfile writes 643system.cpu.misc_regfile_reads 737624314 # number of misc regfile reads | 632system.cpu.cpi 0.691195 # CPI: Cycles Per Instruction 633system.cpu.cpi_total 0.691195 # CPI: Total CPI of All Threads 634system.cpu.ipc 1.446770 # IPC: Instructions Per Cycle 635system.cpu.ipc_total 1.446770 # IPC: Total IPC of All Threads 636system.cpu.int_regfile_reads 9956366000 # number of integer regfile reads 637system.cpu.int_regfile_writes 1937254103 # number of integer regfile writes 638system.cpu.fp_regfile_reads 112 # number of floating regfile reads 639system.cpu.fp_regfile_writes 111 # number of floating regfile writes 640system.cpu.misc_regfile_reads 737634139 # number of misc regfile reads |
| 644system.cpu.misc_regfile_writes 124 # number of misc regfile writes | 641system.cpu.misc_regfile_writes 124 # number of misc regfile writes |
| 645system.cpu.toL2Bus.throughput 1605146644 # Throughput (bytes/s) 646system.cpu.toL2Bus.trans_dist::ReadReq 7709082 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::ReadResp 7709081 # Transaction distribution 648system.cpu.toL2Bus.trans_dist::Writeback 3782685 # Transaction distribution 649system.cpu.toL2Bus.trans_dist::ReadExReq 1893414 # Transaction distribution 650system.cpu.toL2Bus.trans_dist::ReadExResp 1893414 # Transaction distribution | 642system.cpu.toL2Bus.throughput 1604602532 # Throughput (bytes/s) 643system.cpu.toL2Bus.trans_dist::ReadReq 7709032 # Transaction distribution 644system.cpu.toL2Bus.trans_dist::ReadResp 7709031 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::Writeback 3780837 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::ReadExReq 1893445 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::ReadExResp 1893445 # Transaction distribution |
| 651system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes) | 648system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes) |
| 652system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986128 # Packet count per connected master and slave (bytes) 653system.cpu.toL2Bus.pkt_count::total 22987676 # Packet count per connected master and slave (bytes) | 649system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22984242 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.pkt_count::total 22985790 # Packet count per connected master and slave (bytes) |
| 654system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) | 651system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes) |
| 655system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856601984 # Cumulative packet size per connected master and slave (bytes) 656system.cpu.toL2Bus.tot_pkt_size::total 856651520 # Cumulative packet size per connected master and slave (bytes) 657system.cpu.toL2Bus.data_through_bus 856651520 # Total data (bytes) | 652system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856482496 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.tot_pkt_size::total 856532032 # Cumulative packet size per connected master and slave (bytes) 654system.cpu.toL2Bus.data_through_bus 856532032 # Total data (bytes) |
| 658system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 655system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 659system.cpu.toL2Bus.reqLayer0.occupancy 10475431595 # Layer occupancy (ticks) | 656system.cpu.toL2Bus.reqLayer0.occupancy 10472653342 # Layer occupancy (ticks) |
| 660system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) | 657system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) |
| 661system.cpu.toL2Bus.respLayer0.occupancy 1294249 # Layer occupancy (ticks) | 658system.cpu.toL2Bus.respLayer0.occupancy 1293249 # Layer occupancy (ticks) |
| 662system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 659system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 663system.cpu.toL2Bus.respLayer1.occupancy 14768966243 # Layer occupancy (ticks) | 660system.cpu.toL2Bus.respLayer1.occupancy 14769367993 # Layer occupancy (ticks) |
| 664system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) | 661system.cpu.toL2Bus.respLayer1.utilization 2.8 # Layer utilization (%) |
| 665system.cpu.icache.tags.replacements 22 # number of replacements 666system.cpu.icache.tags.tagsinuse 628.527972 # Cycle average of tags in use 667system.cpu.icache.tags.total_refs 289565308 # Total number of references to valid blocks. | 662system.cpu.icache.tags.replacements 20 # number of replacements 663system.cpu.icache.tags.tagsinuse 628.438821 # Cycle average of tags in use 664system.cpu.icache.tags.total_refs 289570320 # Total number of references to valid blocks. |
| 668system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks. | 665system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks. |
| 669system.cpu.icache.tags.avg_refs 374115.385013 # Average number of references to valid blocks. | 666system.cpu.icache.tags.avg_refs 374121.860465 # Average number of references to valid blocks. |
| 670system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 667system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 671system.cpu.icache.tags.occ_blocks::cpu.inst 628.527972 # Average occupied blocks per requestor 672system.cpu.icache.tags.occ_percent::cpu.inst 0.306898 # Average percentage of cache occupancy 673system.cpu.icache.tags.occ_percent::total 0.306898 # Average percentage of cache occupancy 674system.cpu.icache.ReadReq_hits::cpu.inst 289565308 # number of ReadReq hits 675system.cpu.icache.ReadReq_hits::total 289565308 # number of ReadReq hits 676system.cpu.icache.demand_hits::cpu.inst 289565308 # number of demand (read+write) hits 677system.cpu.icache.demand_hits::total 289565308 # number of demand (read+write) hits 678system.cpu.icache.overall_hits::cpu.inst 289565308 # number of overall hits 679system.cpu.icache.overall_hits::total 289565308 # number of overall hits 680system.cpu.icache.ReadReq_misses::cpu.inst 1186 # number of ReadReq misses 681system.cpu.icache.ReadReq_misses::total 1186 # number of ReadReq misses 682system.cpu.icache.demand_misses::cpu.inst 1186 # number of demand (read+write) misses 683system.cpu.icache.demand_misses::total 1186 # number of demand (read+write) misses 684system.cpu.icache.overall_misses::cpu.inst 1186 # number of overall misses 685system.cpu.icache.overall_misses::total 1186 # number of overall misses 686system.cpu.icache.ReadReq_miss_latency::cpu.inst 82924749 # number of ReadReq miss cycles 687system.cpu.icache.ReadReq_miss_latency::total 82924749 # number of ReadReq miss cycles 688system.cpu.icache.demand_miss_latency::cpu.inst 82924749 # number of demand (read+write) miss cycles 689system.cpu.icache.demand_miss_latency::total 82924749 # number of demand (read+write) miss cycles 690system.cpu.icache.overall_miss_latency::cpu.inst 82924749 # number of overall miss cycles 691system.cpu.icache.overall_miss_latency::total 82924749 # number of overall miss cycles 692system.cpu.icache.ReadReq_accesses::cpu.inst 289566494 # number of ReadReq accesses(hits+misses) 693system.cpu.icache.ReadReq_accesses::total 289566494 # number of ReadReq accesses(hits+misses) 694system.cpu.icache.demand_accesses::cpu.inst 289566494 # number of demand (read+write) accesses 695system.cpu.icache.demand_accesses::total 289566494 # number of demand (read+write) accesses 696system.cpu.icache.overall_accesses::cpu.inst 289566494 # number of overall (read+write) accesses 697system.cpu.icache.overall_accesses::total 289566494 # number of overall (read+write) accesses | 668system.cpu.icache.tags.occ_blocks::cpu.inst 628.438821 # Average occupied blocks per requestor 669system.cpu.icache.tags.occ_percent::cpu.inst 0.306855 # Average percentage of cache occupancy 670system.cpu.icache.tags.occ_percent::total 0.306855 # Average percentage of cache occupancy 671system.cpu.icache.ReadReq_hits::cpu.inst 289570320 # number of ReadReq hits 672system.cpu.icache.ReadReq_hits::total 289570320 # number of ReadReq hits 673system.cpu.icache.demand_hits::cpu.inst 289570320 # number of demand (read+write) hits 674system.cpu.icache.demand_hits::total 289570320 # number of demand (read+write) hits 675system.cpu.icache.overall_hits::cpu.inst 289570320 # number of overall hits 676system.cpu.icache.overall_hits::total 289570320 # number of overall hits 677system.cpu.icache.ReadReq_misses::cpu.inst 1208 # number of ReadReq misses 678system.cpu.icache.ReadReq_misses::total 1208 # number of ReadReq misses 679system.cpu.icache.demand_misses::cpu.inst 1208 # number of demand (read+write) misses 680system.cpu.icache.demand_misses::total 1208 # number of demand (read+write) misses 681system.cpu.icache.overall_misses::cpu.inst 1208 # number of overall misses 682system.cpu.icache.overall_misses::total 1208 # number of overall misses 683system.cpu.icache.ReadReq_miss_latency::cpu.inst 83080499 # number of ReadReq miss cycles 684system.cpu.icache.ReadReq_miss_latency::total 83080499 # number of ReadReq miss cycles 685system.cpu.icache.demand_miss_latency::cpu.inst 83080499 # number of demand (read+write) miss cycles 686system.cpu.icache.demand_miss_latency::total 83080499 # number of demand (read+write) miss cycles 687system.cpu.icache.overall_miss_latency::cpu.inst 83080499 # number of overall miss cycles 688system.cpu.icache.overall_miss_latency::total 83080499 # number of overall miss cycles 689system.cpu.icache.ReadReq_accesses::cpu.inst 289571528 # number of ReadReq accesses(hits+misses) 690system.cpu.icache.ReadReq_accesses::total 289571528 # number of ReadReq accesses(hits+misses) 691system.cpu.icache.demand_accesses::cpu.inst 289571528 # number of demand (read+write) accesses 692system.cpu.icache.demand_accesses::total 289571528 # number of demand (read+write) accesses 693system.cpu.icache.overall_accesses::cpu.inst 289571528 # number of overall (read+write) accesses 694system.cpu.icache.overall_accesses::total 289571528 # number of overall (read+write) accesses |
| 698system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 699system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 700system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 701system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 702system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 703system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses | 695system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 696system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 697system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 698system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 699system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 700system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses |
| 704system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69919.687184 # average ReadReq miss latency 705system.cpu.icache.ReadReq_avg_miss_latency::total 69919.687184 # average ReadReq miss latency 706system.cpu.icache.demand_avg_miss_latency::cpu.inst 69919.687184 # average overall miss latency 707system.cpu.icache.demand_avg_miss_latency::total 69919.687184 # average overall miss latency 708system.cpu.icache.overall_avg_miss_latency::cpu.inst 69919.687184 # average overall miss latency 709system.cpu.icache.overall_avg_miss_latency::total 69919.687184 # average overall miss latency | 701system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68775.247517 # average ReadReq miss latency 702system.cpu.icache.ReadReq_avg_miss_latency::total 68775.247517 # average ReadReq miss latency 703system.cpu.icache.demand_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency 704system.cpu.icache.demand_avg_miss_latency::total 68775.247517 # average overall miss latency 705system.cpu.icache.overall_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency 706system.cpu.icache.overall_avg_miss_latency::total 68775.247517 # average overall miss latency |
| 710system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked 711system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 712system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked 713system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 714system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked 715system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 716system.cpu.icache.fast_writes 0 # number of fast writes performed 717system.cpu.icache.cache_copies 0 # number of cache copies performed | 707system.cpu.icache.blocked_cycles::no_mshrs 202 # number of cycles access was blocked 708system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 709system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked 710system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 711system.cpu.icache.avg_blocked_cycles::no_mshrs 50.500000 # average number of cycles each access was blocked 712system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 713system.cpu.icache.fast_writes 0 # number of fast writes performed 714system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 718system.cpu.icache.ReadReq_mshr_hits::cpu.inst 412 # number of ReadReq MSHR hits 719system.cpu.icache.ReadReq_mshr_hits::total 412 # number of ReadReq MSHR hits 720system.cpu.icache.demand_mshr_hits::cpu.inst 412 # number of demand (read+write) MSHR hits 721system.cpu.icache.demand_mshr_hits::total 412 # number of demand (read+write) MSHR hits 722system.cpu.icache.overall_mshr_hits::cpu.inst 412 # number of overall MSHR hits 723system.cpu.icache.overall_mshr_hits::total 412 # number of overall MSHR hits | 715system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits 716system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits 717system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits 718system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits 719system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits 720system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits |
| 724system.cpu.icache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses 725system.cpu.icache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses 726system.cpu.icache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses 727system.cpu.icache.demand_mshr_misses::total 774 # number of demand (read+write) MSHR misses 728system.cpu.icache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses 729system.cpu.icache.overall_mshr_misses::total 774 # number of overall MSHR misses | 721system.cpu.icache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses 722system.cpu.icache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses 723system.cpu.icache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses 724system.cpu.icache.demand_mshr_misses::total 774 # number of demand (read+write) MSHR misses 725system.cpu.icache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses 726system.cpu.icache.overall_mshr_misses::total 774 # number of overall MSHR misses |
| 730system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57029751 # number of ReadReq MSHR miss cycles 731system.cpu.icache.ReadReq_mshr_miss_latency::total 57029751 # number of ReadReq MSHR miss cycles 732system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57029751 # number of demand (read+write) MSHR miss cycles 733system.cpu.icache.demand_mshr_miss_latency::total 57029751 # number of demand (read+write) MSHR miss cycles 734system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57029751 # number of overall MSHR miss cycles 735system.cpu.icache.overall_mshr_miss_latency::total 57029751 # number of overall MSHR miss cycles | 727system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56793251 # number of ReadReq MSHR miss cycles 728system.cpu.icache.ReadReq_mshr_miss_latency::total 56793251 # number of ReadReq MSHR miss cycles 729system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56793251 # number of demand (read+write) MSHR miss cycles 730system.cpu.icache.demand_mshr_miss_latency::total 56793251 # number of demand (read+write) MSHR miss cycles 731system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56793251 # number of overall MSHR miss cycles 732system.cpu.icache.overall_mshr_miss_latency::total 56793251 # number of overall MSHR miss cycles |
| 736system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 737system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 738system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 739system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 740system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 741system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses | 733system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 734system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 735system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 736system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 737system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 738system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses |
| 742system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73681.848837 # average ReadReq mshr miss latency 743system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73681.848837 # average ReadReq mshr miss latency 744system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73681.848837 # average overall mshr miss latency 745system.cpu.icache.demand_avg_mshr_miss_latency::total 73681.848837 # average overall mshr miss latency 746system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73681.848837 # average overall mshr miss latency 747system.cpu.icache.overall_avg_mshr_miss_latency::total 73681.848837 # average overall mshr miss latency | 739system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73376.293282 # average ReadReq mshr miss latency 740system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73376.293282 # average ReadReq mshr miss latency 741system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency 742system.cpu.icache.demand_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency 743system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency 744system.cpu.icache.overall_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency |
| 748system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 745system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 749system.cpu.l2cache.tags.replacements 2213583 # number of replacements 750system.cpu.l2cache.tags.tagsinuse 31532.604049 # Cycle average of tags in use 751system.cpu.l2cache.tags.total_refs 9247674 # Total number of references to valid blocks. 752system.cpu.l2cache.tags.sampled_refs 2243357 # Sample count of references to valid blocks. 753system.cpu.l2cache.tags.avg_refs 4.122248 # Average number of references to valid blocks. | 746system.cpu.l2cache.tags.replacements 2214050 # number of replacements 747system.cpu.l2cache.tags.tagsinuse 31533.035321 # Cycle average of tags in use 748system.cpu.l2cache.tags.total_refs 9245310 # Total number of references to valid blocks. 749system.cpu.l2cache.tags.sampled_refs 2243823 # Sample count of references to valid blocks. 750system.cpu.l2cache.tags.avg_refs 4.120338 # Average number of references to valid blocks. |
| 754system.cpu.l2cache.tags.warmup_cycle 21623958250 # Cycle when the warmup percentage was hit. | 751system.cpu.l2cache.tags.warmup_cycle 21623958250 # Cycle when the warmup percentage was hit. |
| 755system.cpu.l2cache.tags.occ_blocks::writebacks 14306.578053 # Average occupied blocks per requestor 756system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.421352 # Average occupied blocks per requestor 757system.cpu.l2cache.tags.occ_blocks::cpu.data 17205.604643 # Average occupied blocks per requestor 758system.cpu.l2cache.tags.occ_percent::writebacks 0.436602 # Average percentage of cache occupancy 759system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000623 # Average percentage of cache occupancy 760system.cpu.l2cache.tags.occ_percent::cpu.data 0.525073 # Average percentage of cache occupancy 761system.cpu.l2cache.tags.occ_percent::total 0.962299 # Average percentage of cache occupancy 762system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits 763system.cpu.l2cache.ReadReq_hits::cpu.data 6289369 # number of ReadReq hits 764system.cpu.l2cache.ReadReq_hits::total 6289396 # number of ReadReq hits 765system.cpu.l2cache.Writeback_hits::writebacks 3782685 # number of Writeback hits 766system.cpu.l2cache.Writeback_hits::total 3782685 # number of Writeback hits 767system.cpu.l2cache.ReadExReq_hits::cpu.data 1066821 # number of ReadExReq hits 768system.cpu.l2cache.ReadExReq_hits::total 1066821 # number of ReadExReq hits 769system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits 770system.cpu.l2cache.demand_hits::cpu.data 7356190 # number of demand (read+write) hits 771system.cpu.l2cache.demand_hits::total 7356217 # number of demand (read+write) hits 772system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits 773system.cpu.l2cache.overall_hits::cpu.data 7356190 # number of overall hits 774system.cpu.l2cache.overall_hits::total 7356217 # number of overall hits 775system.cpu.l2cache.ReadReq_misses::cpu.inst 747 # number of ReadReq misses 776system.cpu.l2cache.ReadReq_misses::cpu.data 1418939 # number of ReadReq misses 777system.cpu.l2cache.ReadReq_misses::total 1419686 # number of ReadReq misses 778system.cpu.l2cache.ReadExReq_misses::cpu.data 826593 # number of ReadExReq misses 779system.cpu.l2cache.ReadExReq_misses::total 826593 # number of ReadExReq misses 780system.cpu.l2cache.demand_misses::cpu.inst 747 # number of demand (read+write) misses 781system.cpu.l2cache.demand_misses::cpu.data 2245532 # number of demand (read+write) misses 782system.cpu.l2cache.demand_misses::total 2246279 # number of demand (read+write) misses 783system.cpu.l2cache.overall_misses::cpu.inst 747 # number of overall misses 784system.cpu.l2cache.overall_misses::cpu.data 2245532 # number of overall misses 785system.cpu.l2cache.overall_misses::total 2246279 # number of overall misses 786system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55980750 # number of ReadReq miss cycles 787system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125563538750 # number of ReadReq miss cycles 788system.cpu.l2cache.ReadReq_miss_latency::total 125619519500 # number of ReadReq miss cycles 789system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76414651500 # number of ReadExReq miss cycles 790system.cpu.l2cache.ReadExReq_miss_latency::total 76414651500 # number of ReadExReq miss cycles 791system.cpu.l2cache.demand_miss_latency::cpu.inst 55980750 # number of demand (read+write) miss cycles 792system.cpu.l2cache.demand_miss_latency::cpu.data 201978190250 # number of demand (read+write) miss cycles 793system.cpu.l2cache.demand_miss_latency::total 202034171000 # number of demand (read+write) miss cycles 794system.cpu.l2cache.overall_miss_latency::cpu.inst 55980750 # number of overall miss cycles 795system.cpu.l2cache.overall_miss_latency::cpu.data 201978190250 # number of overall miss cycles 796system.cpu.l2cache.overall_miss_latency::total 202034171000 # number of overall miss cycles | 752system.cpu.l2cache.tags.occ_blocks::writebacks 14302.277072 # Average occupied blocks per requestor 753system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.244042 # Average occupied blocks per requestor 754system.cpu.l2cache.tags.occ_blocks::cpu.data 17210.514207 # Average occupied blocks per requestor 755system.cpu.l2cache.tags.occ_percent::writebacks 0.436471 # Average percentage of cache occupancy 756system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000618 # Average percentage of cache occupancy 757system.cpu.l2cache.tags.occ_percent::cpu.data 0.525223 # Average percentage of cache occupancy 758system.cpu.l2cache.tags.occ_percent::total 0.962312 # Average percentage of cache occupancy 759system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits 760system.cpu.l2cache.ReadReq_hits::cpu.data 6288761 # number of ReadReq hits 761system.cpu.l2cache.ReadReq_hits::total 6288789 # number of ReadReq hits 762system.cpu.l2cache.Writeback_hits::writebacks 3780837 # number of Writeback hits 763system.cpu.l2cache.Writeback_hits::total 3780837 # number of Writeback hits 764system.cpu.l2cache.ReadExReq_hits::cpu.data 1066946 # number of ReadExReq hits 765system.cpu.l2cache.ReadExReq_hits::total 1066946 # number of ReadExReq hits 766system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits 767system.cpu.l2cache.demand_hits::cpu.data 7355707 # number of demand (read+write) hits 768system.cpu.l2cache.demand_hits::total 7355735 # number of demand (read+write) hits 769system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits 770system.cpu.l2cache.overall_hits::cpu.data 7355707 # number of overall hits 771system.cpu.l2cache.overall_hits::total 7355735 # number of overall hits 772system.cpu.l2cache.ReadReq_misses::cpu.inst 746 # number of ReadReq misses 773system.cpu.l2cache.ReadReq_misses::cpu.data 1419497 # number of ReadReq misses 774system.cpu.l2cache.ReadReq_misses::total 1420243 # number of ReadReq misses 775system.cpu.l2cache.ReadExReq_misses::cpu.data 826499 # number of ReadExReq misses 776system.cpu.l2cache.ReadExReq_misses::total 826499 # number of ReadExReq misses 777system.cpu.l2cache.demand_misses::cpu.inst 746 # number of demand (read+write) misses 778system.cpu.l2cache.demand_misses::cpu.data 2245996 # number of demand (read+write) misses 779system.cpu.l2cache.demand_misses::total 2246742 # number of demand (read+write) misses 780system.cpu.l2cache.overall_misses::cpu.inst 746 # number of overall misses 781system.cpu.l2cache.overall_misses::cpu.data 2245996 # number of overall misses 782system.cpu.l2cache.overall_misses::total 2246742 # number of overall misses 783system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55733750 # number of ReadReq miss cycles 784system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125730219750 # number of ReadReq miss cycles 785system.cpu.l2cache.ReadReq_miss_latency::total 125785953500 # number of ReadReq miss cycles 786system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76291008750 # number of ReadExReq miss cycles 787system.cpu.l2cache.ReadExReq_miss_latency::total 76291008750 # number of ReadExReq miss cycles 788system.cpu.l2cache.demand_miss_latency::cpu.inst 55733750 # number of demand (read+write) miss cycles 789system.cpu.l2cache.demand_miss_latency::cpu.data 202021228500 # number of demand (read+write) miss cycles 790system.cpu.l2cache.demand_miss_latency::total 202076962250 # number of demand (read+write) miss cycles 791system.cpu.l2cache.overall_miss_latency::cpu.inst 55733750 # number of overall miss cycles 792system.cpu.l2cache.overall_miss_latency::cpu.data 202021228500 # number of overall miss cycles 793system.cpu.l2cache.overall_miss_latency::total 202076962250 # number of overall miss cycles |
| 797system.cpu.l2cache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) | 794system.cpu.l2cache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses) |
| 798system.cpu.l2cache.ReadReq_accesses::cpu.data 7708308 # number of ReadReq accesses(hits+misses) 799system.cpu.l2cache.ReadReq_accesses::total 7709082 # number of ReadReq accesses(hits+misses) 800system.cpu.l2cache.Writeback_accesses::writebacks 3782685 # number of Writeback accesses(hits+misses) 801system.cpu.l2cache.Writeback_accesses::total 3782685 # number of Writeback accesses(hits+misses) 802system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893414 # number of ReadExReq accesses(hits+misses) 803system.cpu.l2cache.ReadExReq_accesses::total 1893414 # number of ReadExReq accesses(hits+misses) | 795system.cpu.l2cache.ReadReq_accesses::cpu.data 7708258 # number of ReadReq accesses(hits+misses) 796system.cpu.l2cache.ReadReq_accesses::total 7709032 # number of ReadReq accesses(hits+misses) 797system.cpu.l2cache.Writeback_accesses::writebacks 3780837 # number of Writeback accesses(hits+misses) 798system.cpu.l2cache.Writeback_accesses::total 3780837 # number of Writeback accesses(hits+misses) 799system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893445 # number of ReadExReq accesses(hits+misses) 800system.cpu.l2cache.ReadExReq_accesses::total 1893445 # number of ReadExReq accesses(hits+misses) |
| 804system.cpu.l2cache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses | 801system.cpu.l2cache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses |
| 805system.cpu.l2cache.demand_accesses::cpu.data 9601722 # number of demand (read+write) accesses 806system.cpu.l2cache.demand_accesses::total 9602496 # number of demand (read+write) accesses | 802system.cpu.l2cache.demand_accesses::cpu.data 9601703 # number of demand (read+write) accesses 803system.cpu.l2cache.demand_accesses::total 9602477 # number of demand (read+write) accesses |
| 807system.cpu.l2cache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses | 804system.cpu.l2cache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses |
| 808system.cpu.l2cache.overall_accesses::cpu.data 9601722 # number of overall (read+write) accesses 809system.cpu.l2cache.overall_accesses::total 9602496 # number of overall (read+write) accesses 810system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.965116 # miss rate for ReadReq accesses 811system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184079 # miss rate for ReadReq accesses 812system.cpu.l2cache.ReadReq_miss_rate::total 0.184158 # miss rate for ReadReq accesses 813system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436562 # miss rate for ReadExReq accesses 814system.cpu.l2cache.ReadExReq_miss_rate::total 0.436562 # miss rate for ReadExReq accesses 815system.cpu.l2cache.demand_miss_rate::cpu.inst 0.965116 # miss rate for demand accesses 816system.cpu.l2cache.demand_miss_rate::cpu.data 0.233868 # miss rate for demand accesses 817system.cpu.l2cache.demand_miss_rate::total 0.233927 # miss rate for demand accesses 818system.cpu.l2cache.overall_miss_rate::cpu.inst 0.965116 # miss rate for overall accesses 819system.cpu.l2cache.overall_miss_rate::cpu.data 0.233868 # miss rate for overall accesses 820system.cpu.l2cache.overall_miss_rate::total 0.233927 # miss rate for overall accesses 821system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74940.763052 # average ReadReq miss latency 822system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88491.146378 # average ReadReq miss latency 823system.cpu.l2cache.ReadReq_avg_miss_latency::total 88484.016536 # average ReadReq miss latency 824system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92445.316498 # average ReadExReq miss latency 825system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92445.316498 # average ReadExReq miss latency 826system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency 827system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency 828system.cpu.l2cache.demand_avg_miss_latency::total 89941.708488 # average overall miss latency 829system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74940.763052 # average overall miss latency 830system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89946.698711 # average overall miss latency 831system.cpu.l2cache.overall_avg_miss_latency::total 89941.708488 # average overall miss latency | 805system.cpu.l2cache.overall_accesses::cpu.data 9601703 # number of overall (read+write) accesses 806system.cpu.l2cache.overall_accesses::total 9602477 # number of overall (read+write) accesses 807system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963824 # miss rate for ReadReq accesses 808system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184153 # miss rate for ReadReq accesses 809system.cpu.l2cache.ReadReq_miss_rate::total 0.184231 # miss rate for ReadReq accesses 810system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436505 # miss rate for ReadExReq accesses 811system.cpu.l2cache.ReadExReq_miss_rate::total 0.436505 # miss rate for ReadExReq accesses 812system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963824 # miss rate for demand accesses 813system.cpu.l2cache.demand_miss_rate::cpu.data 0.233916 # miss rate for demand accesses 814system.cpu.l2cache.demand_miss_rate::total 0.233975 # miss rate for demand accesses 815system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963824 # miss rate for overall accesses 816system.cpu.l2cache.overall_miss_rate::cpu.data 0.233916 # miss rate for overall accesses 817system.cpu.l2cache.overall_miss_rate::total 0.233975 # miss rate for overall accesses 818system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74710.120643 # average ReadReq miss latency 819system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88573.783354 # average ReadReq miss latency 820system.cpu.l2cache.ReadReq_avg_miss_latency::total 88566.501296 # average ReadReq miss latency 821system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92306.232373 # average ReadExReq miss latency 822system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92306.232373 # average ReadExReq miss latency 823system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74710.120643 # average overall miss latency 824system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89947.278846 # average overall miss latency 825system.cpu.l2cache.demand_avg_miss_latency::total 89942.219556 # average overall miss latency 826system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74710.120643 # average overall miss latency 827system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89947.278846 # average overall miss latency 828system.cpu.l2cache.overall_avg_miss_latency::total 89942.219556 # average overall miss latency |
| 832system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 833system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 834system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 835system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 836system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 837system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 838system.cpu.l2cache.fast_writes 0 # number of fast writes performed 839system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 829system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 830system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 831system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 832system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 833system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 834system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 835system.cpu.l2cache.fast_writes 0 # number of fast writes performed 836system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 840system.cpu.l2cache.writebacks::writebacks 1100533 # number of writebacks 841system.cpu.l2cache.writebacks::total 1100533 # number of writebacks | 837system.cpu.l2cache.writebacks::writebacks 1100498 # number of writebacks 838system.cpu.l2cache.writebacks::total 1100498 # number of writebacks |
| 842system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 843system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits 844system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits 845system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 846system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits 847system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 848system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 849system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits 850system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits | 839system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 840system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits 841system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits 842system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 843system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits 844system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits 845system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 846system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits 847system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits |
| 851system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses 852system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1418932 # number of ReadReq MSHR misses 853system.cpu.l2cache.ReadReq_mshr_misses::total 1419678 # number of ReadReq MSHR misses 854system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826593 # number of ReadExReq MSHR misses 855system.cpu.l2cache.ReadExReq_mshr_misses::total 826593 # number of ReadExReq MSHR misses 856system.cpu.l2cache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses 857system.cpu.l2cache.demand_mshr_misses::cpu.data 2245525 # number of demand (read+write) MSHR misses 858system.cpu.l2cache.demand_mshr_misses::total 2246271 # number of demand (read+write) MSHR misses 859system.cpu.l2cache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses 860system.cpu.l2cache.overall_mshr_misses::cpu.data 2245525 # number of overall MSHR misses 861system.cpu.l2cache.overall_mshr_misses::total 2246271 # number of overall MSHR misses 862system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46519250 # number of ReadReq MSHR miss cycles 863system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107766607500 # number of ReadReq MSHR miss cycles 864system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107813126750 # number of ReadReq MSHR miss cycles 865system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 66030369000 # number of ReadExReq MSHR miss cycles 866system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 66030369000 # number of ReadExReq MSHR miss cycles 867system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46519250 # number of demand (read+write) MSHR miss cycles 868system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173796976500 # number of demand (read+write) MSHR miss cycles 869system.cpu.l2cache.demand_mshr_miss_latency::total 173843495750 # number of demand (read+write) MSHR miss cycles 870system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46519250 # number of overall MSHR miss cycles 871system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173796976500 # number of overall MSHR miss cycles 872system.cpu.l2cache.overall_mshr_miss_latency::total 173843495750 # number of overall MSHR miss cycles 873system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for ReadReq accesses 874system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184078 # mshr miss rate for ReadReq accesses 875system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184157 # mshr miss rate for ReadReq accesses 876system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436562 # mshr miss rate for ReadExReq accesses 877system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436562 # mshr miss rate for ReadExReq accesses 878system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for demand accesses 879system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233867 # mshr miss rate for demand accesses 880system.cpu.l2cache.demand_mshr_miss_rate::total 0.233926 # mshr miss rate for demand accesses 881system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963824 # mshr miss rate for overall accesses 882system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233867 # mshr miss rate for overall accesses 883system.cpu.l2cache.overall_mshr_miss_rate::total 0.233926 # mshr miss rate for overall accesses 884system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62358.243968 # average ReadReq mshr miss latency 885system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 75949.099393 # average ReadReq mshr miss latency 886system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 75941.957789 # average ReadReq mshr miss latency 887system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79882.564938 # average ReadExReq mshr miss latency 888system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79882.564938 # average ReadExReq mshr miss latency 889system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62358.243968 # average overall mshr miss latency 890system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77397.034769 # average overall mshr miss latency 891system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77392.040297 # average overall mshr miss latency 892system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62358.243968 # average overall mshr miss latency 893system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77397.034769 # average overall mshr miss latency 894system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77392.040297 # average overall mshr miss latency | 848system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 745 # number of ReadReq MSHR misses 849system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419490 # number of ReadReq MSHR misses 850system.cpu.l2cache.ReadReq_mshr_misses::total 1420235 # number of ReadReq MSHR misses 851system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826499 # number of ReadExReq MSHR misses 852system.cpu.l2cache.ReadExReq_mshr_misses::total 826499 # number of ReadExReq MSHR misses 853system.cpu.l2cache.demand_mshr_misses::cpu.inst 745 # number of demand (read+write) MSHR misses 854system.cpu.l2cache.demand_mshr_misses::cpu.data 2245989 # number of demand (read+write) MSHR misses 855system.cpu.l2cache.demand_mshr_misses::total 2246734 # number of demand (read+write) MSHR misses 856system.cpu.l2cache.overall_mshr_misses::cpu.inst 745 # number of overall MSHR misses 857system.cpu.l2cache.overall_mshr_misses::cpu.data 2245989 # number of overall MSHR misses 858system.cpu.l2cache.overall_mshr_misses::total 2246734 # number of overall MSHR misses 859system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46285250 # number of ReadReq MSHR miss cycles 860system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107925588000 # number of ReadReq MSHR miss cycles 861system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107971873250 # number of ReadReq MSHR miss cycles 862system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65906925250 # number of ReadExReq MSHR miss cycles 863system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65906925250 # number of ReadExReq MSHR miss cycles 864system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46285250 # number of demand (read+write) MSHR miss cycles 865system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173832513250 # number of demand (read+write) MSHR miss cycles 866system.cpu.l2cache.demand_mshr_miss_latency::total 173878798500 # number of demand (read+write) MSHR miss cycles 867system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46285250 # number of overall MSHR miss cycles 868system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173832513250 # number of overall MSHR miss cycles 869system.cpu.l2cache.overall_mshr_miss_latency::total 173878798500 # number of overall MSHR miss cycles 870system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for ReadReq accesses 871system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184152 # mshr miss rate for ReadReq accesses 872system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184230 # mshr miss rate for ReadReq accesses 873system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436505 # mshr miss rate for ReadExReq accesses 874system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436505 # mshr miss rate for ReadExReq accesses 875system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for demand accesses 876system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233916 # mshr miss rate for demand accesses 877system.cpu.l2cache.demand_mshr_miss_rate::total 0.233974 # mshr miss rate for demand accesses 878system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for overall accesses 879system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233916 # mshr miss rate for overall accesses 880system.cpu.l2cache.overall_mshr_miss_rate::total 0.233974 # mshr miss rate for overall accesses 881system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62127.852349 # average ReadReq mshr miss latency 882system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 76031.242207 # average ReadReq mshr miss latency 883system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76023.949030 # average ReadReq mshr miss latency 884system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79742.292792 # average ReadExReq mshr miss latency 885system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79742.292792 # average ReadExReq mshr miss latency 886system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency 887system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency 888system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency 889system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency 890system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency 891system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency |
| 895system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 892system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 896system.cpu.dcache.tags.replacements 9597625 # number of replacements 897system.cpu.dcache.tags.tagsinuse 4088.040332 # Cycle average of tags in use 898system.cpu.dcache.tags.total_refs 656028832 # Total number of references to valid blocks. 899system.cpu.dcache.tags.sampled_refs 9601721 # Sample count of references to valid blocks. 900system.cpu.dcache.tags.avg_refs 68.324088 # Average number of references to valid blocks. | 893system.cpu.dcache.tags.replacements 9597606 # number of replacements 894system.cpu.dcache.tags.tagsinuse 4088.041920 # Cycle average of tags in use 895system.cpu.dcache.tags.total_refs 656019476 # Total number of references to valid blocks. 896system.cpu.dcache.tags.sampled_refs 9601702 # Sample count of references to valid blocks. 897system.cpu.dcache.tags.avg_refs 68.323249 # Average number of references to valid blocks. |
| 901system.cpu.dcache.tags.warmup_cycle 3547188250 # Cycle when the warmup percentage was hit. | 898system.cpu.dcache.tags.warmup_cycle 3547188250 # Cycle when the warmup percentage was hit. |
| 902system.cpu.dcache.tags.occ_blocks::cpu.data 4088.040332 # Average occupied blocks per requestor | 899system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041920 # Average occupied blocks per requestor |
| 903system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy 904system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy | 900system.cpu.dcache.tags.occ_percent::cpu.data 0.998057 # Average percentage of cache occupancy 901system.cpu.dcache.tags.occ_percent::total 0.998057 # Average percentage of cache occupancy |
| 905system.cpu.dcache.ReadReq_hits::cpu.data 489072771 # number of ReadReq hits 906system.cpu.dcache.ReadReq_hits::total 489072771 # number of ReadReq hits 907system.cpu.dcache.WriteReq_hits::cpu.data 166955934 # number of WriteReq hits 908system.cpu.dcache.WriteReq_hits::total 166955934 # number of WriteReq hits 909system.cpu.dcache.LoadLockedReq_hits::cpu.data 66 # number of LoadLockedReq hits 910system.cpu.dcache.LoadLockedReq_hits::total 66 # number of LoadLockedReq hits | 902system.cpu.dcache.ReadReq_hits::cpu.data 489062653 # number of ReadReq hits 903system.cpu.dcache.ReadReq_hits::total 489062653 # number of ReadReq hits 904system.cpu.dcache.WriteReq_hits::cpu.data 166956698 # number of WriteReq hits 905system.cpu.dcache.WriteReq_hits::total 166956698 # number of WriteReq hits 906system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits 907system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits |
| 911system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 912system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits | 908system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 909system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits |
| 913system.cpu.dcache.demand_hits::cpu.data 656028705 # number of demand (read+write) hits 914system.cpu.dcache.demand_hits::total 656028705 # number of demand (read+write) hits 915system.cpu.dcache.overall_hits::cpu.data 656028705 # number of overall hits 916system.cpu.dcache.overall_hits::total 656028705 # number of overall hits 917system.cpu.dcache.ReadReq_misses::cpu.data 11514039 # number of ReadReq misses 918system.cpu.dcache.ReadReq_misses::total 11514039 # number of ReadReq misses 919system.cpu.dcache.WriteReq_misses::cpu.data 5630113 # number of WriteReq misses 920system.cpu.dcache.WriteReq_misses::total 5630113 # number of WriteReq misses | 910system.cpu.dcache.demand_hits::cpu.data 656019351 # number of demand (read+write) hits 911system.cpu.dcache.demand_hits::total 656019351 # number of demand (read+write) hits 912system.cpu.dcache.overall_hits::cpu.data 656019351 # number of overall hits 913system.cpu.dcache.overall_hits::total 656019351 # number of overall hits 914system.cpu.dcache.ReadReq_misses::cpu.data 11507496 # number of ReadReq misses 915system.cpu.dcache.ReadReq_misses::total 11507496 # number of ReadReq misses 916system.cpu.dcache.WriteReq_misses::cpu.data 5629349 # number of WriteReq misses 917system.cpu.dcache.WriteReq_misses::total 5629349 # number of WriteReq misses |
| 921system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 922system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses | 918system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 919system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses |
| 923system.cpu.dcache.demand_misses::cpu.data 17144152 # number of demand (read+write) misses 924system.cpu.dcache.demand_misses::total 17144152 # number of demand (read+write) misses 925system.cpu.dcache.overall_misses::cpu.data 17144152 # number of overall misses 926system.cpu.dcache.overall_misses::total 17144152 # number of overall misses 927system.cpu.dcache.ReadReq_miss_latency::cpu.data 363445631238 # number of ReadReq miss cycles 928system.cpu.dcache.ReadReq_miss_latency::total 363445631238 # number of ReadReq miss cycles 929system.cpu.dcache.WriteReq_miss_latency::cpu.data 307798034677 # number of WriteReq miss cycles 930system.cpu.dcache.WriteReq_miss_latency::total 307798034677 # number of WriteReq miss cycles 931system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 225500 # number of LoadLockedReq miss cycles 932system.cpu.dcache.LoadLockedReq_miss_latency::total 225500 # number of LoadLockedReq miss cycles 933system.cpu.dcache.demand_miss_latency::cpu.data 671243665915 # number of demand (read+write) miss cycles 934system.cpu.dcache.demand_miss_latency::total 671243665915 # number of demand (read+write) miss cycles 935system.cpu.dcache.overall_miss_latency::cpu.data 671243665915 # number of overall miss cycles 936system.cpu.dcache.overall_miss_latency::total 671243665915 # number of overall miss cycles 937system.cpu.dcache.ReadReq_accesses::cpu.data 500586810 # number of ReadReq accesses(hits+misses) 938system.cpu.dcache.ReadReq_accesses::total 500586810 # number of ReadReq accesses(hits+misses) | 920system.cpu.dcache.demand_misses::cpu.data 17136845 # number of demand (read+write) misses 921system.cpu.dcache.demand_misses::total 17136845 # number of demand (read+write) misses 922system.cpu.dcache.overall_misses::cpu.data 17136845 # number of overall misses 923system.cpu.dcache.overall_misses::total 17136845 # number of overall misses 924system.cpu.dcache.ReadReq_miss_latency::cpu.data 363702842488 # number of ReadReq miss cycles 925system.cpu.dcache.ReadReq_miss_latency::total 363702842488 # number of ReadReq miss cycles 926system.cpu.dcache.WriteReq_miss_latency::cpu.data 307744962906 # number of WriteReq miss cycles 927system.cpu.dcache.WriteReq_miss_latency::total 307744962906 # number of WriteReq miss cycles 928system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles 929system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles 930system.cpu.dcache.demand_miss_latency::cpu.data 671447805394 # number of demand (read+write) miss cycles 931system.cpu.dcache.demand_miss_latency::total 671447805394 # number of demand (read+write) miss cycles 932system.cpu.dcache.overall_miss_latency::cpu.data 671447805394 # number of overall miss cycles 933system.cpu.dcache.overall_miss_latency::total 671447805394 # number of overall miss cycles 934system.cpu.dcache.ReadReq_accesses::cpu.data 500570149 # number of ReadReq accesses(hits+misses) 935system.cpu.dcache.ReadReq_accesses::total 500570149 # number of ReadReq accesses(hits+misses) |
| 939system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 940system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) | 936system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 937system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) |
| 941system.cpu.dcache.LoadLockedReq_accesses::cpu.data 69 # number of LoadLockedReq accesses(hits+misses) 942system.cpu.dcache.LoadLockedReq_accesses::total 69 # number of LoadLockedReq accesses(hits+misses) | 938system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses) 939system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses) |
| 943system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 944system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) | 940system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 941system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) |
| 945system.cpu.dcache.demand_accesses::cpu.data 673172857 # number of demand (read+write) accesses 946system.cpu.dcache.demand_accesses::total 673172857 # number of demand (read+write) accesses 947system.cpu.dcache.overall_accesses::cpu.data 673172857 # number of overall (read+write) accesses 948system.cpu.dcache.overall_accesses::total 673172857 # number of overall (read+write) accesses 949system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023001 # miss rate for ReadReq accesses 950system.cpu.dcache.ReadReq_miss_rate::total 0.023001 # miss rate for ReadReq accesses 951system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032622 # miss rate for WriteReq accesses 952system.cpu.dcache.WriteReq_miss_rate::total 0.032622 # miss rate for WriteReq accesses 953system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.043478 # miss rate for LoadLockedReq accesses 954system.cpu.dcache.LoadLockedReq_miss_rate::total 0.043478 # miss rate for LoadLockedReq accesses 955system.cpu.dcache.demand_miss_rate::cpu.data 0.025468 # miss rate for demand accesses 956system.cpu.dcache.demand_miss_rate::total 0.025468 # miss rate for demand accesses 957system.cpu.dcache.overall_miss_rate::cpu.data 0.025468 # miss rate for overall accesses 958system.cpu.dcache.overall_miss_rate::total 0.025468 # miss rate for overall accesses 959system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31565.433402 # average ReadReq miss latency 960system.cpu.dcache.ReadReq_avg_miss_latency::total 31565.433402 # average ReadReq miss latency 961system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54669.956833 # average WriteReq miss latency 962system.cpu.dcache.WriteReq_avg_miss_latency::total 54669.956833 # average WriteReq miss latency 963system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 75166.666667 # average LoadLockedReq miss latency 964system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 75166.666667 # average LoadLockedReq miss latency 965system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency 966system.cpu.dcache.demand_avg_miss_latency::total 39152.923161 # average overall miss latency 967system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.923161 # average overall miss latency 968system.cpu.dcache.overall_avg_miss_latency::total 39152.923161 # average overall miss latency 969system.cpu.dcache.blocked_cycles::no_mshrs 24614592 # number of cycles access was blocked 970system.cpu.dcache.blocked_cycles::no_targets 3988980 # number of cycles access was blocked 971system.cpu.dcache.blocked::no_mshrs 1212230 # number of cycles access was blocked 972system.cpu.dcache.blocked::no_targets 65133 # number of cycles access was blocked 973system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.305216 # average number of cycles each access was blocked 974system.cpu.dcache.avg_blocked_cycles::no_targets 61.243609 # average number of cycles each access was blocked | 942system.cpu.dcache.demand_accesses::cpu.data 673156196 # number of demand (read+write) accesses 943system.cpu.dcache.demand_accesses::total 673156196 # number of demand (read+write) accesses 944system.cpu.dcache.overall_accesses::cpu.data 673156196 # number of overall (read+write) accesses 945system.cpu.dcache.overall_accesses::total 673156196 # number of overall (read+write) accesses 946system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses 947system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses 948system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032618 # miss rate for WriteReq accesses 949system.cpu.dcache.WriteReq_miss_rate::total 0.032618 # miss rate for WriteReq accesses 950system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses 951system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses 952system.cpu.dcache.demand_miss_rate::cpu.data 0.025457 # miss rate for demand accesses 953system.cpu.dcache.demand_miss_rate::total 0.025457 # miss rate for demand accesses 954system.cpu.dcache.overall_miss_rate::cpu.data 0.025457 # miss rate for overall accesses 955system.cpu.dcache.overall_miss_rate::total 0.025457 # miss rate for overall accesses 956system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31605.732688 # average ReadReq miss latency 957system.cpu.dcache.ReadReq_avg_miss_latency::total 31605.732688 # average ReadReq miss latency 958system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54667.948799 # average WriteReq miss latency 959system.cpu.dcache.WriteReq_avg_miss_latency::total 54667.948799 # average WriteReq miss latency 960system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency 961system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency 962system.cpu.dcache.demand_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency 963system.cpu.dcache.demand_avg_miss_latency::total 39181.529937 # average overall miss latency 964system.cpu.dcache.overall_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency 965system.cpu.dcache.overall_avg_miss_latency::total 39181.529937 # average overall miss latency 966system.cpu.dcache.blocked_cycles::no_mshrs 24597243 # number of cycles access was blocked 967system.cpu.dcache.blocked_cycles::no_targets 3988018 # number of cycles access was blocked 968system.cpu.dcache.blocked::no_mshrs 1212289 # number of cycles access was blocked 969system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked 970system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.289917 # average number of cycles each access was blocked 971system.cpu.dcache.avg_blocked_cycles::no_targets 61.230720 # average number of cycles each access was blocked |
| 975system.cpu.dcache.fast_writes 0 # number of fast writes performed 976system.cpu.dcache.cache_copies 0 # number of cache copies performed | 972system.cpu.dcache.fast_writes 0 # number of fast writes performed 973system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 977system.cpu.dcache.writebacks::writebacks 3782685 # number of writebacks 978system.cpu.dcache.writebacks::total 3782685 # number of writebacks 979system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3805731 # number of ReadReq MSHR hits 980system.cpu.dcache.ReadReq_mshr_hits::total 3805731 # number of ReadReq MSHR hits 981system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736699 # number of WriteReq MSHR hits 982system.cpu.dcache.WriteReq_mshr_hits::total 3736699 # number of WriteReq MSHR hits | 974system.cpu.dcache.writebacks::writebacks 3780837 # number of writebacks 975system.cpu.dcache.writebacks::total 3780837 # number of writebacks 976system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3799238 # number of ReadReq MSHR hits 977system.cpu.dcache.ReadReq_mshr_hits::total 3799238 # number of ReadReq MSHR hits 978system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3735904 # number of WriteReq MSHR hits 979system.cpu.dcache.WriteReq_mshr_hits::total 3735904 # number of WriteReq MSHR hits |
| 983system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 984system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits | 980system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 981system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits |
| 985system.cpu.dcache.demand_mshr_hits::cpu.data 7542430 # number of demand (read+write) MSHR hits 986system.cpu.dcache.demand_mshr_hits::total 7542430 # number of demand (read+write) MSHR hits 987system.cpu.dcache.overall_mshr_hits::cpu.data 7542430 # number of overall MSHR hits 988system.cpu.dcache.overall_mshr_hits::total 7542430 # number of overall MSHR hits 989system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708308 # number of ReadReq MSHR misses 990system.cpu.dcache.ReadReq_mshr_misses::total 7708308 # number of ReadReq MSHR misses 991system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893414 # number of WriteReq MSHR misses 992system.cpu.dcache.WriteReq_mshr_misses::total 1893414 # number of WriteReq MSHR misses 993system.cpu.dcache.demand_mshr_misses::cpu.data 9601722 # number of demand (read+write) MSHR misses 994system.cpu.dcache.demand_mshr_misses::total 9601722 # number of demand (read+write) MSHR misses 995system.cpu.dcache.overall_mshr_misses::cpu.data 9601722 # number of overall MSHR misses 996system.cpu.dcache.overall_mshr_misses::total 9601722 # number of overall MSHR misses 997system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198054864257 # number of ReadReq MSHR miss cycles 998system.cpu.dcache.ReadReq_mshr_miss_latency::total 198054864257 # number of ReadReq MSHR miss cycles 999system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89469568032 # number of WriteReq MSHR miss cycles 1000system.cpu.dcache.WriteReq_mshr_miss_latency::total 89469568032 # number of WriteReq MSHR miss cycles 1001system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287524432289 # number of demand (read+write) MSHR miss cycles 1002system.cpu.dcache.demand_mshr_miss_latency::total 287524432289 # number of demand (read+write) MSHR miss cycles 1003system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287524432289 # number of overall MSHR miss cycles 1004system.cpu.dcache.overall_mshr_miss_latency::total 287524432289 # number of overall MSHR miss cycles | 982system.cpu.dcache.demand_mshr_hits::cpu.data 7535142 # number of demand (read+write) MSHR hits 983system.cpu.dcache.demand_mshr_hits::total 7535142 # number of demand (read+write) MSHR hits 984system.cpu.dcache.overall_mshr_hits::cpu.data 7535142 # number of overall MSHR hits 985system.cpu.dcache.overall_mshr_hits::total 7535142 # number of overall MSHR hits 986system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708258 # number of ReadReq MSHR misses 987system.cpu.dcache.ReadReq_mshr_misses::total 7708258 # number of ReadReq MSHR misses 988system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893445 # number of WriteReq MSHR misses 989system.cpu.dcache.WriteReq_mshr_misses::total 1893445 # number of WriteReq MSHR misses 990system.cpu.dcache.demand_mshr_misses::cpu.data 9601703 # number of demand (read+write) MSHR misses 991system.cpu.dcache.demand_mshr_misses::total 9601703 # number of demand (read+write) MSHR misses 992system.cpu.dcache.overall_mshr_misses::cpu.data 9601703 # number of overall MSHR misses 993system.cpu.dcache.overall_mshr_misses::total 9601703 # number of overall MSHR misses 994system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198213123757 # number of ReadReq MSHR miss cycles 995system.cpu.dcache.ReadReq_mshr_miss_latency::total 198213123757 # number of ReadReq MSHR miss cycles 996system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89346986214 # number of WriteReq MSHR miss cycles 997system.cpu.dcache.WriteReq_mshr_miss_latency::total 89346986214 # number of WriteReq MSHR miss cycles 998system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287560109971 # number of demand (read+write) MSHR miss cycles 999system.cpu.dcache.demand_mshr_miss_latency::total 287560109971 # number of demand (read+write) MSHR miss cycles 1000system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287560109971 # number of overall MSHR miss cycles 1001system.cpu.dcache.overall_mshr_miss_latency::total 287560109971 # number of overall MSHR miss cycles |
| 1005system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses 1006system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses 1007system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses 1008system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses | 1002system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses 1003system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses 1004system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses 1005system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses |
| 1009system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for demand accesses 1010system.cpu.dcache.demand_mshr_miss_rate::total 0.014263 # mshr miss rate for demand accesses 1011system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014263 # mshr miss rate for overall accesses 1012system.cpu.dcache.overall_mshr_miss_rate::total 0.014263 # mshr miss rate for overall accesses 1013system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25693.688454 # average ReadReq mshr miss latency 1014system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25693.688454 # average ReadReq mshr miss latency 1015system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47253.040292 # average WriteReq mshr miss latency 1016system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47253.040292 # average WriteReq mshr miss latency 1017system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency 1018system.cpu.dcache.demand_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency 1019system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29945.090296 # average overall mshr miss latency 1020system.cpu.dcache.overall_avg_mshr_miss_latency::total 29945.090296 # average overall mshr miss latency | 1006system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for demand accesses 1007system.cpu.dcache.demand_mshr_miss_rate::total 0.014264 # mshr miss rate for demand accesses 1008system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for overall accesses 1009system.cpu.dcache.overall_mshr_miss_rate::total 0.014264 # mshr miss rate for overall accesses 1010system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25714.386280 # average ReadReq mshr miss latency 1011system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25714.386280 # average ReadReq mshr miss latency 1012system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47187.526553 # average WriteReq mshr miss latency 1013system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47187.526553 # average WriteReq mshr miss latency 1014system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency 1015system.cpu.dcache.demand_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency 1016system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency 1017system.cpu.dcache.overall_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency |
| 1021system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1022 1023---------- End Simulation Statistics ---------- | 1018system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1019 1020---------- End Simulation Statistics ---------- |