| stats.txt (9322:01c8c5ff2c3b) | stats.txt (9348:44d31345e360) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.515058 # Number of seconds simulated 4sim_ticks 515058060000 # Number of ticks simulated 5final_tick 515058060000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.506343 # Number of seconds simulated 4sim_ticks 506342716000 # Number of ticks simulated 5final_tick 506342716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 166099 # Simulator instruction rate (inst/s) 8host_op_rate 185296 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 55388247 # Simulator tick rate (ticks/s) 10host_mem_usage 494292 # Number of bytes of host memory used 11host_seconds 9299.05 # Real time elapsed on the host 12sim_insts 1544563078 # Number of instructions simulated 13sim_ops 1723073890 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 48320 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 144392128 # Number of bytes read from this memory 16system.physmem.bytes_read::total 144440448 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 48320 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 48320 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 70617600 # Number of bytes written to this memory 20system.physmem.bytes_written::total 70617600 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 755 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2256127 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2256882 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1103400 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1103400 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 93815 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 280341459 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 280435274 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 93815 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 93815 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 137106096 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 137106096 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 137106096 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 93815 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 280341459 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 417541370 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 2256882 # Total number of read requests seen 38system.physmem.writeReqs 1103400 # Total number of write requests seen 39system.physmem.cpureqs 3360282 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 144440448 # Total number of bytes read from memory 41system.physmem.bytesWritten 70617600 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 144440448 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 70617600 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 637 # Number of read reqs serviced by write Q | 7host_inst_rate 134396 # Simulator instruction rate (inst/s) 8host_op_rate 149928 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 44057957 # Simulator tick rate (ticks/s) 10host_mem_usage 522896 # Number of bytes of host memory used 11host_seconds 11492.65 # Real time elapsed on the host 12sim_insts 1544563043 # Number of instructions simulated 13sim_ops 1723073855 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 47744 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 143751360 # Number of bytes read from this memory 16system.physmem.bytes_read::total 143799104 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 47744 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 47744 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 70435456 # Number of bytes written to this memory 20system.physmem.bytes_written::total 70435456 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 746 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2246115 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2246861 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1100554 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1100554 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 94292 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 283901309 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 283995601 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 94292 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 94292 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 139106289 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 139106289 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 139106289 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 94292 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 283901309 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 423101890 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 2246861 # Total number of read requests seen 38system.physmem.writeReqs 1100554 # Total number of write requests seen 39system.physmem.cpureqs 3347415 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 143799104 # Total number of bytes read from memory 41system.physmem.bytesWritten 70435456 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 143799104 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 70435456 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 613 # Number of read reqs serviced by write Q |
| 45system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed | 45system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed |
| 46system.physmem.perBankRdReqs::0 140407 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 144367 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 142491 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 141453 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 138510 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 140931 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 142120 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 141749 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 141832 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 140373 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 140948 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 141413 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 137790 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 141680 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 139536 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 140645 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 69366 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 70506 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 69820 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 68968 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 67927 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 68673 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 68853 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 68680 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 68439 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 68530 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 68800 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 68663 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 67351 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 70531 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 69216 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 69077 # Track writes on a per bank basis | 46system.physmem.perBankRdReqs::0 139880 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 143856 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 141905 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 140877 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 137960 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 140233 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 141491 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 140982 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 141233 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 139496 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 140455 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 140890 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 137116 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 141034 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 138952 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 139888 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 69217 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 70379 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 69592 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 68832 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 67727 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 68464 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 68713 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 68501 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 68243 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 68230 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 68643 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 68550 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 67188 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 70321 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 69053 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 68901 # Track writes on a per bank basis |
| 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 80system.physmem.totGap 515058007000 # Total gap between requests | 80system.physmem.totGap 506342647500 # Total gap between requests |
| 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes | 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 87system.physmem.readPktSize::6 2256882 # Categorize read packet sizes | 87system.physmem.readPktSize::6 2246861 # Categorize read packet sizes |
| 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes | 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes |
| 96system.physmem.writePktSize::6 1103400 # categorize write packet sizes | 96system.physmem.writePktSize::6 1100554 # categorize write packet sizes |
| 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes | 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| 108system.physmem.rdQLenPdf::0 1580398 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 450395 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 158442 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 66982 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 24 # What read queue length does an incoming req see | 108system.physmem.rdQLenPdf::0 1577627 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 446326 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 156341 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 65934 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see |
| 113system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see | 113system.physmem.rdQLenPdf::5 4 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see |
| 141system.physmem.wrQLenPdf::0 45630 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 47618 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 47927 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 47968 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 47973 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 47974 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 47974 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 47974 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 47974 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 47974 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 47974 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 47974 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 47974 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 47974 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 47974 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 47974 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 47974 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 47974 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 47974 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 47974 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 47974 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 47973 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 47973 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 2344 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 356 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 47 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see | 141system.physmem.wrQLenPdf::0 45498 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 47479 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 47800 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 47843 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 47850 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 47850 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 47850 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 47850 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 47850 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 47850 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 47850 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 47850 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 47850 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 47850 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 47850 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 47850 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 47850 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 47850 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 47850 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 47850 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 47850 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 47850 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 47850 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 2353 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 372 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 51 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 8 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| 174system.physmem.totQLat 27231628654 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 103251704654 # Sum of mem lat for all requests 176system.physmem.totBusLat 9024980000 # Total cycles spent in databus access 177system.physmem.totBankLat 66995096000 # Total cycles spent in bank access 178system.physmem.avgQLat 12069.45 # Average queueing delay per request 179system.physmem.avgBankLat 29693.18 # Average bank access latency per request | 174system.physmem.totQLat 27053022176 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 102785772176 # Sum of mem lat for all requests 176system.physmem.totBusLat 8984992000 # Total cycles spent in databus access 177system.physmem.totBankLat 66747758000 # Total cycles spent in bank access 178system.physmem.avgQLat 12043.65 # Average queueing delay per request 179system.physmem.avgBankLat 29715.22 # Average bank access latency per request |
| 180system.physmem.avgBusLat 4000.00 # Average bus latency per request | 180system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| 181system.physmem.avgMemAccLat 45762.63 # Average memory access latency 182system.physmem.avgRdBW 280.44 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 137.11 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 280.44 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 137.11 # Average consumed write bandwidth in MB/s | 181system.physmem.avgMemAccLat 45758.87 # Average memory access latency 182system.physmem.avgRdBW 284.00 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 139.11 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 284.00 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 139.11 # Average consumed write bandwidth in MB/s |
| 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s | 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s |
| 187system.physmem.busUtil 2.61 # Data bus utilization in percentage | 187system.physmem.busUtil 2.64 # Data bus utilization in percentage |
| 188system.physmem.avgRdQLen 0.20 # Average read queue length over time | 188system.physmem.avgRdQLen 0.20 # Average read queue length over time |
| 189system.physmem.avgWrQLen 11.32 # Average write queue length over time 190system.physmem.readRowHits 919391 # Number of row buffer hits during reads 191system.physmem.writeRowHits 189315 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 40.75 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 17.16 # Row buffer hit rate for writes 194system.physmem.avgGap 153278.21 # Average gap between requests | 189system.physmem.avgWrQLen 10.20 # Average write queue length over time 190system.physmem.readRowHits 914443 # Number of row buffer hits during reads 191system.physmem.writeRowHits 189193 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 40.71 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 17.19 # Row buffer hit rate for writes 194system.physmem.avgGap 151263.78 # Average gap between requests |
| 195system.cpu.dtb.inst_hits 0 # ITB inst hits 196system.cpu.dtb.inst_misses 0 # ITB inst misses 197system.cpu.dtb.read_hits 0 # DTB read hits 198system.cpu.dtb.read_misses 0 # DTB read misses 199system.cpu.dtb.write_hits 0 # DTB write hits 200system.cpu.dtb.write_misses 0 # DTB write misses 201system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 202system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 230system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu.itb.read_accesses 0 # DTB read accesses 232system.cpu.itb.write_accesses 0 # DTB write accesses 233system.cpu.itb.inst_accesses 0 # ITB inst accesses 234system.cpu.itb.hits 0 # DTB hits 235system.cpu.itb.misses 0 # DTB misses 236system.cpu.itb.accesses 0 # DTB accesses 237system.cpu.workload.num_syscalls 46 # Number of system calls | 195system.cpu.dtb.inst_hits 0 # ITB inst hits 196system.cpu.dtb.inst_misses 0 # ITB inst misses 197system.cpu.dtb.read_hits 0 # DTB read hits 198system.cpu.dtb.read_misses 0 # DTB read misses 199system.cpu.dtb.write_hits 0 # DTB write hits 200system.cpu.dtb.write_misses 0 # DTB write misses 201system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 202system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 230system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu.itb.read_accesses 0 # DTB read accesses 232system.cpu.itb.write_accesses 0 # DTB write accesses 233system.cpu.itb.inst_accesses 0 # ITB inst accesses 234system.cpu.itb.hits 0 # DTB hits 235system.cpu.itb.misses 0 # DTB misses 236system.cpu.itb.accesses 0 # DTB accesses 237system.cpu.workload.num_syscalls 46 # Number of system calls |
| 238system.cpu.numCycles 1030116121 # number of cpu cycles simulated | 238system.cpu.numCycles 1012685433 # number of cpu cycles simulated |
| 239system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 240system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 239system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 240system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 241system.cpu.BPredUnit.lookups 307748972 # Number of BP lookups 242system.cpu.BPredUnit.condPredicted 253170818 # Number of conditional branches predicted 243system.cpu.BPredUnit.condIncorrect 16168830 # Number of conditional branches incorrect 244system.cpu.BPredUnit.BTBLookups 178836343 # Number of BTB lookups 245system.cpu.BPredUnit.BTBHits 162524431 # Number of BTB hits | 241system.cpu.BPredUnit.lookups 301954621 # Number of BP lookups 242system.cpu.BPredUnit.condPredicted 248216809 # Number of conditional branches predicted 243system.cpu.BPredUnit.condIncorrect 15201913 # Number of conditional branches incorrect 244system.cpu.BPredUnit.BTBLookups 174080905 # Number of BTB lookups 245system.cpu.BPredUnit.BTBHits 160275912 # Number of BTB hits |
| 246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 247system.cpu.BPredUnit.usedRAS 18394581 # Number of times the RAS was used to get a target. 248system.cpu.BPredUnit.RASInCorrect 234 # Number of incorrect RAS predictions. 249system.cpu.fetch.icacheStallCycles 302711500 # Number of cycles fetch is stalled on an Icache miss 250system.cpu.fetch.Insts 2208582342 # Number of instructions fetch has processed 251system.cpu.fetch.Branches 307748972 # Number of branches that fetch encountered 252system.cpu.fetch.predictedBranches 180919012 # Number of branches that fetch has predicted taken 253system.cpu.fetch.Cycles 439713036 # Number of cycles fetch has run and was not squashing or blocked 254system.cpu.fetch.SquashCycles 91477277 # Number of cycles fetch has spent squashing 255system.cpu.fetch.BlockedCycles 153604124 # Number of cycles fetch has spent blocked 256system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 257system.cpu.fetch.PendingTrapStallCycles 69 # Number of stall cycles due to pending traps 258system.cpu.fetch.IcacheWaitRetryStallCycles 9 # Number of stall cycles due to full MSHR 259system.cpu.fetch.CacheLines 292882660 # Number of cache lines fetched 260system.cpu.fetch.IcacheSquashes 6106896 # Number of outstanding Icache misses that were squashed 261system.cpu.fetch.rateDist::samples 969047070 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::mean 2.529561 # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::stdev 3.216174 # Number of instructions fetched each cycle (Total) | 247system.cpu.BPredUnit.usedRAS 17543051 # Number of times the RAS was used to get a target. 248system.cpu.BPredUnit.RASInCorrect 217 # Number of incorrect RAS predictions. 249system.cpu.fetch.icacheStallCycles 296171329 # Number of cycles fetch is stalled on an Icache miss 250system.cpu.fetch.Insts 2177000343 # Number of instructions fetch has processed 251system.cpu.fetch.Branches 301954621 # Number of branches that fetch encountered 252system.cpu.fetch.predictedBranches 177818963 # Number of branches that fetch has predicted taken 253system.cpu.fetch.Cycles 433079666 # Number of cycles fetch has run and was not squashing or blocked 254system.cpu.fetch.SquashCycles 86445035 # Number of cycles fetch has spent squashing 255system.cpu.fetch.BlockedCycles 152984584 # Number of cycles fetch has spent blocked 256system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 257system.cpu.fetch.PendingTrapStallCycles 67 # Number of stall cycles due to pending traps 258system.cpu.fetch.CacheLines 286733341 # Number of cache lines fetched 259system.cpu.fetch.IcacheSquashes 5527590 # Number of outstanding Icache misses that were squashed 260system.cpu.fetch.rateDist::samples 951199831 # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::mean 2.533171 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::stdev 3.216208 # Number of instructions fetched each cycle (Total) |
| 264system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 263system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 265system.cpu.fetch.rateDist::0 529334144 54.62% 54.62% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::1 25043926 2.58% 57.21% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::2 39264186 4.05% 61.26% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::3 48337631 4.99% 66.25% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::4 43062270 4.44% 70.69% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::5 47882627 4.94% 75.63% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::6 39313310 4.06% 79.69% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::7 19335068 2.00% 81.69% # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::8 177473908 18.31% 100.00% # Number of instructions fetched each cycle (Total) | 264system.cpu.fetch.rateDist::0 518120232 54.47% 54.47% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::1 25036737 2.63% 57.10% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::2 39011944 4.10% 61.20% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::3 48247673 5.07% 66.28% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::4 42552998 4.47% 70.75% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::5 46316076 4.87% 75.62% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::6 38402395 4.04% 79.66% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::7 18552878 1.95% 81.61% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::8 174958898 18.39% 100.00% # Number of instructions fetched each cycle (Total) |
| 274system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 273system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 277system.cpu.fetch.rateDist::total 969047070 # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.branchRate 0.298752 # Number of branch fetches per cycle 279system.cpu.fetch.rate 2.144013 # Number of inst fetches per cycle 280system.cpu.decode.IdleCycles 334775915 # Number of cycles decode is idle 281system.cpu.decode.BlockedCycles 131820236 # Number of cycles decode is blocked 282system.cpu.decode.RunCycles 409429631 # Number of cycles decode is running 283system.cpu.decode.UnblockCycles 20003640 # Number of cycles decode is unblocking 284system.cpu.decode.SquashCycles 73017648 # Number of cycles decode is squashing 285system.cpu.decode.BranchResolved 46459880 # Number of times decode resolved a branch 286system.cpu.decode.BranchMispred 721 # Number of times decode detected a branch misprediction 287system.cpu.decode.DecodedInsts 2395467722 # Number of instructions handled by decode 288system.cpu.decode.SquashedInsts 2521 # Number of squashed instructions handled by decode 289system.cpu.rename.SquashCycles 73017648 # Number of cycles rename is squashing 290system.cpu.rename.IdleCycles 358478616 # Number of cycles rename is idle 291system.cpu.rename.BlockCycles 61310545 # Number of cycles rename is blocking 292system.cpu.rename.serializeStallCycles 17059 # count of cycles rename stalled for serializing inst 293system.cpu.rename.RunCycles 404218624 # Number of cycles rename is running 294system.cpu.rename.UnblockCycles 72004578 # Number of cycles rename is unblocking 295system.cpu.rename.RenamedInsts 2331266224 # Number of instructions processed by rename 296system.cpu.rename.ROBFullEvents 128849 # Number of times rename has blocked due to ROB full 297system.cpu.rename.IQFullEvents 5208113 # Number of times rename has blocked due to IQ full 298system.cpu.rename.LSQFullEvents 58805545 # Number of times rename has blocked due to LSQ full 299system.cpu.rename.FullRegisterEvents 5 # Number of times there has been no free registers 300system.cpu.rename.RenamedOperands 2308002536 # Number of destination operands rename has renamed 301system.cpu.rename.RenameLookups 10761064902 # Number of register rename lookups that rename has made 302system.cpu.rename.int_rename_lookups 10761060796 # Number of integer rename lookups 303system.cpu.rename.fp_rename_lookups 4106 # Number of floating rename lookups 304system.cpu.rename.CommittedMaps 1706320018 # Number of HB maps that are committed 305system.cpu.rename.UndoneMaps 601682518 # Number of HB maps that are undone due to squashing 306system.cpu.rename.serializingInsts 1074 # count of serializing insts renamed 307system.cpu.rename.tempSerializingInsts 1071 # count of temporary serializing insts renamed 308system.cpu.rename.skidInsts 160130696 # count of insts added to the skid buffer 309system.cpu.memDep0.insertedLoads 634128265 # Number of loads inserted to the mem dependence unit. 310system.cpu.memDep0.insertedStores 221560674 # Number of stores inserted to the mem dependence unit. 311system.cpu.memDep0.conflictingLoads 87711423 # Number of conflicting loads. 312system.cpu.memDep0.conflictingStores 69100091 # Number of conflicting stores. 313system.cpu.iq.iqInstsAdded 2223438682 # Number of instructions added to the IQ (excludes non-spec) 314system.cpu.iq.iqNonSpecInstsAdded 1093 # Number of non-speculative instructions added to the IQ 315system.cpu.iq.iqInstsIssued 2032725138 # Number of instructions issued 316system.cpu.iq.iqSquashedInstsIssued 5162970 # Number of squashed instructions issued 317system.cpu.iq.iqSquashedInstsExamined 495697928 # Number of squashed instructions iterated over during squash; mainly for profiling 318system.cpu.iq.iqSquashedOperandsExamined 1172411676 # Number of squashed operands that are examined and possibly removed from graph 319system.cpu.iq.iqSquashedNonSpecRemoved 912 # Number of squashed non-spec instructions that were removed 320system.cpu.iq.issued_per_cycle::samples 969047070 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::mean 2.097654 # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::stdev 1.906175 # Number of insts issued each cycle | 276system.cpu.fetch.rateDist::total 951199831 # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.branchRate 0.298172 # Number of branch fetches per cycle 278system.cpu.fetch.rate 2.149730 # Number of inst fetches per cycle 279system.cpu.decode.IdleCycles 327457175 # Number of cycles decode is idle 280system.cpu.decode.BlockedCycles 131287653 # Number of cycles decode is blocked 281system.cpu.decode.RunCycles 403449648 # Number of cycles decode is running 282system.cpu.decode.UnblockCycles 20041830 # Number of cycles decode is unblocking 283system.cpu.decode.SquashCycles 68963525 # Number of cycles decode is squashing 284system.cpu.decode.BranchResolved 46005772 # Number of times decode resolved a branch 285system.cpu.decode.BranchMispred 694 # Number of times decode detected a branch misprediction 286system.cpu.decode.DecodedInsts 2358153457 # Number of instructions handled by decode 287system.cpu.decode.SquashedInsts 2386 # Number of squashed instructions handled by decode 288system.cpu.rename.SquashCycles 68963525 # Number of cycles rename is squashing 289system.cpu.rename.IdleCycles 350605393 # Number of cycles rename is idle 290system.cpu.rename.BlockCycles 61238175 # Number of cycles rename is blocking 291system.cpu.rename.serializeStallCycles 13721 # count of cycles rename stalled for serializing inst 292system.cpu.rename.RunCycles 398828619 # Number of cycles rename is running 293system.cpu.rename.UnblockCycles 71550398 # Number of cycles rename is unblocking 294system.cpu.rename.RenamedInsts 2297300888 # Number of instructions processed by rename 295system.cpu.rename.ROBFullEvents 126992 # Number of times rename has blocked due to ROB full 296system.cpu.rename.IQFullEvents 5036459 # Number of times rename has blocked due to IQ full 297system.cpu.rename.LSQFullEvents 58395724 # Number of times rename has blocked due to LSQ full 298system.cpu.rename.FullRegisterEvents 6 # Number of times there has been no free registers 299system.cpu.rename.RenamedOperands 2272291937 # Number of destination operands rename has renamed 300system.cpu.rename.RenameLookups 10608987199 # Number of register rename lookups that rename has made 301system.cpu.rename.int_rename_lookups 10608983762 # Number of integer rename lookups 302system.cpu.rename.fp_rename_lookups 3437 # Number of floating rename lookups 303system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed 304system.cpu.rename.UndoneMaps 565971975 # Number of HB maps that are undone due to squashing 305system.cpu.rename.serializingInsts 462 # count of serializing insts renamed 306system.cpu.rename.tempSerializingInsts 459 # count of temporary serializing insts renamed 307system.cpu.rename.skidInsts 158423553 # count of insts added to the skid buffer 308system.cpu.memDep0.insertedLoads 623142693 # Number of loads inserted to the mem dependence unit. 309system.cpu.memDep0.insertedStores 220479196 # Number of stores inserted to the mem dependence unit. 310system.cpu.memDep0.conflictingLoads 86005454 # Number of conflicting loads. 311system.cpu.memDep0.conflictingStores 70775057 # Number of conflicting stores. 312system.cpu.iq.iqInstsAdded 2196663707 # Number of instructions added to the IQ (excludes non-spec) 313system.cpu.iq.iqNonSpecInstsAdded 506 # Number of non-speculative instructions added to the IQ 314system.cpu.iq.iqInstsIssued 2016028881 # Number of instructions issued 315system.cpu.iq.iqSquashedInstsIssued 3978647 # Number of squashed instructions issued 316system.cpu.iq.iqSquashedInstsExamined 469035072 # Number of squashed instructions iterated over during squash; mainly for profiling 317system.cpu.iq.iqSquashedOperandsExamined 1108322137 # Number of squashed operands that are examined and possibly removed from graph 318system.cpu.iq.iqSquashedNonSpecRemoved 332 # Number of squashed non-spec instructions that were removed 319system.cpu.iq.issued_per_cycle::samples 951199831 # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::mean 2.119459 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::stdev 1.906333 # Number of insts issued each cycle |
| 323system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 322system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 324system.cpu.iq.issued_per_cycle::0 282916763 29.20% 29.20% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::1 152378116 15.72% 44.92% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::2 162831122 16.80% 61.72% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::3 119917560 12.37% 74.10% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::4 126106053 13.01% 87.11% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::5 74105592 7.65% 94.76% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::6 38169342 3.94% 98.70% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::7 10016302 1.03% 99.73% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::8 2606220 0.27% 100.00% # Number of insts issued each cycle | 323system.cpu.iq.issued_per_cycle::0 271401880 28.53% 28.53% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::1 150954811 15.87% 44.40% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::2 160752249 16.90% 61.30% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::3 119324059 12.54% 73.85% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::4 124037458 13.04% 86.89% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::5 73914082 7.77% 94.66% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::6 38408733 4.04% 98.70% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::7 9827717 1.03% 99.73% # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::8 2578842 0.27% 100.00% # Number of insts issued each cycle |
| 333system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 332system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 336system.cpu.iq.issued_per_cycle::total 969047070 # Number of insts issued each cycle | 335system.cpu.iq.issued_per_cycle::total 951199831 # Number of insts issued each cycle |
| 337system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 336system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 338system.cpu.iq.fu_full::IntAlu 856823 3.47% 3.47% # attempts to use FU when none available 339system.cpu.iq.fu_full::IntMult 4485 0.02% 3.49% # attempts to use FU when none available 340system.cpu.iq.fu_full::IntDiv 0 0.00% 3.49% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.49% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.49% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.49% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatMult 0 0.00% 3.49% # attempts to use FU when none available 345system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.49% # attempts to use FU when none available 346system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.49% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.49% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.49% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.49% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.49% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.49% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.49% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdMult 0 0.00% 3.49% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.49% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdShift 0 0.00% 3.49% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.49% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.49% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.49% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.49% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.49% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.49% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.49% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.49% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.49% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.49% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.49% # attempts to use FU when none available 367system.cpu.iq.fu_full::MemRead 18914760 76.65% 80.14% # attempts to use FU when none available 368system.cpu.iq.fu_full::MemWrite 4900553 19.86% 100.00% # attempts to use FU when none available | 337system.cpu.iq.fu_full::IntAlu 872713 3.66% 3.66% # attempts to use FU when none available 338system.cpu.iq.fu_full::IntMult 5800 0.02% 3.68% # attempts to use FU when none available 339system.cpu.iq.fu_full::IntDiv 0 0.00% 3.68% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.68% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.68% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.68% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatMult 0 0.00% 3.68% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.68% # attempts to use FU when none available 345system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.68% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.68% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.68% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.68% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.68% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.68% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.68% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdMult 0 0.00% 3.68% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.68% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdShift 0 0.00% 3.68% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.68% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.68% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.68% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.68% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.68% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.68% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.68% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.68% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.68% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.68% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.68% # attempts to use FU when none available 366system.cpu.iq.fu_full::MemRead 18252533 76.46% 80.14% # attempts to use FU when none available 367system.cpu.iq.fu_full::MemWrite 4741041 19.86% 100.00% # attempts to use FU when none available |
| 369system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 370system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 371system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 368system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 369system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 370system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 372system.cpu.iq.FU_type_0::IntAlu 1244244744 61.21% 61.21% # Type of FU issued 373system.cpu.iq.FU_type_0::IntMult 933049 0.05% 61.26% # Type of FU issued 374system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued 375system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued 376system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued 377system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued 379system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued 380system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.26% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.26% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.26% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.26% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.26% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.26% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatCvt 77 0.00% 61.26% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued 401system.cpu.iq.FU_type_0::MemRead 593617066 29.20% 90.46% # Type of FU issued 402system.cpu.iq.FU_type_0::MemWrite 193930151 9.54% 100.00% # Type of FU issued | 371system.cpu.iq.FU_type_0::IntAlu 1235530867 61.29% 61.29% # Type of FU issued 372system.cpu.iq.FU_type_0::IntMult 926678 0.05% 61.33% # Type of FU issued 373system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued 374system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.33% # Type of FU issued 375system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued 376system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued 377system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued 379system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdFloatCvt 58 0.00% 61.33% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.33% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdFloatMisc 25 0.00% 61.33% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdFloatMult 11 0.00% 61.33% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued 400system.cpu.iq.FU_type_0::MemRead 586539458 29.09% 90.43% # Type of FU issued 401system.cpu.iq.FU_type_0::MemWrite 193031781 9.57% 100.00% # Type of FU issued |
| 403system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 404system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 402system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 403system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 405system.cpu.iq.FU_type_0::total 2032725138 # Type of FU issued 406system.cpu.iq.rate 1.973297 # Inst issue rate 407system.cpu.iq.fu_busy_cnt 24676621 # FU busy when requested 408system.cpu.iq.fu_busy_rate 0.012140 # FU busy rate (busy events/executed inst) 409system.cpu.iq.int_inst_queue_reads 5064336479 # Number of integer instruction queue reads 410system.cpu.iq.int_inst_queue_writes 2719325477 # Number of integer instruction queue writes 411system.cpu.iq.int_inst_queue_wakeup_accesses 1969225475 # Number of integer instruction queue wakeup accesses 412system.cpu.iq.fp_inst_queue_reads 458 # Number of floating instruction queue reads 413system.cpu.iq.fp_inst_queue_writes 784 # Number of floating instruction queue writes 414system.cpu.iq.fp_inst_queue_wakeup_accesses 183 # Number of floating instruction queue wakeup accesses 415system.cpu.iq.int_alu_accesses 2057401528 # Number of integer alu accesses 416system.cpu.iq.fp_alu_accesses 231 # Number of floating point alu accesses 417system.cpu.iew.lsq.thread0.forwLoads 63678179 # Number of loads that had data forwarded from stores | 404system.cpu.iq.FU_type_0::total 2016028881 # Type of FU issued 405system.cpu.iq.rate 1.990775 # Inst issue rate 406system.cpu.iq.fu_busy_cnt 23872087 # FU busy when requested 407system.cpu.iq.fu_busy_rate 0.011841 # FU busy rate (busy events/executed inst) 408system.cpu.iq.int_inst_queue_reads 5011107955 # Number of integer instruction queue reads 409system.cpu.iq.int_inst_queue_writes 2665888919 # Number of integer instruction queue writes 410system.cpu.iq.int_inst_queue_wakeup_accesses 1956633156 # Number of integer instruction queue wakeup accesses 411system.cpu.iq.fp_inst_queue_reads 372 # Number of floating instruction queue reads 412system.cpu.iq.fp_inst_queue_writes 668 # Number of floating instruction queue writes 413system.cpu.iq.fp_inst_queue_wakeup_accesses 148 # Number of floating instruction queue wakeup accesses 414system.cpu.iq.int_alu_accesses 2039900782 # Number of integer alu accesses 415system.cpu.iq.fp_alu_accesses 186 # Number of floating point alu accesses 416system.cpu.iew.lsq.thread0.forwLoads 64729425 # Number of loads that had data forwarded from stores |
| 418system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 417system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 419system.cpu.iew.lsq.thread0.squashedLoads 148201485 # Number of loads squashed 420system.cpu.iew.lsq.thread0.ignoredResponses 301622 # Number of memory responses ignored because the instruction is squashed 421system.cpu.iew.lsq.thread0.memOrderViolation 191452 # Number of memory ordering violations 422system.cpu.iew.lsq.thread0.squashedStores 46713618 # Number of stores squashed | 418system.cpu.iew.lsq.thread0.squashedLoads 137215920 # Number of loads squashed 419system.cpu.iew.lsq.thread0.ignoredResponses 273705 # Number of memory responses ignored because the instruction is squashed 420system.cpu.iew.lsq.thread0.memOrderViolation 192829 # Number of memory ordering violations 421system.cpu.iew.lsq.thread0.squashedStores 45632147 # Number of stores squashed |
| 423system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 424system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 422system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 423system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 425system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 426system.cpu.iew.lsq.thread0.cacheBlocked 3827005 # Number of times an access to memory failed due to the cache being blocked | 424system.cpu.iew.lsq.thread0.rescheduledLoads 3 # Number of loads that were rescheduled 425system.cpu.iew.lsq.thread0.cacheBlocked 3804190 # Number of times an access to memory failed due to the cache being blocked |
| 427system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 426system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 428system.cpu.iew.iewSquashCycles 73017648 # Number of cycles IEW is squashing 429system.cpu.iew.iewBlockCycles 27244100 # Number of cycles IEW is blocking 430system.cpu.iew.iewUnblockCycles 1491546 # Number of cycles IEW is unblocking 431system.cpu.iew.iewDispatchedInsts 2223439933 # Number of instructions dispatched to IQ 432system.cpu.iew.iewDispSquashedInsts 6134188 # Number of squashed instructions skipped by dispatch 433system.cpu.iew.iewDispLoadInsts 634128265 # Number of dispatched load instructions 434system.cpu.iew.iewDispStoreInsts 221560674 # Number of dispatched store instructions 435system.cpu.iew.iewDispNonSpecInsts 1025 # Number of dispatched non-speculative instructions 436system.cpu.iew.iewIQFullEvents 470403 # Number of times the IQ has become full, causing a stall 437system.cpu.iew.iewLSQFullEvents 82153 # Number of times the LSQ has become full, causing a stall 438system.cpu.iew.memOrderViolationEvents 191452 # Number of memory order violations 439system.cpu.iew.predictedTakenIncorrect 8679785 # Number of branches that were predicted taken incorrectly 440system.cpu.iew.predictedNotTakenIncorrect 10261943 # Number of branches that were predicted not taken incorrectly 441system.cpu.iew.branchMispredicts 18941728 # Number of branch mispredicts detected at execute 442system.cpu.iew.iewExecutedInsts 2001081478 # Number of executed instructions 443system.cpu.iew.iewExecLoadInsts 578449212 # Number of load instructions executed 444system.cpu.iew.iewExecSquashedInsts 31643660 # Number of squashed instructions skipped in execute | 427system.cpu.iew.iewSquashCycles 68963525 # Number of cycles IEW is squashing 428system.cpu.iew.iewBlockCycles 27139108 # Number of cycles IEW is blocking 429system.cpu.iew.iewUnblockCycles 1495868 # Number of cycles IEW is unblocking 430system.cpu.iew.iewDispatchedInsts 2196664320 # Number of instructions dispatched to IQ 431system.cpu.iew.iewDispSquashedInsts 6096220 # Number of squashed instructions skipped by dispatch 432system.cpu.iew.iewDispLoadInsts 623142693 # Number of dispatched load instructions 433system.cpu.iew.iewDispStoreInsts 220479196 # Number of dispatched store instructions 434system.cpu.iew.iewDispNonSpecInsts 440 # Number of dispatched non-speculative instructions 435system.cpu.iew.iewIQFullEvents 474677 # Number of times the IQ has become full, causing a stall 436system.cpu.iew.iewLSQFullEvents 89373 # Number of times the LSQ has become full, causing a stall 437system.cpu.iew.memOrderViolationEvents 192829 # Number of memory order violations 438system.cpu.iew.predictedTakenIncorrect 8139641 # Number of branches that were predicted taken incorrectly 439system.cpu.iew.predictedNotTakenIncorrect 9611816 # Number of branches that were predicted not taken incorrectly 440system.cpu.iew.branchMispredicts 17751457 # Number of branch mispredicts detected at execute 441system.cpu.iew.iewExecutedInsts 1986428018 # Number of executed instructions 442system.cpu.iew.iewExecLoadInsts 573006458 # Number of load instructions executed 443system.cpu.iew.iewExecSquashedInsts 29600863 # Number of squashed instructions skipped in execute |
| 445system.cpu.iew.exec_swp 0 # number of swp insts executed | 444system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 446system.cpu.iew.exec_nop 158 # number of nop insts executed 447system.cpu.iew.exec_refs 769422153 # number of memory reference insts executed 448system.cpu.iew.exec_branches 239265351 # Number of branches executed 449system.cpu.iew.exec_stores 190972941 # Number of stores executed 450system.cpu.iew.exec_rate 1.942579 # Inst execution rate 451system.cpu.iew.wb_sent 1978131551 # cumulative count of insts sent to commit 452system.cpu.iew.wb_count 1969225658 # cumulative count of insts written-back 453system.cpu.iew.wb_producers 1302526017 # num instructions producing a value 454system.cpu.iew.wb_consumers 2074719324 # num instructions consuming a value | 445system.cpu.iew.exec_nop 107 # number of nop insts executed 446system.cpu.iew.exec_refs 763162577 # number of memory reference insts executed 447system.cpu.iew.exec_branches 238305506 # Number of branches executed 448system.cpu.iew.exec_stores 190156119 # Number of stores executed 449system.cpu.iew.exec_rate 1.961545 # Inst execution rate 450system.cpu.iew.wb_sent 1965069993 # cumulative count of insts sent to commit 451system.cpu.iew.wb_count 1956633304 # cumulative count of insts written-back 452system.cpu.iew.wb_producers 1295741844 # num instructions producing a value 453system.cpu.iew.wb_consumers 2060291868 # num instructions consuming a value |
| 455system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 454system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 456system.cpu.iew.wb_rate 1.911654 # insts written-back per cycle 457system.cpu.iew.wb_fanout 0.627808 # average fanout of values written-back | 455system.cpu.iew.wb_rate 1.932123 # insts written-back per cycle 456system.cpu.iew.wb_fanout 0.628912 # average fanout of values written-back |
| 458system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 457system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 459system.cpu.commit.commitSquashedInsts 500462812 # The number of squashed insts skipped by commit 460system.cpu.commit.commitNonSpecStalls 181 # The number of times commit has been forced to stall to communicate backwards 461system.cpu.commit.branchMispredicts 16168149 # The number of times a branch was mispredicted 462system.cpu.commit.committed_per_cycle::samples 896029423 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::mean 1.923010 # Number of insts commited each cycle 464system.cpu.commit.committed_per_cycle::stdev 2.718948 # Number of insts commited each cycle | 458system.cpu.commit.commitSquashedInsts 473688675 # The number of squashed insts skipped by commit 459system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards 460system.cpu.commit.branchMispredicts 15201254 # The number of times a branch was mispredicted 461system.cpu.commit.committed_per_cycle::samples 882236307 # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::mean 1.953075 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::stdev 2.733441 # Number of insts commited each cycle |
| 465system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 464system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 466system.cpu.commit.committed_per_cycle::0 406862083 45.41% 45.41% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::1 193059933 21.55% 66.95% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::2 73977423 8.26% 75.21% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::3 35390708 3.95% 79.16% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::4 18895903 2.11% 81.27% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::5 30453376 3.40% 84.67% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::6 19841212 2.21% 86.88% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::7 11401039 1.27% 88.15% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::8 106147746 11.85% 100.00% # Number of insts commited each cycle | 465system.cpu.commit.committed_per_cycle::0 395033936 44.78% 44.78% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::1 192005187 21.76% 66.54% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::2 72432268 8.21% 74.75% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::3 35243986 3.99% 78.74% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::4 18949129 2.15% 80.89% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::5 30789454 3.49% 84.38% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::6 20064460 2.27% 86.66% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::7 11401450 1.29% 87.95% # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::8 106316437 12.05% 100.00% # Number of insts commited each cycle |
| 475system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 474system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 478system.cpu.commit.committed_per_cycle::total 896029423 # Number of insts commited each cycle 479system.cpu.commit.committedInsts 1544563096 # Number of instructions committed 480system.cpu.commit.committedOps 1723073908 # Number of ops (including micro ops) committed | 477system.cpu.commit.committed_per_cycle::total 882236307 # Number of insts commited each cycle 478system.cpu.commit.committedInsts 1544563061 # Number of instructions committed 479system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed |
| 481system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 480system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 482system.cpu.commit.refs 660773836 # Number of memory references committed 483system.cpu.commit.loads 485926780 # Number of loads committed | 481system.cpu.commit.refs 660773822 # Number of memory references committed 482system.cpu.commit.loads 485926773 # Number of loads committed |
| 484system.cpu.commit.membars 62 # Number of memory barriers committed | 483system.cpu.commit.membars 62 # Number of memory barriers committed |
| 485system.cpu.commit.branches 213462437 # Number of branches committed | 484system.cpu.commit.branches 213462430 # Number of branches committed |
| 486system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. | 485system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. |
| 487system.cpu.commit.int_insts 1536941885 # Number of committed integer instructions. | 486system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. |
| 488system.cpu.commit.function_calls 13665177 # Number of function calls committed. | 487system.cpu.commit.function_calls 13665177 # Number of function calls committed. |
| 489system.cpu.commit.bw_lim_events 106147746 # number cycles where commit BW limit reached | 488system.cpu.commit.bw_lim_events 106316437 # number cycles where commit BW limit reached |
| 490system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 489system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 491system.cpu.rob.rob_reads 3013417798 # The number of ROB reads 492system.cpu.rob.rob_writes 4520246386 # The number of ROB writes 493system.cpu.timesIdled 1016810 # Number of times that the entire CPU went into an idle state and unscheduled itself 494system.cpu.idleCycles 61069051 # Total number of cycles that the CPU has spent unscheduled due to idling 495system.cpu.committedInsts 1544563078 # Number of Instructions Simulated 496system.cpu.committedOps 1723073890 # Number of Ops (including micro ops) Simulated 497system.cpu.committedInsts_total 1544563078 # Number of Instructions Simulated 498system.cpu.cpi 0.666930 # CPI: Cycles Per Instruction 499system.cpu.cpi_total 0.666930 # CPI: Total CPI of All Threads 500system.cpu.ipc 1.499407 # IPC: Instructions Per Cycle 501system.cpu.ipc_total 1.499407 # IPC: Total IPC of All Threads 502system.cpu.int_regfile_reads 10019536016 # number of integer regfile reads 503system.cpu.int_regfile_writes 1949927429 # number of integer regfile writes 504system.cpu.fp_regfile_reads 198 # number of floating regfile reads 505system.cpu.fp_regfile_writes 204 # number of floating regfile writes 506system.cpu.misc_regfile_reads 2950890294 # number of misc regfile reads 507system.cpu.misc_regfile_writes 146 # number of misc regfile writes 508system.cpu.icache.replacements 21 # number of replacements 509system.cpu.icache.tagsinuse 635.874030 # Cycle average of tags in use 510system.cpu.icache.total_refs 292881421 # Total number of references to valid blocks. 511system.cpu.icache.sampled_refs 787 # Sample count of references to valid blocks. 512system.cpu.icache.avg_refs 372149.200762 # Average number of references to valid blocks. | 490system.cpu.rob.rob_reads 2972681819 # The number of ROB reads 491system.cpu.rob.rob_writes 4462636284 # The number of ROB writes 492system.cpu.timesIdled 1007749 # Number of times that the entire CPU went into an idle state and unscheduled itself 493system.cpu.idleCycles 61485602 # Total number of cycles that the CPU has spent unscheduled due to idling 494system.cpu.committedInsts 1544563043 # Number of Instructions Simulated 495system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated 496system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated 497system.cpu.cpi 0.655645 # CPI: Cycles Per Instruction 498system.cpu.cpi_total 0.655645 # CPI: Total CPI of All Threads 499system.cpu.ipc 1.525215 # IPC: Instructions Per Cycle 500system.cpu.ipc_total 1.525215 # IPC: Total IPC of All Threads 501system.cpu.int_regfile_reads 9949187154 # number of integer regfile reads 502system.cpu.int_regfile_writes 1936551418 # number of integer regfile writes 503system.cpu.fp_regfile_reads 155 # number of floating regfile reads 504system.cpu.fp_regfile_writes 154 # number of floating regfile writes 505system.cpu.misc_regfile_reads 2914618242 # number of misc regfile reads 506system.cpu.misc_regfile_writes 132 # number of misc regfile writes 507system.cpu.icache.replacements 22 # number of replacements 508system.cpu.icache.tagsinuse 625.107966 # Cycle average of tags in use 509system.cpu.icache.total_refs 286732187 # Total number of references to valid blocks. 510system.cpu.icache.sampled_refs 775 # Sample count of references to valid blocks. 511system.cpu.icache.avg_refs 369977.015484 # Average number of references to valid blocks. |
| 513system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 512system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 514system.cpu.icache.occ_blocks::cpu.inst 635.874030 # Average occupied blocks per requestor 515system.cpu.icache.occ_percent::cpu.inst 0.310485 # Average percentage of cache occupancy 516system.cpu.icache.occ_percent::total 0.310485 # Average percentage of cache occupancy 517system.cpu.icache.ReadReq_hits::cpu.inst 292881421 # number of ReadReq hits 518system.cpu.icache.ReadReq_hits::total 292881421 # number of ReadReq hits 519system.cpu.icache.demand_hits::cpu.inst 292881421 # number of demand (read+write) hits 520system.cpu.icache.demand_hits::total 292881421 # number of demand (read+write) hits 521system.cpu.icache.overall_hits::cpu.inst 292881421 # number of overall hits 522system.cpu.icache.overall_hits::total 292881421 # number of overall hits 523system.cpu.icache.ReadReq_misses::cpu.inst 1239 # number of ReadReq misses 524system.cpu.icache.ReadReq_misses::total 1239 # number of ReadReq misses 525system.cpu.icache.demand_misses::cpu.inst 1239 # number of demand (read+write) misses 526system.cpu.icache.demand_misses::total 1239 # number of demand (read+write) misses 527system.cpu.icache.overall_misses::cpu.inst 1239 # number of overall misses 528system.cpu.icache.overall_misses::total 1239 # number of overall misses 529system.cpu.icache.ReadReq_miss_latency::cpu.inst 62929999 # number of ReadReq miss cycles 530system.cpu.icache.ReadReq_miss_latency::total 62929999 # number of ReadReq miss cycles 531system.cpu.icache.demand_miss_latency::cpu.inst 62929999 # number of demand (read+write) miss cycles 532system.cpu.icache.demand_miss_latency::total 62929999 # number of demand (read+write) miss cycles 533system.cpu.icache.overall_miss_latency::cpu.inst 62929999 # number of overall miss cycles 534system.cpu.icache.overall_miss_latency::total 62929999 # number of overall miss cycles 535system.cpu.icache.ReadReq_accesses::cpu.inst 292882660 # number of ReadReq accesses(hits+misses) 536system.cpu.icache.ReadReq_accesses::total 292882660 # number of ReadReq accesses(hits+misses) 537system.cpu.icache.demand_accesses::cpu.inst 292882660 # number of demand (read+write) accesses 538system.cpu.icache.demand_accesses::total 292882660 # number of demand (read+write) accesses 539system.cpu.icache.overall_accesses::cpu.inst 292882660 # number of overall (read+write) accesses 540system.cpu.icache.overall_accesses::total 292882660 # number of overall (read+write) accesses | 513system.cpu.icache.occ_blocks::cpu.inst 625.107966 # Average occupied blocks per requestor 514system.cpu.icache.occ_percent::cpu.inst 0.305228 # Average percentage of cache occupancy 515system.cpu.icache.occ_percent::total 0.305228 # Average percentage of cache occupancy 516system.cpu.icache.ReadReq_hits::cpu.inst 286732187 # number of ReadReq hits 517system.cpu.icache.ReadReq_hits::total 286732187 # number of ReadReq hits 518system.cpu.icache.demand_hits::cpu.inst 286732187 # number of demand (read+write) hits 519system.cpu.icache.demand_hits::total 286732187 # number of demand (read+write) hits 520system.cpu.icache.overall_hits::cpu.inst 286732187 # number of overall hits 521system.cpu.icache.overall_hits::total 286732187 # number of overall hits 522system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses 523system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses 524system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses 525system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses 526system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses 527system.cpu.icache.overall_misses::total 1154 # number of overall misses 528system.cpu.icache.ReadReq_miss_latency::cpu.inst 59543000 # number of ReadReq miss cycles 529system.cpu.icache.ReadReq_miss_latency::total 59543000 # number of ReadReq miss cycles 530system.cpu.icache.demand_miss_latency::cpu.inst 59543000 # number of demand (read+write) miss cycles 531system.cpu.icache.demand_miss_latency::total 59543000 # number of demand (read+write) miss cycles 532system.cpu.icache.overall_miss_latency::cpu.inst 59543000 # number of overall miss cycles 533system.cpu.icache.overall_miss_latency::total 59543000 # number of overall miss cycles 534system.cpu.icache.ReadReq_accesses::cpu.inst 286733341 # number of ReadReq accesses(hits+misses) 535system.cpu.icache.ReadReq_accesses::total 286733341 # number of ReadReq accesses(hits+misses) 536system.cpu.icache.demand_accesses::cpu.inst 286733341 # number of demand (read+write) accesses 537system.cpu.icache.demand_accesses::total 286733341 # number of demand (read+write) accesses 538system.cpu.icache.overall_accesses::cpu.inst 286733341 # number of overall (read+write) accesses 539system.cpu.icache.overall_accesses::total 286733341 # number of overall (read+write) accesses |
| 541system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 542system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 543system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 544system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 545system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 546system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses | 540system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 541system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 542system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 543system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 544system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 545system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses |
| 547system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50790.959645 # average ReadReq miss latency 548system.cpu.icache.ReadReq_avg_miss_latency::total 50790.959645 # average ReadReq miss latency 549system.cpu.icache.demand_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency 550system.cpu.icache.demand_avg_miss_latency::total 50790.959645 # average overall miss latency 551system.cpu.icache.overall_avg_miss_latency::cpu.inst 50790.959645 # average overall miss latency 552system.cpu.icache.overall_avg_miss_latency::total 50790.959645 # average overall miss latency 553system.cpu.icache.blocked_cycles::no_mshrs 213 # number of cycles access was blocked | 546system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51597.053726 # average ReadReq miss latency 547system.cpu.icache.ReadReq_avg_miss_latency::total 51597.053726 # average ReadReq miss latency 548system.cpu.icache.demand_avg_miss_latency::cpu.inst 51597.053726 # average overall miss latency 549system.cpu.icache.demand_avg_miss_latency::total 51597.053726 # average overall miss latency 550system.cpu.icache.overall_avg_miss_latency::cpu.inst 51597.053726 # average overall miss latency 551system.cpu.icache.overall_avg_miss_latency::total 51597.053726 # average overall miss latency 552system.cpu.icache.blocked_cycles::no_mshrs 207 # number of cycles access was blocked |
| 554system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 555system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 556system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 553system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked 555system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 557system.cpu.icache.avg_blocked_cycles::no_mshrs 71 # average number of cycles each access was blocked | 556system.cpu.icache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked |
| 558system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 559system.cpu.icache.fast_writes 0 # number of fast writes performed 560system.cpu.icache.cache_copies 0 # number of cache copies performed | 557system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 558system.cpu.icache.fast_writes 0 # number of fast writes performed 559system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 561system.cpu.icache.ReadReq_mshr_hits::cpu.inst 452 # number of ReadReq MSHR hits 562system.cpu.icache.ReadReq_mshr_hits::total 452 # number of ReadReq MSHR hits 563system.cpu.icache.demand_mshr_hits::cpu.inst 452 # number of demand (read+write) MSHR hits 564system.cpu.icache.demand_mshr_hits::total 452 # number of demand (read+write) MSHR hits 565system.cpu.icache.overall_mshr_hits::cpu.inst 452 # number of overall MSHR hits 566system.cpu.icache.overall_mshr_hits::total 452 # number of overall MSHR hits 567system.cpu.icache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses 568system.cpu.icache.ReadReq_mshr_misses::total 787 # number of ReadReq MSHR misses 569system.cpu.icache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses 570system.cpu.icache.demand_mshr_misses::total 787 # number of demand (read+write) MSHR misses 571system.cpu.icache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses 572system.cpu.icache.overall_mshr_misses::total 787 # number of overall MSHR misses 573system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42672499 # number of ReadReq MSHR miss cycles 574system.cpu.icache.ReadReq_mshr_miss_latency::total 42672499 # number of ReadReq MSHR miss cycles 575system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42672499 # number of demand (read+write) MSHR miss cycles 576system.cpu.icache.demand_mshr_miss_latency::total 42672499 # number of demand (read+write) MSHR miss cycles 577system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42672499 # number of overall MSHR miss cycles 578system.cpu.icache.overall_mshr_miss_latency::total 42672499 # number of overall MSHR miss cycles | 560system.cpu.icache.ReadReq_mshr_hits::cpu.inst 379 # number of ReadReq MSHR hits 561system.cpu.icache.ReadReq_mshr_hits::total 379 # number of ReadReq MSHR hits 562system.cpu.icache.demand_mshr_hits::cpu.inst 379 # number of demand (read+write) MSHR hits 563system.cpu.icache.demand_mshr_hits::total 379 # number of demand (read+write) MSHR hits 564system.cpu.icache.overall_mshr_hits::cpu.inst 379 # number of overall MSHR hits 565system.cpu.icache.overall_mshr_hits::total 379 # number of overall MSHR hits 566system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses 567system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses 568system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses 569system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses 570system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses 571system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses 572system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 41824000 # number of ReadReq MSHR miss cycles 573system.cpu.icache.ReadReq_mshr_miss_latency::total 41824000 # number of ReadReq MSHR miss cycles 574system.cpu.icache.demand_mshr_miss_latency::cpu.inst 41824000 # number of demand (read+write) MSHR miss cycles 575system.cpu.icache.demand_mshr_miss_latency::total 41824000 # number of demand (read+write) MSHR miss cycles 576system.cpu.icache.overall_mshr_miss_latency::cpu.inst 41824000 # number of overall MSHR miss cycles 577system.cpu.icache.overall_mshr_miss_latency::total 41824000 # number of overall MSHR miss cycles |
| 579system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 580system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 581system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 582system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 583system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 584system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses | 578system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 579system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 580system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 581system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 582system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 583system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses |
| 585system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 54221.726811 # average ReadReq mshr miss latency 586system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 54221.726811 # average ReadReq mshr miss latency 587system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency 588system.cpu.icache.demand_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency 589system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 54221.726811 # average overall mshr miss latency 590system.cpu.icache.overall_avg_mshr_miss_latency::total 54221.726811 # average overall mshr miss latency | 584system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53966.451613 # average ReadReq mshr miss latency 585system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53966.451613 # average ReadReq mshr miss latency 586system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency 587system.cpu.icache.demand_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency 588system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53966.451613 # average overall mshr miss latency 589system.cpu.icache.overall_avg_mshr_miss_latency::total 53966.451613 # average overall mshr miss latency |
| 591system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 590system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 592system.cpu.dcache.replacements 9616996 # number of replacements 593system.cpu.dcache.tagsinuse 4088.070177 # Cycle average of tags in use 594system.cpu.dcache.total_refs 662383558 # Total number of references to valid blocks. 595system.cpu.dcache.sampled_refs 9621092 # Sample count of references to valid blocks. 596system.cpu.dcache.avg_refs 68.847025 # Average number of references to valid blocks. 597system.cpu.dcache.warmup_cycle 3431633000 # Cycle when the warmup percentage was hit. 598system.cpu.dcache.occ_blocks::cpu.data 4088.070177 # Average occupied blocks per requestor 599system.cpu.dcache.occ_percent::cpu.data 0.998064 # Average percentage of cache occupancy 600system.cpu.dcache.occ_percent::total 0.998064 # Average percentage of cache occupancy 601system.cpu.dcache.ReadReq_hits::cpu.data 495328808 # number of ReadReq hits 602system.cpu.dcache.ReadReq_hits::total 495328808 # number of ReadReq hits 603system.cpu.dcache.WriteReq_hits::cpu.data 167054576 # number of WriteReq hits 604system.cpu.dcache.WriteReq_hits::total 167054576 # number of WriteReq hits 605system.cpu.dcache.LoadLockedReq_hits::cpu.data 102 # number of LoadLockedReq hits 606system.cpu.dcache.LoadLockedReq_hits::total 102 # number of LoadLockedReq hits 607system.cpu.dcache.StoreCondReq_hits::cpu.data 72 # number of StoreCondReq hits 608system.cpu.dcache.StoreCondReq_hits::total 72 # number of StoreCondReq hits 609system.cpu.dcache.demand_hits::cpu.data 662383384 # number of demand (read+write) hits 610system.cpu.dcache.demand_hits::total 662383384 # number of demand (read+write) hits 611system.cpu.dcache.overall_hits::cpu.data 662383384 # number of overall hits 612system.cpu.dcache.overall_hits::total 662383384 # number of overall hits 613system.cpu.dcache.ReadReq_misses::cpu.data 11493898 # number of ReadReq misses 614system.cpu.dcache.ReadReq_misses::total 11493898 # number of ReadReq misses 615system.cpu.dcache.WriteReq_misses::cpu.data 5531471 # number of WriteReq misses 616system.cpu.dcache.WriteReq_misses::total 5531471 # number of WriteReq misses 617system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 618system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 619system.cpu.dcache.demand_misses::cpu.data 17025369 # number of demand (read+write) misses 620system.cpu.dcache.demand_misses::total 17025369 # number of demand (read+write) misses 621system.cpu.dcache.overall_misses::cpu.data 17025369 # number of overall misses 622system.cpu.dcache.overall_misses::total 17025369 # number of overall misses 623system.cpu.dcache.ReadReq_miss_latency::cpu.data 300469698500 # number of ReadReq miss cycles 624system.cpu.dcache.ReadReq_miss_latency::total 300469698500 # number of ReadReq miss cycles 625system.cpu.dcache.WriteReq_miss_latency::cpu.data 217116494201 # number of WriteReq miss cycles 626system.cpu.dcache.WriteReq_miss_latency::total 217116494201 # number of WriteReq miss cycles 627system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 190500 # number of LoadLockedReq miss cycles 628system.cpu.dcache.LoadLockedReq_miss_latency::total 190500 # number of LoadLockedReq miss cycles 629system.cpu.dcache.demand_miss_latency::cpu.data 517586192701 # number of demand (read+write) miss cycles 630system.cpu.dcache.demand_miss_latency::total 517586192701 # number of demand (read+write) miss cycles 631system.cpu.dcache.overall_miss_latency::cpu.data 517586192701 # number of overall miss cycles 632system.cpu.dcache.overall_miss_latency::total 517586192701 # number of overall miss cycles 633system.cpu.dcache.ReadReq_accesses::cpu.data 506822706 # number of ReadReq accesses(hits+misses) 634system.cpu.dcache.ReadReq_accesses::total 506822706 # number of ReadReq accesses(hits+misses) 635system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 636system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 637system.cpu.dcache.LoadLockedReq_accesses::cpu.data 105 # number of LoadLockedReq accesses(hits+misses) 638system.cpu.dcache.LoadLockedReq_accesses::total 105 # number of LoadLockedReq accesses(hits+misses) 639system.cpu.dcache.StoreCondReq_accesses::cpu.data 72 # number of StoreCondReq accesses(hits+misses) 640system.cpu.dcache.StoreCondReq_accesses::total 72 # number of StoreCondReq accesses(hits+misses) 641system.cpu.dcache.demand_accesses::cpu.data 679408753 # number of demand (read+write) accesses 642system.cpu.dcache.demand_accesses::total 679408753 # number of demand (read+write) accesses 643system.cpu.dcache.overall_accesses::cpu.data 679408753 # number of overall (read+write) accesses 644system.cpu.dcache.overall_accesses::total 679408753 # number of overall (read+write) accesses 645system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022678 # miss rate for ReadReq accesses 646system.cpu.dcache.ReadReq_miss_rate::total 0.022678 # miss rate for ReadReq accesses 647system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032051 # miss rate for WriteReq accesses 648system.cpu.dcache.WriteReq_miss_rate::total 0.032051 # miss rate for WriteReq accesses 649system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.028571 # miss rate for LoadLockedReq accesses 650system.cpu.dcache.LoadLockedReq_miss_rate::total 0.028571 # miss rate for LoadLockedReq accesses 651system.cpu.dcache.demand_miss_rate::cpu.data 0.025059 # miss rate for demand accesses 652system.cpu.dcache.demand_miss_rate::total 0.025059 # miss rate for demand accesses 653system.cpu.dcache.overall_miss_rate::cpu.data 0.025059 # miss rate for overall accesses 654system.cpu.dcache.overall_miss_rate::total 0.025059 # miss rate for overall accesses 655system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26141.670867 # average ReadReq miss latency 656system.cpu.dcache.ReadReq_avg_miss_latency::total 26141.670867 # average ReadReq miss latency 657system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39251.131245 # average WriteReq miss latency 658system.cpu.dcache.WriteReq_avg_miss_latency::total 39251.131245 # average WriteReq miss latency 659system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency 660system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency 661system.cpu.dcache.demand_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency 662system.cpu.dcache.demand_avg_miss_latency::total 30400.879576 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::cpu.data 30400.879576 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::total 30400.879576 # average overall miss latency 665system.cpu.dcache.blocked_cycles::no_mshrs 19937535 # number of cycles access was blocked 666system.cpu.dcache.blocked_cycles::no_targets 989836 # number of cycles access was blocked 667system.cpu.dcache.blocked::no_mshrs 1174592 # number of cycles access was blocked 668system.cpu.dcache.blocked::no_targets 64547 # number of cycles access was blocked 669system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.974009 # average number of cycles each access was blocked 670system.cpu.dcache.avg_blocked_cycles::no_targets 15.335120 # average number of cycles each access was blocked 671system.cpu.dcache.fast_writes 0 # number of fast writes performed 672system.cpu.dcache.cache_copies 0 # number of cache copies performed 673system.cpu.dcache.writebacks::writebacks 3785750 # number of writebacks 674system.cpu.dcache.writebacks::total 3785750 # number of writebacks 675system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3766794 # number of ReadReq MSHR hits 676system.cpu.dcache.ReadReq_mshr_hits::total 3766794 # number of ReadReq MSHR hits 677system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3637483 # number of WriteReq MSHR hits 678system.cpu.dcache.WriteReq_mshr_hits::total 3637483 # number of WriteReq MSHR hits 679system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 680system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 681system.cpu.dcache.demand_mshr_hits::cpu.data 7404277 # number of demand (read+write) MSHR hits 682system.cpu.dcache.demand_mshr_hits::total 7404277 # number of demand (read+write) MSHR hits 683system.cpu.dcache.overall_mshr_hits::cpu.data 7404277 # number of overall MSHR hits 684system.cpu.dcache.overall_mshr_hits::total 7404277 # number of overall MSHR hits 685system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7727104 # number of ReadReq MSHR misses 686system.cpu.dcache.ReadReq_mshr_misses::total 7727104 # number of ReadReq MSHR misses 687system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893988 # number of WriteReq MSHR misses 688system.cpu.dcache.WriteReq_mshr_misses::total 1893988 # number of WriteReq MSHR misses 689system.cpu.dcache.demand_mshr_misses::cpu.data 9621092 # number of demand (read+write) MSHR misses 690system.cpu.dcache.demand_mshr_misses::total 9621092 # number of demand (read+write) MSHR misses 691system.cpu.dcache.overall_mshr_misses::cpu.data 9621092 # number of overall MSHR misses 692system.cpu.dcache.overall_mshr_misses::total 9621092 # number of overall MSHR misses 693system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 171327843500 # number of ReadReq MSHR miss cycles 694system.cpu.dcache.ReadReq_mshr_miss_latency::total 171327843500 # number of ReadReq MSHR miss cycles 695system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71936813831 # number of WriteReq MSHR miss cycles 696system.cpu.dcache.WriteReq_mshr_miss_latency::total 71936813831 # number of WriteReq MSHR miss cycles 697system.cpu.dcache.demand_mshr_miss_latency::cpu.data 243264657331 # number of demand (read+write) MSHR miss cycles 698system.cpu.dcache.demand_mshr_miss_latency::total 243264657331 # number of demand (read+write) MSHR miss cycles 699system.cpu.dcache.overall_mshr_miss_latency::cpu.data 243264657331 # number of overall MSHR miss cycles 700system.cpu.dcache.overall_mshr_miss_latency::total 243264657331 # number of overall MSHR miss cycles 701system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015246 # mshr miss rate for ReadReq accesses 702system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015246 # mshr miss rate for ReadReq accesses 703system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses 704system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses 705system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for demand accesses 706system.cpu.dcache.demand_mshr_miss_rate::total 0.014161 # mshr miss rate for demand accesses 707system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014161 # mshr miss rate for overall accesses 708system.cpu.dcache.overall_mshr_miss_rate::total 0.014161 # mshr miss rate for overall accesses 709system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22172.322710 # average ReadReq mshr miss latency 710system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22172.322710 # average ReadReq mshr miss latency 711system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37981.662941 # average WriteReq mshr miss latency 712system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37981.662941 # average WriteReq mshr miss latency 713system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25284.516283 # average overall mshr miss latency 714system.cpu.dcache.demand_avg_mshr_miss_latency::total 25284.516283 # average overall mshr miss latency 715system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25284.516283 # average overall mshr miss latency 716system.cpu.dcache.overall_avg_mshr_miss_latency::total 25284.516283 # average overall mshr miss latency 717system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 718system.cpu.l2cache.replacements 2224194 # number of replacements 719system.cpu.l2cache.tagsinuse 31538.307180 # Cycle average of tags in use 720system.cpu.l2cache.total_refs 9258938 # Total number of references to valid blocks. 721system.cpu.l2cache.sampled_refs 2253968 # Sample count of references to valid blocks. 722system.cpu.l2cache.avg_refs 4.107839 # Average number of references to valid blocks. 723system.cpu.l2cache.warmup_cycle 20485728502 # Cycle when the warmup percentage was hit. 724system.cpu.l2cache.occ_blocks::writebacks 14439.228019 # Average occupied blocks per requestor 725system.cpu.l2cache.occ_blocks::cpu.inst 20.648477 # Average occupied blocks per requestor 726system.cpu.l2cache.occ_blocks::cpu.data 17078.430684 # Average occupied blocks per requestor 727system.cpu.l2cache.occ_percent::writebacks 0.440650 # Average percentage of cache occupancy 728system.cpu.l2cache.occ_percent::cpu.inst 0.000630 # Average percentage of cache occupancy 729system.cpu.l2cache.occ_percent::cpu.data 0.521192 # Average percentage of cache occupancy 730system.cpu.l2cache.occ_percent::total 0.962473 # Average percentage of cache occupancy 731system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits 732system.cpu.l2cache.ReadReq_hits::cpu.data 6299217 # number of ReadReq hits 733system.cpu.l2cache.ReadReq_hits::total 6299247 # number of ReadReq hits 734system.cpu.l2cache.Writeback_hits::writebacks 3785750 # number of Writeback hits 735system.cpu.l2cache.Writeback_hits::total 3785750 # number of Writeback hits 736system.cpu.l2cache.ReadExReq_hits::cpu.data 1065742 # number of ReadExReq hits 737system.cpu.l2cache.ReadExReq_hits::total 1065742 # number of ReadExReq hits 738system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits 739system.cpu.l2cache.demand_hits::cpu.data 7364959 # number of demand (read+write) hits 740system.cpu.l2cache.demand_hits::total 7364989 # number of demand (read+write) hits 741system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits 742system.cpu.l2cache.overall_hits::cpu.data 7364959 # number of overall hits 743system.cpu.l2cache.overall_hits::total 7364989 # number of overall hits 744system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses 745system.cpu.l2cache.ReadReq_misses::cpu.data 1427887 # number of ReadReq misses 746system.cpu.l2cache.ReadReq_misses::total 1428644 # number of ReadReq misses 747system.cpu.l2cache.ReadExReq_misses::cpu.data 828246 # number of ReadExReq misses 748system.cpu.l2cache.ReadExReq_misses::total 828246 # number of ReadExReq misses 749system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses 750system.cpu.l2cache.demand_misses::cpu.data 2256133 # number of demand (read+write) misses 751system.cpu.l2cache.demand_misses::total 2256890 # number of demand (read+write) misses 752system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses 753system.cpu.l2cache.overall_misses::cpu.data 2256133 # number of overall misses 754system.cpu.l2cache.overall_misses::total 2256890 # number of overall misses 755system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41571500 # number of ReadReq miss cycles 756system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98780136000 # number of ReadReq miss cycles 757system.cpu.l2cache.ReadReq_miss_latency::total 98821707500 # number of ReadReq miss cycles 758system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58846759000 # number of ReadExReq miss cycles 759system.cpu.l2cache.ReadExReq_miss_latency::total 58846759000 # number of ReadExReq miss cycles 760system.cpu.l2cache.demand_miss_latency::cpu.inst 41571500 # number of demand (read+write) miss cycles 761system.cpu.l2cache.demand_miss_latency::cpu.data 157626895000 # number of demand (read+write) miss cycles 762system.cpu.l2cache.demand_miss_latency::total 157668466500 # number of demand (read+write) miss cycles 763system.cpu.l2cache.overall_miss_latency::cpu.inst 41571500 # number of overall miss cycles 764system.cpu.l2cache.overall_miss_latency::cpu.data 157626895000 # number of overall miss cycles 765system.cpu.l2cache.overall_miss_latency::total 157668466500 # number of overall miss cycles 766system.cpu.l2cache.ReadReq_accesses::cpu.inst 787 # number of ReadReq accesses(hits+misses) 767system.cpu.l2cache.ReadReq_accesses::cpu.data 7727104 # number of ReadReq accesses(hits+misses) 768system.cpu.l2cache.ReadReq_accesses::total 7727891 # number of ReadReq accesses(hits+misses) 769system.cpu.l2cache.Writeback_accesses::writebacks 3785750 # number of Writeback accesses(hits+misses) 770system.cpu.l2cache.Writeback_accesses::total 3785750 # number of Writeback accesses(hits+misses) 771system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893988 # number of ReadExReq accesses(hits+misses) 772system.cpu.l2cache.ReadExReq_accesses::total 1893988 # number of ReadExReq accesses(hits+misses) 773system.cpu.l2cache.demand_accesses::cpu.inst 787 # number of demand (read+write) accesses 774system.cpu.l2cache.demand_accesses::cpu.data 9621092 # number of demand (read+write) accesses 775system.cpu.l2cache.demand_accesses::total 9621879 # number of demand (read+write) accesses 776system.cpu.l2cache.overall_accesses::cpu.inst 787 # number of overall (read+write) accesses 777system.cpu.l2cache.overall_accesses::cpu.data 9621092 # number of overall (read+write) accesses 778system.cpu.l2cache.overall_accesses::total 9621879 # number of overall (read+write) accesses 779system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961881 # miss rate for ReadReq accesses 780system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184789 # miss rate for ReadReq accesses 781system.cpu.l2cache.ReadReq_miss_rate::total 0.184869 # miss rate for ReadReq accesses 782system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.437303 # miss rate for ReadExReq accesses 783system.cpu.l2cache.ReadExReq_miss_rate::total 0.437303 # miss rate for ReadExReq accesses 784system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961881 # miss rate for demand accesses 785system.cpu.l2cache.demand_miss_rate::cpu.data 0.234499 # miss rate for demand accesses 786system.cpu.l2cache.demand_miss_rate::total 0.234558 # miss rate for demand accesses 787system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961881 # miss rate for overall accesses 788system.cpu.l2cache.overall_miss_rate::cpu.data 0.234499 # miss rate for overall accesses 789system.cpu.l2cache.overall_miss_rate::total 0.234558 # miss rate for overall accesses 790system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54916.116248 # average ReadReq miss latency 791system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69179.238973 # average ReadReq miss latency 792system.cpu.l2cache.ReadReq_avg_miss_latency::total 69171.681329 # average ReadReq miss latency 793system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71049.855961 # average ReadExReq miss latency 794system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71049.855961 # average ReadExReq miss latency 795system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency 796system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency 797system.cpu.l2cache.demand_avg_miss_latency::total 69860.944264 # average overall miss latency 798system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54916.116248 # average overall miss latency 799system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69865.958700 # average overall miss latency 800system.cpu.l2cache.overall_avg_miss_latency::total 69860.944264 # average overall miss latency | 591system.cpu.l2cache.replacements 2214170 # number of replacements 592system.cpu.l2cache.tagsinuse 31523.647608 # Cycle average of tags in use 593system.cpu.l2cache.total_refs 9246689 # Total number of references to valid blocks. 594system.cpu.l2cache.sampled_refs 2243948 # Sample count of references to valid blocks. 595system.cpu.l2cache.avg_refs 4.120723 # Average number of references to valid blocks. 596system.cpu.l2cache.warmup_cycle 20415148502 # Cycle when the warmup percentage was hit. 597system.cpu.l2cache.occ_blocks::writebacks 14433.962078 # Average occupied blocks per requestor 598system.cpu.l2cache.occ_blocks::cpu.inst 20.520835 # Average occupied blocks per requestor 599system.cpu.l2cache.occ_blocks::cpu.data 17069.164694 # Average occupied blocks per requestor 600system.cpu.l2cache.occ_percent::writebacks 0.440490 # Average percentage of cache occupancy 601system.cpu.l2cache.occ_percent::cpu.inst 0.000626 # Average percentage of cache occupancy 602system.cpu.l2cache.occ_percent::cpu.data 0.520910 # Average percentage of cache occupancy 603system.cpu.l2cache.occ_percent::total 0.962025 # Average percentage of cache occupancy 604system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits 605system.cpu.l2cache.ReadReq_hits::cpu.data 6288951 # number of ReadReq hits 606system.cpu.l2cache.ReadReq_hits::total 6288979 # number of ReadReq hits 607system.cpu.l2cache.Writeback_hits::writebacks 3781955 # number of Writeback hits 608system.cpu.l2cache.Writeback_hits::total 3781955 # number of Writeback hits 609system.cpu.l2cache.ReadExReq_hits::cpu.data 1067075 # number of ReadExReq hits 610system.cpu.l2cache.ReadExReq_hits::total 1067075 # number of ReadExReq hits 611system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits 612system.cpu.l2cache.demand_hits::cpu.data 7356026 # number of demand (read+write) hits 613system.cpu.l2cache.demand_hits::total 7356054 # number of demand (read+write) hits 614system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits 615system.cpu.l2cache.overall_hits::cpu.data 7356026 # number of overall hits 616system.cpu.l2cache.overall_hits::total 7356054 # number of overall hits 617system.cpu.l2cache.ReadReq_misses::cpu.inst 747 # number of ReadReq misses 618system.cpu.l2cache.ReadReq_misses::cpu.data 1419691 # number of ReadReq misses 619system.cpu.l2cache.ReadReq_misses::total 1420438 # number of ReadReq misses 620system.cpu.l2cache.ReadExReq_misses::cpu.data 826431 # number of ReadExReq misses 621system.cpu.l2cache.ReadExReq_misses::total 826431 # number of ReadExReq misses 622system.cpu.l2cache.demand_misses::cpu.inst 747 # number of demand (read+write) misses 623system.cpu.l2cache.demand_misses::cpu.data 2246122 # number of demand (read+write) misses 624system.cpu.l2cache.demand_misses::total 2246869 # number of demand (read+write) misses 625system.cpu.l2cache.overall_misses::cpu.inst 747 # number of overall misses 626system.cpu.l2cache.overall_misses::cpu.data 2246122 # number of overall misses 627system.cpu.l2cache.overall_misses::total 2246869 # number of overall misses 628system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 40761000 # number of ReadReq miss cycles 629system.cpu.l2cache.ReadReq_miss_latency::cpu.data 98155765500 # number of ReadReq miss cycles 630system.cpu.l2cache.ReadReq_miss_latency::total 98196526500 # number of ReadReq miss cycles 631system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 58740659000 # number of ReadExReq miss cycles 632system.cpu.l2cache.ReadExReq_miss_latency::total 58740659000 # number of ReadExReq miss cycles 633system.cpu.l2cache.demand_miss_latency::cpu.inst 40761000 # number of demand (read+write) miss cycles 634system.cpu.l2cache.demand_miss_latency::cpu.data 156896424500 # number of demand (read+write) miss cycles 635system.cpu.l2cache.demand_miss_latency::total 156937185500 # number of demand (read+write) miss cycles 636system.cpu.l2cache.overall_miss_latency::cpu.inst 40761000 # number of overall miss cycles 637system.cpu.l2cache.overall_miss_latency::cpu.data 156896424500 # number of overall miss cycles 638system.cpu.l2cache.overall_miss_latency::total 156937185500 # number of overall miss cycles 639system.cpu.l2cache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses) 640system.cpu.l2cache.ReadReq_accesses::cpu.data 7708642 # number of ReadReq accesses(hits+misses) 641system.cpu.l2cache.ReadReq_accesses::total 7709417 # number of ReadReq accesses(hits+misses) 642system.cpu.l2cache.Writeback_accesses::writebacks 3781955 # number of Writeback accesses(hits+misses) 643system.cpu.l2cache.Writeback_accesses::total 3781955 # number of Writeback accesses(hits+misses) 644system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893506 # number of ReadExReq accesses(hits+misses) 645system.cpu.l2cache.ReadExReq_accesses::total 1893506 # number of ReadExReq accesses(hits+misses) 646system.cpu.l2cache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses 647system.cpu.l2cache.demand_accesses::cpu.data 9602148 # number of demand (read+write) accesses 648system.cpu.l2cache.demand_accesses::total 9602923 # number of demand (read+write) accesses 649system.cpu.l2cache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses 650system.cpu.l2cache.overall_accesses::cpu.data 9602148 # number of overall (read+write) accesses 651system.cpu.l2cache.overall_accesses::total 9602923 # number of overall (read+write) accesses 652system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963871 # miss rate for ReadReq accesses 653system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184169 # miss rate for ReadReq accesses 654system.cpu.l2cache.ReadReq_miss_rate::total 0.184247 # miss rate for ReadReq accesses 655system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436455 # miss rate for ReadExReq accesses 656system.cpu.l2cache.ReadExReq_miss_rate::total 0.436455 # miss rate for ReadExReq accesses 657system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963871 # miss rate for demand accesses 658system.cpu.l2cache.demand_miss_rate::cpu.data 0.233919 # miss rate for demand accesses 659system.cpu.l2cache.demand_miss_rate::total 0.233978 # miss rate for demand accesses 660system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963871 # miss rate for overall accesses 661system.cpu.l2cache.overall_miss_rate::cpu.data 0.233919 # miss rate for overall accesses 662system.cpu.l2cache.overall_miss_rate::total 0.233978 # miss rate for overall accesses 663system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 54566.265060 # average ReadReq miss latency 664system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69138.823519 # average ReadReq miss latency 665system.cpu.l2cache.ReadReq_avg_miss_latency::total 69131.159896 # average ReadReq miss latency 666system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 71077.511613 # average ReadExReq miss latency 667system.cpu.l2cache.ReadExReq_avg_miss_latency::total 71077.511613 # average ReadExReq miss latency 668system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 54566.265060 # average overall miss latency 669system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69852.138263 # average overall miss latency 670system.cpu.l2cache.demand_avg_miss_latency::total 69847.056281 # average overall miss latency 671system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 54566.265060 # average overall miss latency 672system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69852.138263 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::total 69847.056281 # average overall miss latency |
| 801system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 802system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 804system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 805system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 806system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 807system.cpu.l2cache.fast_writes 0 # number of fast writes performed 808system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 674system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 675system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 676system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 678system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 679system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 680system.cpu.l2cache.fast_writes 0 # number of fast writes performed 681system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 809system.cpu.l2cache.writebacks::writebacks 1103400 # number of writebacks 810system.cpu.l2cache.writebacks::total 1103400 # number of writebacks 811system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits 812system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits | 682system.cpu.l2cache.writebacks::writebacks 1100554 # number of writebacks 683system.cpu.l2cache.writebacks::total 1100554 # number of writebacks 684system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 685system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits |
| 813system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits | 686system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits |
| 814system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits 815system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits | 687system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 688system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits |
| 816system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits | 689system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits |
| 817system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits 818system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits | 690system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 691system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits |
| 819system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits | 692system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits |
| 820system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 755 # number of ReadReq MSHR misses 821system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1427881 # number of ReadReq MSHR misses 822system.cpu.l2cache.ReadReq_mshr_misses::total 1428636 # number of ReadReq MSHR misses 823system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 828246 # number of ReadExReq MSHR misses 824system.cpu.l2cache.ReadExReq_mshr_misses::total 828246 # number of ReadExReq MSHR misses 825system.cpu.l2cache.demand_mshr_misses::cpu.inst 755 # number of demand (read+write) MSHR misses 826system.cpu.l2cache.demand_mshr_misses::cpu.data 2256127 # number of demand (read+write) MSHR misses 827system.cpu.l2cache.demand_mshr_misses::total 2256882 # number of demand (read+write) MSHR misses 828system.cpu.l2cache.overall_mshr_misses::cpu.inst 755 # number of overall MSHR misses 829system.cpu.l2cache.overall_mshr_misses::cpu.data 2256127 # number of overall MSHR misses 830system.cpu.l2cache.overall_mshr_misses::total 2256882 # number of overall MSHR misses 831system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31971694 # number of ReadReq MSHR miss cycles 832system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80731453067 # number of ReadReq MSHR miss cycles 833system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80763424761 # number of ReadReq MSHR miss cycles 834system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48402066091 # number of ReadExReq MSHR miss cycles 835system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48402066091 # number of ReadExReq MSHR miss cycles 836system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31971694 # number of demand (read+write) MSHR miss cycles 837system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 129133519158 # number of demand (read+write) MSHR miss cycles 838system.cpu.l2cache.demand_mshr_miss_latency::total 129165490852 # number of demand (read+write) MSHR miss cycles 839system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31971694 # number of overall MSHR miss cycles 840system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 129133519158 # number of overall MSHR miss cycles 841system.cpu.l2cache.overall_mshr_miss_latency::total 129165490852 # number of overall MSHR miss cycles 842system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for ReadReq accesses 843system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184789 # mshr miss rate for ReadReq accesses 844system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184868 # mshr miss rate for ReadReq accesses 845system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.437303 # mshr miss rate for ReadExReq accesses 846system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.437303 # mshr miss rate for ReadExReq accesses 847system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for demand accesses 848system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for demand accesses 849system.cpu.l2cache.demand_mshr_miss_rate::total 0.234557 # mshr miss rate for demand accesses 850system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959339 # mshr miss rate for overall accesses 851system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.234498 # mshr miss rate for overall accesses 852system.cpu.l2cache.overall_mshr_miss_rate::total 0.234557 # mshr miss rate for overall accesses 853system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42346.614570 # average ReadReq mshr miss latency 854system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56539.342611 # average ReadReq mshr miss latency 855system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56531.842093 # average ReadReq mshr miss latency 856system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58439.239177 # average ReadExReq mshr miss latency 857system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58439.239177 # average ReadExReq mshr miss latency 858system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency 859system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency 860system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency 861system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42346.614570 # average overall mshr miss latency 862system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57236.812980 # average overall mshr miss latency 863system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57231.831727 # average overall mshr miss latency | 693system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses 694system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419684 # number of ReadReq MSHR misses 695system.cpu.l2cache.ReadReq_mshr_misses::total 1420430 # number of ReadReq MSHR misses 696system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826431 # number of ReadExReq MSHR misses 697system.cpu.l2cache.ReadExReq_mshr_misses::total 826431 # number of ReadExReq MSHR misses 698system.cpu.l2cache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses 699system.cpu.l2cache.demand_mshr_misses::cpu.data 2246115 # number of demand (read+write) MSHR misses 700system.cpu.l2cache.demand_mshr_misses::total 2246861 # number of demand (read+write) MSHR misses 701system.cpu.l2cache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses 702system.cpu.l2cache.overall_mshr_misses::cpu.data 2246115 # number of overall MSHR misses 703system.cpu.l2cache.overall_mshr_misses::total 2246861 # number of overall MSHR misses 704system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31288684 # number of ReadReq MSHR miss cycles 705system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80209878843 # number of ReadReq MSHR miss cycles 706system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80241167527 # number of ReadReq MSHR miss cycles 707system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48317396987 # number of ReadExReq MSHR miss cycles 708system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48317396987 # number of ReadExReq MSHR miss cycles 709system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31288684 # number of demand (read+write) MSHR miss cycles 710system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 128527275830 # number of demand (read+write) MSHR miss cycles 711system.cpu.l2cache.demand_mshr_miss_latency::total 128558564514 # number of demand (read+write) MSHR miss cycles 712system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31288684 # number of overall MSHR miss cycles 713system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 128527275830 # number of overall MSHR miss cycles 714system.cpu.l2cache.overall_mshr_miss_latency::total 128558564514 # number of overall MSHR miss cycles 715system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962581 # mshr miss rate for ReadReq accesses 716system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184168 # mshr miss rate for ReadReq accesses 717system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184246 # mshr miss rate for ReadReq accesses 718system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436455 # mshr miss rate for ReadExReq accesses 719system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436455 # mshr miss rate for ReadExReq accesses 720system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962581 # mshr miss rate for demand accesses 721system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233918 # mshr miss rate for demand accesses 722system.cpu.l2cache.demand_mshr_miss_rate::total 0.233977 # mshr miss rate for demand accesses 723system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962581 # mshr miss rate for overall accesses 724system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233918 # mshr miss rate for overall accesses 725system.cpu.l2cache.overall_mshr_miss_rate::total 0.233977 # mshr miss rate for overall accesses 726system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 41941.935657 # average ReadReq mshr miss latency 727system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 56498.403055 # average ReadReq mshr miss latency 728system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56490.758099 # average ReadReq mshr miss latency 729system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58465.131375 # average ReadExReq mshr miss latency 730system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58465.131375 # average ReadExReq mshr miss latency 731system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 41941.935657 # average overall mshr miss latency 732system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57222.037086 # average overall mshr miss latency 733system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57216.963806 # average overall mshr miss latency 734system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 41941.935657 # average overall mshr miss latency 735system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57222.037086 # average overall mshr miss latency 736system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57216.963806 # average overall mshr miss latency |
| 864system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 737system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 738system.cpu.dcache.replacements 9598051 # number of replacements 739system.cpu.dcache.tagsinuse 4087.935978 # Cycle average of tags in use 740system.cpu.dcache.total_refs 655966956 # Total number of references to valid blocks. 741system.cpu.dcache.sampled_refs 9602147 # Sample count of references to valid blocks. 742system.cpu.dcache.avg_refs 68.314613 # Average number of references to valid blocks. 743system.cpu.dcache.warmup_cycle 3423729000 # Cycle when the warmup percentage was hit. 744system.cpu.dcache.occ_blocks::cpu.data 4087.935978 # Average occupied blocks per requestor 745system.cpu.dcache.occ_percent::cpu.data 0.998031 # Average percentage of cache occupancy 746system.cpu.dcache.occ_percent::total 0.998031 # Average percentage of cache occupancy 747system.cpu.dcache.ReadReq_hits::cpu.data 488912900 # number of ReadReq hits 748system.cpu.dcache.ReadReq_hits::total 488912900 # number of ReadReq hits 749system.cpu.dcache.WriteReq_hits::cpu.data 167053904 # number of WriteReq hits 750system.cpu.dcache.WriteReq_hits::total 167053904 # number of WriteReq hits 751system.cpu.dcache.LoadLockedReq_hits::cpu.data 87 # number of LoadLockedReq hits 752system.cpu.dcache.LoadLockedReq_hits::total 87 # number of LoadLockedReq hits 753system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits 754system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits 755system.cpu.dcache.demand_hits::cpu.data 655966804 # number of demand (read+write) hits 756system.cpu.dcache.demand_hits::total 655966804 # number of demand (read+write) hits 757system.cpu.dcache.overall_hits::cpu.data 655966804 # number of overall hits 758system.cpu.dcache.overall_hits::total 655966804 # number of overall hits 759system.cpu.dcache.ReadReq_misses::cpu.data 11479195 # number of ReadReq misses 760system.cpu.dcache.ReadReq_misses::total 11479195 # number of ReadReq misses 761system.cpu.dcache.WriteReq_misses::cpu.data 5532143 # number of WriteReq misses 762system.cpu.dcache.WriteReq_misses::total 5532143 # number of WriteReq misses 763system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 764system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses 765system.cpu.dcache.demand_misses::cpu.data 17011338 # number of demand (read+write) misses 766system.cpu.dcache.demand_misses::total 17011338 # number of demand (read+write) misses 767system.cpu.dcache.overall_misses::cpu.data 17011338 # number of overall misses 768system.cpu.dcache.overall_misses::total 17011338 # number of overall misses 769system.cpu.dcache.ReadReq_miss_latency::cpu.data 299504228000 # number of ReadReq miss cycles 770system.cpu.dcache.ReadReq_miss_latency::total 299504228000 # number of ReadReq miss cycles 771system.cpu.dcache.WriteReq_miss_latency::cpu.data 217114926916 # number of WriteReq miss cycles 772system.cpu.dcache.WriteReq_miss_latency::total 217114926916 # number of WriteReq miss cycles 773system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 187000 # number of LoadLockedReq miss cycles 774system.cpu.dcache.LoadLockedReq_miss_latency::total 187000 # number of LoadLockedReq miss cycles 775system.cpu.dcache.demand_miss_latency::cpu.data 516619154916 # number of demand (read+write) miss cycles 776system.cpu.dcache.demand_miss_latency::total 516619154916 # number of demand (read+write) miss cycles 777system.cpu.dcache.overall_miss_latency::cpu.data 516619154916 # number of overall miss cycles 778system.cpu.dcache.overall_miss_latency::total 516619154916 # number of overall miss cycles 779system.cpu.dcache.ReadReq_accesses::cpu.data 500392095 # number of ReadReq accesses(hits+misses) 780system.cpu.dcache.ReadReq_accesses::total 500392095 # number of ReadReq accesses(hits+misses) 781system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 782system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 783system.cpu.dcache.LoadLockedReq_accesses::cpu.data 90 # number of LoadLockedReq accesses(hits+misses) 784system.cpu.dcache.LoadLockedReq_accesses::total 90 # number of LoadLockedReq accesses(hits+misses) 785system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses) 786system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses) 787system.cpu.dcache.demand_accesses::cpu.data 672978142 # number of demand (read+write) accesses 788system.cpu.dcache.demand_accesses::total 672978142 # number of demand (read+write) accesses 789system.cpu.dcache.overall_accesses::cpu.data 672978142 # number of overall (read+write) accesses 790system.cpu.dcache.overall_accesses::total 672978142 # number of overall (read+write) accesses 791system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022940 # miss rate for ReadReq accesses 792system.cpu.dcache.ReadReq_miss_rate::total 0.022940 # miss rate for ReadReq accesses 793system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032054 # miss rate for WriteReq accesses 794system.cpu.dcache.WriteReq_miss_rate::total 0.032054 # miss rate for WriteReq accesses 795system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.033333 # miss rate for LoadLockedReq accesses 796system.cpu.dcache.LoadLockedReq_miss_rate::total 0.033333 # miss rate for LoadLockedReq accesses 797system.cpu.dcache.demand_miss_rate::cpu.data 0.025278 # miss rate for demand accesses 798system.cpu.dcache.demand_miss_rate::total 0.025278 # miss rate for demand accesses 799system.cpu.dcache.overall_miss_rate::cpu.data 0.025278 # miss rate for overall accesses 800system.cpu.dcache.overall_miss_rate::total 0.025278 # miss rate for overall accesses 801system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26091.048022 # average ReadReq miss latency 802system.cpu.dcache.ReadReq_avg_miss_latency::total 26091.048022 # average ReadReq miss latency 803system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39246.080030 # average WriteReq miss latency 804system.cpu.dcache.WriteReq_avg_miss_latency::total 39246.080030 # average WriteReq miss latency 805system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62333.333333 # average LoadLockedReq miss latency 806system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62333.333333 # average LoadLockedReq miss latency 807system.cpu.dcache.demand_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency 808system.cpu.dcache.demand_avg_miss_latency::total 30369.107646 # average overall miss latency 809system.cpu.dcache.overall_avg_miss_latency::cpu.data 30369.107646 # average overall miss latency 810system.cpu.dcache.overall_avg_miss_latency::total 30369.107646 # average overall miss latency 811system.cpu.dcache.blocked_cycles::no_mshrs 19754018 # number of cycles access was blocked 812system.cpu.dcache.blocked_cycles::no_targets 992148 # number of cycles access was blocked 813system.cpu.dcache.blocked::no_mshrs 1171998 # number of cycles access was blocked 814system.cpu.dcache.blocked::no_targets 64543 # number of cycles access was blocked 815system.cpu.dcache.avg_blocked_cycles::no_mshrs 16.854993 # average number of cycles each access was blocked 816system.cpu.dcache.avg_blocked_cycles::no_targets 15.371892 # average number of cycles each access was blocked 817system.cpu.dcache.fast_writes 0 # number of fast writes performed 818system.cpu.dcache.cache_copies 0 # number of cache copies performed 819system.cpu.dcache.writebacks::writebacks 3781955 # number of writebacks 820system.cpu.dcache.writebacks::total 3781955 # number of writebacks 821system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3770552 # number of ReadReq MSHR hits 822system.cpu.dcache.ReadReq_mshr_hits::total 3770552 # number of ReadReq MSHR hits 823system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3638638 # number of WriteReq MSHR hits 824system.cpu.dcache.WriteReq_mshr_hits::total 3638638 # number of WriteReq MSHR hits 825system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 826system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits 827system.cpu.dcache.demand_mshr_hits::cpu.data 7409190 # number of demand (read+write) MSHR hits 828system.cpu.dcache.demand_mshr_hits::total 7409190 # number of demand (read+write) MSHR hits 829system.cpu.dcache.overall_mshr_hits::cpu.data 7409190 # number of overall MSHR hits 830system.cpu.dcache.overall_mshr_hits::total 7409190 # number of overall MSHR hits 831system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708643 # number of ReadReq MSHR misses 832system.cpu.dcache.ReadReq_mshr_misses::total 7708643 # number of ReadReq MSHR misses 833system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893505 # number of WriteReq MSHR misses 834system.cpu.dcache.WriteReq_mshr_misses::total 1893505 # number of WriteReq MSHR misses 835system.cpu.dcache.demand_mshr_misses::cpu.data 9602148 # number of demand (read+write) MSHR misses 836system.cpu.dcache.demand_mshr_misses::total 9602148 # number of demand (read+write) MSHR misses 837system.cpu.dcache.overall_mshr_misses::cpu.data 9602148 # number of overall MSHR misses 838system.cpu.dcache.overall_mshr_misses::total 9602148 # number of overall MSHR misses 839system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 170578712500 # number of ReadReq MSHR miss cycles 840system.cpu.dcache.ReadReq_mshr_miss_latency::total 170578712500 # number of ReadReq MSHR miss cycles 841system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 71843645589 # number of WriteReq MSHR miss cycles 842system.cpu.dcache.WriteReq_mshr_miss_latency::total 71843645589 # number of WriteReq MSHR miss cycles 843system.cpu.dcache.demand_mshr_miss_latency::cpu.data 242422358089 # number of demand (read+write) MSHR miss cycles 844system.cpu.dcache.demand_mshr_miss_latency::total 242422358089 # number of demand (read+write) MSHR miss cycles 845system.cpu.dcache.overall_mshr_miss_latency::cpu.data 242422358089 # number of overall MSHR miss cycles 846system.cpu.dcache.overall_mshr_miss_latency::total 242422358089 # number of overall MSHR miss cycles 847system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015405 # mshr miss rate for ReadReq accesses 848system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015405 # mshr miss rate for ReadReq accesses 849system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010971 # mshr miss rate for WriteReq accesses 850system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010971 # mshr miss rate for WriteReq accesses 851system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for demand accesses 852system.cpu.dcache.demand_mshr_miss_rate::total 0.014268 # mshr miss rate for demand accesses 853system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014268 # mshr miss rate for overall accesses 854system.cpu.dcache.overall_mshr_miss_rate::total 0.014268 # mshr miss rate for overall accesses 855system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22128.241313 # average ReadReq mshr miss latency 856system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22128.241313 # average ReadReq mshr miss latency 857system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37942.147282 # average WriteReq mshr miss latency 858system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37942.147282 # average WriteReq mshr miss latency 859system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency 860system.cpu.dcache.demand_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency 861system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25246.680023 # average overall mshr miss latency 862system.cpu.dcache.overall_avg_mshr_miss_latency::total 25246.680023 # average overall mshr miss latency 863system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 865 866---------- End Simulation Statistics ---------- | 864 865---------- End Simulation Statistics ---------- |