| stats.txt (9289:a31a1243a3ed) | stats.txt (9312:e05e1b69ebf2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.454149 # Number of seconds simulated 4sim_ticks 454149445000 # Number of ticks simulated 5final_tick 454149445000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.473434 # Number of seconds simulated 4sim_ticks 473433799500 # Number of ticks simulated 5final_tick 473433799500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 251011 # Simulator instruction rate (inst/s) 8host_op_rate 280022 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 73805166 # Simulator tick rate (ticks/s) 10host_mem_usage 228580 # Number of bytes of host memory used 11host_seconds 6153.36 # Real time elapsed on the host 12sim_insts 1544563043 # Number of instructions simulated 13sim_ops 1723073855 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 48256 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 156265984 # Number of bytes read from this memory 16system.physmem.bytes_read::total 156314240 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 48256 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 48256 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 71930048 # Number of bytes written to this memory 20system.physmem.bytes_written::total 71930048 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 754 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2441656 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2442410 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1123907 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1123907 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 106256 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 344084939 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 344191195 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 106256 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 106256 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 158384093 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 158384093 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 158384093 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 106256 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 344084939 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 502575288 # Total bandwidth to/from this memory (bytes/s) | 7host_inst_rate 169995 # Simulator instruction rate (inst/s) 8host_op_rate 189642 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 52106394 # Simulator tick rate (ticks/s) 10host_mem_usage 499160 # Number of bytes of host memory used 11host_seconds 9085.91 # Real time elapsed on the host 12sim_insts 1544563083 # Number of instructions simulated 13sim_ops 1723073895 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 48384 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 156296704 # Number of bytes read from this memory 16system.physmem.bytes_read::total 156345088 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 48384 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 48384 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 71931712 # Number of bytes written to this memory 20system.physmem.bytes_written::total 71931712 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 756 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2442136 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2442892 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1123933 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1123933 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 102198 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 330134232 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 330236430 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 102198 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 102198 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 151936157 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 151936157 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 151936157 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 102198 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 330134232 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 482172587 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 2442892 # Total number of read requests seen 38system.physmem.writeReqs 1123933 # Total number of write requests seen 39system.physmem.cpureqs 3566825 # Reqs generatd by CPU via cache - shady 40system.physmem.bytesRead 156345088 # Total number of bytes read from memory 41system.physmem.bytesWritten 71931712 # Total number of bytes written to memory 42system.physmem.bytesConsumedRd 156345088 # bytesRead derated as per pkt->getSize() 43system.physmem.bytesConsumedWr 71931712 # bytesWritten derated as per pkt->getSize() 44system.physmem.servicedByWrQ 1286 # Number of read reqs serviced by write Q 45system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 46system.physmem.perBankRdReqs::0 151934 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::1 156031 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::2 154856 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::3 153024 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::4 150249 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::5 152372 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::6 153472 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::7 154746 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::8 153379 # Track reads on a per bank basis 55system.physmem.perBankRdReqs::9 151879 # Track reads on a per bank basis 56system.physmem.perBankRdReqs::10 152199 # Track reads on a per bank basis 57system.physmem.perBankRdReqs::11 152305 # Track reads on a per bank basis 58system.physmem.perBankRdReqs::12 150118 # Track reads on a per bank basis 59system.physmem.perBankRdReqs::13 153271 # Track reads on a per bank basis 60system.physmem.perBankRdReqs::14 150713 # Track reads on a per bank basis 61system.physmem.perBankRdReqs::15 151058 # Track reads on a per bank basis 62system.physmem.perBankWrReqs::0 70393 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::1 72288 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::2 71658 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::3 69978 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::4 69490 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::5 69799 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::6 70024 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::7 70449 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::8 69754 # Track writes on a per bank basis 71system.physmem.perBankWrReqs::9 69615 # Track writes on a per bank basis 72system.physmem.perBankWrReqs::10 69971 # Track writes on a per bank basis 73system.physmem.perBankWrReqs::11 69698 # Track writes on a per bank basis 74system.physmem.perBankWrReqs::12 68976 # Track writes on a per bank basis 75system.physmem.perBankWrReqs::13 71736 # Track writes on a per bank basis 76system.physmem.perBankWrReqs::14 70217 # Track writes on a per bank basis 77system.physmem.perBankWrReqs::15 69887 # Track writes on a per bank basis 78system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 79system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry 80system.physmem.totGap 473433771000 # Total gap between requests 81system.physmem.readPktSize::0 0 # Categorize read packet sizes 82system.physmem.readPktSize::1 0 # Categorize read packet sizes 83system.physmem.readPktSize::2 0 # Categorize read packet sizes 84system.physmem.readPktSize::3 0 # Categorize read packet sizes 85system.physmem.readPktSize::4 0 # Categorize read packet sizes 86system.physmem.readPktSize::5 0 # Categorize read packet sizes 87system.physmem.readPktSize::6 2442892 # Categorize read packet sizes 88system.physmem.readPktSize::7 0 # Categorize read packet sizes 89system.physmem.readPktSize::8 0 # Categorize read packet sizes 90system.physmem.writePktSize::0 0 # categorize write packet sizes 91system.physmem.writePktSize::1 0 # categorize write packet sizes 92system.physmem.writePktSize::2 0 # categorize write packet sizes 93system.physmem.writePktSize::3 0 # categorize write packet sizes 94system.physmem.writePktSize::4 0 # categorize write packet sizes 95system.physmem.writePktSize::5 0 # categorize write packet sizes 96system.physmem.writePktSize::6 1123933 # categorize write packet sizes 97system.physmem.writePktSize::7 0 # categorize write packet sizes 98system.physmem.writePktSize::8 0 # categorize write packet sizes 99system.physmem.neitherpktsize::0 0 # categorize neither packet sizes 100system.physmem.neitherpktsize::1 0 # categorize neither packet sizes 101system.physmem.neitherpktsize::2 0 # categorize neither packet sizes 102system.physmem.neitherpktsize::3 0 # categorize neither packet sizes 103system.physmem.neitherpktsize::4 0 # categorize neither packet sizes 104system.physmem.neitherpktsize::5 0 # categorize neither packet sizes 105system.physmem.neitherpktsize::6 0 # categorize neither packet sizes 106system.physmem.neitherpktsize::7 0 # categorize neither packet sizes 107system.physmem.neitherpktsize::8 0 # categorize neither packet sizes 108system.physmem.rdQLenPdf::0 1613567 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::1 411043 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::2 122672 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::3 76227 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::4 63723 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::5 50754 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::6 36534 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::7 28949 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::8 23035 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::9 15102 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 136system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 137system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 138system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 139system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 140system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see 141system.physmem.wrQLenPdf::0 43358 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::1 46512 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::2 47775 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::3 48422 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::4 48759 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::5 48833 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::6 48858 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::7 48865 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::8 48866 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::9 48867 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::10 48867 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::11 48867 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::12 48867 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::13 48867 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::14 48867 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::15 48866 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::16 48866 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::17 48866 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::18 48866 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::19 48866 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::20 48866 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::21 48866 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::22 48866 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::23 5509 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::24 2355 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::25 1092 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::26 445 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::27 108 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::28 34 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::29 9 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::31 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 174system.physmem.totQLat 39045821973 # Total cycles spent in queuing delays 175system.physmem.totMemAccLat 121584903973 # Sum of mem lat for all requests 176system.physmem.totBusLat 9766424000 # Total cycles spent in databus access 177system.physmem.totBankLat 72772658000 # Total cycles spent in bank access 178system.physmem.avgQLat 15991.86 # Average queueing delay per request 179system.physmem.avgBankLat 29805.24 # Average bank access latency per request 180system.physmem.avgBusLat 4000.00 # Average bus latency per request 181system.physmem.avgMemAccLat 49797.10 # Average memory access latency 182system.physmem.avgRdBW 330.24 # Average achieved read bandwidth in MB/s 183system.physmem.avgWrBW 151.94 # Average achieved write bandwidth in MB/s 184system.physmem.avgConsumedRdBW 330.24 # Average consumed read bandwidth in MB/s 185system.physmem.avgConsumedWrBW 151.94 # Average consumed write bandwidth in MB/s 186system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 187system.physmem.busUtil 3.01 # Data bus utilization in percentage 188system.physmem.avgRdQLen 0.26 # Average read queue length over time 189system.physmem.avgWrQLen 10.90 # Average write queue length over time 190system.physmem.readRowHits 966664 # Number of row buffer hits during reads 191system.physmem.writeRowHits 336338 # Number of row buffer hits during writes 192system.physmem.readRowHitRate 39.59 # Row buffer hit rate for reads 193system.physmem.writeRowHitRate 29.93 # Row buffer hit rate for writes 194system.physmem.avgGap 132732.55 # Average gap between requests |
| 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 72system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 73system.cpu.itb.read_accesses 0 # DTB read accesses 74system.cpu.itb.write_accesses 0 # DTB write accesses 75system.cpu.itb.inst_accesses 0 # ITB inst accesses 76system.cpu.itb.hits 0 # DTB hits 77system.cpu.itb.misses 0 # DTB misses 78system.cpu.itb.accesses 0 # DTB accesses 79system.cpu.workload.num_syscalls 46 # Number of system calls | 195system.cpu.dtb.inst_hits 0 # ITB inst hits 196system.cpu.dtb.inst_misses 0 # ITB inst misses 197system.cpu.dtb.read_hits 0 # DTB read hits 198system.cpu.dtb.read_misses 0 # DTB read misses 199system.cpu.dtb.write_hits 0 # DTB write hits 200system.cpu.dtb.write_misses 0 # DTB write misses 201system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 202system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 230system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 231system.cpu.itb.read_accesses 0 # DTB read accesses 232system.cpu.itb.write_accesses 0 # DTB write accesses 233system.cpu.itb.inst_accesses 0 # ITB inst accesses 234system.cpu.itb.hits 0 # DTB hits 235system.cpu.itb.misses 0 # DTB misses 236system.cpu.itb.accesses 0 # DTB accesses 237system.cpu.workload.num_syscalls 46 # Number of system calls |
| 80system.cpu.numCycles 908298891 # number of cpu cycles simulated | 238system.cpu.numCycles 946867600 # number of cpu cycles simulated |
| 81system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 82system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 239system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 240system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 83system.cpu.BPredUnit.lookups 299221505 # Number of BP lookups 84system.cpu.BPredUnit.condPredicted 245089393 # Number of conditional branches predicted 85system.cpu.BPredUnit.condIncorrect 16036207 # Number of conditional branches incorrect 86system.cpu.BPredUnit.BTBLookups 167476566 # Number of BTB lookups 87system.cpu.BPredUnit.BTBHits 155260747 # Number of BTB hits | 241system.cpu.BPredUnit.lookups 299593765 # Number of BP lookups 242system.cpu.BPredUnit.condPredicted 245452602 # Number of conditional branches predicted 243system.cpu.BPredUnit.condIncorrect 16045022 # Number of conditional branches incorrect 244system.cpu.BPredUnit.BTBLookups 170764551 # Number of BTB lookups 245system.cpu.BPredUnit.BTBHits 155662191 # Number of BTB hits |
| 88system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 246system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 89system.cpu.BPredUnit.usedRAS 18353715 # Number of times the RAS was used to get a target. 90system.cpu.BPredUnit.RASInCorrect 235 # Number of incorrect RAS predictions. 91system.cpu.fetch.icacheStallCycles 291143927 # Number of cycles fetch is stalled on an Icache miss 92system.cpu.fetch.Insts 2147541842 # Number of instructions fetch has processed 93system.cpu.fetch.Branches 299221505 # Number of branches that fetch encountered 94system.cpu.fetch.predictedBranches 173614462 # Number of branches that fetch has predicted taken 95system.cpu.fetch.Cycles 427042376 # Number of cycles fetch has run and was not squashing or blocked 96system.cpu.fetch.SquashCycles 81995589 # Number of cycles fetch has spent squashing 97system.cpu.fetch.BlockedCycles 117912816 # Number of cycles fetch has spent blocked | 247system.cpu.BPredUnit.usedRAS 18346296 # Number of times the RAS was used to get a target. 248system.cpu.BPredUnit.RASInCorrect 201 # Number of incorrect RAS predictions. 249system.cpu.fetch.icacheStallCycles 291830558 # Number of cycles fetch is stalled on an Icache miss 250system.cpu.fetch.Insts 2150759454 # Number of instructions fetch has processed 251system.cpu.fetch.Branches 299593765 # Number of branches that fetch encountered 252system.cpu.fetch.predictedBranches 174008487 # Number of branches that fetch has predicted taken 253system.cpu.fetch.Cycles 427702866 # Number of cycles fetch has run and was not squashing or blocked 254system.cpu.fetch.SquashCycles 82463506 # Number of cycles fetch has spent squashing 255system.cpu.fetch.BlockedCycles 122599229 # Number of cycles fetch has spent blocked |
| 98system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 256system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 99system.cpu.fetch.PendingTrapStallCycles 94 # Number of stall cycles due to pending traps 100system.cpu.fetch.CacheLines 282188311 # Number of cache lines fetched 101system.cpu.fetch.IcacheSquashes 5315637 # Number of outstanding Icache misses that were squashed 102system.cpu.fetch.rateDist::samples 901821520 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::mean 2.649341 # Number of instructions fetched each cycle (Total) 104system.cpu.fetch.rateDist::stdev 3.246532 # Number of instructions fetched each cycle (Total) | 257system.cpu.fetch.PendingTrapStallCycles 88 # Number of stall cycles due to pending traps 258system.cpu.fetch.CacheLines 282801731 # Number of cache lines fetched 259system.cpu.fetch.IcacheSquashes 5377782 # Number of outstanding Icache misses that were squashed 260system.cpu.fetch.rateDist::samples 908156186 # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::mean 2.634401 # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::stdev 3.243337 # Number of instructions fetched each cycle (Total) |
| 105system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 263system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 106system.cpu.fetch.rateDist::0 474779291 52.65% 52.65% # Number of instructions fetched each cycle (Total) 107system.cpu.fetch.rateDist::1 22710427 2.52% 55.16% # Number of instructions fetched each cycle (Total) 108system.cpu.fetch.rateDist::2 38716038 4.29% 59.46% # Number of instructions fetched each cycle (Total) 109system.cpu.fetch.rateDist::3 47664478 5.29% 64.74% # Number of instructions fetched each cycle (Total) 110system.cpu.fetch.rateDist::4 40313573 4.47% 69.21% # Number of instructions fetched each cycle (Total) 111system.cpu.fetch.rateDist::5 46765093 5.19% 74.40% # Number of instructions fetched each cycle (Total) 112system.cpu.fetch.rateDist::6 38987797 4.32% 78.72% # Number of instructions fetched each cycle (Total) 113system.cpu.fetch.rateDist::7 17988591 1.99% 80.72% # Number of instructions fetched each cycle (Total) 114system.cpu.fetch.rateDist::8 173896232 19.28% 100.00% # Number of instructions fetched each cycle (Total) | 264system.cpu.fetch.rateDist::0 480453401 52.90% 52.90% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::1 22859151 2.52% 55.42% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::2 38736937 4.27% 59.69% # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::3 47688218 5.25% 64.94% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::4 40498646 4.46% 69.40% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::5 46746329 5.15% 74.54% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::6 38999717 4.29% 78.84% # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::7 18064778 1.99% 80.83% # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::8 174109009 19.17% 100.00% # Number of instructions fetched each cycle (Total) |
| 115system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 116system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 117system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 273system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 274system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 275system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 118system.cpu.fetch.rateDist::total 901821520 # Number of instructions fetched each cycle (Total) 119system.cpu.fetch.branchRate 0.329431 # Number of branch fetches per cycle 120system.cpu.fetch.rate 2.364356 # Number of inst fetches per cycle 121system.cpu.decode.IdleCycles 319221723 # Number of cycles decode is idle 122system.cpu.decode.BlockedCycles 98997420 # Number of cycles decode is blocked 123system.cpu.decode.RunCycles 402809489 # Number of cycles decode is running 124system.cpu.decode.UnblockCycles 15071254 # Number of cycles decode is unblocking 125system.cpu.decode.SquashCycles 65721634 # Number of cycles decode is squashing 126system.cpu.decode.BranchResolved 46024947 # Number of times decode resolved a branch 127system.cpu.decode.BranchMispred 700 # Number of times decode detected a branch misprediction 128system.cpu.decode.DecodedInsts 2336308946 # Number of instructions handled by decode 129system.cpu.decode.SquashedInsts 2514 # Number of squashed instructions handled by decode 130system.cpu.rename.SquashCycles 65721634 # Number of cycles rename is squashing 131system.cpu.rename.IdleCycles 340227863 # Number of cycles rename is idle 132system.cpu.rename.BlockCycles 45083280 # Number of cycles rename is blocking 133system.cpu.rename.serializeStallCycles 12690 # count of cycles rename stalled for serializing inst 134system.cpu.rename.RunCycles 395699548 # Number of cycles rename is running 135system.cpu.rename.UnblockCycles 55076505 # Number of cycles rename is unblocking 136system.cpu.rename.RenamedInsts 2280327240 # Number of instructions processed by rename 137system.cpu.rename.ROBFullEvents 18280 # Number of times rename has blocked due to ROB full 138system.cpu.rename.IQFullEvents 4628387 # Number of times rename has blocked due to IQ full 139system.cpu.rename.LSQFullEvents 42035635 # Number of times rename has blocked due to LSQ full 140system.cpu.rename.RenamedOperands 2254967875 # Number of destination operands rename has renamed 141system.cpu.rename.RenameLookups 10525732443 # Number of register rename lookups that rename has made 142system.cpu.rename.int_rename_lookups 10525728121 # Number of integer rename lookups 143system.cpu.rename.fp_rename_lookups 4322 # Number of floating rename lookups 144system.cpu.rename.CommittedMaps 1706319962 # Number of HB maps that are committed 145system.cpu.rename.UndoneMaps 548647913 # Number of HB maps that are undone due to squashing 146system.cpu.rename.serializingInsts 1655 # count of serializing insts renamed 147system.cpu.rename.tempSerializingInsts 1650 # count of temporary serializing insts renamed 148system.cpu.rename.skidInsts 127333779 # count of insts added to the skid buffer 149system.cpu.memDep0.insertedLoads 622133622 # Number of loads inserted to the mem dependence unit. 150system.cpu.memDep0.insertedStores 217936550 # Number of stores inserted to the mem dependence unit. 151system.cpu.memDep0.conflictingLoads 85018666 # Number of conflicting loads. 152system.cpu.memDep0.conflictingStores 64907509 # Number of conflicting stores. 153system.cpu.iq.iqInstsAdded 2181155194 # Number of instructions added to the IQ (excludes non-spec) 154system.cpu.iq.iqNonSpecInstsAdded 1636 # Number of non-speculative instructions added to the IQ 155system.cpu.iq.iqInstsIssued 2010118619 # Number of instructions issued 156system.cpu.iq.iqSquashedInstsIssued 4778350 # Number of squashed instructions issued 157system.cpu.iq.iqSquashedInstsExamined 453891413 # Number of squashed instructions iterated over during squash; mainly for profiling 158system.cpu.iq.iqSquashedOperandsExamined 1054915735 # Number of squashed operands that are examined and possibly removed from graph 159system.cpu.iq.iqSquashedNonSpecRemoved 1462 # Number of squashed non-spec instructions that were removed 160system.cpu.iq.issued_per_cycle::samples 901821520 # Number of insts issued each cycle 161system.cpu.iq.issued_per_cycle::mean 2.228954 # Number of insts issued each cycle 162system.cpu.iq.issued_per_cycle::stdev 1.928169 # Number of insts issued each cycle | 276system.cpu.fetch.rateDist::total 908156186 # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.branchRate 0.316405 # Number of branch fetches per cycle 278system.cpu.fetch.rate 2.271447 # Number of inst fetches per cycle 279system.cpu.decode.IdleCycles 320351849 # Number of cycles decode is idle 280system.cpu.decode.BlockedCycles 103310609 # Number of cycles decode is blocked 281system.cpu.decode.RunCycles 403372314 # Number of cycles decode is running 282system.cpu.decode.UnblockCycles 15098642 # Number of cycles decode is unblocking 283system.cpu.decode.SquashCycles 66022772 # Number of cycles decode is squashing 284system.cpu.decode.BranchResolved 46034722 # Number of times decode resolved a branch 285system.cpu.decode.BranchMispred 704 # Number of times decode detected a branch misprediction 286system.cpu.decode.DecodedInsts 2339352792 # Number of instructions handled by decode 287system.cpu.decode.SquashedInsts 2529 # Number of squashed instructions handled by decode 288system.cpu.rename.SquashCycles 66022772 # Number of cycles rename is squashing 289system.cpu.rename.IdleCycles 341796573 # Number of cycles rename is idle 290system.cpu.rename.BlockCycles 48717971 # Number of cycles rename is blocking 291system.cpu.rename.serializeStallCycles 14906 # count of cycles rename stalled for serializing inst 292system.cpu.rename.RunCycles 395855837 # Number of cycles rename is running 293system.cpu.rename.UnblockCycles 55748127 # Number of cycles rename is unblocking 294system.cpu.rename.RenamedInsts 2282794185 # Number of instructions processed by rename 295system.cpu.rename.ROBFullEvents 39847 # Number of times rename has blocked due to ROB full 296system.cpu.rename.IQFullEvents 4611517 # Number of times rename has blocked due to IQ full 297system.cpu.rename.LSQFullEvents 42695661 # Number of times rename has blocked due to LSQ full 298system.cpu.rename.RenamedOperands 2257537981 # Number of destination operands rename has renamed 299system.cpu.rename.RenameLookups 10537280026 # Number of register rename lookups that rename has made 300system.cpu.rename.int_rename_lookups 10537275559 # Number of integer rename lookups 301system.cpu.rename.fp_rename_lookups 4467 # Number of floating rename lookups 302system.cpu.rename.CommittedMaps 1706320026 # Number of HB maps that are committed 303system.cpu.rename.UndoneMaps 551217955 # Number of HB maps that are undone due to squashing 304system.cpu.rename.serializingInsts 838 # count of serializing insts renamed 305system.cpu.rename.tempSerializingInsts 835 # count of temporary serializing insts renamed 306system.cpu.rename.skidInsts 129599333 # count of insts added to the skid buffer 307system.cpu.memDep0.insertedLoads 622569059 # Number of loads inserted to the mem dependence unit. 308system.cpu.memDep0.insertedStores 218142237 # Number of stores inserted to the mem dependence unit. 309system.cpu.memDep0.conflictingLoads 84983278 # Number of conflicting loads. 310system.cpu.memDep0.conflictingStores 64739003 # Number of conflicting stores. 311system.cpu.iq.iqInstsAdded 2182778805 # Number of instructions added to the IQ (excludes non-spec) 312system.cpu.iq.iqNonSpecInstsAdded 865 # Number of non-speculative instructions added to the IQ 313system.cpu.iq.iqInstsIssued 2010794421 # Number of instructions issued 314system.cpu.iq.iqSquashedInstsIssued 4810108 # Number of squashed instructions issued 315system.cpu.iq.iqSquashedInstsExamined 455220170 # Number of squashed instructions iterated over during squash; mainly for profiling 316system.cpu.iq.iqSquashedOperandsExamined 1060725588 # Number of squashed operands that are examined and possibly removed from graph 317system.cpu.iq.iqSquashedNonSpecRemoved 683 # Number of squashed non-spec instructions that were removed 318system.cpu.iq.issued_per_cycle::samples 908156186 # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::mean 2.214150 # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::stdev 1.929063 # Number of insts issued each cycle |
| 163system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 321system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 164system.cpu.iq.issued_per_cycle::0 241649201 26.80% 26.80% # Number of insts issued each cycle 165system.cpu.iq.issued_per_cycle::1 133398569 14.79% 41.59% # Number of insts issued each cycle 166system.cpu.iq.issued_per_cycle::2 156277076 17.33% 58.92% # Number of insts issued each cycle 167system.cpu.iq.issued_per_cycle::3 115862389 12.85% 71.76% # Number of insts issued each cycle 168system.cpu.iq.issued_per_cycle::4 125673548 13.94% 85.70% # Number of insts issued each cycle 169system.cpu.iq.issued_per_cycle::5 75895678 8.42% 94.12% # Number of insts issued each cycle 170system.cpu.iq.issued_per_cycle::6 39700475 4.40% 98.52% # Number of insts issued each cycle 171system.cpu.iq.issued_per_cycle::7 10713373 1.19% 99.71% # Number of insts issued each cycle 172system.cpu.iq.issued_per_cycle::8 2651211 0.29% 100.00% # Number of insts issued each cycle | 322system.cpu.iq.issued_per_cycle::0 247277493 27.23% 27.23% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::1 133932127 14.75% 41.98% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::2 156228000 17.20% 59.18% # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::3 116195915 12.79% 71.97% # Number of insts issued each cycle 326system.cpu.iq.issued_per_cycle::4 125706835 13.84% 85.82% # Number of insts issued each cycle 327system.cpu.iq.issued_per_cycle::5 75923793 8.36% 94.18% # Number of insts issued each cycle 328system.cpu.iq.issued_per_cycle::6 39533015 4.35% 98.53% # Number of insts issued each cycle 329system.cpu.iq.issued_per_cycle::7 10697910 1.18% 99.71% # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::8 2661098 0.29% 100.00% # Number of insts issued each cycle |
| 173system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 174system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 175system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 331system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 332system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 333system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 176system.cpu.iq.issued_per_cycle::total 901821520 # Number of insts issued each cycle | 334system.cpu.iq.issued_per_cycle::total 908156186 # Number of insts issued each cycle |
| 177system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 335system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 178system.cpu.iq.fu_full::IntAlu 707951 2.82% 2.82% # attempts to use FU when none available 179system.cpu.iq.fu_full::IntMult 4768 0.02% 2.84% # attempts to use FU when none available 180system.cpu.iq.fu_full::IntDiv 0 0.00% 2.84% # attempts to use FU when none available 181system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.84% # attempts to use FU when none available 182system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.84% # attempts to use FU when none available 183system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.84% # attempts to use FU when none available 184system.cpu.iq.fu_full::FloatMult 0 0.00% 2.84% # attempts to use FU when none available 185system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.84% # attempts to use FU when none available 186system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.84% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.84% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.84% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.84% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.84% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.84% # attempts to use FU when none available 192system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.84% # attempts to use FU when none available 193system.cpu.iq.fu_full::SimdMult 0 0.00% 2.84% # attempts to use FU when none available 194system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.84% # attempts to use FU when none available 195system.cpu.iq.fu_full::SimdShift 0 0.00% 2.84% # attempts to use FU when none available 196system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.84% # attempts to use FU when none available 197system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.84% # attempts to use FU when none available 198system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.84% # attempts to use FU when none available 199system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.84% # attempts to use FU when none available 200system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.84% # attempts to use FU when none available 201system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.84% # attempts to use FU when none available 202system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.84% # attempts to use FU when none available 203system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.84% # attempts to use FU when none available 204system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.84% # attempts to use FU when none available 205system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.84% # attempts to use FU when none available 206system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.84% # attempts to use FU when none available 207system.cpu.iq.fu_full::MemRead 19054904 75.97% 78.81% # attempts to use FU when none available 208system.cpu.iq.fu_full::MemWrite 5315511 21.19% 100.00% # attempts to use FU when none available | 336system.cpu.iq.fu_full::IntAlu 703286 2.81% 2.81% # attempts to use FU when none available 337system.cpu.iq.fu_full::IntMult 4771 0.02% 2.83% # attempts to use FU when none available 338system.cpu.iq.fu_full::IntDiv 0 0.00% 2.83% # attempts to use FU when none available 339system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.83% # attempts to use FU when none available 340system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.83% # attempts to use FU when none available 341system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.83% # attempts to use FU when none available 342system.cpu.iq.fu_full::FloatMult 0 0.00% 2.83% # attempts to use FU when none available 343system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.83% # attempts to use FU when none available 344system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.83% # attempts to use FU when none available 345system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.83% # attempts to use FU when none available 346system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.83% # attempts to use FU when none available 347system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.83% # attempts to use FU when none available 348system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.83% # attempts to use FU when none available 349system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.83% # attempts to use FU when none available 350system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.83% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdMult 0 0.00% 2.83% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.83% # attempts to use FU when none available 353system.cpu.iq.fu_full::SimdShift 0 0.00% 2.83% # attempts to use FU when none available 354system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.83% # attempts to use FU when none available 355system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.83% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.83% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.83% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.83% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.83% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.83% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.83% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.83% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.83% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.83% # attempts to use FU when none available 365system.cpu.iq.fu_full::MemRead 19012865 76.06% 78.90% # attempts to use FU when none available 366system.cpu.iq.fu_full::MemWrite 5274676 21.10% 100.00% # attempts to use FU when none available |
| 209system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 210system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 211system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 367system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 368system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 369system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 212system.cpu.iq.FU_type_0::IntAlu 1230445204 61.21% 61.21% # Type of FU issued 213system.cpu.iq.FU_type_0::IntMult 929764 0.05% 61.26% # Type of FU issued | 370system.cpu.iq.FU_type_0::IntAlu 1230823853 61.21% 61.21% # Type of FU issued 371system.cpu.iq.FU_type_0::IntMult 930532 0.05% 61.26% # Type of FU issued |
| 214system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued 215system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued 216system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued 217system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued 218system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued 219system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued 220system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued --- 6 unchanged lines hidden (view full) --- 228system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued 229system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued 230system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued 231system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued 232system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued 233system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued 234system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued 235system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued | 372system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.26% # Type of FU issued 373system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.26% # Type of FU issued 374system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.26% # Type of FU issued 375system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.26% # Type of FU issued 376system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.26% # Type of FU issued 377system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.26% # Type of FU issued 378system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.26% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.26% # Type of FU issued --- 6 unchanged lines hidden (view full) --- 386system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.26% # Type of FU issued 387system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.26% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.26% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.26% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.26% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.26% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.26% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdFloatCvt 72 0.00% 61.26% # Type of FU issued |
| 236system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 61.26% # Type of FU issued 237system.cpu.iq.FU_type_0::SimdFloatMisc 31 0.00% 61.26% # Type of FU issued 238system.cpu.iq.FU_type_0::SimdFloatMult 14 0.00% 61.26% # Type of FU issued | 394system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.26% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdFloatMisc 30 0.00% 61.26% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdFloatMult 15 0.00% 61.26% # Type of FU issued |
| 239system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued 240system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued | 397system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.26% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.26% # Type of FU issued |
| 241system.cpu.iq.FU_type_0::MemRead 585105545 29.11% 90.37% # Type of FU issued 242system.cpu.iq.FU_type_0::MemWrite 193637984 9.63% 100.00% # Type of FU issued | 399system.cpu.iq.FU_type_0::MemRead 585374477 29.11% 90.37% # Type of FU issued 400system.cpu.iq.FU_type_0::MemWrite 193665439 9.63% 100.00% # Type of FU issued |
| 243system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 244system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 401system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 402system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 245system.cpu.iq.FU_type_0::total 2010118619 # Type of FU issued 246system.cpu.iq.rate 2.213059 # Inst issue rate 247system.cpu.iq.fu_busy_cnt 25083134 # FU busy when requested 248system.cpu.iq.fu_busy_rate 0.012478 # FU busy rate (busy events/executed inst) 249system.cpu.iq.int_inst_queue_reads 4951919807 # Number of integer instruction queue reads 250system.cpu.iq.int_inst_queue_writes 2635232712 # Number of integer instruction queue writes 251system.cpu.iq.int_inst_queue_wakeup_accesses 1952804452 # Number of integer instruction queue wakeup accesses 252system.cpu.iq.fp_inst_queue_reads 435 # Number of floating instruction queue reads 253system.cpu.iq.fp_inst_queue_writes 778 # Number of floating instruction queue writes 254system.cpu.iq.fp_inst_queue_wakeup_accesses 167 # Number of floating instruction queue wakeup accesses 255system.cpu.iq.int_alu_accesses 2035201532 # Number of integer alu accesses 256system.cpu.iq.fp_alu_accesses 221 # Number of floating point alu accesses 257system.cpu.iew.lsq.thread0.forwLoads 63665905 # Number of loads that had data forwarded from stores | 403system.cpu.iq.FU_type_0::total 2010794421 # Type of FU issued 404system.cpu.iq.rate 2.123628 # Inst issue rate 405system.cpu.iq.fu_busy_cnt 24995598 # FU busy when requested 406system.cpu.iq.fu_busy_rate 0.012431 # FU busy rate (busy events/executed inst) 407system.cpu.iq.int_inst_queue_reads 4959550302 # Number of integer instruction queue reads 408system.cpu.iq.int_inst_queue_writes 2638184259 # Number of integer instruction queue writes 409system.cpu.iq.int_inst_queue_wakeup_accesses 1953078988 # Number of integer instruction queue wakeup accesses 410system.cpu.iq.fp_inst_queue_reads 432 # Number of floating instruction queue reads 411system.cpu.iq.fp_inst_queue_writes 858 # Number of floating instruction queue writes 412system.cpu.iq.fp_inst_queue_wakeup_accesses 164 # Number of floating instruction queue wakeup accesses 413system.cpu.iq.int_alu_accesses 2035789802 # Number of integer alu accesses 414system.cpu.iq.fp_alu_accesses 217 # Number of floating point alu accesses 415system.cpu.iew.lsq.thread0.forwLoads 63764603 # Number of loads that had data forwarded from stores |
| 258system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 416system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 259system.cpu.iew.lsq.thread0.squashedLoads 136206849 # Number of loads squashed 260system.cpu.iew.lsq.thread0.ignoredResponses 286531 # Number of memory responses ignored because the instruction is squashed 261system.cpu.iew.lsq.thread0.memOrderViolation 188011 # Number of memory ordering violations 262system.cpu.iew.lsq.thread0.squashedStores 43089501 # Number of stores squashed | 417system.cpu.iew.lsq.thread0.squashedLoads 136642278 # Number of loads squashed 418system.cpu.iew.lsq.thread0.ignoredResponses 284566 # Number of memory responses ignored because the instruction is squashed 419system.cpu.iew.lsq.thread0.memOrderViolation 187935 # Number of memory ordering violations 420system.cpu.iew.lsq.thread0.squashedStores 43295180 # Number of stores squashed |
| 263system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 264system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 421system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 422system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 265system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled 266system.cpu.iew.lsq.thread0.cacheBlocked 117367 # Number of times an access to memory failed due to the cache being blocked | 423system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 424system.cpu.iew.lsq.thread0.cacheBlocked 386993 # Number of times an access to memory failed due to the cache being blocked |
| 267system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 425system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 268system.cpu.iew.iewSquashCycles 65721634 # Number of cycles IEW is squashing 269system.cpu.iew.iewBlockCycles 20156212 # Number of cycles IEW is blocking 270system.cpu.iew.iewUnblockCycles 1080802 # Number of cycles IEW is unblocking 271system.cpu.iew.iewDispatchedInsts 2181156911 # Number of instructions dispatched to IQ 272system.cpu.iew.iewDispSquashedInsts 5548348 # Number of squashed instructions skipped by dispatch 273system.cpu.iew.iewDispLoadInsts 622133622 # Number of dispatched load instructions 274system.cpu.iew.iewDispStoreInsts 217936550 # Number of dispatched store instructions 275system.cpu.iew.iewDispNonSpecInsts 1571 # Number of dispatched non-speculative instructions 276system.cpu.iew.iewIQFullEvents 177848 # Number of times the IQ has become full, causing a stall 277system.cpu.iew.iewLSQFullEvents 42316 # Number of times the LSQ has become full, causing a stall 278system.cpu.iew.memOrderViolationEvents 188011 # Number of memory order violations 279system.cpu.iew.predictedTakenIncorrect 8591764 # Number of branches that were predicted taken incorrectly 280system.cpu.iew.predictedNotTakenIncorrect 10177079 # Number of branches that were predicted not taken incorrectly 281system.cpu.iew.branchMispredicts 18768843 # Number of branch mispredicts detected at execute 282system.cpu.iew.iewExecutedInsts 1980852010 # Number of executed instructions 283system.cpu.iew.iewExecLoadInsts 570685009 # Number of load instructions executed 284system.cpu.iew.iewExecSquashedInsts 29266609 # Number of squashed instructions skipped in execute | 426system.cpu.iew.iewSquashCycles 66022772 # Number of cycles IEW is squashing 427system.cpu.iew.iewBlockCycles 23145640 # Number of cycles IEW is blocking 428system.cpu.iew.iewUnblockCycles 1044628 # Number of cycles IEW is unblocking 429system.cpu.iew.iewDispatchedInsts 2182779773 # Number of instructions dispatched to IQ 430system.cpu.iew.iewDispSquashedInsts 5713944 # Number of squashed instructions skipped by dispatch 431system.cpu.iew.iewDispLoadInsts 622569059 # Number of dispatched load instructions 432system.cpu.iew.iewDispStoreInsts 218142237 # Number of dispatched store instructions 433system.cpu.iew.iewDispNonSpecInsts 798 # Number of dispatched non-speculative instructions 434system.cpu.iew.iewIQFullEvents 173655 # Number of times the IQ has become full, causing a stall 435system.cpu.iew.iewLSQFullEvents 44651 # Number of times the LSQ has become full, causing a stall 436system.cpu.iew.memOrderViolationEvents 187935 # Number of memory order violations 437system.cpu.iew.predictedTakenIncorrect 8601247 # Number of branches that were predicted taken incorrectly 438system.cpu.iew.predictedNotTakenIncorrect 10177350 # Number of branches that were predicted not taken incorrectly 439system.cpu.iew.branchMispredicts 18778597 # Number of branch mispredicts detected at execute 440system.cpu.iew.iewExecutedInsts 1981378382 # Number of executed instructions 441system.cpu.iew.iewExecLoadInsts 570935022 # Number of load instructions executed 442system.cpu.iew.iewExecSquashedInsts 29416039 # Number of squashed instructions skipped in execute |
| 285system.cpu.iew.exec_swp 0 # number of swp insts executed | 443system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 286system.cpu.iew.exec_nop 81 # number of nop insts executed 287system.cpu.iew.exec_refs 761345389 # number of memory reference insts executed 288system.cpu.iew.exec_branches 237537296 # Number of branches executed 289system.cpu.iew.exec_stores 190660380 # Number of stores executed 290system.cpu.iew.exec_rate 2.180837 # Inst execution rate 291system.cpu.iew.wb_sent 1961817327 # cumulative count of insts sent to commit 292system.cpu.iew.wb_count 1952804619 # cumulative count of insts written-back 293system.cpu.iew.wb_producers 1293399468 # num instructions producing a value 294system.cpu.iew.wb_consumers 2065182627 # num instructions consuming a value | 444system.cpu.iew.exec_nop 103 # number of nop insts executed 445system.cpu.iew.exec_refs 761630934 # number of memory reference insts executed 446system.cpu.iew.exec_branches 237544754 # Number of branches executed 447system.cpu.iew.exec_stores 190695912 # Number of stores executed 448system.cpu.iew.exec_rate 2.092561 # Inst execution rate 449system.cpu.iew.wb_sent 1962075581 # cumulative count of insts sent to commit 450system.cpu.iew.wb_count 1953079152 # cumulative count of insts written-back 451system.cpu.iew.wb_producers 1293757962 # num instructions producing a value 452system.cpu.iew.wb_consumers 2065123050 # num instructions consuming a value |
| 295system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 453system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 296system.cpu.iew.wb_rate 2.149958 # insts written-back per cycle 297system.cpu.iew.wb_fanout 0.626288 # average fanout of values written-back | 454system.cpu.iew.wb_rate 2.062674 # insts written-back per cycle 455system.cpu.iew.wb_fanout 0.626480 # average fanout of values written-back |
| 298system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 456system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 299system.cpu.commit.commitSquashedInsts 458146610 # The number of squashed insts skipped by commit 300system.cpu.commit.commitNonSpecStalls 174 # The number of times commit has been forced to stall to communicate backwards 301system.cpu.commit.branchMispredicts 16035536 # The number of times a branch was mispredicted 302system.cpu.commit.committed_per_cycle::samples 836099887 # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::mean 2.060847 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::stdev 2.764107 # Number of insts commited each cycle | 457system.cpu.commit.commitSquashedInsts 459769347 # The number of squashed insts skipped by commit 458system.cpu.commit.commitNonSpecStalls 182 # The number of times commit has been forced to stall to communicate backwards 459system.cpu.commit.branchMispredicts 16044351 # The number of times a branch was mispredicted 460system.cpu.commit.committed_per_cycle::samples 842133415 # Number of insts commited each cycle 461system.cpu.commit.committed_per_cycle::mean 2.046082 # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::stdev 2.757625 # Number of insts commited each cycle |
| 305system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 463system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 306system.cpu.commit.committed_per_cycle::0 346421369 41.43% 41.43% # Number of insts commited each cycle 307system.cpu.commit.committed_per_cycle::1 193942009 23.20% 64.63% # Number of insts commited each cycle 308system.cpu.commit.committed_per_cycle::2 73849330 8.83% 73.46% # Number of insts commited each cycle 309system.cpu.commit.committed_per_cycle::3 35339477 4.23% 77.69% # Number of insts commited each cycle 310system.cpu.commit.committed_per_cycle::4 18485791 2.21% 79.90% # Number of insts commited each cycle 311system.cpu.commit.committed_per_cycle::5 30991807 3.71% 83.61% # Number of insts commited each cycle 312system.cpu.commit.committed_per_cycle::6 19654660 2.35% 85.96% # Number of insts commited each cycle 313system.cpu.commit.committed_per_cycle::7 10738938 1.28% 87.24% # Number of insts commited each cycle 314system.cpu.commit.committed_per_cycle::8 106676506 12.76% 100.00% # Number of insts commited each cycle | 464system.cpu.commit.committed_per_cycle::0 351966566 41.79% 41.79% # Number of insts commited each cycle 465system.cpu.commit.committed_per_cycle::1 194208080 23.06% 64.86% # Number of insts commited each cycle 466system.cpu.commit.committed_per_cycle::2 73932281 8.78% 73.64% # Number of insts commited each cycle 467system.cpu.commit.committed_per_cycle::3 35396184 4.20% 77.84% # Number of insts commited each cycle 468system.cpu.commit.committed_per_cycle::4 18675547 2.22% 80.06% # Number of insts commited each cycle 469system.cpu.commit.committed_per_cycle::5 31087553 3.69% 83.75% # Number of insts commited each cycle 470system.cpu.commit.committed_per_cycle::6 19760319 2.35% 86.09% # Number of insts commited each cycle 471system.cpu.commit.committed_per_cycle::7 10744228 1.28% 87.37% # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::8 106362657 12.63% 100.00% # Number of insts commited each cycle |
| 315system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 316system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 317system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 473system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 474system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 475system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 318system.cpu.commit.committed_per_cycle::total 836099887 # Number of insts commited each cycle 319system.cpu.commit.committedInsts 1544563061 # Number of instructions committed 320system.cpu.commit.committedOps 1723073873 # Number of ops (including micro ops) committed | 476system.cpu.commit.committed_per_cycle::total 842133415 # Number of insts commited each cycle 477system.cpu.commit.committedInsts 1544563101 # Number of instructions committed 478system.cpu.commit.committedOps 1723073913 # Number of ops (including micro ops) committed |
| 321system.cpu.commit.swp_count 0 # Number of s/w prefetches committed | 479system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| 322system.cpu.commit.refs 660773822 # Number of memory references committed 323system.cpu.commit.loads 485926773 # Number of loads committed | 480system.cpu.commit.refs 660773838 # Number of memory references committed 481system.cpu.commit.loads 485926781 # Number of loads committed |
| 324system.cpu.commit.membars 62 # Number of memory barriers committed | 482system.cpu.commit.membars 62 # Number of memory barriers committed |
| 325system.cpu.commit.branches 213462430 # Number of branches committed | 483system.cpu.commit.branches 213462438 # Number of branches committed |
| 326system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. | 484system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. |
| 327system.cpu.commit.int_insts 1536941857 # Number of committed integer instructions. | 485system.cpu.commit.int_insts 1536941889 # Number of committed integer instructions. |
| 328system.cpu.commit.function_calls 13665177 # Number of function calls committed. | 486system.cpu.commit.function_calls 13665177 # Number of function calls committed. |
| 329system.cpu.commit.bw_lim_events 106676506 # number cycles where commit BW limit reached | 487system.cpu.commit.bw_lim_events 106362657 # number cycles where commit BW limit reached |
| 330system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 488system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 331system.cpu.rob.rob_reads 2910643265 # The number of ROB reads 332system.cpu.rob.rob_writes 4428322151 # The number of ROB writes 333system.cpu.timesIdled 678500 # Number of times that the entire CPU went into an idle state and unscheduled itself 334system.cpu.idleCycles 6477371 # Total number of cycles that the CPU has spent unscheduled due to idling 335system.cpu.committedInsts 1544563043 # Number of Instructions Simulated 336system.cpu.committedOps 1723073855 # Number of Ops (including micro ops) Simulated 337system.cpu.committedInsts_total 1544563043 # Number of Instructions Simulated 338system.cpu.cpi 0.588062 # CPI: Cycles Per Instruction 339system.cpu.cpi_total 0.588062 # CPI: Total CPI of All Threads 340system.cpu.ipc 1.700501 # IPC: Instructions Per Cycle 341system.cpu.ipc_total 1.700501 # IPC: Total IPC of All Threads 342system.cpu.int_regfile_reads 9924419417 # number of integer regfile reads 343system.cpu.int_regfile_writes 1932830839 # number of integer regfile writes 344system.cpu.fp_regfile_reads 180 # number of floating regfile reads 345system.cpu.fp_regfile_writes 196 # number of floating regfile writes 346system.cpu.misc_regfile_reads 2885680755 # number of misc regfile reads 347system.cpu.misc_regfile_writes 132 # number of misc regfile writes 348system.cpu.icache.replacements 25 # number of replacements 349system.cpu.icache.tagsinuse 628.471657 # Cycle average of tags in use 350system.cpu.icache.total_refs 282187157 # Total number of references to valid blocks. 351system.cpu.icache.sampled_refs 785 # Sample count of references to valid blocks. 352system.cpu.icache.avg_refs 359474.085350 # Average number of references to valid blocks. | 489system.cpu.rob.rob_reads 2918613419 # The number of ROB reads 490system.cpu.rob.rob_writes 4431868415 # The number of ROB writes 491system.cpu.timesIdled 795856 # Number of times that the entire CPU went into an idle state and unscheduled itself 492system.cpu.idleCycles 38711414 # Total number of cycles that the CPU has spent unscheduled due to idling 493system.cpu.committedInsts 1544563083 # Number of Instructions Simulated 494system.cpu.committedOps 1723073895 # Number of Ops (including micro ops) Simulated 495system.cpu.committedInsts_total 1544563083 # Number of Instructions Simulated 496system.cpu.cpi 0.613033 # CPI: Cycles Per Instruction 497system.cpu.cpi_total 0.613033 # CPI: Total CPI of All Threads 498system.cpu.ipc 1.631234 # IPC: Instructions Per Cycle 499system.cpu.ipc_total 1.631234 # IPC: Total IPC of All Threads 500system.cpu.int_regfile_reads 9926647662 # number of integer regfile reads 501system.cpu.int_regfile_writes 1933066427 # number of integer regfile writes 502system.cpu.fp_regfile_reads 168 # number of floating regfile reads 503system.cpu.fp_regfile_writes 190 # number of floating regfile writes 504system.cpu.misc_regfile_reads 2888912367 # number of misc regfile reads 505system.cpu.misc_regfile_writes 148 # number of misc regfile writes 506system.cpu.icache.replacements 20 # number of replacements 507system.cpu.icache.tagsinuse 632.636403 # Cycle average of tags in use 508system.cpu.icache.total_refs 282800594 # Total number of references to valid blocks. 509system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks. 510system.cpu.icache.avg_refs 359797.193384 # Average number of references to valid blocks. |
| 353system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 511system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 354system.cpu.icache.occ_blocks::cpu.inst 628.471657 # Average occupied blocks per requestor 355system.cpu.icache.occ_percent::cpu.inst 0.306871 # Average percentage of cache occupancy 356system.cpu.icache.occ_percent::total 0.306871 # Average percentage of cache occupancy 357system.cpu.icache.ReadReq_hits::cpu.inst 282187157 # number of ReadReq hits 358system.cpu.icache.ReadReq_hits::total 282187157 # number of ReadReq hits 359system.cpu.icache.demand_hits::cpu.inst 282187157 # number of demand (read+write) hits 360system.cpu.icache.demand_hits::total 282187157 # number of demand (read+write) hits 361system.cpu.icache.overall_hits::cpu.inst 282187157 # number of overall hits 362system.cpu.icache.overall_hits::total 282187157 # number of overall hits 363system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses 364system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses 365system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses 366system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses 367system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses 368system.cpu.icache.overall_misses::total 1154 # number of overall misses 369system.cpu.icache.ReadReq_miss_latency::cpu.inst 39417000 # number of ReadReq miss cycles 370system.cpu.icache.ReadReq_miss_latency::total 39417000 # number of ReadReq miss cycles 371system.cpu.icache.demand_miss_latency::cpu.inst 39417000 # number of demand (read+write) miss cycles 372system.cpu.icache.demand_miss_latency::total 39417000 # number of demand (read+write) miss cycles 373system.cpu.icache.overall_miss_latency::cpu.inst 39417000 # number of overall miss cycles 374system.cpu.icache.overall_miss_latency::total 39417000 # number of overall miss cycles 375system.cpu.icache.ReadReq_accesses::cpu.inst 282188311 # number of ReadReq accesses(hits+misses) 376system.cpu.icache.ReadReq_accesses::total 282188311 # number of ReadReq accesses(hits+misses) 377system.cpu.icache.demand_accesses::cpu.inst 282188311 # number of demand (read+write) accesses 378system.cpu.icache.demand_accesses::total 282188311 # number of demand (read+write) accesses 379system.cpu.icache.overall_accesses::cpu.inst 282188311 # number of overall (read+write) accesses 380system.cpu.icache.overall_accesses::total 282188311 # number of overall (read+write) accesses | 512system.cpu.icache.occ_blocks::cpu.inst 632.636403 # Average occupied blocks per requestor 513system.cpu.icache.occ_percent::cpu.inst 0.308904 # Average percentage of cache occupancy 514system.cpu.icache.occ_percent::total 0.308904 # Average percentage of cache occupancy 515system.cpu.icache.ReadReq_hits::cpu.inst 282800594 # number of ReadReq hits 516system.cpu.icache.ReadReq_hits::total 282800594 # number of ReadReq hits 517system.cpu.icache.demand_hits::cpu.inst 282800594 # number of demand (read+write) hits 518system.cpu.icache.demand_hits::total 282800594 # number of demand (read+write) hits 519system.cpu.icache.overall_hits::cpu.inst 282800594 # number of overall hits 520system.cpu.icache.overall_hits::total 282800594 # number of overall hits 521system.cpu.icache.ReadReq_misses::cpu.inst 1137 # number of ReadReq misses 522system.cpu.icache.ReadReq_misses::total 1137 # number of ReadReq misses 523system.cpu.icache.demand_misses::cpu.inst 1137 # number of demand (read+write) misses 524system.cpu.icache.demand_misses::total 1137 # number of demand (read+write) misses 525system.cpu.icache.overall_misses::cpu.inst 1137 # number of overall misses 526system.cpu.icache.overall_misses::total 1137 # number of overall misses 527system.cpu.icache.ReadReq_miss_latency::cpu.inst 39598000 # number of ReadReq miss cycles 528system.cpu.icache.ReadReq_miss_latency::total 39598000 # number of ReadReq miss cycles 529system.cpu.icache.demand_miss_latency::cpu.inst 39598000 # number of demand (read+write) miss cycles 530system.cpu.icache.demand_miss_latency::total 39598000 # number of demand (read+write) miss cycles 531system.cpu.icache.overall_miss_latency::cpu.inst 39598000 # number of overall miss cycles 532system.cpu.icache.overall_miss_latency::total 39598000 # number of overall miss cycles 533system.cpu.icache.ReadReq_accesses::cpu.inst 282801731 # number of ReadReq accesses(hits+misses) 534system.cpu.icache.ReadReq_accesses::total 282801731 # number of ReadReq accesses(hits+misses) 535system.cpu.icache.demand_accesses::cpu.inst 282801731 # number of demand (read+write) accesses 536system.cpu.icache.demand_accesses::total 282801731 # number of demand (read+write) accesses 537system.cpu.icache.overall_accesses::cpu.inst 282801731 # number of overall (read+write) accesses 538system.cpu.icache.overall_accesses::total 282801731 # number of overall (read+write) accesses |
| 381system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 382system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 383system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 384system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 385system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 386system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses | 539system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses 540system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses 541system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses 542system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses 543system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses 544system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses |
| 387system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34156.845754 # average ReadReq miss latency 388system.cpu.icache.ReadReq_avg_miss_latency::total 34156.845754 # average ReadReq miss latency 389system.cpu.icache.demand_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency 390system.cpu.icache.demand_avg_miss_latency::total 34156.845754 # average overall miss latency 391system.cpu.icache.overall_avg_miss_latency::cpu.inst 34156.845754 # average overall miss latency 392system.cpu.icache.overall_avg_miss_latency::total 34156.845754 # average overall miss latency | 545system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34826.737027 # average ReadReq miss latency 546system.cpu.icache.ReadReq_avg_miss_latency::total 34826.737027 # average ReadReq miss latency 547system.cpu.icache.demand_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency 548system.cpu.icache.demand_avg_miss_latency::total 34826.737027 # average overall miss latency 549system.cpu.icache.overall_avg_miss_latency::cpu.inst 34826.737027 # average overall miss latency 550system.cpu.icache.overall_avg_miss_latency::total 34826.737027 # average overall miss latency |
| 393system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 394system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 395system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 396system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 397system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 398system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 399system.cpu.icache.fast_writes 0 # number of fast writes performed 400system.cpu.icache.cache_copies 0 # number of cache copies performed | 551system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 552system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 553system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 554system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 555system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 556system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 557system.cpu.icache.fast_writes 0 # number of fast writes performed 558system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 401system.cpu.icache.ReadReq_mshr_hits::cpu.inst 369 # number of ReadReq MSHR hits 402system.cpu.icache.ReadReq_mshr_hits::total 369 # number of ReadReq MSHR hits 403system.cpu.icache.demand_mshr_hits::cpu.inst 369 # number of demand (read+write) MSHR hits 404system.cpu.icache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits 405system.cpu.icache.overall_mshr_hits::cpu.inst 369 # number of overall MSHR hits 406system.cpu.icache.overall_mshr_hits::total 369 # number of overall MSHR hits 407system.cpu.icache.ReadReq_mshr_misses::cpu.inst 785 # number of ReadReq MSHR misses 408system.cpu.icache.ReadReq_mshr_misses::total 785 # number of ReadReq MSHR misses 409system.cpu.icache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses 410system.cpu.icache.demand_mshr_misses::total 785 # number of demand (read+write) MSHR misses 411system.cpu.icache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses 412system.cpu.icache.overall_mshr_misses::total 785 # number of overall MSHR misses 413system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28514500 # number of ReadReq MSHR miss cycles 414system.cpu.icache.ReadReq_mshr_miss_latency::total 28514500 # number of ReadReq MSHR miss cycles 415system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28514500 # number of demand (read+write) MSHR miss cycles 416system.cpu.icache.demand_mshr_miss_latency::total 28514500 # number of demand (read+write) MSHR miss cycles 417system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28514500 # number of overall MSHR miss cycles 418system.cpu.icache.overall_mshr_miss_latency::total 28514500 # number of overall MSHR miss cycles | 559system.cpu.icache.ReadReq_mshr_hits::cpu.inst 351 # number of ReadReq MSHR hits 560system.cpu.icache.ReadReq_mshr_hits::total 351 # number of ReadReq MSHR hits 561system.cpu.icache.demand_mshr_hits::cpu.inst 351 # number of demand (read+write) MSHR hits 562system.cpu.icache.demand_mshr_hits::total 351 # number of demand (read+write) MSHR hits 563system.cpu.icache.overall_mshr_hits::cpu.inst 351 # number of overall MSHR hits 564system.cpu.icache.overall_mshr_hits::total 351 # number of overall MSHR hits 565system.cpu.icache.ReadReq_mshr_misses::cpu.inst 786 # number of ReadReq MSHR misses 566system.cpu.icache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses 567system.cpu.icache.demand_mshr_misses::cpu.inst 786 # number of demand (read+write) MSHR misses 568system.cpu.icache.demand_mshr_misses::total 786 # number of demand (read+write) MSHR misses 569system.cpu.icache.overall_mshr_misses::cpu.inst 786 # number of overall MSHR misses 570system.cpu.icache.overall_mshr_misses::total 786 # number of overall MSHR misses 571system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28796000 # number of ReadReq MSHR miss cycles 572system.cpu.icache.ReadReq_mshr_miss_latency::total 28796000 # number of ReadReq MSHR miss cycles 573system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28796000 # number of demand (read+write) MSHR miss cycles 574system.cpu.icache.demand_mshr_miss_latency::total 28796000 # number of demand (read+write) MSHR miss cycles 575system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28796000 # number of overall MSHR miss cycles 576system.cpu.icache.overall_mshr_miss_latency::total 28796000 # number of overall MSHR miss cycles |
| 419system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 420system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 421system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 422system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 423system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 424system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses | 577system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses 578system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses 579system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses 580system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses 581system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses 582system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses |
| 425system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36324.203822 # average ReadReq mshr miss latency 426system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36324.203822 # average ReadReq mshr miss latency 427system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency 428system.cpu.icache.demand_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency 429system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36324.203822 # average overall mshr miss latency 430system.cpu.icache.overall_avg_mshr_miss_latency::total 36324.203822 # average overall mshr miss latency | 583system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36636.132316 # average ReadReq mshr miss latency 584system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36636.132316 # average ReadReq mshr miss latency 585system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency 586system.cpu.icache.demand_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency 587system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36636.132316 # average overall mshr miss latency 588system.cpu.icache.overall_avg_mshr_miss_latency::total 36636.132316 # average overall mshr miss latency |
| 431system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 589system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 432system.cpu.dcache.replacements 9616145 # number of replacements 433system.cpu.dcache.tagsinuse 4087.425286 # Cycle average of tags in use 434system.cpu.dcache.total_refs 659915514 # Total number of references to valid blocks. 435system.cpu.dcache.sampled_refs 9620241 # Sample count of references to valid blocks. 436system.cpu.dcache.avg_refs 68.596568 # Average number of references to valid blocks. 437system.cpu.dcache.warmup_cycle 3361698000 # Cycle when the warmup percentage was hit. 438system.cpu.dcache.occ_blocks::cpu.data 4087.425286 # Average occupied blocks per requestor 439system.cpu.dcache.occ_percent::cpu.data 0.997907 # Average percentage of cache occupancy 440system.cpu.dcache.occ_percent::total 0.997907 # Average percentage of cache occupancy 441system.cpu.dcache.ReadReq_hits::cpu.data 492504705 # number of ReadReq hits 442system.cpu.dcache.ReadReq_hits::total 492504705 # number of ReadReq hits 443system.cpu.dcache.WriteReq_hits::cpu.data 167410650 # number of WriteReq hits 444system.cpu.dcache.WriteReq_hits::total 167410650 # number of WriteReq hits 445system.cpu.dcache.LoadLockedReq_hits::cpu.data 94 # number of LoadLockedReq hits 446system.cpu.dcache.LoadLockedReq_hits::total 94 # number of LoadLockedReq hits 447system.cpu.dcache.StoreCondReq_hits::cpu.data 65 # number of StoreCondReq hits 448system.cpu.dcache.StoreCondReq_hits::total 65 # number of StoreCondReq hits 449system.cpu.dcache.demand_hits::cpu.data 659915355 # number of demand (read+write) hits 450system.cpu.dcache.demand_hits::total 659915355 # number of demand (read+write) hits 451system.cpu.dcache.overall_hits::cpu.data 659915355 # number of overall hits 452system.cpu.dcache.overall_hits::total 659915355 # number of overall hits 453system.cpu.dcache.ReadReq_misses::cpu.data 10104493 # number of ReadReq misses 454system.cpu.dcache.ReadReq_misses::total 10104493 # number of ReadReq misses 455system.cpu.dcache.WriteReq_misses::cpu.data 5175397 # number of WriteReq misses 456system.cpu.dcache.WriteReq_misses::total 5175397 # number of WriteReq misses | 590system.cpu.dcache.replacements 9616903 # number of replacements 591system.cpu.dcache.tagsinuse 4087.861296 # Cycle average of tags in use 592system.cpu.dcache.total_refs 660505517 # Total number of references to valid blocks. 593system.cpu.dcache.sampled_refs 9620999 # Sample count of references to valid blocks. 594system.cpu.dcache.avg_refs 68.652488 # Average number of references to valid blocks. 595system.cpu.dcache.warmup_cycle 3324501000 # Cycle when the warmup percentage was hit. 596system.cpu.dcache.occ_blocks::cpu.data 4087.861296 # Average occupied blocks per requestor 597system.cpu.dcache.occ_percent::cpu.data 0.998013 # Average percentage of cache occupancy 598system.cpu.dcache.occ_percent::total 0.998013 # Average percentage of cache occupancy 599system.cpu.dcache.ReadReq_hits::cpu.data 492433938 # number of ReadReq hits 600system.cpu.dcache.ReadReq_hits::total 492433938 # number of ReadReq hits 601system.cpu.dcache.WriteReq_hits::cpu.data 168071407 # number of WriteReq hits 602system.cpu.dcache.WriteReq_hits::total 168071407 # number of WriteReq hits 603system.cpu.dcache.LoadLockedReq_hits::cpu.data 99 # number of LoadLockedReq hits 604system.cpu.dcache.LoadLockedReq_hits::total 99 # number of LoadLockedReq hits 605system.cpu.dcache.StoreCondReq_hits::cpu.data 73 # number of StoreCondReq hits 606system.cpu.dcache.StoreCondReq_hits::total 73 # number of StoreCondReq hits 607system.cpu.dcache.demand_hits::cpu.data 660505345 # number of demand (read+write) hits 608system.cpu.dcache.demand_hits::total 660505345 # number of demand (read+write) hits 609system.cpu.dcache.overall_hits::cpu.data 660505345 # number of overall hits 610system.cpu.dcache.overall_hits::total 660505345 # number of overall hits 611system.cpu.dcache.ReadReq_misses::cpu.data 10054191 # number of ReadReq misses 612system.cpu.dcache.ReadReq_misses::total 10054191 # number of ReadReq misses 613system.cpu.dcache.WriteReq_misses::cpu.data 4514640 # number of WriteReq misses 614system.cpu.dcache.WriteReq_misses::total 4514640 # number of WriteReq misses |
| 457system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 458system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses | 615system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses 616system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses |
| 459system.cpu.dcache.demand_misses::cpu.data 15279890 # number of demand (read+write) misses 460system.cpu.dcache.demand_misses::total 15279890 # number of demand (read+write) misses 461system.cpu.dcache.overall_misses::cpu.data 15279890 # number of overall misses 462system.cpu.dcache.overall_misses::total 15279890 # number of overall misses 463system.cpu.dcache.ReadReq_miss_latency::cpu.data 151975224500 # number of ReadReq miss cycles 464system.cpu.dcache.ReadReq_miss_latency::total 151975224500 # number of ReadReq miss cycles 465system.cpu.dcache.WriteReq_miss_latency::cpu.data 119867822584 # number of WriteReq miss cycles 466system.cpu.dcache.WriteReq_miss_latency::total 119867822584 # number of WriteReq miss cycles 467system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 111500 # number of LoadLockedReq miss cycles 468system.cpu.dcache.LoadLockedReq_miss_latency::total 111500 # number of LoadLockedReq miss cycles 469system.cpu.dcache.demand_miss_latency::cpu.data 271843047084 # number of demand (read+write) miss cycles 470system.cpu.dcache.demand_miss_latency::total 271843047084 # number of demand (read+write) miss cycles 471system.cpu.dcache.overall_miss_latency::cpu.data 271843047084 # number of overall miss cycles 472system.cpu.dcache.overall_miss_latency::total 271843047084 # number of overall miss cycles 473system.cpu.dcache.ReadReq_accesses::cpu.data 502609198 # number of ReadReq accesses(hits+misses) 474system.cpu.dcache.ReadReq_accesses::total 502609198 # number of ReadReq accesses(hits+misses) | 617system.cpu.dcache.demand_misses::cpu.data 14568831 # number of demand (read+write) misses 618system.cpu.dcache.demand_misses::total 14568831 # number of demand (read+write) misses 619system.cpu.dcache.overall_misses::cpu.data 14568831 # number of overall misses 620system.cpu.dcache.overall_misses::total 14568831 # number of overall misses 621system.cpu.dcache.ReadReq_miss_latency::cpu.data 192605585000 # number of ReadReq miss cycles 622system.cpu.dcache.ReadReq_miss_latency::total 192605585000 # number of ReadReq miss cycles 623system.cpu.dcache.WriteReq_miss_latency::cpu.data 133759941491 # number of WriteReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::total 133759941491 # number of WriteReq miss cycles 625system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 146500 # number of LoadLockedReq miss cycles 626system.cpu.dcache.LoadLockedReq_miss_latency::total 146500 # number of LoadLockedReq miss cycles 627system.cpu.dcache.demand_miss_latency::cpu.data 326365526491 # number of demand (read+write) miss cycles 628system.cpu.dcache.demand_miss_latency::total 326365526491 # number of demand (read+write) miss cycles 629system.cpu.dcache.overall_miss_latency::cpu.data 326365526491 # number of overall miss cycles 630system.cpu.dcache.overall_miss_latency::total 326365526491 # number of overall miss cycles 631system.cpu.dcache.ReadReq_accesses::cpu.data 502488129 # number of ReadReq accesses(hits+misses) 632system.cpu.dcache.ReadReq_accesses::total 502488129 # number of ReadReq accesses(hits+misses) |
| 475system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 476system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) | 633system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 634system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) |
| 477system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses) 478system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) 479system.cpu.dcache.StoreCondReq_accesses::cpu.data 65 # number of StoreCondReq accesses(hits+misses) 480system.cpu.dcache.StoreCondReq_accesses::total 65 # number of StoreCondReq accesses(hits+misses) 481system.cpu.dcache.demand_accesses::cpu.data 675195245 # number of demand (read+write) accesses 482system.cpu.dcache.demand_accesses::total 675195245 # number of demand (read+write) accesses 483system.cpu.dcache.overall_accesses::cpu.data 675195245 # number of overall (read+write) accesses 484system.cpu.dcache.overall_accesses::total 675195245 # number of overall (read+write) accesses 485system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020104 # miss rate for ReadReq accesses 486system.cpu.dcache.ReadReq_miss_rate::total 0.020104 # miss rate for ReadReq accesses 487system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029987 # miss rate for WriteReq accesses 488system.cpu.dcache.WriteReq_miss_rate::total 0.029987 # miss rate for WriteReq accesses 489system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses 490system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses 491system.cpu.dcache.demand_miss_rate::cpu.data 0.022630 # miss rate for demand accesses 492system.cpu.dcache.demand_miss_rate::total 0.022630 # miss rate for demand accesses 493system.cpu.dcache.overall_miss_rate::cpu.data 0.022630 # miss rate for overall accesses 494system.cpu.dcache.overall_miss_rate::total 0.022630 # miss rate for overall accesses 495system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15040.361204 # average ReadReq miss latency 496system.cpu.dcache.ReadReq_avg_miss_latency::total 15040.361204 # average ReadReq miss latency 497system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23161.087465 # average WriteReq miss latency 498system.cpu.dcache.WriteReq_avg_miss_latency::total 23161.087465 # average WriteReq miss latency 499system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37166.666667 # average LoadLockedReq miss latency 500system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37166.666667 # average LoadLockedReq miss latency 501system.cpu.dcache.demand_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency 502system.cpu.dcache.demand_avg_miss_latency::total 17790.903409 # average overall miss latency 503system.cpu.dcache.overall_avg_miss_latency::cpu.data 17790.903409 # average overall miss latency 504system.cpu.dcache.overall_avg_miss_latency::total 17790.903409 # average overall miss latency 505system.cpu.dcache.blocked_cycles::no_mshrs 547911 # number of cycles access was blocked 506system.cpu.dcache.blocked_cycles::no_targets 306 # number of cycles access was blocked 507system.cpu.dcache.blocked::no_mshrs 59951 # number of cycles access was blocked 508system.cpu.dcache.blocked::no_targets 9 # number of cycles access was blocked 509system.cpu.dcache.avg_blocked_cycles::no_mshrs 9.139314 # average number of cycles each access was blocked 510system.cpu.dcache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked | 635system.cpu.dcache.LoadLockedReq_accesses::cpu.data 102 # number of LoadLockedReq accesses(hits+misses) 636system.cpu.dcache.LoadLockedReq_accesses::total 102 # number of LoadLockedReq accesses(hits+misses) 637system.cpu.dcache.StoreCondReq_accesses::cpu.data 73 # number of StoreCondReq accesses(hits+misses) 638system.cpu.dcache.StoreCondReq_accesses::total 73 # number of StoreCondReq accesses(hits+misses) 639system.cpu.dcache.demand_accesses::cpu.data 675074176 # number of demand (read+write) accesses 640system.cpu.dcache.demand_accesses::total 675074176 # number of demand (read+write) accesses 641system.cpu.dcache.overall_accesses::cpu.data 675074176 # number of overall (read+write) accesses 642system.cpu.dcache.overall_accesses::total 675074176 # number of overall (read+write) accesses 643system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020009 # miss rate for ReadReq accesses 644system.cpu.dcache.ReadReq_miss_rate::total 0.020009 # miss rate for ReadReq accesses 645system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.026159 # miss rate for WriteReq accesses 646system.cpu.dcache.WriteReq_miss_rate::total 0.026159 # miss rate for WriteReq accesses 647system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.029412 # miss rate for LoadLockedReq accesses 648system.cpu.dcache.LoadLockedReq_miss_rate::total 0.029412 # miss rate for LoadLockedReq accesses 649system.cpu.dcache.demand_miss_rate::cpu.data 0.021581 # miss rate for demand accesses 650system.cpu.dcache.demand_miss_rate::total 0.021581 # miss rate for demand accesses 651system.cpu.dcache.overall_miss_rate::cpu.data 0.021581 # miss rate for overall accesses 652system.cpu.dcache.overall_miss_rate::total 0.021581 # miss rate for overall accesses 653system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19156.746177 # average ReadReq miss latency 654system.cpu.dcache.ReadReq_avg_miss_latency::total 19156.746177 # average ReadReq miss latency 655system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29628.041547 # average WriteReq miss latency 656system.cpu.dcache.WriteReq_avg_miss_latency::total 29628.041547 # average WriteReq miss latency 657system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48833.333333 # average LoadLockedReq miss latency 658system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48833.333333 # average LoadLockedReq miss latency 659system.cpu.dcache.demand_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency 660system.cpu.dcache.demand_avg_miss_latency::total 22401.627591 # average overall miss latency 661system.cpu.dcache.overall_avg_miss_latency::cpu.data 22401.627591 # average overall miss latency 662system.cpu.dcache.overall_avg_miss_latency::total 22401.627591 # average overall miss latency 663system.cpu.dcache.blocked_cycles::no_mshrs 1880438 # number of cycles access was blocked 664system.cpu.dcache.blocked_cycles::no_targets 248831 # number of cycles access was blocked 665system.cpu.dcache.blocked::no_mshrs 88187 # number of cycles access was blocked 666system.cpu.dcache.blocked::no_targets 1969 # number of cycles access was blocked 667system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.323302 # average number of cycles each access was blocked 668system.cpu.dcache.avg_blocked_cycles::no_targets 126.374302 # average number of cycles each access was blocked |
| 511system.cpu.dcache.fast_writes 0 # number of fast writes performed 512system.cpu.dcache.cache_copies 0 # number of cache copies performed | 669system.cpu.dcache.fast_writes 0 # number of fast writes performed 670system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 513system.cpu.dcache.writebacks::writebacks 3473179 # number of writebacks 514system.cpu.dcache.writebacks::total 3473179 # number of writebacks 515system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2378385 # number of ReadReq MSHR hits 516system.cpu.dcache.ReadReq_mshr_hits::total 2378385 # number of ReadReq MSHR hits 517system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3281264 # number of WriteReq MSHR hits 518system.cpu.dcache.WriteReq_mshr_hits::total 3281264 # number of WriteReq MSHR hits | 671system.cpu.dcache.writebacks::writebacks 3473899 # number of writebacks 672system.cpu.dcache.writebacks::total 3473899 # number of writebacks 673system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2327206 # number of ReadReq MSHR hits 674system.cpu.dcache.ReadReq_mshr_hits::total 2327206 # number of ReadReq MSHR hits 675system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2620625 # number of WriteReq MSHR hits 676system.cpu.dcache.WriteReq_mshr_hits::total 2620625 # number of WriteReq MSHR hits |
| 519system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 520system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits | 677system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits 678system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits |
| 521system.cpu.dcache.demand_mshr_hits::cpu.data 5659649 # number of demand (read+write) MSHR hits 522system.cpu.dcache.demand_mshr_hits::total 5659649 # number of demand (read+write) MSHR hits 523system.cpu.dcache.overall_mshr_hits::cpu.data 5659649 # number of overall MSHR hits 524system.cpu.dcache.overall_mshr_hits::total 5659649 # number of overall MSHR hits 525system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726108 # number of ReadReq MSHR misses 526system.cpu.dcache.ReadReq_mshr_misses::total 7726108 # number of ReadReq MSHR misses 527system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894133 # number of WriteReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::total 1894133 # number of WriteReq MSHR misses 529system.cpu.dcache.demand_mshr_misses::cpu.data 9620241 # number of demand (read+write) MSHR misses 530system.cpu.dcache.demand_mshr_misses::total 9620241 # number of demand (read+write) MSHR misses 531system.cpu.dcache.overall_mshr_misses::cpu.data 9620241 # number of overall MSHR misses 532system.cpu.dcache.overall_mshr_misses::total 9620241 # number of overall MSHR misses 533system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 75134366500 # number of ReadReq MSHR miss cycles 534system.cpu.dcache.ReadReq_mshr_miss_latency::total 75134366500 # number of ReadReq MSHR miss cycles 535system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 39443717607 # number of WriteReq MSHR miss cycles 536system.cpu.dcache.WriteReq_mshr_miss_latency::total 39443717607 # number of WriteReq MSHR miss cycles 537system.cpu.dcache.demand_mshr_miss_latency::cpu.data 114578084107 # number of demand (read+write) MSHR miss cycles 538system.cpu.dcache.demand_mshr_miss_latency::total 114578084107 # number of demand (read+write) MSHR miss cycles 539system.cpu.dcache.overall_mshr_miss_latency::cpu.data 114578084107 # number of overall MSHR miss cycles 540system.cpu.dcache.overall_mshr_miss_latency::total 114578084107 # number of overall MSHR miss cycles 541system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015372 # mshr miss rate for ReadReq accesses 542system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015372 # mshr miss rate for ReadReq accesses 543system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses 544system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses 545system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for demand accesses 546system.cpu.dcache.demand_mshr_miss_rate::total 0.014248 # mshr miss rate for demand accesses 547system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014248 # mshr miss rate for overall accesses 548system.cpu.dcache.overall_mshr_miss_rate::total 0.014248 # mshr miss rate for overall accesses 549system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 9724.736763 # average ReadReq mshr miss latency 550system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 9724.736763 # average ReadReq mshr miss latency 551system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20824.154168 # average WriteReq mshr miss latency 552system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 20824.154168 # average WriteReq mshr miss latency 553system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency 554system.cpu.dcache.demand_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency 555system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11910.105382 # average overall mshr miss latency 556system.cpu.dcache.overall_avg_mshr_miss_latency::total 11910.105382 # average overall mshr miss latency | 679system.cpu.dcache.demand_mshr_hits::cpu.data 4947831 # number of demand (read+write) MSHR hits 680system.cpu.dcache.demand_mshr_hits::total 4947831 # number of demand (read+write) MSHR hits 681system.cpu.dcache.overall_mshr_hits::cpu.data 4947831 # number of overall MSHR hits 682system.cpu.dcache.overall_mshr_hits::total 4947831 # number of overall MSHR hits 683system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7726985 # number of ReadReq MSHR misses 684system.cpu.dcache.ReadReq_mshr_misses::total 7726985 # number of ReadReq MSHR misses 685system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894015 # number of WriteReq MSHR misses 686system.cpu.dcache.WriteReq_mshr_misses::total 1894015 # number of WriteReq MSHR misses 687system.cpu.dcache.demand_mshr_misses::cpu.data 9621000 # number of demand (read+write) MSHR misses 688system.cpu.dcache.demand_mshr_misses::total 9621000 # number of demand (read+write) MSHR misses 689system.cpu.dcache.overall_mshr_misses::cpu.data 9621000 # number of overall MSHR misses 690system.cpu.dcache.overall_mshr_misses::total 9621000 # number of overall MSHR misses 691system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 100672222000 # number of ReadReq MSHR miss cycles 692system.cpu.dcache.ReadReq_mshr_miss_latency::total 100672222000 # number of ReadReq MSHR miss cycles 693system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 58875647012 # number of WriteReq MSHR miss cycles 694system.cpu.dcache.WriteReq_mshr_miss_latency::total 58875647012 # number of WriteReq MSHR miss cycles 695system.cpu.dcache.demand_mshr_miss_latency::cpu.data 159547869012 # number of demand (read+write) MSHR miss cycles 696system.cpu.dcache.demand_mshr_miss_latency::total 159547869012 # number of demand (read+write) MSHR miss cycles 697system.cpu.dcache.overall_mshr_miss_latency::cpu.data 159547869012 # number of overall MSHR miss cycles 698system.cpu.dcache.overall_mshr_miss_latency::total 159547869012 # number of overall MSHR miss cycles 699system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015377 # mshr miss rate for ReadReq accesses 700system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015377 # mshr miss rate for ReadReq accesses 701system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses 702system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses 703system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014252 # mshr miss rate for demand accesses 704system.cpu.dcache.demand_mshr_miss_rate::total 0.014252 # mshr miss rate for demand accesses 705system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014252 # mshr miss rate for overall accesses 706system.cpu.dcache.overall_mshr_miss_rate::total 0.014252 # mshr miss rate for overall accesses 707system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13028.655032 # average ReadReq mshr miss latency 708system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13028.655032 # average ReadReq mshr miss latency 709system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31085.100705 # average WriteReq mshr miss latency 710system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31085.100705 # average WriteReq mshr miss latency 711system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency 712system.cpu.dcache.demand_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency 713system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16583.293734 # average overall mshr miss latency 714system.cpu.dcache.overall_avg_mshr_miss_latency::total 16583.293734 # average overall mshr miss latency |
| 557system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 715system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 558system.cpu.l2cache.replacements 2426778 # number of replacements 559system.cpu.l2cache.tagsinuse 31133.069432 # Cycle average of tags in use 560system.cpu.l2cache.total_refs 8743063 # Total number of references to valid blocks. 561system.cpu.l2cache.sampled_refs 2456493 # Sample count of references to valid blocks. 562system.cpu.l2cache.avg_refs 3.559165 # Average number of references to valid blocks. 563system.cpu.l2cache.warmup_cycle 77443387000 # Cycle when the warmup percentage was hit. 564system.cpu.l2cache.occ_blocks::writebacks 14066.378954 # Average occupied blocks per requestor 565system.cpu.l2cache.occ_blocks::cpu.inst 15.908545 # Average occupied blocks per requestor 566system.cpu.l2cache.occ_blocks::cpu.data 17050.781934 # Average occupied blocks per requestor 567system.cpu.l2cache.occ_percent::writebacks 0.429272 # Average percentage of cache occupancy 568system.cpu.l2cache.occ_percent::cpu.inst 0.000485 # Average percentage of cache occupancy 569system.cpu.l2cache.occ_percent::cpu.data 0.520349 # Average percentage of cache occupancy 570system.cpu.l2cache.occ_percent::total 0.950106 # Average percentage of cache occupancy 571system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits 572system.cpu.l2cache.ReadReq_hits::cpu.data 6115252 # number of ReadReq hits 573system.cpu.l2cache.ReadReq_hits::total 6115280 # number of ReadReq hits 574system.cpu.l2cache.Writeback_hits::writebacks 3473179 # number of Writeback hits 575system.cpu.l2cache.Writeback_hits::total 3473179 # number of Writeback hits 576system.cpu.l2cache.ReadExReq_hits::cpu.data 1063326 # number of ReadExReq hits 577system.cpu.l2cache.ReadExReq_hits::total 1063326 # number of ReadExReq hits 578system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits 579system.cpu.l2cache.demand_hits::cpu.data 7178578 # number of demand (read+write) hits 580system.cpu.l2cache.demand_hits::total 7178606 # number of demand (read+write) hits 581system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits 582system.cpu.l2cache.overall_hits::cpu.data 7178578 # number of overall hits 583system.cpu.l2cache.overall_hits::total 7178606 # number of overall hits | 716system.cpu.l2cache.replacements 2427272 # number of replacements 717system.cpu.l2cache.tagsinuse 31171.716737 # Cycle average of tags in use 718system.cpu.l2cache.total_refs 8744168 # Total number of references to valid blocks. 719system.cpu.l2cache.sampled_refs 2456984 # Sample count of references to valid blocks. 720system.cpu.l2cache.avg_refs 3.558903 # Average number of references to valid blocks. 721system.cpu.l2cache.warmup_cycle 80002919000 # Cycle when the warmup percentage was hit. 722system.cpu.l2cache.occ_blocks::writebacks 14002.042506 # Average occupied blocks per requestor 723system.cpu.l2cache.occ_blocks::cpu.inst 15.065518 # Average occupied blocks per requestor 724system.cpu.l2cache.occ_blocks::cpu.data 17154.608713 # Average occupied blocks per requestor 725system.cpu.l2cache.occ_percent::writebacks 0.427308 # Average percentage of cache occupancy 726system.cpu.l2cache.occ_percent::cpu.inst 0.000460 # Average percentage of cache occupancy 727system.cpu.l2cache.occ_percent::cpu.data 0.523517 # Average percentage of cache occupancy 728system.cpu.l2cache.occ_percent::total 0.951285 # Average percentage of cache occupancy 729system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits 730system.cpu.l2cache.ReadReq_hits::cpu.data 6115863 # number of ReadReq hits 731system.cpu.l2cache.ReadReq_hits::total 6115892 # number of ReadReq hits 732system.cpu.l2cache.Writeback_hits::writebacks 3473899 # number of Writeback hits 733system.cpu.l2cache.Writeback_hits::total 3473899 # number of Writeback hits 734system.cpu.l2cache.ReadExReq_hits::cpu.data 1062992 # number of ReadExReq hits 735system.cpu.l2cache.ReadExReq_hits::total 1062992 # number of ReadExReq hits 736system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits 737system.cpu.l2cache.demand_hits::cpu.data 7178855 # number of demand (read+write) hits 738system.cpu.l2cache.demand_hits::total 7178884 # number of demand (read+write) hits 739system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits 740system.cpu.l2cache.overall_hits::cpu.data 7178855 # number of overall hits 741system.cpu.l2cache.overall_hits::total 7178884 # number of overall hits |
| 584system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses | 742system.cpu.l2cache.ReadReq_misses::cpu.inst 757 # number of ReadReq misses |
| 585system.cpu.l2cache.ReadReq_misses::cpu.data 1610856 # number of ReadReq misses 586system.cpu.l2cache.ReadReq_misses::total 1611613 # number of ReadReq misses 587system.cpu.l2cache.ReadExReq_misses::cpu.data 830807 # number of ReadExReq misses 588system.cpu.l2cache.ReadExReq_misses::total 830807 # number of ReadExReq misses | 743system.cpu.l2cache.ReadReq_misses::cpu.data 1611122 # number of ReadReq misses 744system.cpu.l2cache.ReadReq_misses::total 1611879 # number of ReadReq misses 745system.cpu.l2cache.ReadExReq_misses::cpu.data 831023 # number of ReadExReq misses 746system.cpu.l2cache.ReadExReq_misses::total 831023 # number of ReadExReq misses |
| 589system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses | 747system.cpu.l2cache.demand_misses::cpu.inst 757 # number of demand (read+write) misses |
| 590system.cpu.l2cache.demand_misses::cpu.data 2441663 # number of demand (read+write) misses 591system.cpu.l2cache.demand_misses::total 2442420 # number of demand (read+write) misses | 748system.cpu.l2cache.demand_misses::cpu.data 2442145 # number of demand (read+write) misses 749system.cpu.l2cache.demand_misses::total 2442902 # number of demand (read+write) misses |
| 592system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses | 750system.cpu.l2cache.overall_misses::cpu.inst 757 # number of overall misses |
| 593system.cpu.l2cache.overall_misses::cpu.data 2441663 # number of overall misses 594system.cpu.l2cache.overall_misses::total 2442420 # number of overall misses 595system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27670500 # number of ReadReq miss cycles 596system.cpu.l2cache.ReadReq_miss_latency::cpu.data 59328864000 # number of ReadReq miss cycles 597system.cpu.l2cache.ReadReq_miss_latency::total 59356534500 # number of ReadReq miss cycles 598system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 35694611500 # number of ReadExReq miss cycles 599system.cpu.l2cache.ReadExReq_miss_latency::total 35694611500 # number of ReadExReq miss cycles 600system.cpu.l2cache.demand_miss_latency::cpu.inst 27670500 # number of demand (read+write) miss cycles 601system.cpu.l2cache.demand_miss_latency::cpu.data 95023475500 # number of demand (read+write) miss cycles 602system.cpu.l2cache.demand_miss_latency::total 95051146000 # number of demand (read+write) miss cycles 603system.cpu.l2cache.overall_miss_latency::cpu.inst 27670500 # number of overall miss cycles 604system.cpu.l2cache.overall_miss_latency::cpu.data 95023475500 # number of overall miss cycles 605system.cpu.l2cache.overall_miss_latency::total 95051146000 # number of overall miss cycles 606system.cpu.l2cache.ReadReq_accesses::cpu.inst 785 # number of ReadReq accesses(hits+misses) 607system.cpu.l2cache.ReadReq_accesses::cpu.data 7726108 # number of ReadReq accesses(hits+misses) 608system.cpu.l2cache.ReadReq_accesses::total 7726893 # number of ReadReq accesses(hits+misses) 609system.cpu.l2cache.Writeback_accesses::writebacks 3473179 # number of Writeback accesses(hits+misses) 610system.cpu.l2cache.Writeback_accesses::total 3473179 # number of Writeback accesses(hits+misses) 611system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894133 # number of ReadExReq accesses(hits+misses) 612system.cpu.l2cache.ReadExReq_accesses::total 1894133 # number of ReadExReq accesses(hits+misses) 613system.cpu.l2cache.demand_accesses::cpu.inst 785 # number of demand (read+write) accesses 614system.cpu.l2cache.demand_accesses::cpu.data 9620241 # number of demand (read+write) accesses 615system.cpu.l2cache.demand_accesses::total 9621026 # number of demand (read+write) accesses 616system.cpu.l2cache.overall_accesses::cpu.inst 785 # number of overall (read+write) accesses 617system.cpu.l2cache.overall_accesses::cpu.data 9620241 # number of overall (read+write) accesses 618system.cpu.l2cache.overall_accesses::total 9621026 # number of overall (read+write) accesses 619system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964331 # miss rate for ReadReq accesses 620system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208495 # miss rate for ReadReq accesses 621system.cpu.l2cache.ReadReq_miss_rate::total 0.208572 # miss rate for ReadReq accesses 622system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438621 # miss rate for ReadExReq accesses 623system.cpu.l2cache.ReadExReq_miss_rate::total 0.438621 # miss rate for ReadExReq accesses 624system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964331 # miss rate for demand accesses 625system.cpu.l2cache.demand_miss_rate::cpu.data 0.253805 # miss rate for demand accesses 626system.cpu.l2cache.demand_miss_rate::total 0.253863 # miss rate for demand accesses 627system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964331 # miss rate for overall accesses 628system.cpu.l2cache.overall_miss_rate::cpu.data 0.253805 # miss rate for overall accesses 629system.cpu.l2cache.overall_miss_rate::total 0.253863 # miss rate for overall accesses 630system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36552.840159 # average ReadReq miss latency 631system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 36830.644080 # average ReadReq miss latency 632system.cpu.l2cache.ReadReq_avg_miss_latency::total 36830.513591 # average ReadReq miss latency 633system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42963.782804 # average ReadExReq miss latency 634system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42963.782804 # average ReadExReq miss latency 635system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency 636system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency 637system.cpu.l2cache.demand_avg_miss_latency::total 38916.789905 # average overall miss latency 638system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36552.840159 # average overall miss latency 639system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38917.522811 # average overall miss latency 640system.cpu.l2cache.overall_avg_miss_latency::total 38916.789905 # average overall miss latency 641system.cpu.l2cache.blocked_cycles::no_mshrs 229442 # number of cycles access was blocked | 751system.cpu.l2cache.overall_misses::cpu.data 2442145 # number of overall misses 752system.cpu.l2cache.overall_misses::total 2442902 # number of overall misses 753system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27934500 # number of ReadReq miss cycles 754system.cpu.l2cache.ReadReq_miss_latency::cpu.data 84953945000 # number of ReadReq miss cycles 755system.cpu.l2cache.ReadReq_miss_latency::total 84981879500 # number of ReadReq miss cycles 756system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 55209394500 # number of ReadExReq miss cycles 757system.cpu.l2cache.ReadExReq_miss_latency::total 55209394500 # number of ReadExReq miss cycles 758system.cpu.l2cache.demand_miss_latency::cpu.inst 27934500 # number of demand (read+write) miss cycles 759system.cpu.l2cache.demand_miss_latency::cpu.data 140163339500 # number of demand (read+write) miss cycles 760system.cpu.l2cache.demand_miss_latency::total 140191274000 # number of demand (read+write) miss cycles 761system.cpu.l2cache.overall_miss_latency::cpu.inst 27934500 # number of overall miss cycles 762system.cpu.l2cache.overall_miss_latency::cpu.data 140163339500 # number of overall miss cycles 763system.cpu.l2cache.overall_miss_latency::total 140191274000 # number of overall miss cycles 764system.cpu.l2cache.ReadReq_accesses::cpu.inst 786 # number of ReadReq accesses(hits+misses) 765system.cpu.l2cache.ReadReq_accesses::cpu.data 7726985 # number of ReadReq accesses(hits+misses) 766system.cpu.l2cache.ReadReq_accesses::total 7727771 # number of ReadReq accesses(hits+misses) 767system.cpu.l2cache.Writeback_accesses::writebacks 3473899 # number of Writeback accesses(hits+misses) 768system.cpu.l2cache.Writeback_accesses::total 3473899 # number of Writeback accesses(hits+misses) 769system.cpu.l2cache.ReadExReq_accesses::cpu.data 1894015 # number of ReadExReq accesses(hits+misses) 770system.cpu.l2cache.ReadExReq_accesses::total 1894015 # number of ReadExReq accesses(hits+misses) 771system.cpu.l2cache.demand_accesses::cpu.inst 786 # number of demand (read+write) accesses 772system.cpu.l2cache.demand_accesses::cpu.data 9621000 # number of demand (read+write) accesses 773system.cpu.l2cache.demand_accesses::total 9621786 # number of demand (read+write) accesses 774system.cpu.l2cache.overall_accesses::cpu.inst 786 # number of overall (read+write) accesses 775system.cpu.l2cache.overall_accesses::cpu.data 9621000 # number of overall (read+write) accesses 776system.cpu.l2cache.overall_accesses::total 9621786 # number of overall (read+write) accesses 777system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963104 # miss rate for ReadReq accesses 778system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.208506 # miss rate for ReadReq accesses 779system.cpu.l2cache.ReadReq_miss_rate::total 0.208583 # miss rate for ReadReq accesses 780system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.438763 # miss rate for ReadExReq accesses 781system.cpu.l2cache.ReadExReq_miss_rate::total 0.438763 # miss rate for ReadExReq accesses 782system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963104 # miss rate for demand accesses 783system.cpu.l2cache.demand_miss_rate::cpu.data 0.253835 # miss rate for demand accesses 784system.cpu.l2cache.demand_miss_rate::total 0.253893 # miss rate for demand accesses 785system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963104 # miss rate for overall accesses 786system.cpu.l2cache.overall_miss_rate::cpu.data 0.253835 # miss rate for overall accesses 787system.cpu.l2cache.overall_miss_rate::total 0.253893 # miss rate for overall accesses 788system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 36901.585205 # average ReadReq miss latency 789system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52729.678448 # average ReadReq miss latency 790system.cpu.l2cache.ReadReq_avg_miss_latency::total 52722.244970 # average ReadReq miss latency 791system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 66435.459067 # average ReadExReq miss latency 792system.cpu.l2cache.ReadExReq_avg_miss_latency::total 66435.459067 # average ReadExReq miss latency 793system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 36901.585205 # average overall miss latency 794system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57393.537034 # average overall miss latency 795system.cpu.l2cache.demand_avg_miss_latency::total 57387.187042 # average overall miss latency 796system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 36901.585205 # average overall miss latency 797system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57393.537034 # average overall miss latency 798system.cpu.l2cache.overall_avg_miss_latency::total 57387.187042 # average overall miss latency 799system.cpu.l2cache.blocked_cycles::no_mshrs 1390172 # number of cycles access was blocked |
| 642system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 800system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 643system.cpu.l2cache.blocked::no_mshrs 20875 # number of cycles access was blocked | 801system.cpu.l2cache.blocked::no_mshrs 31316 # number of cycles access was blocked |
| 644system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 802system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 645system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10.991234 # average number of cycles each access was blocked | 803system.cpu.l2cache.avg_blocked_cycles::no_mshrs 44.391749 # average number of cycles each access was blocked |
| 646system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 647system.cpu.l2cache.fast_writes 0 # number of fast writes performed 648system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 804system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 805system.cpu.l2cache.fast_writes 0 # number of fast writes performed 806system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 649system.cpu.l2cache.writebacks::writebacks 1123907 # number of writebacks 650system.cpu.l2cache.writebacks::total 1123907 # number of writebacks 651system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits 652system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits | 807system.cpu.l2cache.writebacks::writebacks 1123933 # number of writebacks 808system.cpu.l2cache.writebacks::total 1123933 # number of writebacks 809system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 810system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits |
| 653system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits | 811system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits |
| 654system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits 655system.cpu.l2cache.demand_mshr_hits::cpu.data 7 # number of demand (read+write) MSHR hits | 812system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 813system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits |
| 656system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits | 814system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits |
| 657system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits 658system.cpu.l2cache.overall_mshr_hits::cpu.data 7 # number of overall MSHR hits | 815system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 816system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits |
| 659system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits | 817system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits |
| 660system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 754 # number of ReadReq MSHR misses 661system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1610849 # number of ReadReq MSHR misses 662system.cpu.l2cache.ReadReq_mshr_misses::total 1611603 # number of ReadReq MSHR misses 663system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 830807 # number of ReadExReq MSHR misses 664system.cpu.l2cache.ReadExReq_mshr_misses::total 830807 # number of ReadExReq MSHR misses 665system.cpu.l2cache.demand_mshr_misses::cpu.inst 754 # number of demand (read+write) MSHR misses 666system.cpu.l2cache.demand_mshr_misses::cpu.data 2441656 # number of demand (read+write) MSHR misses 667system.cpu.l2cache.demand_mshr_misses::total 2442410 # number of demand (read+write) MSHR misses 668system.cpu.l2cache.overall_mshr_misses::cpu.inst 754 # number of overall MSHR misses 669system.cpu.l2cache.overall_mshr_misses::cpu.data 2441656 # number of overall MSHR misses 670system.cpu.l2cache.overall_mshr_misses::total 2442410 # number of overall MSHR misses 671system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25220000 # number of ReadReq MSHR miss cycles 672system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54195045500 # number of ReadReq MSHR miss cycles 673system.cpu.l2cache.ReadReq_mshr_miss_latency::total 54220265500 # number of ReadReq MSHR miss cycles 674system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33065264000 # number of ReadExReq MSHR miss cycles 675system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33065264000 # number of ReadExReq MSHR miss cycles 676system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25220000 # number of demand (read+write) MSHR miss cycles 677system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 87260309500 # number of demand (read+write) MSHR miss cycles 678system.cpu.l2cache.demand_mshr_miss_latency::total 87285529500 # number of demand (read+write) MSHR miss cycles 679system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25220000 # number of overall MSHR miss cycles 680system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 87260309500 # number of overall MSHR miss cycles 681system.cpu.l2cache.overall_mshr_miss_latency::total 87285529500 # number of overall MSHR miss cycles 682system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for ReadReq accesses 683system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208494 # mshr miss rate for ReadReq accesses 684system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208571 # mshr miss rate for ReadReq accesses 685system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438621 # mshr miss rate for ReadExReq accesses 686system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438621 # mshr miss rate for ReadExReq accesses 687system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for demand accesses 688system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for demand accesses 689system.cpu.l2cache.demand_mshr_miss_rate::total 0.253862 # mshr miss rate for demand accesses 690system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960510 # mshr miss rate for overall accesses 691system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253804 # mshr miss rate for overall accesses 692system.cpu.l2cache.overall_mshr_miss_rate::total 0.253862 # mshr miss rate for overall accesses 693system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33448.275862 # average ReadReq mshr miss latency 694system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 33643.777598 # average ReadReq mshr miss latency 695system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 33643.686131 # average ReadReq mshr miss latency 696system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39798.971362 # average ReadExReq mshr miss latency 697system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39798.971362 # average ReadExReq mshr miss latency 698system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency 699system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency 700system.cpu.l2cache.demand_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency 701system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33448.275862 # average overall mshr miss latency 702system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35738.166843 # average overall mshr miss latency 703system.cpu.l2cache.overall_avg_mshr_miss_latency::total 35737.459927 # average overall mshr miss latency | 818system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 756 # number of ReadReq MSHR misses 819system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1611113 # number of ReadReq MSHR misses 820system.cpu.l2cache.ReadReq_mshr_misses::total 1611869 # number of ReadReq MSHR misses 821system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 831023 # number of ReadExReq MSHR misses 822system.cpu.l2cache.ReadExReq_mshr_misses::total 831023 # number of ReadExReq MSHR misses 823system.cpu.l2cache.demand_mshr_misses::cpu.inst 756 # number of demand (read+write) MSHR misses 824system.cpu.l2cache.demand_mshr_misses::cpu.data 2442136 # number of demand (read+write) MSHR misses 825system.cpu.l2cache.demand_mshr_misses::total 2442892 # number of demand (read+write) MSHR misses 826system.cpu.l2cache.overall_mshr_misses::cpu.inst 756 # number of overall MSHR misses 827system.cpu.l2cache.overall_mshr_misses::cpu.data 2442136 # number of overall MSHR misses 828system.cpu.l2cache.overall_mshr_misses::total 2442892 # number of overall MSHR misses 829system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 25190143 # number of ReadReq MSHR miss cycles 830system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 79130491462 # number of ReadReq MSHR miss cycles 831system.cpu.l2cache.ReadReq_mshr_miss_latency::total 79155681605 # number of ReadReq MSHR miss cycles 832system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 52276530586 # number of ReadExReq MSHR miss cycles 833system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 52276530586 # number of ReadExReq MSHR miss cycles 834system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 25190143 # number of demand (read+write) MSHR miss cycles 835system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 131407022048 # number of demand (read+write) MSHR miss cycles 836system.cpu.l2cache.demand_mshr_miss_latency::total 131432212191 # number of demand (read+write) MSHR miss cycles 837system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 25190143 # number of overall MSHR miss cycles 838system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 131407022048 # number of overall MSHR miss cycles 839system.cpu.l2cache.overall_mshr_miss_latency::total 131432212191 # number of overall MSHR miss cycles 840system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for ReadReq accesses 841system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.208505 # mshr miss rate for ReadReq accesses 842system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.208581 # mshr miss rate for ReadReq accesses 843system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.438763 # mshr miss rate for ReadExReq accesses 844system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.438763 # mshr miss rate for ReadExReq accesses 845system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for demand accesses 846system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for demand accesses 847system.cpu.l2cache.demand_mshr_miss_rate::total 0.253892 # mshr miss rate for demand accesses 848system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961832 # mshr miss rate for overall accesses 849system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.253834 # mshr miss rate for overall accesses 850system.cpu.l2cache.overall_mshr_miss_rate::total 0.253892 # mshr miss rate for overall accesses 851system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 33320.294974 # average ReadReq mshr miss latency 852system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 49115.419876 # average ReadReq mshr miss latency 853system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49108.011634 # average ReadReq mshr miss latency 854system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62906.237957 # average ReadExReq mshr miss latency 855system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62906.237957 # average ReadExReq mshr miss latency 856system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency 857system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency 858system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency 859system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 33320.294974 # average overall mshr miss latency 860system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 53808.232649 # average overall mshr miss latency 861system.cpu.l2cache.overall_avg_mshr_miss_latency::total 53801.892262 # average overall mshr miss latency |
| 704system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 705 706---------- End Simulation Statistics ---------- | 862system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 863 864---------- End Simulation Statistics ---------- |