| stats.txt (8983:8800b05e1cb3) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.463994 # Number of seconds simulated 4sim_ticks 463993693500 # Number of ticks simulated 5final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.463994 # Number of seconds simulated 4sim_ticks 463993693500 # Number of ticks simulated 5final_tick 463993693500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 113228 # Simulator instruction rate (inst/s) 8host_op_rate 126315 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 34014323 # Simulator tick rate (ticks/s) 10host_mem_usage 231672 # Number of bytes of host memory used 11host_seconds 13641.13 # Real time elapsed on the host | 7host_inst_rate 128371 # Simulator instruction rate (inst/s) 8host_op_rate 143208 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 38563333 # Simulator tick rate (ticks/s) 10host_mem_usage 232076 # Number of bytes of host memory used 11host_seconds 12031.99 # Real time elapsed on the host |
| 12sim_insts 1544563066 # Number of instructions simulated 13sim_ops 1723073879 # Number of ops (including micro ops) simulated | 12sim_insts 1544563066 # Number of instructions simulated 13sim_ops 1723073879 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 189795648 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 49344 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 78222144 # Number of bytes written to this memory 17system.physmem.num_reads 2965557 # Number of read requests responded to by this memory 18system.physmem.num_writes 1222221 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 409047904 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 106346 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_write 168584498 # Write bandwidth from this memory (bytes/s) 23system.physmem.bw_total 577632403 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 49344 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 189746304 # Number of bytes read from this memory 16system.physmem.bytes_read::total 189795648 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 49344 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 49344 # Number of instructions bytes read from this memory 19system.physmem.bytes_written::writebacks 78222144 # Number of bytes written to this memory 20system.physmem.bytes_written::total 78222144 # Number of bytes written to this memory 21system.physmem.num_reads::cpu.inst 771 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 2964786 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2965557 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1222221 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1222221 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 106346 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 408941558 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::total 409047904 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::cpu.inst 106346 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::total 106346 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_write::writebacks 168584498 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_write::total 168584498 # Write bandwidth from this memory (bytes/s) 33system.physmem.bw_total::writebacks 168584498 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.inst 106346 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.data 408941558 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 577632403 # Total bandwidth to/from this memory (bytes/s) |
| 24system.cpu.dtb.inst_hits 0 # ITB inst hits 25system.cpu.dtb.inst_misses 0 # ITB inst misses 26system.cpu.dtb.read_hits 0 # DTB read hits 27system.cpu.dtb.read_misses 0 # DTB read misses 28system.cpu.dtb.write_hits 0 # DTB write hits 29system.cpu.dtb.write_misses 0 # DTB write misses 30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 332 unchanged lines hidden (view full) --- 364system.cpu.icache.overall_miss_latency::total 39840000 # number of overall miss cycles 365system.cpu.icache.ReadReq_accesses::cpu.inst 283730265 # number of ReadReq accesses(hits+misses) 366system.cpu.icache.ReadReq_accesses::total 283730265 # number of ReadReq accesses(hits+misses) 367system.cpu.icache.demand_accesses::cpu.inst 283730265 # number of demand (read+write) accesses 368system.cpu.icache.demand_accesses::total 283730265 # number of demand (read+write) accesses 369system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses 370system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses 371system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses | 37system.cpu.dtb.inst_hits 0 # ITB inst hits 38system.cpu.dtb.inst_misses 0 # ITB inst misses 39system.cpu.dtb.read_hits 0 # DTB read hits 40system.cpu.dtb.read_misses 0 # DTB read misses 41system.cpu.dtb.write_hits 0 # DTB write hits 42system.cpu.dtb.write_misses 0 # DTB write misses 43system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 44system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 332 unchanged lines hidden (view full) --- 377system.cpu.icache.overall_miss_latency::total 39840000 # number of overall miss cycles 378system.cpu.icache.ReadReq_accesses::cpu.inst 283730265 # number of ReadReq accesses(hits+misses) 379system.cpu.icache.ReadReq_accesses::total 283730265 # number of ReadReq accesses(hits+misses) 380system.cpu.icache.demand_accesses::cpu.inst 283730265 # number of demand (read+write) accesses 381system.cpu.icache.demand_accesses::total 283730265 # number of demand (read+write) accesses 382system.cpu.icache.overall_accesses::cpu.inst 283730265 # number of overall (read+write) accesses 383system.cpu.icache.overall_accesses::total 283730265 # number of overall (read+write) accesses 384system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses |
| 385system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses |
|
| 372system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses | 386system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses |
| 387system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses |
|
| 373system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses | 388system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses |
| 389system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses |
|
| 374system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency | 390system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33283.208020 # average ReadReq miss latency |
| 391system.cpu.icache.ReadReq_avg_miss_latency::total 33283.208020 # average ReadReq miss latency |
|
| 375system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency | 392system.cpu.icache.demand_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency |
| 393system.cpu.icache.demand_avg_miss_latency::total 33283.208020 # average overall miss latency |
|
| 376system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency | 394system.cpu.icache.overall_avg_miss_latency::cpu.inst 33283.208020 # average overall miss latency |
| 395system.cpu.icache.overall_avg_miss_latency::total 33283.208020 # average overall miss latency |
|
| 377system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 378system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 379system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 380system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 381system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 382system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 383system.cpu.icache.fast_writes 0 # number of fast writes performed 384system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 396system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses 397system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27579500 # number of ReadReq MSHR miss cycles 398system.cpu.icache.ReadReq_mshr_miss_latency::total 27579500 # number of ReadReq MSHR miss cycles 399system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27579500 # number of demand (read+write) MSHR miss cycles 400system.cpu.icache.demand_mshr_miss_latency::total 27579500 # number of demand (read+write) MSHR miss cycles 401system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27579500 # number of overall MSHR miss cycles 402system.cpu.icache.overall_mshr_miss_latency::total 27579500 # number of overall MSHR miss cycles 403system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses | 396system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 397system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 398system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 399system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 400system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 401system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 402system.cpu.icache.fast_writes 0 # number of fast writes performed 403system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 415system.cpu.icache.overall_mshr_misses::total 801 # number of overall MSHR misses 416system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27579500 # number of ReadReq MSHR miss cycles 417system.cpu.icache.ReadReq_mshr_miss_latency::total 27579500 # number of ReadReq MSHR miss cycles 418system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27579500 # number of demand (read+write) MSHR miss cycles 419system.cpu.icache.demand_mshr_miss_latency::total 27579500 # number of demand (read+write) MSHR miss cycles 420system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27579500 # number of overall MSHR miss cycles 421system.cpu.icache.overall_mshr_miss_latency::total 27579500 # number of overall MSHR miss cycles 422system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for ReadReq accesses |
| 423system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000003 # mshr miss rate for ReadReq accesses |
|
| 404system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses | 424system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for demand accesses |
| 425system.cpu.icache.demand_mshr_miss_rate::total 0.000003 # mshr miss rate for demand accesses |
|
| 405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses | 426system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000003 # mshr miss rate for overall accesses |
| 427system.cpu.icache.overall_mshr_miss_rate::total 0.000003 # mshr miss rate for overall accesses |
|
| 406system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency | 428system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34431.335830 # average ReadReq mshr miss latency |
| 429system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34431.335830 # average ReadReq mshr miss latency |
|
| 407system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency | 430system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency |
| 431system.cpu.icache.demand_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency |
|
| 408system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency | 432system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34431.335830 # average overall mshr miss latency |
| 433system.cpu.icache.overall_avg_mshr_miss_latency::total 34431.335830 # average overall mshr miss latency |
|
| 409system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 410system.cpu.dcache.replacements 9619302 # number of replacements 411system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use 412system.cpu.dcache.total_refs 660726669 # Total number of references to valid blocks. 413system.cpu.dcache.sampled_refs 9623398 # Sample count of references to valid blocks. 414system.cpu.dcache.avg_refs 68.658354 # Average number of references to valid blocks. 415system.cpu.dcache.warmup_cycle 3346373000 # Cycle when the warmup percentage was hit. 416system.cpu.dcache.occ_blocks::cpu.data 4087.756066 # Average occupied blocks per requestor --- 39 unchanged lines hidden (view full) --- 456system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) 457system.cpu.dcache.StoreCondReq_accesses::cpu.data 68 # number of StoreCondReq accesses(hits+misses) 458system.cpu.dcache.StoreCondReq_accesses::total 68 # number of StoreCondReq accesses(hits+misses) 459system.cpu.dcache.demand_accesses::cpu.data 676628084 # number of demand (read+write) accesses 460system.cpu.dcache.demand_accesses::total 676628084 # number of demand (read+write) accesses 461system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses 462system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses 463system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses | 434system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 435system.cpu.dcache.replacements 9619302 # number of replacements 436system.cpu.dcache.tagsinuse 4087.756066 # Cycle average of tags in use 437system.cpu.dcache.total_refs 660726669 # Total number of references to valid blocks. 438system.cpu.dcache.sampled_refs 9623398 # Sample count of references to valid blocks. 439system.cpu.dcache.avg_refs 68.658354 # Average number of references to valid blocks. 440system.cpu.dcache.warmup_cycle 3346373000 # Cycle when the warmup percentage was hit. 441system.cpu.dcache.occ_blocks::cpu.data 4087.756066 # Average occupied blocks per requestor --- 39 unchanged lines hidden (view full) --- 481system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.StoreCondReq_accesses::cpu.data 68 # number of StoreCondReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::total 68 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.demand_accesses::cpu.data 676628084 # number of demand (read+write) accesses 485system.cpu.dcache.demand_accesses::total 676628084 # number of demand (read+write) accesses 486system.cpu.dcache.overall_accesses::cpu.data 676628084 # number of overall (read+write) accesses 487system.cpu.dcache.overall_accesses::total 676628084 # number of overall (read+write) accesses 488system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021216 # miss rate for ReadReq accesses |
| 489system.cpu.dcache.ReadReq_miss_rate::total 0.021216 # miss rate for ReadReq accesses |
|
| 464system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses | 490system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses |
| 491system.cpu.dcache.WriteReq_miss_rate::total 0.030175 # miss rate for WriteReq accesses |
|
| 465system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses | 492system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.030928 # miss rate for LoadLockedReq accesses |
| 493system.cpu.dcache.LoadLockedReq_miss_rate::total 0.030928 # miss rate for LoadLockedReq accesses |
|
| 466system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses | 494system.cpu.dcache.demand_miss_rate::cpu.data 0.023501 # miss rate for demand accesses |
| 495system.cpu.dcache.demand_miss_rate::total 0.023501 # miss rate for demand accesses |
|
| 467system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses | 496system.cpu.dcache.overall_miss_rate::cpu.data 0.023501 # miss rate for overall accesses |
| 497system.cpu.dcache.overall_miss_rate::total 0.023501 # miss rate for overall accesses |
|
| 468system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency | 498system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17679.887499 # average ReadReq miss latency |
| 499system.cpu.dcache.ReadReq_avg_miss_latency::total 17679.887499 # average ReadReq miss latency |
|
| 469system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency | 500system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24831.987697 # average WriteReq miss latency |
| 501system.cpu.dcache.WriteReq_avg_miss_latency::total 24831.987697 # average WriteReq miss latency |
|
| 470system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency | 502system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency |
| 503system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 37833.333333 # average LoadLockedReq miss latency |
|
| 471system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency | 504system.cpu.dcache.demand_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency |
| 505system.cpu.dcache.demand_avg_miss_latency::total 20022.197405 # average overall miss latency |
|
| 472system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency | 506system.cpu.dcache.overall_avg_miss_latency::cpu.data 20022.197405 # average overall miss latency |
| 507system.cpu.dcache.overall_avg_miss_latency::total 20022.197405 # average overall miss latency |
|
| 473system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked 474system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked 475system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked 476system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked 477system.cpu.dcache.avg_blocked_cycles::no_mshrs 2951.821014 # average number of cycles each access was blocked 478system.cpu.dcache.avg_blocked_cycles::no_targets 16450 # average number of cycles each access was blocked 479system.cpu.dcache.fast_writes 0 # number of fast writes performed 480system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 502system.cpu.dcache.ReadReq_mshr_miss_latency::total 93061119500 # number of ReadReq MSHR miss cycles 503system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45369971960 # number of WriteReq MSHR miss cycles 504system.cpu.dcache.WriteReq_mshr_miss_latency::total 45369971960 # number of WriteReq MSHR miss cycles 505system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138431091460 # number of demand (read+write) MSHR miss cycles 506system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 # number of demand (read+write) MSHR miss cycles 507system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles 508system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles 509system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses | 508system.cpu.dcache.blocked_cycles::no_mshrs 271440605 # number of cycles access was blocked 509system.cpu.dcache.blocked_cycles::no_targets 164500 # number of cycles access was blocked 510system.cpu.dcache.blocked::no_mshrs 91957 # number of cycles access was blocked 511system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked 512system.cpu.dcache.avg_blocked_cycles::no_mshrs 2951.821014 # average number of cycles each access was blocked 513system.cpu.dcache.avg_blocked_cycles::no_targets 16450 # average number of cycles each access was blocked 514system.cpu.dcache.fast_writes 0 # number of fast writes performed 515system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 21 unchanged lines hidden (view full) --- 537system.cpu.dcache.ReadReq_mshr_miss_latency::total 93061119500 # number of ReadReq MSHR miss cycles 538system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45369971960 # number of WriteReq MSHR miss cycles 539system.cpu.dcache.WriteReq_mshr_miss_latency::total 45369971960 # number of WriteReq MSHR miss cycles 540system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138431091460 # number of demand (read+write) MSHR miss cycles 541system.cpu.dcache.demand_mshr_miss_latency::total 138431091460 # number of demand (read+write) MSHR miss cycles 542system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138431091460 # number of overall MSHR miss cycles 543system.cpu.dcache.overall_mshr_miss_latency::total 138431091460 # number of overall MSHR miss cycles 544system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015335 # mshr miss rate for ReadReq accesses |
| 545system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015335 # mshr miss rate for ReadReq accesses |
|
| 510system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses | 546system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses |
| 547system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010974 # mshr miss rate for WriteReq accesses |
|
| 511system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses | 548system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for demand accesses |
| 549system.cpu.dcache.demand_mshr_miss_rate::total 0.014223 # mshr miss rate for demand accesses |
|
| 512system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses | 550system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014223 # mshr miss rate for overall accesses |
| 551system.cpu.dcache.overall_mshr_miss_rate::total 0.014223 # mshr miss rate for overall accesses |
|
| 513system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency | 552system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12039.817537 # average ReadReq mshr miss latency |
| 553system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12039.817537 # average ReadReq mshr miss latency |
|
| 514system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency | 554system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23955.185749 # average WriteReq mshr miss latency |
| 555system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 23955.185749 # average WriteReq mshr miss latency |
|
| 515system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency | 556system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency |
| 557system.cpu.dcache.demand_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency |
|
| 516system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency | 558system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14384.845297 # average overall mshr miss latency |
| 559system.cpu.dcache.overall_avg_mshr_miss_latency::total 14384.845297 # average overall mshr miss latency |
|
| 517system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 518system.cpu.l2cache.replacements 2953110 # number of replacements 519system.cpu.l2cache.tagsinuse 26875.343151 # Cycle average of tags in use 520system.cpu.l2cache.total_refs 7878336 # Total number of references to valid blocks. 521system.cpu.l2cache.sampled_refs 2980430 # Sample count of references to valid blocks. 522system.cpu.l2cache.avg_refs 2.643355 # Average number of references to valid blocks. 523system.cpu.l2cache.warmup_cycle 100989511500 # Cycle when the warmup percentage was hit. 524system.cpu.l2cache.occ_blocks::writebacks 10758.137226 # Average occupied blocks per requestor --- 48 unchanged lines hidden (view full) --- 573system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses 574system.cpu.l2cache.demand_accesses::cpu.data 9623398 # number of demand (read+write) accesses 575system.cpu.l2cache.demand_accesses::total 9624199 # number of demand (read+write) accesses 576system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses 577system.cpu.l2cache.overall_accesses::cpu.data 9623398 # number of overall (read+write) accesses 578system.cpu.l2cache.overall_accesses::total 9624199 # number of overall (read+write) accesses 579system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963795 # miss rate for ReadReq accesses 580system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265109 # miss rate for ReadReq accesses | 560system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 561system.cpu.l2cache.replacements 2953110 # number of replacements 562system.cpu.l2cache.tagsinuse 26875.343151 # Cycle average of tags in use 563system.cpu.l2cache.total_refs 7878336 # Total number of references to valid blocks. 564system.cpu.l2cache.sampled_refs 2980430 # Sample count of references to valid blocks. 565system.cpu.l2cache.avg_refs 2.643355 # Average number of references to valid blocks. 566system.cpu.l2cache.warmup_cycle 100989511500 # Cycle when the warmup percentage was hit. 567system.cpu.l2cache.occ_blocks::writebacks 10758.137226 # Average occupied blocks per requestor --- 48 unchanged lines hidden (view full) --- 616system.cpu.l2cache.demand_accesses::cpu.inst 801 # number of demand (read+write) accesses 617system.cpu.l2cache.demand_accesses::cpu.data 9623398 # number of demand (read+write) accesses 618system.cpu.l2cache.demand_accesses::total 9624199 # number of demand (read+write) accesses 619system.cpu.l2cache.overall_accesses::cpu.inst 801 # number of overall (read+write) accesses 620system.cpu.l2cache.overall_accesses::cpu.data 9623398 # number of overall (read+write) accesses 621system.cpu.l2cache.overall_accesses::total 9624199 # number of overall (read+write) accesses 622system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963795 # miss rate for ReadReq accesses 623system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265109 # miss rate for ReadReq accesses |
| 624system.cpu.l2cache.ReadReq_miss_rate::total 0.265181 # miss rate for ReadReq accesses |
|
| 581system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483459 # miss rate for ReadExReq accesses | 625system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483459 # miss rate for ReadExReq accesses |
| 626system.cpu.l2cache.ReadExReq_miss_rate::total 0.483459 # miss rate for ReadExReq accesses |
|
| 582system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963795 # miss rate for demand accesses 583system.cpu.l2cache.demand_miss_rate::cpu.data 0.308082 # miss rate for demand accesses | 627system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963795 # miss rate for demand accesses 628system.cpu.l2cache.demand_miss_rate::cpu.data 0.308082 # miss rate for demand accesses |
| 629system.cpu.l2cache.demand_miss_rate::total 0.308136 # miss rate for demand accesses |
|
| 584system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963795 # miss rate for overall accesses 585system.cpu.l2cache.overall_miss_rate::cpu.data 0.308082 # miss rate for overall accesses | 630system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963795 # miss rate for overall accesses 631system.cpu.l2cache.overall_miss_rate::cpu.data 0.308082 # miss rate for overall accesses |
| 632system.cpu.l2cache.overall_miss_rate::total 0.308136 # miss rate for overall accesses |
|
| 586system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.865285 # average ReadReq miss latency 587system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.448450 # average ReadReq miss latency | 633system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.865285 # average ReadReq miss latency 634system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.448450 # average ReadReq miss latency |
| 635system.cpu.l2cache.ReadReq_avg_miss_latency::total 34328.459152 # average ReadReq miss latency |
|
| 588system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34690.748311 # average ReadExReq miss latency | 636system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34690.748311 # average ReadExReq miss latency |
| 637system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34690.748311 # average ReadExReq miss latency |
|
| 589system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency 590system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency | 638system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency 639system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency |
| 640system.cpu.l2cache.demand_avg_miss_latency::total 34440.319656 # average overall miss latency |
|
| 591system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency 592system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency | 641system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.865285 # average overall miss latency 642system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.341386 # average overall miss latency |
| 643system.cpu.l2cache.overall_avg_miss_latency::total 34440.319656 # average overall miss latency |
|
| 593system.cpu.l2cache.blocked_cycles::no_mshrs 57329500 # number of cycles access was blocked 594system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 595system.cpu.l2cache.blocked::no_mshrs 6735 # number of cycles access was blocked 596system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 597system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8512.175204 # average number of cycles each access was blocked 598system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 599system.cpu.l2cache.fast_writes 0 # number of fast writes performed 600system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 27 unchanged lines hidden (view full) --- 628system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24050500 # number of demand (read+write) MSHR miss cycles 629system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92824744500 # number of demand (read+write) MSHR miss cycles 630system.cpu.l2cache.demand_mshr_miss_latency::total 92848795000 # number of demand (read+write) MSHR miss cycles 631system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24050500 # number of overall MSHR miss cycles 632system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92824744500 # number of overall MSHR miss cycles 633system.cpu.l2cache.overall_mshr_miss_latency::total 92848795000 # number of overall MSHR miss cycles 634system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for ReadReq accesses 635system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265108 # mshr miss rate for ReadReq accesses | 644system.cpu.l2cache.blocked_cycles::no_mshrs 57329500 # number of cycles access was blocked 645system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 646system.cpu.l2cache.blocked::no_mshrs 6735 # number of cycles access was blocked 647system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 648system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8512.175204 # average number of cycles each access was blocked 649system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 650system.cpu.l2cache.fast_writes 0 # number of fast writes performed 651system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 27 unchanged lines hidden (view full) --- 679system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24050500 # number of demand (read+write) MSHR miss cycles 680system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92824744500 # number of demand (read+write) MSHR miss cycles 681system.cpu.l2cache.demand_mshr_miss_latency::total 92848795000 # number of demand (read+write) MSHR miss cycles 682system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24050500 # number of overall MSHR miss cycles 683system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92824744500 # number of overall MSHR miss cycles 684system.cpu.l2cache.overall_mshr_miss_latency::total 92848795000 # number of overall MSHR miss cycles 685system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for ReadReq accesses 686system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265108 # mshr miss rate for ReadReq accesses |
| 687system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.265180 # mshr miss rate for ReadReq accesses |
|
| 636system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483459 # mshr miss rate for ReadExReq accesses | 688system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483459 # mshr miss rate for ReadExReq accesses |
| 689system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.483459 # mshr miss rate for ReadExReq accesses |
|
| 637system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for demand accesses 638system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for demand accesses | 690system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for demand accesses 691system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for demand accesses |
| 692system.cpu.l2cache.demand_mshr_miss_rate::total 0.308135 # mshr miss rate for demand accesses |
|
| 639system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for overall accesses 640system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses | 693system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962547 # mshr miss rate for overall accesses 694system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308081 # mshr miss rate for overall accesses |
| 695system.cpu.l2cache.overall_mshr_miss_rate::total 0.308135 # mshr miss rate for overall accesses |
|
| 641system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency 642system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency | 696system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31193.904021 # average ReadReq mshr miss latency 697system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31187.061187 # average ReadReq mshr miss latency |
| 698system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31187.063761 # average ReadReq mshr miss latency |
|
| 643system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency | 699system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31582.171225 # average ReadExReq mshr miss latency |
| 700system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31582.171225 # average ReadExReq mshr miss latency |
|
| 644system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency 645system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency | 701system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency 702system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency |
| 703system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency |
|
| 646system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency 647system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency | 704system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31193.904021 # average overall mshr miss latency 705system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31309.087570 # average overall mshr miss latency |
| 706system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31309.057624 # average overall mshr miss latency |
|
| 648system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 649 650---------- End Simulation Statistics ---------- | 707system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 708 709---------- End Simulation Statistics ---------- |