| stats.txt (11860:67dee11badea) | stats.txt (11955:1170d039b31e) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.787836 # Number of seconds simulated 4sim_ticks 787835965500 # Number of ticks simulated 5final_tick 787835965500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 263266 # Simulator instruction rate (inst/s) 8host_op_rate 283629 # Simulator op (including micro ops) rate (op/s) --- 431 unchanged lines hidden (view full) --- 440system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 441system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 442system.cpu.itb.read_accesses 0 # DTB read accesses 443system.cpu.itb.write_accesses 0 # DTB write accesses 444system.cpu.itb.inst_accesses 0 # ITB inst accesses 445system.cpu.itb.hits 0 # DTB hits 446system.cpu.itb.misses 0 # DTB misses 447system.cpu.itb.accesses 0 # DTB accesses | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.787836 # Number of seconds simulated 4sim_ticks 787835965500 # Number of ticks simulated 5final_tick 787835965500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 263266 # Simulator instruction rate (inst/s) 8host_op_rate 283629 # Simulator op (including micro ops) rate (op/s) --- 431 unchanged lines hidden (view full) --- 440system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 441system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 442system.cpu.itb.read_accesses 0 # DTB read accesses 443system.cpu.itb.write_accesses 0 # DTB write accesses 444system.cpu.itb.inst_accesses 0 # ITB inst accesses 445system.cpu.itb.hits 0 # DTB hits 446system.cpu.itb.misses 0 # DTB misses 447system.cpu.itb.accesses 0 # DTB accesses |
| 448system.cpu.workload.num_syscalls 46 # Number of system calls | 448system.cpu.workload.numSyscalls 46 # Number of system calls |
| 449system.cpu.pwrStateResidencyTicks::ON 787835965500 # Cumulative time (in ticks) in various power states 450system.cpu.numCycles 1575671932 # number of cpu cycles simulated 451system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 452system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 453system.cpu.fetch.icacheStallCycles 13942337 # Number of cycles fetch is stalled on an Icache miss 454system.cpu.fetch.Insts 2067450540 # Number of instructions fetch has processed 455system.cpu.fetch.Branches 286288991 # Number of branches that fetch encountered 456system.cpu.fetch.predictedBranches 166955076 # Number of branches that fetch has predicted taken --- 826 unchanged lines hidden --- | 449system.cpu.pwrStateResidencyTicks::ON 787835965500 # Cumulative time (in ticks) in various power states 450system.cpu.numCycles 1575671932 # number of cpu cycles simulated 451system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 452system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 453system.cpu.fetch.icacheStallCycles 13942337 # Number of cycles fetch is stalled on an Icache miss 454system.cpu.fetch.Insts 2067450540 # Number of instructions fetch has processed 455system.cpu.fetch.Branches 286288991 # Number of branches that fetch encountered 456system.cpu.fetch.predictedBranches 166955076 # Number of branches that fetch has predicted taken --- 826 unchanged lines hidden --- |