| stats.txt (11754:c209cb86278a) | stats.txt (11860:67dee11badea) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.787540 # Number of seconds simulated 4sim_ticks 787540181500 # Number of ticks simulated 5final_tick 787540181500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.787836 # Number of seconds simulated 4sim_ticks 787835965500 # Number of ticks simulated 5final_tick 787835965500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 265954 # Simulator instruction rate (inst/s) 8host_op_rate 286525 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 135604104 # Simulator tick rate (ticks/s) 10host_mem_usage 328428 # Number of bytes of host memory used 11host_seconds 5807.64 # Real time elapsed on the host | 7host_inst_rate 263266 # Simulator instruction rate (inst/s) 8host_op_rate 283629 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 134283963 # Simulator tick rate (ticks/s) 10host_mem_usage 329624 # Number of bytes of host memory used 11host_seconds 5866.94 # Real time elapsed on the host |
| 12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 65088 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 236130432 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 63765312 # Number of bytes read from this memory 20system.physmem.bytes_read::total 299960832 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 65088 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 65088 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 104600704 # Number of bytes written to this memory 24system.physmem.bytes_written::total 104600704 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 1017 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 3689538 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 996333 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 4686888 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 1634386 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 1634386 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 82647 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 299832869 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 80967693 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 380883210 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 82647 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 82647 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 132819514 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 132819514 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 132819514 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 82647 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 299832869 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 80967693 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 513702723 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 4686888 # Number of read requests accepted 45system.physmem.writeReqs 1634386 # Number of write requests accepted 46system.physmem.readBursts 4686888 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 1634386 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 299458048 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 502784 # Total number of bytes read from write queue 50system.physmem.bytesWritten 104597376 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 299960832 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 104600704 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 7856 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 65344 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 236015808 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 63804544 # Number of bytes read from this memory 20system.physmem.bytes_read::total 299885696 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 65344 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 65344 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 104593152 # Number of bytes written to this memory 24system.physmem.bytes_written::total 104593152 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 1021 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 3687747 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 996946 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 4685714 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 1634268 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 1634268 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 82941 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 299574808 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 80987092 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 380644841 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 82941 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 82941 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 132760062 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 132760062 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 132760062 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 82941 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 299574808 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 80987092 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 513404904 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 4685714 # Number of read requests accepted 45system.physmem.writeReqs 1634268 # Number of write requests accepted 46system.physmem.readBursts 4685714 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 1634268 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 299374336 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 511360 # Total number of bytes read from write queue 50system.physmem.bytesWritten 104589440 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 299885696 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 104593152 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 7990 # Number of DRAM read bursts serviced by the write queue 54system.physmem.mergedWrBursts 28 # Number of DRAM write bursts merged with an existing one |
| 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 302302 # Per bank write bursts 57system.physmem.perBankRdBursts::1 301952 # Per bank write bursts 58system.physmem.perBankRdBursts::2 285792 # Per bank write bursts 59system.physmem.perBankRdBursts::3 288384 # Per bank write bursts 60system.physmem.perBankRdBursts::4 288196 # Per bank write bursts 61system.physmem.perBankRdBursts::5 285903 # Per bank write bursts 62system.physmem.perBankRdBursts::6 281854 # Per bank write bursts 63system.physmem.perBankRdBursts::7 277846 # Per bank write bursts 64system.physmem.perBankRdBursts::8 294690 # Per bank write bursts 65system.physmem.perBankRdBursts::9 300083 # Per bank write bursts 66system.physmem.perBankRdBursts::10 291836 # Per bank write bursts 67system.physmem.perBankRdBursts::11 298648 # Per bank write bursts 68system.physmem.perBankRdBursts::12 299589 # Per bank write bursts 69system.physmem.perBankRdBursts::13 298339 # Per bank write bursts 70system.physmem.perBankRdBursts::14 293778 # Per bank write bursts 71system.physmem.perBankRdBursts::15 289840 # Per bank write bursts 72system.physmem.perBankWrBursts::0 103932 # Per bank write bursts 73system.physmem.perBankWrBursts::1 101641 # Per bank write bursts 74system.physmem.perBankWrBursts::2 99135 # Per bank write bursts 75system.physmem.perBankWrBursts::3 99721 # Per bank write bursts 76system.physmem.perBankWrBursts::4 98850 # Per bank write bursts 77system.physmem.perBankWrBursts::5 98703 # Per bank write bursts 78system.physmem.perBankWrBursts::6 102612 # Per bank write bursts 79system.physmem.perBankWrBursts::7 104045 # Per bank write bursts 80system.physmem.perBankWrBursts::8 105476 # Per bank write bursts 81system.physmem.perBankWrBursts::9 104249 # Per bank write bursts 82system.physmem.perBankWrBursts::10 101862 # Per bank write bursts 83system.physmem.perBankWrBursts::11 102612 # Per bank write bursts 84system.physmem.perBankWrBursts::12 102593 # Per bank write bursts 85system.physmem.perBankWrBursts::13 102283 # Per bank write bursts 86system.physmem.perBankWrBursts::14 104155 # Per bank write bursts 87system.physmem.perBankWrBursts::15 102465 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 301500 # Per bank write bursts 57system.physmem.perBankRdBursts::1 301960 # Per bank write bursts 58system.physmem.perBankRdBursts::2 285447 # Per bank write bursts 59system.physmem.perBankRdBursts::3 288137 # Per bank write bursts 60system.physmem.perBankRdBursts::4 288946 # Per bank write bursts 61system.physmem.perBankRdBursts::5 285921 # Per bank write bursts 62system.physmem.perBankRdBursts::6 281288 # Per bank write bursts 63system.physmem.perBankRdBursts::7 278400 # Per bank write bursts 64system.physmem.perBankRdBursts::8 294011 # Per bank write bursts 65system.physmem.perBankRdBursts::9 300115 # Per bank write bursts 66system.physmem.perBankRdBursts::10 292046 # Per bank write bursts 67system.physmem.perBankRdBursts::11 297684 # Per bank write bursts 68system.physmem.perBankRdBursts::12 299531 # Per bank write bursts 69system.physmem.perBankRdBursts::13 298464 # Per bank write bursts 70system.physmem.perBankRdBursts::14 294115 # Per bank write bursts 71system.physmem.perBankRdBursts::15 290159 # Per bank write bursts 72system.physmem.perBankWrBursts::0 103775 # Per bank write bursts 73system.physmem.perBankWrBursts::1 101738 # Per bank write bursts 74system.physmem.perBankWrBursts::2 99347 # Per bank write bursts 75system.physmem.perBankWrBursts::3 99748 # Per bank write bursts 76system.physmem.perBankWrBursts::4 99113 # Per bank write bursts 77system.physmem.perBankWrBursts::5 98946 # Per bank write bursts 78system.physmem.perBankWrBursts::6 102275 # Per bank write bursts 79system.physmem.perBankWrBursts::7 103989 # Per bank write bursts 80system.physmem.perBankWrBursts::8 105110 # Per bank write bursts 81system.physmem.perBankWrBursts::9 104316 # Per bank write bursts 82system.physmem.perBankWrBursts::10 101973 # Per bank write bursts 83system.physmem.perBankWrBursts::11 102390 # Per bank write bursts 84system.physmem.perBankWrBursts::12 102662 # Per bank write bursts 85system.physmem.perBankWrBursts::13 102242 # Per bank write bursts 86system.physmem.perBankWrBursts::14 104082 # Per bank write bursts 87system.physmem.perBankWrBursts::15 102504 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 90system.physmem.totGap 787540140500 # Total gap between requests | 90system.physmem.totGap 787835924500 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 4686888 # Read request sizes (log2) | 97system.physmem.readPktSize::6 4685714 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 1634386 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 2728191 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 1051856 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 328268 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 233236 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 157524 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 89904 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 39917 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 24410 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 17981 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 4434 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1760 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 828 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 462 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 250 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 9 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 1634268 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 2727826 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 1050681 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 326941 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 233426 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 158423 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 90275 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 39813 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 24457 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 17994 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 4464 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1780 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 895 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 477 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 261 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 24307 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 26803 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 55730 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 73031 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 84525 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 93506 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 99632 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 103284 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 105231 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 105756 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 106392 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 107277 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 108481 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 109650 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 110259 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 109107 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 102133 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 101095 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 4500 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 1820 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 869 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 440 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 230 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 126 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 76 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 37 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 20 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 5 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::15 24253 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 26721 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 55721 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 72860 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 84494 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 93247 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 99524 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 103226 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 104977 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 106102 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 106319 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 107599 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 108399 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 109635 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 109963 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 109142 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 102277 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 101239 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 4710 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 1941 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 910 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 451 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 238 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 127 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 69 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 40 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 17 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 11 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 7 # What write queue length does an incoming req see |
| 181system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see | 181system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see |
| 182system.physmem.wrQLenPdf::45 5 # What write queue length does an incoming req see | 182system.physmem.wrQLenPdf::45 2 # What write queue length does an incoming req see |
| 183system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see | 183system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see |
| 184system.physmem.wrQLenPdf::47 3 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 1 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 1 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 1 # What write queue length does an incoming req see | 184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see |
| 188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 201system.physmem.bytesPerActivate::samples 4260550 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 94.836056 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 78.812158 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 102.756680 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 3400540 79.81% 79.81% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 663329 15.57% 95.38% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 94665 2.22% 97.61% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 34624 0.81% 98.42% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 22478 0.53% 98.95% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 12365 0.29% 99.24% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 7339 0.17% 99.41% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 5272 0.12% 99.53% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 19938 0.47% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 4260550 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 97975 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 47.757050 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 99.440701 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-255 95549 97.52% 97.52% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::256-511 1198 1.22% 98.75% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::512-767 700 0.71% 99.46% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::768-1023 381 0.39% 99.85% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::1024-1279 109 0.11% 99.96% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::1280-1535 28 0.03% 99.99% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::1536-1791 2 0.00% 99.99% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::1792-2047 1 0.00% 99.99% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::2304-2559 1 0.00% 99.99% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::2816-3071 2 0.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::3328-3583 2 0.00% 100.00% # Reads before turning the bus around for writes | 201system.physmem.bytesPerActivate::samples 4259361 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 94.841028 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 78.814946 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 102.698820 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 3400000 79.82% 79.82% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 662329 15.55% 95.37% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 94740 2.22% 97.60% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 35136 0.82% 98.42% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 22172 0.52% 98.94% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 12513 0.29% 99.24% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 7488 0.18% 99.41% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 5149 0.12% 99.53% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 19834 0.47% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 4259361 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 98005 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 47.729004 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 99.044358 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-255 95588 97.53% 97.53% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::256-511 1180 1.20% 98.74% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::512-767 706 0.72% 99.46% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::768-1023 397 0.41% 99.86% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::1024-1279 101 0.10% 99.97% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::1280-1535 19 0.02% 99.99% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::1536-1791 5 0.01% 99.99% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::2048-2303 3 0.00% 100.00% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::2560-2815 1 0.00% 100.00% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::3072-3327 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 230system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes | 230system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 231system.physmem.rdPerTurnAround::total 97975 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 97975 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 16.681133 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 16.640632 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 1.211305 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16 70258 71.71% 71.71% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::17 1952 1.99% 73.70% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::18 17579 17.94% 91.64% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::19 5262 5.37% 97.02% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20 1746 1.78% 98.80% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::21 657 0.67% 99.47% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::22 283 0.29% 99.76% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::23 119 0.12% 99.88% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::24 69 0.07% 99.95% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::25 29 0.03% 99.98% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::26 11 0.01% 99.99% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::31 1 0.00% 100.00% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::total 97975 # Writes before turning the bus around for reads 251system.physmem.totQLat 162188930459 # Total ticks spent queuing 252system.physmem.totMemAccLat 249920780459 # Total ticks spent from burst creation until serviced by the DRAM 253system.physmem.totBusLat 23395160000 # Total ticks spent in databus transfers 254system.physmem.avgQLat 34662.92 # Average queueing delay per DRAM burst | 231system.physmem.rdPerTurnAround::total 98005 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 98005 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 16.674761 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 16.634865 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 1.202481 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16 70360 71.79% 71.79% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::17 1982 2.02% 73.81% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::18 17660 18.02% 91.83% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::19 5209 5.32% 97.15% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20 1729 1.76% 98.91% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::21 596 0.61% 99.52% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::22 225 0.23% 99.75% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::23 114 0.12% 99.87% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::24 71 0.07% 99.94% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::25 31 0.03% 99.97% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::26 17 0.02% 99.99% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::27 4 0.00% 99.99% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::28 3 0.00% 100.00% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::31 2 0.00% 100.00% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::33 1 0.00% 100.00% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::total 98005 # Writes before turning the bus around for reads 253system.physmem.totQLat 162836208305 # Total ticks spent queuing 254system.physmem.totMemAccLat 250543533305 # Total ticks spent from burst creation until serviced by the DRAM 255system.physmem.totBusLat 23388620000 # Total ticks spent in databus transfers 256system.physmem.avgQLat 34810.99 # Average queueing delay per DRAM burst |
| 255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 257system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 256system.physmem.avgMemAccLat 53412.92 # Average memory access latency per DRAM burst 257system.physmem.avgRdBW 380.24 # Average DRAM read bandwidth in MiByte/s 258system.physmem.avgWrBW 132.82 # Average achieved write bandwidth in MiByte/s 259system.physmem.avgRdBWSys 380.88 # Average system read bandwidth in MiByte/s 260system.physmem.avgWrBWSys 132.82 # Average system write bandwidth in MiByte/s | 258system.physmem.avgMemAccLat 53560.99 # Average memory access latency per DRAM burst 259system.physmem.avgRdBW 380.00 # Average DRAM read bandwidth in MiByte/s 260system.physmem.avgWrBW 132.76 # Average achieved write bandwidth in MiByte/s 261system.physmem.avgRdBWSys 380.64 # Average system read bandwidth in MiByte/s 262system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s |
| 261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 262system.physmem.busUtil 4.01 # Data bus utilization in percentage 263system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads 264system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes 265system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing | 263system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 264system.physmem.busUtil 4.01 # Data bus utilization in percentage 265system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads 266system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes 267system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing |
| 266system.physmem.avgWrQLen 24.99 # Average write queue length when enqueuing 267system.physmem.readRowHits 1713351 # Number of row buffer hits during reads 268system.physmem.writeRowHits 339452 # Number of row buffer hits during writes 269system.physmem.readRowHitRate 36.62 # Row buffer hit rate for reads 270system.physmem.writeRowHitRate 20.77 # Row buffer hit rate for writes 271system.physmem.avgGap 124585.67 # Average gap between requests | 268system.physmem.avgWrQLen 24.94 # Average write queue length when enqueuing 269system.physmem.readRowHits 1712017 # Number of row buffer hits during reads 270system.physmem.writeRowHits 340548 # Number of row buffer hits during writes 271system.physmem.readRowHitRate 36.60 # Row buffer hit rate for reads 272system.physmem.writeRowHitRate 20.84 # Row buffer hit rate for writes 273system.physmem.avgGap 124657.94 # Average gap between requests |
| 272system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined | 274system.physmem.pageHitRate 32.52 # Row buffer hit rate, read and write combined |
| 273system.physmem_0.actEnergy 15118214580 # Energy for activate commands per rank (pJ) 274system.physmem_0.preEnergy 8035491255 # Energy for precharge commands per rank (pJ) 275system.physmem_0.readEnergy 16509315060 # Energy for read commands per rank (pJ) 276system.physmem_0.writeEnergy 4221095580 # Energy for write commands per rank (pJ) 277system.physmem_0.refreshEnergy 59433229440.000015 # Energy for refresh commands per rank (pJ) 278system.physmem_0.actBackEnergy 64449448560 # Energy for active background per rank (pJ) 279system.physmem_0.preBackEnergy 1619596800 # Energy for precharge background per rank (pJ) 280system.physmem_0.actPowerDownEnergy 222781261830 # Energy for active power-down per rank (pJ) 281system.physmem_0.prePowerDownEnergy 36127794240 # Energy for precharge power-down per rank (pJ) 282system.physmem_0.selfRefreshEnergy 16128721335 # Energy for self refresh per rank (pJ) 283system.physmem_0.totalEnergy 444435904680 # Total energy per rank (pJ) 284system.physmem_0.averagePower 564.334256 # Core power per rank (mW) 285system.physmem_0.totalIdleTime 641954026654 # Total Idle time Per DRAM Rank 286system.physmem_0.memoryStateTime::IDLE 1425644900 # Time in different power states 287system.physmem_0.memoryStateTime::REF 25162536000 # Time in different power states 288system.physmem_0.memoryStateTime::SREF 59321643250 # Time in different power states 289system.physmem_0.memoryStateTime::PRE_PDN 94080310817 # Time in different power states 290system.physmem_0.memoryStateTime::ACT 118997964696 # Time in different power states 291system.physmem_0.memoryStateTime::ACT_PDN 488552081837 # Time in different power states 292system.physmem_1.actEnergy 15302205240 # Energy for activate commands per rank (pJ) 293system.physmem_1.preEnergy 8133295995 # Energy for precharge commands per rank (pJ) 294system.physmem_1.readEnergy 16898973420 # Energy for read commands per rank (pJ) 295system.physmem_1.writeEnergy 4310127900 # Energy for write commands per rank (pJ) 296system.physmem_1.refreshEnergy 58889273040.000015 # Energy for refresh commands per rank (pJ) 297system.physmem_1.actBackEnergy 64896379290 # Energy for active background per rank (pJ) 298system.physmem_1.preBackEnergy 1612760640 # Energy for precharge background per rank (pJ) 299system.physmem_1.actPowerDownEnergy 219232237770 # Energy for active power-down per rank (pJ) 300system.physmem_1.prePowerDownEnergy 35640720960 # Energy for precharge power-down per rank (pJ) 301system.physmem_1.selfRefreshEnergy 18160779360 # Energy for self refresh per rank (pJ) 302system.physmem_1.totalEnergy 443087552175 # Total energy per rank (pJ) 303system.physmem_1.averagePower 562.622143 # Core power per rank (mW) 304system.physmem_1.totalIdleTime 640996653350 # Total Idle time Per DRAM Rank 305system.physmem_1.memoryStateTime::IDLE 1453270191 # Time in different power states 306system.physmem_1.memoryStateTime::REF 24933432000 # Time in different power states 307system.physmem_1.memoryStateTime::SREF 67412776000 # Time in different power states 308system.physmem_1.memoryStateTime::PRE_PDN 92813399032 # Time in different power states 309system.physmem_1.memoryStateTime::ACT 120155386459 # Time in different power states 310system.physmem_1.memoryStateTime::ACT_PDN 480771917818 # Time in different power states 311system.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 312system.cpu.branchPred.lookups 286296319 # Number of BP lookups 313system.cpu.branchPred.condPredicted 223413056 # Number of conditional branches predicted 314system.cpu.branchPred.condIncorrect 14631953 # Number of conditional branches incorrect 315system.cpu.branchPred.BTBLookups 158681776 # Number of BTB lookups 316system.cpu.branchPred.BTBHits 150365310 # Number of BTB hits | 275system.physmem_0.actEnergy 15118935720 # Energy for activate commands per rank (pJ) 276system.physmem_0.preEnergy 8035889730 # Energy for precharge commands per rank (pJ) 277system.physmem_0.readEnergy 16504816860 # Energy for read commands per rank (pJ) 278system.physmem_0.writeEnergy 4222619820 # Energy for write commands per rank (pJ) 279system.physmem_0.refreshEnergy 59457815040.000015 # Energy for refresh commands per rank (pJ) 280system.physmem_0.actBackEnergy 64415436660 # Energy for active background per rank (pJ) 281system.physmem_0.preBackEnergy 1624122240 # Energy for precharge background per rank (pJ) 282system.physmem_0.actPowerDownEnergy 222796740750 # Energy for active power-down per rank (pJ) 283system.physmem_0.prePowerDownEnergy 36224267040 # Energy for precharge power-down per rank (pJ) 284system.physmem_0.selfRefreshEnergy 16152645360 # Energy for self refresh per rank (pJ) 285system.physmem_0.totalEnergy 444563646270 # Total energy per rank (pJ) 286system.physmem_0.averagePower 564.284526 # Core power per rank (mW) 287system.physmem_0.totalIdleTime 642315388170 # Total Idle time Per DRAM Rank 288system.physmem_0.memoryStateTime::IDLE 1436139102 # Time in different power states 289system.physmem_0.memoryStateTime::REF 25173062000 # Time in different power states 290system.physmem_0.memoryStateTime::SREF 59398115500 # Time in different power states 291system.physmem_0.memoryStateTime::PRE_PDN 94331998561 # Time in different power states 292system.physmem_0.memoryStateTime::ACT 118911366978 # Time in different power states 293system.physmem_0.memoryStateTime::ACT_PDN 488585283359 # Time in different power states 294system.physmem_1.actEnergy 15292958940 # Energy for activate commands per rank (pJ) 295system.physmem_1.preEnergy 8128385265 # Energy for precharge commands per rank (pJ) 296system.physmem_1.readEnergy 16894132500 # Energy for read commands per rank (pJ) 297system.physmem_1.writeEnergy 4307956380 # Energy for write commands per rank (pJ) 298system.physmem_1.refreshEnergy 58918161120.000015 # Energy for refresh commands per rank (pJ) 299system.physmem_1.actBackEnergy 64834688190 # Energy for active background per rank (pJ) 300system.physmem_1.preBackEnergy 1616111040 # Energy for precharge background per rank (pJ) 301system.physmem_1.actPowerDownEnergy 219342669570 # Energy for active power-down per rank (pJ) 302system.physmem_1.prePowerDownEnergy 35641510560 # Energy for precharge power-down per rank (pJ) 303system.physmem_1.selfRefreshEnergy 18222503400 # Energy for self refresh per rank (pJ) 304system.physmem_1.totalEnergy 443208649005 # Total energy per rank (pJ) 305system.physmem_1.averagePower 562.564626 # Core power per rank (mW) 306system.physmem_1.totalIdleTime 641423107931 # Total Idle time Per DRAM Rank 307system.physmem_1.memoryStateTime::IDLE 1455389769 # Time in different power states 308system.physmem_1.memoryStateTime::REF 24945910000 # Time in different power states 309system.physmem_1.memoryStateTime::SREF 67593570250 # Time in different power states 310system.physmem_1.memoryStateTime::PRE_PDN 92814429154 # Time in different power states 311system.physmem_1.memoryStateTime::ACT 120009883050 # Time in different power states 312system.physmem_1.memoryStateTime::ACT_PDN 481016783277 # Time in different power states 313system.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 314system.cpu.branchPred.lookups 286288991 # Number of BP lookups 315system.cpu.branchPred.condPredicted 223379889 # Number of conditional branches predicted 316system.cpu.branchPred.condIncorrect 14638803 # Number of conditional branches incorrect 317system.cpu.branchPred.BTBLookups 157014468 # Number of BTB lookups 318system.cpu.branchPred.BTBHits 150316303 # Number of BTB hits |
| 317system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 319system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 318system.cpu.branchPred.BTBHitPct 94.759029 # BTB Hit Percentage 319system.cpu.branchPred.usedRAS 16643535 # Number of times the RAS was used to get a target. 320system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. 321system.cpu.branchPred.indirectLookups 3038 # Number of indirect predictor lookups. 322system.cpu.branchPred.indirectHits 1928 # Number of indirect target hits. 323system.cpu.branchPred.indirectMisses 1110 # Number of indirect misses. 324system.cpu.branchPredindirectMispredicted 135 # Number of mispredicted indirect branches. | 320system.cpu.branchPred.BTBHitPct 95.734046 # BTB Hit Percentage 321system.cpu.branchPred.usedRAS 16636731 # Number of times the RAS was used to get a target. 322system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions. 323system.cpu.branchPred.indirectLookups 3547 # Number of indirect predictor lookups. 324system.cpu.branchPred.indirectHits 2042 # Number of indirect target hits. 325system.cpu.branchPred.indirectMisses 1505 # Number of indirect misses. 326system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. |
| 325system.cpu_clk_domain.clock 500 # Clock period in ticks | 327system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 326system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states | 328system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states |
| 327system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 328system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 329system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 330system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 331system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 348system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 349system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 350system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 351system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 352system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 353system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 354system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 355system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 329system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 330system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 336system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 350system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 351system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 352system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 353system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 354system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 355system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 356system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 357system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 356system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states | 358system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states |
| 357system.cpu.dtb.walker.walks 0 # Table walker walks requested 358system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 378system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.dtb.read_accesses 0 # DTB read accesses 381system.cpu.dtb.write_accesses 0 # DTB write accesses 382system.cpu.dtb.inst_accesses 0 # ITB inst accesses 383system.cpu.dtb.hits 0 # DTB hits 384system.cpu.dtb.misses 0 # DTB misses 385system.cpu.dtb.accesses 0 # DTB accesses | 359system.cpu.dtb.walker.walks 0 # Table walker walks requested 360system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 363system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 366system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 380system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 381system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 382system.cpu.dtb.read_accesses 0 # DTB read accesses 383system.cpu.dtb.write_accesses 0 # DTB write accesses 384system.cpu.dtb.inst_accesses 0 # ITB inst accesses 385system.cpu.dtb.hits 0 # DTB hits 386system.cpu.dtb.misses 0 # DTB misses 387system.cpu.dtb.accesses 0 # DTB accesses |
| 386system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states | 388system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states |
| 387system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 388system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 391system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 394system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 408system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 409system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 410system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 411system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 412system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 413system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 414system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 415system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 389system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 390system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 391system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 392system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 393system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 394system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 396system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 410system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 411system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 412system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 413system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 414system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 415system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 416system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 417system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 416system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states | 418system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states |
| 417system.cpu.itb.walker.walks 0 # Table walker walks requested 418system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 419system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 420system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 421system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 422system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 423system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 424system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 439system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 440system.cpu.itb.read_accesses 0 # DTB read accesses 441system.cpu.itb.write_accesses 0 # DTB write accesses 442system.cpu.itb.inst_accesses 0 # ITB inst accesses 443system.cpu.itb.hits 0 # DTB hits 444system.cpu.itb.misses 0 # DTB misses 445system.cpu.itb.accesses 0 # DTB accesses 446system.cpu.workload.num_syscalls 46 # Number of system calls | 419system.cpu.itb.walker.walks 0 # Table walker walks requested 420system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 421system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 422system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 423system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 424system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 425system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 426system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 441system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 442system.cpu.itb.read_accesses 0 # DTB read accesses 443system.cpu.itb.write_accesses 0 # DTB write accesses 444system.cpu.itb.inst_accesses 0 # ITB inst accesses 445system.cpu.itb.hits 0 # DTB hits 446system.cpu.itb.misses 0 # DTB misses 447system.cpu.itb.accesses 0 # DTB accesses 448system.cpu.workload.num_syscalls 46 # Number of system calls |
| 447system.cpu.pwrStateResidencyTicks::ON 787540181500 # Cumulative time (in ticks) in various power states 448system.cpu.numCycles 1575080364 # number of cpu cycles simulated | 449system.cpu.pwrStateResidencyTicks::ON 787835965500 # Cumulative time (in ticks) in various power states 450system.cpu.numCycles 1575671932 # number of cpu cycles simulated |
| 449system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 450system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 451system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 452system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 451system.cpu.fetch.icacheStallCycles 13929690 # Number of cycles fetch is stalled on an Icache miss 452system.cpu.fetch.Insts 2067600144 # Number of instructions fetch has processed 453system.cpu.fetch.Branches 286296319 # Number of branches that fetch encountered 454system.cpu.fetch.predictedBranches 167010773 # Number of branches that fetch has predicted taken 455system.cpu.fetch.Cycles 1546402654 # Number of cycles fetch has run and was not squashing or blocked 456system.cpu.fetch.SquashCycles 29288795 # Number of cycles fetch has spent squashing 457system.cpu.fetch.MiscStallCycles 390 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 458system.cpu.fetch.IcacheWaitRetryStallCycles 943 # Number of stall cycles due to full MSHR 459system.cpu.fetch.CacheLines 656982335 # Number of cache lines fetched 460system.cpu.fetch.IcacheSquashes 916 # Number of outstanding Icache misses that were squashed 461system.cpu.fetch.rateDist::samples 1574978074 # Number of instructions fetched each cycle (Total) 462system.cpu.fetch.rateDist::mean 1.406414 # Number of instructions fetched each cycle (Total) 463system.cpu.fetch.rateDist::stdev 1.233446 # Number of instructions fetched each cycle (Total) | 453system.cpu.fetch.icacheStallCycles 13942337 # Number of cycles fetch is stalled on an Icache miss 454system.cpu.fetch.Insts 2067450540 # Number of instructions fetch has processed 455system.cpu.fetch.Branches 286288991 # Number of branches that fetch encountered 456system.cpu.fetch.predictedBranches 166955076 # Number of branches that fetch has predicted taken 457system.cpu.fetch.Cycles 1546978368 # Number of cycles fetch has run and was not squashing or blocked 458system.cpu.fetch.SquashCycles 29302455 # Number of cycles fetch has spent squashing 459system.cpu.fetch.MiscStallCycles 311 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 460system.cpu.fetch.IcacheWaitRetryStallCycles 1029 # Number of stall cycles due to full MSHR 461system.cpu.fetch.CacheLines 656906223 # Number of cache lines fetched 462system.cpu.fetch.IcacheSquashes 925 # Number of outstanding Icache misses that were squashed 463system.cpu.fetch.rateDist::samples 1575573272 # Number of instructions fetched each cycle (Total) 464system.cpu.fetch.rateDist::mean 1.405744 # Number of instructions fetched each cycle (Total) 465system.cpu.fetch.rateDist::stdev 1.233501 # Number of instructions fetched each cycle (Total) |
| 464system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 466system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 465system.cpu.fetch.rateDist::0 492512848 31.27% 31.27% # Number of instructions fetched each cycle (Total) 466system.cpu.fetch.rateDist::1 465448024 29.55% 60.82% # Number of instructions fetched each cycle (Total) 467system.cpu.fetch.rateDist::2 101428874 6.44% 67.26% # Number of instructions fetched each cycle (Total) 468system.cpu.fetch.rateDist::3 515588328 32.74% 100.00% # Number of instructions fetched each cycle (Total) | 467system.cpu.fetch.rateDist::0 493163312 31.30% 31.30% # Number of instructions fetched each cycle (Total) 468system.cpu.fetch.rateDist::1 465492881 29.54% 60.84% # Number of instructions fetched each cycle (Total) 469system.cpu.fetch.rateDist::2 101391668 6.44% 67.28% # Number of instructions fetched each cycle (Total) 470system.cpu.fetch.rateDist::3 515525411 32.72% 100.00% # Number of instructions fetched each cycle (Total) |
| 469system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 470system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 471system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 471system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 472system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 473system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 472system.cpu.fetch.rateDist::total 1574978074 # Number of instructions fetched each cycle (Total) 473system.cpu.fetch.branchRate 0.181766 # Number of branch fetches per cycle 474system.cpu.fetch.rate 1.312695 # Number of inst fetches per cycle 475system.cpu.decode.IdleCycles 74681637 # Number of cycles decode is idle 476system.cpu.decode.BlockedCycles 577546655 # Number of cycles decode is blocked 477system.cpu.decode.RunCycles 849949420 # Number of cycles decode is running 478system.cpu.decode.UnblockCycles 58156641 # Number of cycles decode is unblocking 479system.cpu.decode.SquashCycles 14643721 # Number of cycles decode is squashing 480system.cpu.decode.BranchResolved 42204470 # Number of times decode resolved a branch 481system.cpu.decode.BranchMispred 713 # Number of times decode detected a branch misprediction 482system.cpu.decode.DecodedInsts 2037236907 # Number of instructions handled by decode 483system.cpu.decode.SquashedInsts 52506596 # Number of squashed instructions handled by decode 484system.cpu.rename.SquashCycles 14643721 # Number of cycles rename is squashing 485system.cpu.rename.IdleCycles 139754890 # Number of cycles rename is idle 486system.cpu.rename.BlockCycles 492363005 # Number of cycles rename is blocking 487system.cpu.rename.serializeStallCycles 15806 # count of cycles rename stalled for serializing inst 488system.cpu.rename.RunCycles 837855661 # Number of cycles rename is running 489system.cpu.rename.UnblockCycles 90344991 # Number of cycles rename is unblocking 490system.cpu.rename.RenamedInsts 1976429927 # Number of instructions processed by rename 491system.cpu.rename.SquashedInsts 26743123 # Number of squashed instructions processed by rename 492system.cpu.rename.ROBFullEvents 45374465 # Number of times rename has blocked due to ROB full 493system.cpu.rename.IQFullEvents 126519 # Number of times rename has blocked due to IQ full 494system.cpu.rename.LQFullEvents 1703162 # Number of times rename has blocked due to LQ full 495system.cpu.rename.SQFullEvents 29238118 # Number of times rename has blocked due to SQ full 496system.cpu.rename.RenamedOperands 1985901380 # Number of destination operands rename has renamed 497system.cpu.rename.RenameLookups 9128373257 # Number of register rename lookups that rename has made 498system.cpu.rename.int_rename_lookups 2432925820 # Number of integer rename lookups 499system.cpu.rename.fp_rename_lookups 137 # Number of floating rename lookups | 474system.cpu.fetch.rateDist::total 1575573272 # Number of instructions fetched each cycle (Total) 475system.cpu.fetch.branchRate 0.181693 # Number of branch fetches per cycle 476system.cpu.fetch.rate 1.312107 # Number of inst fetches per cycle 477system.cpu.decode.IdleCycles 74679257 # Number of cycles decode is idle 478system.cpu.decode.BlockedCycles 578142352 # Number of cycles decode is blocked 479system.cpu.decode.RunCycles 849952798 # Number of cycles decode is running 480system.cpu.decode.UnblockCycles 58148325 # Number of cycles decode is unblocking 481system.cpu.decode.SquashCycles 14650540 # Number of cycles decode is squashing 482system.cpu.decode.BranchResolved 135611620 # Number of times decode resolved a branch 483system.cpu.decode.BranchMispred 746 # Number of times decode detected a branch misprediction 484system.cpu.decode.DecodedInsts 2037153887 # Number of instructions handled by decode 485system.cpu.decode.SquashedInsts 52516232 # Number of squashed instructions handled by decode 486system.cpu.rename.SquashCycles 14650540 # Number of cycles rename is squashing 487system.cpu.rename.IdleCycles 139761664 # Number of cycles rename is idle 488system.cpu.rename.BlockCycles 493000122 # Number of cycles rename is blocking 489system.cpu.rename.serializeStallCycles 16309 # count of cycles rename stalled for serializing inst 490system.cpu.rename.RunCycles 837842196 # Number of cycles rename is running 491system.cpu.rename.UnblockCycles 90302441 # Number of cycles rename is unblocking 492system.cpu.rename.RenamedInsts 1976324662 # Number of instructions processed by rename 493system.cpu.rename.SquashedInsts 26749907 # Number of squashed instructions processed by rename 494system.cpu.rename.ROBFullEvents 45308958 # Number of times rename has blocked due to ROB full 495system.cpu.rename.IQFullEvents 126668 # Number of times rename has blocked due to IQ full 496system.cpu.rename.LQFullEvents 1624936 # Number of times rename has blocked due to LQ full 497system.cpu.rename.SQFullEvents 29276583 # Number of times rename has blocked due to SQ full 498system.cpu.rename.RenamedOperands 1985726338 # Number of destination operands rename has renamed 499system.cpu.rename.RenameLookups 9127758695 # Number of register rename lookups that rename has made 500system.cpu.rename.int_rename_lookups 2432766069 # Number of integer rename lookups 501system.cpu.rename.fp_rename_lookups 161 # Number of floating rename lookups |
| 500system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed | 502system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed |
| 501system.cpu.rename.UndoneMaps 311002435 # Number of HB maps that are undone due to squashing 502system.cpu.rename.serializingInsts 176 # count of serializing insts renamed | 503system.cpu.rename.UndoneMaps 310827393 # Number of HB maps that are undone due to squashing 504system.cpu.rename.serializingInsts 177 # count of serializing insts renamed |
| 503system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed | 505system.cpu.rename.tempSerializingInsts 174 # count of temporary serializing insts renamed |
| 504system.cpu.rename.skidInsts 111413296 # count of insts added to the skid buffer 505system.cpu.memDep0.insertedLoads 542580071 # Number of loads inserted to the mem dependence unit. 506system.cpu.memDep0.insertedStores 199306810 # Number of stores inserted to the mem dependence unit. 507system.cpu.memDep0.conflictingLoads 26873371 # Number of conflicting loads. 508system.cpu.memDep0.conflictingStores 29046971 # Number of conflicting stores. 509system.cpu.iq.iqInstsAdded 1948011764 # Number of instructions added to the IQ (excludes non-spec) 510system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ 511system.cpu.iq.iqInstsIssued 1857503284 # Number of instructions issued 512system.cpu.iq.iqSquashedInstsIssued 13502415 # Number of squashed instructions issued 513system.cpu.iq.iqSquashedInstsExamined 283979579 # Number of squashed instructions iterated over during squash; mainly for profiling 514system.cpu.iq.iqSquashedOperandsExamined 647409512 # Number of squashed operands that are examined and possibly removed from graph 515system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed 516system.cpu.iq.issued_per_cycle::samples 1574978074 # Number of insts issued each cycle 517system.cpu.iq.issued_per_cycle::mean 1.179384 # Number of insts issued each cycle 518system.cpu.iq.issued_per_cycle::stdev 1.151840 # Number of insts issued each cycle | 506system.cpu.rename.skidInsts 111376144 # count of insts added to the skid buffer 507system.cpu.memDep0.insertedLoads 542477238 # Number of loads inserted to the mem dependence unit. 508system.cpu.memDep0.insertedStores 199268014 # Number of stores inserted to the mem dependence unit. 509system.cpu.memDep0.conflictingLoads 26870545 # Number of conflicting loads. 510system.cpu.memDep0.conflictingStores 28963209 # Number of conflicting stores. 511system.cpu.iq.iqInstsAdded 1947887828 # Number of instructions added to the IQ (excludes non-spec) 512system.cpu.iq.iqNonSpecInstsAdded 229 # Number of non-speculative instructions added to the IQ 513system.cpu.iq.iqInstsIssued 1857408251 # Number of instructions issued 514system.cpu.iq.iqSquashedInstsIssued 13517769 # Number of squashed instructions issued 515system.cpu.iq.iqSquashedInstsExamined 283855641 # Number of squashed instructions iterated over during squash; mainly for profiling 516system.cpu.iq.iqSquashedOperandsExamined 647022412 # Number of squashed operands that are examined and possibly removed from graph 517system.cpu.iq.iqSquashedNonSpecRemoved 59 # Number of squashed non-spec instructions that were removed 518system.cpu.iq.issued_per_cycle::samples 1575573272 # Number of insts issued each cycle 519system.cpu.iq.issued_per_cycle::mean 1.178878 # Number of insts issued each cycle 520system.cpu.iq.issued_per_cycle::stdev 1.151815 # Number of insts issued each cycle |
| 519system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 521system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 520system.cpu.iq.issued_per_cycle::0 622116780 39.50% 39.50% # Number of insts issued each cycle 521system.cpu.iq.issued_per_cycle::1 325952300 20.70% 60.20% # Number of insts issued each cycle 522system.cpu.iq.issued_per_cycle::2 378187133 24.01% 84.21% # Number of insts issued each cycle 523system.cpu.iq.issued_per_cycle::3 219716912 13.95% 98.16% # Number of insts issued each cycle 524system.cpu.iq.issued_per_cycle::4 28998763 1.84% 100.00% # Number of insts issued each cycle 525system.cpu.iq.issued_per_cycle::5 6186 0.00% 100.00% # Number of insts issued each cycle | 522system.cpu.iq.issued_per_cycle::0 622703787 39.52% 39.52% # Number of insts issued each cycle 523system.cpu.iq.issued_per_cycle::1 326030740 20.69% 60.22% # Number of insts issued each cycle 524system.cpu.iq.issued_per_cycle::2 378156304 24.00% 84.22% # Number of insts issued each cycle 525system.cpu.iq.issued_per_cycle::3 219671219 13.94% 98.16% # Number of insts issued each cycle 526system.cpu.iq.issued_per_cycle::4 29004864 1.84% 100.00% # Number of insts issued each cycle 527system.cpu.iq.issued_per_cycle::5 6358 0.00% 100.00% # Number of insts issued each cycle |
| 526system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 527system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 528system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 529system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 530system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 531system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 528system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 529system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 530system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 531system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 532system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 533system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 532system.cpu.iq.issued_per_cycle::total 1574978074 # Number of insts issued each cycle | 534system.cpu.iq.issued_per_cycle::total 1575573272 # Number of insts issued each cycle |
| 533system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 535system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 534system.cpu.iq.fu_full::IntAlu 166073423 40.98% 40.98% # attempts to use FU when none available 535system.cpu.iq.fu_full::IntMult 2008 0.00% 40.98% # attempts to use FU when none available 536system.cpu.iq.fu_full::IntDiv 0 0.00% 40.98% # attempts to use FU when none available 537system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.98% # attempts to use FU when none available 538system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.98% # attempts to use FU when none available 539system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.98% # attempts to use FU when none available 540system.cpu.iq.fu_full::FloatMult 0 0.00% 40.98% # attempts to use FU when none available 541system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available 542system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.98% # attempts to use FU when none available 543system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.98% # attempts to use FU when none available 544system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.98% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.98% # attempts to use FU when none available 546system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.98% # attempts to use FU when none available 547system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.98% # attempts to use FU when none available 548system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.98% # attempts to use FU when none available 549system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.98% # attempts to use FU when none available 550system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.98% # attempts to use FU when none available 551system.cpu.iq.fu_full::SimdMult 0 0.00% 40.98% # attempts to use FU when none available 552system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.98% # attempts to use FU when none available 553system.cpu.iq.fu_full::SimdShift 0 0.00% 40.98% # attempts to use FU when none available 554system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.98% # attempts to use FU when none available 555system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.98% # attempts to use FU when none available 556system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.98% # attempts to use FU when none available 557system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.98% # attempts to use FU when none available 558system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.98% # attempts to use FU when none available 559system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.98% # attempts to use FU when none available 560system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.98% # attempts to use FU when none available 561system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.98% # attempts to use FU when none available 562system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.98% # attempts to use FU when none available 563system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.98% # attempts to use FU when none available 564system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.98% # attempts to use FU when none available 565system.cpu.iq.fu_full::MemRead 191445503 47.24% 88.22% # attempts to use FU when none available 566system.cpu.iq.fu_full::MemWrite 47741848 11.78% 100.00% # attempts to use FU when none available | 536system.cpu.iq.fu_full::IntAlu 166096777 40.98% 40.98% # attempts to use FU when none available 537system.cpu.iq.fu_full::IntMult 2401 0.00% 40.99% # attempts to use FU when none available 538system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available 539system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available 540system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available 541system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available 542system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available 543system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available 544system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available 545system.cpu.iq.fu_full::FloatMisc 0 0.00% 40.99% # attempts to use FU when none available 546system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 547system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available 548system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available 549system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available 550system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available 551system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available 552system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available 553system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available 554system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available 555system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available 556system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available 557system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available 558system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available 559system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available 560system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available 561system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available 562system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available 563system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available 564system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available 565system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available 566system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 567system.cpu.iq.fu_full::MemRead 191354081 47.22% 88.20% # attempts to use FU when none available 568system.cpu.iq.fu_full::MemWrite 47812478 11.80% 100.00% # attempts to use FU when none available |
| 567system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available | 569system.cpu.iq.fu_full::FloatMemRead 19 0.00% 100.00% # attempts to use FU when none available |
| 568system.cpu.iq.fu_full::FloatMemWrite 31 0.00% 100.00% # attempts to use FU when none available | 570system.cpu.iq.fu_full::FloatMemWrite 28 0.00% 100.00% # attempts to use FU when none available |
| 569system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 570system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 571system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 571system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 572system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 573system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 572system.cpu.iq.FU_type_0::IntAlu 1138255860 61.28% 61.28% # Type of FU issued 573system.cpu.iq.FU_type_0::IntMult 800923 0.04% 61.32% # Type of FU issued | 574system.cpu.iq.FU_type_0::IntAlu 1138249696 61.28% 61.28% # Type of FU issued 575system.cpu.iq.FU_type_0::IntMult 803001 0.04% 61.32% # Type of FU issued |
| 574system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 575system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued 576system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 577system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 578system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 579system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.32% # Type of FU issued 580system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 581system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.32% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 589system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 590system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 591system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 592system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 593system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 594system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 595system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 596system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued | 576system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 577system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued 578system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 579system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 580system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 581system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 61.32% # Type of FU issued 582system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 583system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 61.32% # Type of FU issued --- 7 unchanged lines hidden (view full) --- 591system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 592system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 593system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 594system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 595system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 596system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 597system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 598system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued |
| 597system.cpu.iq.FU_type_0::SimdFloatCvt 30 0.00% 61.32% # Type of FU issued | 599system.cpu.iq.FU_type_0::SimdFloatCvt 34 0.00% 61.32% # Type of FU issued |
| 598system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued 599system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued 600system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued 601system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 602system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued | 600system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued 601system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued 602system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued 603system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 604system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued |
| 603system.cpu.iq.FU_type_0::MemRead 532128426 28.65% 89.97% # Type of FU issued 604system.cpu.iq.FU_type_0::MemWrite 186317966 10.03% 100.00% # Type of FU issued 605system.cpu.iq.FU_type_0::FloatMemRead 33 0.00% 100.00% # Type of FU issued | 605system.cpu.iq.FU_type_0::MemRead 532063614 28.65% 89.97% # Type of FU issued 606system.cpu.iq.FU_type_0::MemWrite 186291823 10.03% 100.00% # Type of FU issued 607system.cpu.iq.FU_type_0::FloatMemRead 37 0.00% 100.00% # Type of FU issued |
| 606system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued 607system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 608system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 608system.cpu.iq.FU_type_0::FloatMemWrite 24 0.00% 100.00% # Type of FU issued 609system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 610system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 609system.cpu.iq.FU_type_0::total 1857503284 # Type of FU issued 610system.cpu.iq.rate 1.179307 # Inst issue rate 611system.cpu.iq.fu_busy_cnt 405262832 # FU busy when requested 612system.cpu.iq.fu_busy_rate 0.218176 # FU busy rate (busy events/executed inst) 613system.cpu.iq.int_inst_queue_reads 5708749627 # Number of integer instruction queue reads 614system.cpu.iq.int_inst_queue_writes 2232004447 # Number of integer instruction queue writes 615system.cpu.iq.int_inst_queue_wakeup_accesses 1805721857 # Number of integer instruction queue wakeup accesses 616system.cpu.iq.fp_inst_queue_reads 262 # Number of floating instruction queue reads 617system.cpu.iq.fp_inst_queue_writes 240 # Number of floating instruction queue writes 618system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses 619system.cpu.iq.int_alu_accesses 2262765960 # Number of integer alu accesses 620system.cpu.iq.fp_alu_accesses 156 # Number of floating point alu accesses 621system.cpu.iew.lsq.thread0.forwLoads 17817152 # Number of loads that had data forwarded from stores | 611system.cpu.iq.FU_type_0::total 1857408251 # Type of FU issued 612system.cpu.iq.rate 1.178804 # Inst issue rate 613system.cpu.iq.fu_busy_cnt 405265784 # FU busy when requested 614system.cpu.iq.fu_busy_rate 0.218189 # FU busy rate (busy events/executed inst) 615system.cpu.iq.int_inst_queue_reads 5709173052 # Number of integer instruction queue reads 616system.cpu.iq.int_inst_queue_writes 2231756417 # Number of integer instruction queue writes 617system.cpu.iq.int_inst_queue_wakeup_accesses 1805664221 # Number of integer instruction queue wakeup accesses 618system.cpu.iq.fp_inst_queue_reads 275 # Number of floating instruction queue reads 619system.cpu.iq.fp_inst_queue_writes 288 # Number of floating instruction queue writes 620system.cpu.iq.fp_inst_queue_wakeup_accesses 75 # Number of floating instruction queue wakeup accesses 621system.cpu.iq.int_alu_accesses 2262673874 # Number of integer alu accesses 622system.cpu.iq.fp_alu_accesses 161 # Number of floating point alu accesses 623system.cpu.iew.lsq.thread0.forwLoads 17815816 # Number of loads that had data forwarded from stores |
| 622system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 624system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 623system.cpu.iew.lsq.thread0.squashedLoads 84273737 # Number of loads squashed 624system.cpu.iew.lsq.thread0.ignoredResponses 66671 # Number of memory responses ignored because the instruction is squashed 625system.cpu.iew.lsq.thread0.memOrderViolation 13339 # Number of memory ordering violations 626system.cpu.iew.lsq.thread0.squashedStores 24459765 # Number of stores squashed | 625system.cpu.iew.lsq.thread0.squashedLoads 84170904 # Number of loads squashed 626system.cpu.iew.lsq.thread0.ignoredResponses 66799 # Number of memory responses ignored because the instruction is squashed 627system.cpu.iew.lsq.thread0.memOrderViolation 13274 # Number of memory ordering violations 628system.cpu.iew.lsq.thread0.squashedStores 24420969 # Number of stores squashed |
| 627system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 628system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 629system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 630system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 629system.cpu.iew.lsq.thread0.rescheduledLoads 4534666 # Number of loads that were rescheduled 630system.cpu.iew.lsq.thread0.cacheBlocked 4848313 # Number of times an access to memory failed due to the cache being blocked | 631system.cpu.iew.lsq.thread0.rescheduledLoads 4535474 # Number of loads that were rescheduled 632system.cpu.iew.lsq.thread0.cacheBlocked 4852528 # Number of times an access to memory failed due to the cache being blocked |
| 631system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 633system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 632system.cpu.iew.iewSquashCycles 14643721 # Number of cycles IEW is squashing 633system.cpu.iew.iewBlockCycles 25440287 # Number of cycles IEW is blocking 634system.cpu.iew.iewUnblockCycles 1476217 # Number of cycles IEW is unblocking 635system.cpu.iew.iewDispatchedInsts 1948012141 # Number of instructions dispatched to IQ | 634system.cpu.iew.iewSquashCycles 14650540 # Number of cycles IEW is squashing 635system.cpu.iew.iewBlockCycles 25426885 # Number of cycles IEW is blocking 636system.cpu.iew.iewUnblockCycles 1470128 # Number of cycles IEW is unblocking 637system.cpu.iew.iewDispatchedInsts 1947888203 # Number of instructions dispatched to IQ |
| 636system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 638system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 637system.cpu.iew.iewDispLoadInsts 542580071 # Number of dispatched load instructions 638system.cpu.iew.iewDispStoreInsts 199306810 # Number of dispatched store instructions 639system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions 640system.cpu.iew.iewIQFullEvents 159536 # Number of times the IQ has become full, causing a stall 641system.cpu.iew.iewLSQFullEvents 1315183 # Number of times the LSQ has become full, causing a stall 642system.cpu.iew.memOrderViolationEvents 13339 # Number of memory order violations 643system.cpu.iew.predictedTakenIncorrect 7701795 # Number of branches that were predicted taken incorrectly 644system.cpu.iew.predictedNotTakenIncorrect 8704622 # Number of branches that were predicted not taken incorrectly 645system.cpu.iew.branchMispredicts 16406417 # Number of branch mispredicts detected at execute 646system.cpu.iew.iewExecutedInsts 1827836046 # Number of executed instructions 647system.cpu.iew.iewExecLoadInsts 516947496 # Number of load instructions executed 648system.cpu.iew.iewExecSquashedInsts 29667238 # Number of squashed instructions skipped in execute | 639system.cpu.iew.iewDispLoadInsts 542477238 # Number of dispatched load instructions 640system.cpu.iew.iewDispStoreInsts 199268014 # Number of dispatched store instructions 641system.cpu.iew.iewDispNonSpecInsts 167 # Number of dispatched non-speculative instructions 642system.cpu.iew.iewIQFullEvents 159099 # Number of times the IQ has become full, causing a stall 643system.cpu.iew.iewLSQFullEvents 1309527 # Number of times the LSQ has become full, causing a stall 644system.cpu.iew.memOrderViolationEvents 13274 # Number of memory order violations 645system.cpu.iew.predictedTakenIncorrect 7696809 # Number of branches that were predicted taken incorrectly 646system.cpu.iew.predictedNotTakenIncorrect 8718333 # Number of branches that were predicted not taken incorrectly 647system.cpu.iew.branchMispredicts 16415142 # Number of branch mispredicts detected at execute 648system.cpu.iew.iewExecutedInsts 1827780120 # Number of executed instructions 649system.cpu.iew.iewExecLoadInsts 516898840 # Number of load instructions executed 650system.cpu.iew.iewExecSquashedInsts 29628131 # Number of squashed instructions skipped in execute |
| 649system.cpu.iew.exec_swp 0 # number of swp insts executed 650system.cpu.iew.exec_nop 146 # number of nop insts executed | 651system.cpu.iew.exec_swp 0 # number of swp insts executed 652system.cpu.iew.exec_nop 146 # number of nop insts executed |
| 651system.cpu.iew.exec_refs 698700973 # number of memory reference insts executed 652system.cpu.iew.exec_branches 229547821 # Number of branches executed 653system.cpu.iew.exec_stores 181753477 # Number of stores executed 654system.cpu.iew.exec_rate 1.160472 # Inst execution rate 655system.cpu.iew.wb_sent 1808752239 # cumulative count of insts sent to commit 656system.cpu.iew.wb_count 1805721927 # cumulative count of insts written-back 657system.cpu.iew.wb_producers 1169243033 # num instructions producing a value 658system.cpu.iew.wb_consumers 1689661119 # num instructions consuming a value 659system.cpu.iew.wb_rate 1.146432 # insts written-back per cycle 660system.cpu.iew.wb_fanout 0.691999 # average fanout of values written-back 661system.cpu.commit.commitSquashedInsts 258080144 # The number of squashed insts skipped by commit | 653system.cpu.iew.exec_refs 698650840 # number of memory reference insts executed 654system.cpu.iew.exec_branches 229565077 # Number of branches executed 655system.cpu.iew.exec_stores 181752000 # Number of stores executed 656system.cpu.iew.exec_rate 1.160000 # Inst execution rate 657system.cpu.iew.wb_sent 1808693799 # cumulative count of insts sent to commit 658system.cpu.iew.wb_count 1805664296 # cumulative count of insts written-back 659system.cpu.iew.wb_producers 1169145221 # num instructions producing a value 660system.cpu.iew.wb_consumers 1689395973 # num instructions consuming a value 661system.cpu.iew.wb_rate 1.145965 # insts written-back per cycle 662system.cpu.iew.wb_fanout 0.692049 # average fanout of values written-back 663system.cpu.commit.commitSquashedInsts 257953466 # The number of squashed insts skipped by commit |
| 662system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards | 664system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards |
| 663system.cpu.commit.branchMispredicts 14631277 # The number of times a branch was mispredicted 664system.cpu.commit.committed_per_cycle::samples 1535484809 # Number of insts commited each cycle 665system.cpu.commit.committed_per_cycle::mean 1.083718 # Number of insts commited each cycle 666system.cpu.commit.committed_per_cycle::stdev 2.009601 # Number of insts commited each cycle | 665system.cpu.commit.branchMispredicts 14638116 # The number of times a branch was mispredicted 666system.cpu.commit.committed_per_cycle::samples 1536081048 # Number of insts commited each cycle 667system.cpu.commit.committed_per_cycle::mean 1.083297 # Number of insts commited each cycle 668system.cpu.commit.committed_per_cycle::stdev 2.009309 # Number of insts commited each cycle |
| 667system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 669system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 668system.cpu.commit.committed_per_cycle::0 955186516 62.21% 62.21% # Number of insts commited each cycle 669system.cpu.commit.committed_per_cycle::1 250636789 16.32% 78.53% # Number of insts commited each cycle 670system.cpu.commit.committed_per_cycle::2 110101292 7.17% 85.70% # Number of insts commited each cycle 671system.cpu.commit.committed_per_cycle::3 55286350 3.60% 89.30% # Number of insts commited each cycle 672system.cpu.commit.committed_per_cycle::4 29268667 1.91% 91.21% # Number of insts commited each cycle 673system.cpu.commit.committed_per_cycle::5 34069623 2.22% 93.43% # Number of insts commited each cycle 674system.cpu.commit.committed_per_cycle::6 24728092 1.61% 95.04% # Number of insts commited each cycle 675system.cpu.commit.committed_per_cycle::7 18117164 1.18% 96.22% # Number of insts commited each cycle 676system.cpu.commit.committed_per_cycle::8 58090316 3.78% 100.00% # Number of insts commited each cycle | 670system.cpu.commit.committed_per_cycle::0 955788021 62.22% 62.22% # Number of insts commited each cycle 671system.cpu.commit.committed_per_cycle::1 250630730 16.32% 78.54% # Number of insts commited each cycle 672system.cpu.commit.committed_per_cycle::2 110093475 7.17% 85.71% # Number of insts commited each cycle 673system.cpu.commit.committed_per_cycle::3 55285008 3.60% 89.31% # Number of insts commited each cycle 674system.cpu.commit.committed_per_cycle::4 29278263 1.91% 91.21% # Number of insts commited each cycle 675system.cpu.commit.committed_per_cycle::5 34064309 2.22% 93.43% # Number of insts commited each cycle 676system.cpu.commit.committed_per_cycle::6 24750177 1.61% 95.04% # Number of insts commited each cycle 677system.cpu.commit.committed_per_cycle::7 18104449 1.18% 96.22% # Number of insts commited each cycle 678system.cpu.commit.committed_per_cycle::8 58086616 3.78% 100.00% # Number of insts commited each cycle |
| 677system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 678system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 679system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 679system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 680system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 681system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 680system.cpu.commit.committed_per_cycle::total 1535484809 # Number of insts commited each cycle | 682system.cpu.commit.committed_per_cycle::total 1536081048 # Number of insts commited each cycle |
| 681system.cpu.commit.committedInsts 1544563042 # Number of instructions committed 682system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed 683system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 684system.cpu.commit.refs 633153379 # Number of memory references committed 685system.cpu.commit.loads 458306334 # Number of loads committed 686system.cpu.commit.membars 62 # Number of memory barriers committed 687system.cpu.commit.branches 213462427 # Number of branches committed 688system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 722system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 723system.cpu.commit.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction 724system.cpu.commit.op_class_0::MemWrite 174847021 10.51% 100.00% # Class of committed instruction 725system.cpu.commit.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction 726system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction 727system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 728system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 729system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction | 683system.cpu.commit.committedInsts 1544563042 # Number of instructions committed 684system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed 685system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 686system.cpu.commit.refs 633153379 # Number of memory references committed 687system.cpu.commit.loads 458306334 # Number of loads committed 688system.cpu.commit.membars 62 # Number of memory barriers committed 689system.cpu.commit.branches 213462427 # Number of branches committed 690system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 724system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 725system.cpu.commit.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction 726system.cpu.commit.op_class_0::MemWrite 174847021 10.51% 100.00% # Class of committed instruction 727system.cpu.commit.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction 728system.cpu.commit.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction 729system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 730system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 731system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction |
| 730system.cpu.commit.bw_lim_events 58090316 # number cycles where commit BW limit reached 731system.cpu.rob.rob_reads 3399506472 # The number of ROB reads 732system.cpu.rob.rob_writes 3883723576 # The number of ROB writes 733system.cpu.timesIdled 829 # Number of times that the entire CPU went into an idle state and unscheduled itself 734system.cpu.idleCycles 102290 # Total number of cycles that the CPU has spent unscheduled due to idling | 732system.cpu.commit.bw_lim_events 58086616 # number cycles where commit BW limit reached 733system.cpu.rob.rob_reads 3399979733 # The number of ROB reads 734system.cpu.rob.rob_writes 3883469027 # The number of ROB writes 735system.cpu.timesIdled 836 # Number of times that the entire CPU went into an idle state and unscheduled itself 736system.cpu.idleCycles 98660 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 735system.cpu.committedInsts 1544563024 # Number of Instructions Simulated 736system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated | 737system.cpu.committedInsts 1544563024 # Number of Instructions Simulated 738system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated |
| 737system.cpu.cpi 1.019758 # CPI: Cycles Per Instruction 738system.cpu.cpi_total 1.019758 # CPI: Total CPI of All Threads 739system.cpu.ipc 0.980625 # IPC: Instructions Per Cycle 740system.cpu.ipc_total 0.980625 # IPC: Total IPC of All Threads 741system.cpu.int_regfile_reads 2175817673 # number of integer regfile reads 742system.cpu.int_regfile_writes 1261583983 # number of integer regfile writes 743system.cpu.fp_regfile_reads 40 # number of floating regfile reads 744system.cpu.fp_regfile_writes 52 # number of floating regfile writes 745system.cpu.cc_regfile_reads 6965793426 # number of cc regfile reads 746system.cpu.cc_regfile_writes 551861251 # number of cc regfile writes 747system.cpu.misc_regfile_reads 675850688 # number of misc regfile reads | 739system.cpu.cpi 1.020141 # CPI: Cycles Per Instruction 740system.cpu.cpi_total 1.020141 # CPI: Total CPI of All Threads 741system.cpu.ipc 0.980257 # IPC: Instructions Per Cycle 742system.cpu.ipc_total 0.980257 # IPC: Total IPC of All Threads 743system.cpu.int_regfile_reads 2175723378 # number of integer regfile reads 744system.cpu.int_regfile_writes 1261531313 # number of integer regfile writes 745system.cpu.fp_regfile_reads 42 # number of floating regfile reads 746system.cpu.fp_regfile_writes 57 # number of floating regfile writes 747system.cpu.cc_regfile_reads 6965468307 # number of cc regfile reads 748system.cpu.cc_regfile_writes 551796531 # number of cc regfile writes 749system.cpu.misc_regfile_reads 675796862 # number of misc regfile reads |
| 748system.cpu.misc_regfile_writes 124 # number of misc regfile writes | 750system.cpu.misc_regfile_writes 124 # number of misc regfile writes |
| 749system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 750system.cpu.dcache.tags.replacements 17003339 # number of replacements 751system.cpu.dcache.tags.tagsinuse 511.963435 # Cycle average of tags in use 752system.cpu.dcache.tags.total_refs 638067140 # Total number of references to valid blocks. 753system.cpu.dcache.tags.sampled_refs 17003851 # Sample count of references to valid blocks. 754system.cpu.dcache.tags.avg_refs 37.524861 # Average number of references to valid blocks. 755system.cpu.dcache.tags.warmup_cycle 82999500 # Cycle when the warmup percentage was hit. 756system.cpu.dcache.tags.occ_blocks::cpu.data 511.963435 # Average occupied blocks per requestor 757system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy 758system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy | 751system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 752system.cpu.dcache.tags.replacements 17001793 # number of replacements 753system.cpu.dcache.tags.tagsinuse 511.963908 # Cycle average of tags in use 754system.cpu.dcache.tags.total_refs 638014747 # Total number of references to valid blocks. 755system.cpu.dcache.tags.sampled_refs 17002305 # Sample count of references to valid blocks. 756system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. 757system.cpu.dcache.tags.warmup_cycle 81846500 # Cycle when the warmup percentage was hit. 758system.cpu.dcache.tags.occ_blocks::cpu.data 511.963908 # Average occupied blocks per requestor 759system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy 760system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy |
| 759system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 761system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 760system.cpu.dcache.tags.age_task_id_blocks_1024::0 379 # Occupied blocks per task id 761system.cpu.dcache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id | 762system.cpu.dcache.tags.age_task_id_blocks_1024::0 367 # Occupied blocks per task id 763system.cpu.dcache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id |
| 762system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 764system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 763system.cpu.dcache.tags.tag_accesses 1335713311 # Number of tag accesses 764system.cpu.dcache.tags.data_accesses 1335713311 # Number of data accesses 765system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 766system.cpu.dcache.ReadReq_hits::cpu.data 469350712 # number of ReadReq hits 767system.cpu.dcache.ReadReq_hits::total 469350712 # number of ReadReq hits 768system.cpu.dcache.WriteReq_hits::cpu.data 168716268 # number of WriteReq hits 769system.cpu.dcache.WriteReq_hits::total 168716268 # number of WriteReq hits | 765system.cpu.dcache.tags.tag_accesses 1335598455 # Number of tag accesses 766system.cpu.dcache.tags.data_accesses 1335598455 # Number of data accesses 767system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 768system.cpu.dcache.ReadReq_hits::cpu.data 469297691 # number of ReadReq hits 769system.cpu.dcache.ReadReq_hits::total 469297691 # number of ReadReq hits 770system.cpu.dcache.WriteReq_hits::cpu.data 168716899 # number of WriteReq hits 771system.cpu.dcache.WriteReq_hits::total 168716899 # number of WriteReq hits |
| 770system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 771system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 772system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 773system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits | 772system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 773system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 774system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 775system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits |
| 774system.cpu.dcache.demand_hits::cpu.data 638066980 # number of demand (read+write) hits 775system.cpu.dcache.demand_hits::total 638066980 # number of demand (read+write) hits 776system.cpu.dcache.overall_hits::cpu.data 638066980 # number of overall hits 777system.cpu.dcache.overall_hits::total 638066980 # number of overall hits 778system.cpu.dcache.ReadReq_misses::cpu.data 17417847 # number of ReadReq misses 779system.cpu.dcache.ReadReq_misses::total 17417847 # number of ReadReq misses 780system.cpu.dcache.WriteReq_misses::cpu.data 3869779 # number of WriteReq misses 781system.cpu.dcache.WriteReq_misses::total 3869779 # number of WriteReq misses | 776system.cpu.dcache.demand_hits::cpu.data 638014590 # number of demand (read+write) hits 777system.cpu.dcache.demand_hits::total 638014590 # number of demand (read+write) hits 778system.cpu.dcache.overall_hits::cpu.data 638014590 # number of overall hits 779system.cpu.dcache.overall_hits::total 638014590 # number of overall hits 780system.cpu.dcache.ReadReq_misses::cpu.data 17414213 # number of ReadReq misses 781system.cpu.dcache.ReadReq_misses::total 17414213 # number of ReadReq misses 782system.cpu.dcache.WriteReq_misses::cpu.data 3869148 # number of WriteReq misses 783system.cpu.dcache.WriteReq_misses::total 3869148 # number of WriteReq misses |
| 782system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 783system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 784system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 785system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses | 784system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 785system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 786system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 787system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses |
| 786system.cpu.dcache.demand_misses::cpu.data 21287626 # number of demand (read+write) misses 787system.cpu.dcache.demand_misses::total 21287626 # number of demand (read+write) misses 788system.cpu.dcache.overall_misses::cpu.data 21287628 # number of overall misses 789system.cpu.dcache.overall_misses::total 21287628 # number of overall misses 790system.cpu.dcache.ReadReq_miss_latency::cpu.data 440481080000 # number of ReadReq miss cycles 791system.cpu.dcache.ReadReq_miss_latency::total 440481080000 # number of ReadReq miss cycles 792system.cpu.dcache.WriteReq_miss_latency::cpu.data 157197656848 # number of WriteReq miss cycles 793system.cpu.dcache.WriteReq_miss_latency::total 157197656848 # number of WriteReq miss cycles 794system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 217500 # number of LoadLockedReq miss cycles 795system.cpu.dcache.LoadLockedReq_miss_latency::total 217500 # number of LoadLockedReq miss cycles 796system.cpu.dcache.demand_miss_latency::cpu.data 597678736848 # number of demand (read+write) miss cycles 797system.cpu.dcache.demand_miss_latency::total 597678736848 # number of demand (read+write) miss cycles 798system.cpu.dcache.overall_miss_latency::cpu.data 597678736848 # number of overall miss cycles 799system.cpu.dcache.overall_miss_latency::total 597678736848 # number of overall miss cycles 800system.cpu.dcache.ReadReq_accesses::cpu.data 486768559 # number of ReadReq accesses(hits+misses) 801system.cpu.dcache.ReadReq_accesses::total 486768559 # number of ReadReq accesses(hits+misses) | 788system.cpu.dcache.demand_misses::cpu.data 21283361 # number of demand (read+write) misses 789system.cpu.dcache.demand_misses::total 21283361 # number of demand (read+write) misses 790system.cpu.dcache.overall_misses::cpu.data 21283363 # number of overall misses 791system.cpu.dcache.overall_misses::total 21283363 # number of overall misses 792system.cpu.dcache.ReadReq_miss_latency::cpu.data 440649629000 # number of ReadReq miss cycles 793system.cpu.dcache.ReadReq_miss_latency::total 440649629000 # number of ReadReq miss cycles 794system.cpu.dcache.WriteReq_miss_latency::cpu.data 157410000348 # number of WriteReq miss cycles 795system.cpu.dcache.WriteReq_miss_latency::total 157410000348 # number of WriteReq miss cycles 796system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 389500 # number of LoadLockedReq miss cycles 797system.cpu.dcache.LoadLockedReq_miss_latency::total 389500 # number of LoadLockedReq miss cycles 798system.cpu.dcache.demand_miss_latency::cpu.data 598059629348 # number of demand (read+write) miss cycles 799system.cpu.dcache.demand_miss_latency::total 598059629348 # number of demand (read+write) miss cycles 800system.cpu.dcache.overall_miss_latency::cpu.data 598059629348 # number of overall miss cycles 801system.cpu.dcache.overall_miss_latency::total 598059629348 # number of overall miss cycles 802system.cpu.dcache.ReadReq_accesses::cpu.data 486711904 # number of ReadReq accesses(hits+misses) 803system.cpu.dcache.ReadReq_accesses::total 486711904 # number of ReadReq accesses(hits+misses) |
| 802system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 803system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 804system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) 805system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) 806system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 807system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 808system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 809system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) | 804system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 805system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 806system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) 807system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) 808system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 809system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 810system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 811system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) |
| 810system.cpu.dcache.demand_accesses::cpu.data 659354606 # number of demand (read+write) accesses 811system.cpu.dcache.demand_accesses::total 659354606 # number of demand (read+write) accesses 812system.cpu.dcache.overall_accesses::cpu.data 659354608 # number of overall (read+write) accesses 813system.cpu.dcache.overall_accesses::total 659354608 # number of overall (read+write) accesses 814system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses 815system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses 816system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022422 # miss rate for WriteReq accesses 817system.cpu.dcache.WriteReq_miss_rate::total 0.022422 # miss rate for WriteReq accesses | 812system.cpu.dcache.demand_accesses::cpu.data 659297951 # number of demand (read+write) accesses 813system.cpu.dcache.demand_accesses::total 659297951 # number of demand (read+write) accesses 814system.cpu.dcache.overall_accesses::cpu.data 659297953 # number of overall (read+write) accesses 815system.cpu.dcache.overall_accesses::total 659297953 # number of overall (read+write) accesses 816system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035779 # miss rate for ReadReq accesses 817system.cpu.dcache.ReadReq_miss_rate::total 0.035779 # miss rate for ReadReq accesses 818system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022419 # miss rate for WriteReq accesses 819system.cpu.dcache.WriteReq_miss_rate::total 0.022419 # miss rate for WriteReq accesses |
| 818system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 819system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 820system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses 821system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses | 820system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 821system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 822system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses 823system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses |
| 822system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses 823system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses 824system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses 825system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses 826system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25289.065864 # average ReadReq miss latency 827system.cpu.dcache.ReadReq_avg_miss_latency::total 25289.065864 # average ReadReq miss latency 828system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40621.869323 # average WriteReq miss latency 829system.cpu.dcache.WriteReq_avg_miss_latency::total 40621.869323 # average WriteReq miss latency 830system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 54375 # average LoadLockedReq miss latency 831system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 54375 # average LoadLockedReq miss latency 832system.cpu.dcache.demand_avg_miss_latency::cpu.data 28076.345237 # average overall miss latency 833system.cpu.dcache.demand_avg_miss_latency::total 28076.345237 # average overall miss latency 834system.cpu.dcache.overall_avg_miss_latency::cpu.data 28076.342599 # average overall miss latency 835system.cpu.dcache.overall_avg_miss_latency::total 28076.342599 # average overall miss latency 836system.cpu.dcache.blocked_cycles::no_mshrs 21218402 # number of cycles access was blocked 837system.cpu.dcache.blocked_cycles::no_targets 3791861 # number of cycles access was blocked 838system.cpu.dcache.blocked::no_mshrs 939506 # number of cycles access was blocked 839system.cpu.dcache.blocked::no_targets 67507 # number of cycles access was blocked 840system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.584637 # average number of cycles each access was blocked 841system.cpu.dcache.avg_blocked_cycles::no_targets 56.169893 # average number of cycles each access was blocked 842system.cpu.dcache.writebacks::writebacks 17003339 # number of writebacks 843system.cpu.dcache.writebacks::total 17003339 # number of writebacks 844system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151564 # number of ReadReq MSHR hits 845system.cpu.dcache.ReadReq_mshr_hits::total 3151564 # number of ReadReq MSHR hits 846system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132202 # number of WriteReq MSHR hits 847system.cpu.dcache.WriteReq_mshr_hits::total 1132202 # number of WriteReq MSHR hits | 824system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses 825system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses 826system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses 827system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses 828system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25304.022008 # average ReadReq miss latency 829system.cpu.dcache.ReadReq_avg_miss_latency::total 25304.022008 # average ReadReq miss latency 830system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40683.375345 # average WriteReq miss latency 831system.cpu.dcache.WriteReq_avg_miss_latency::total 40683.375345 # average WriteReq miss latency 832system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 97375 # average LoadLockedReq miss latency 833system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 97375 # average LoadLockedReq miss latency 834system.cpu.dcache.demand_avg_miss_latency::cpu.data 28099.867749 # average overall miss latency 835system.cpu.dcache.demand_avg_miss_latency::total 28099.867749 # average overall miss latency 836system.cpu.dcache.overall_avg_miss_latency::cpu.data 28099.865108 # average overall miss latency 837system.cpu.dcache.overall_avg_miss_latency::total 28099.865108 # average overall miss latency 838system.cpu.dcache.blocked_cycles::no_mshrs 21246265 # number of cycles access was blocked 839system.cpu.dcache.blocked_cycles::no_targets 3823077 # number of cycles access was blocked 840system.cpu.dcache.blocked::no_mshrs 940794 # number of cycles access was blocked 841system.cpu.dcache.blocked::no_targets 67416 # number of cycles access was blocked 842system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.583334 # average number of cycles each access was blocked 843system.cpu.dcache.avg_blocked_cycles::no_targets 56.708749 # average number of cycles each access was blocked 844system.cpu.dcache.writebacks::writebacks 17001793 # number of writebacks 845system.cpu.dcache.writebacks::total 17001793 # number of writebacks 846system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3149457 # number of ReadReq MSHR hits 847system.cpu.dcache.ReadReq_mshr_hits::total 3149457 # number of ReadReq MSHR hits 848system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1131591 # number of WriteReq MSHR hits 849system.cpu.dcache.WriteReq_mshr_hits::total 1131591 # number of WriteReq MSHR hits |
| 848system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 849system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits | 850system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 851system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits |
| 850system.cpu.dcache.demand_mshr_hits::cpu.data 4283766 # number of demand (read+write) MSHR hits 851system.cpu.dcache.demand_mshr_hits::total 4283766 # number of demand (read+write) MSHR hits 852system.cpu.dcache.overall_mshr_hits::cpu.data 4283766 # number of overall MSHR hits 853system.cpu.dcache.overall_mshr_hits::total 4283766 # number of overall MSHR hits 854system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266283 # number of ReadReq MSHR misses 855system.cpu.dcache.ReadReq_mshr_misses::total 14266283 # number of ReadReq MSHR misses 856system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737577 # number of WriteReq MSHR misses 857system.cpu.dcache.WriteReq_mshr_misses::total 2737577 # number of WriteReq MSHR misses | 852system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits 853system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits 854system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits 855system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits 856system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14264756 # number of ReadReq MSHR misses 857system.cpu.dcache.ReadReq_mshr_misses::total 14264756 # number of ReadReq MSHR misses 858system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737557 # number of WriteReq MSHR misses 859system.cpu.dcache.WriteReq_mshr_misses::total 2737557 # number of WriteReq MSHR misses |
| 858system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 859system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses | 860system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 861system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses |
| 860system.cpu.dcache.demand_mshr_misses::cpu.data 17003860 # number of demand (read+write) MSHR misses 861system.cpu.dcache.demand_mshr_misses::total 17003860 # number of demand (read+write) MSHR misses 862system.cpu.dcache.overall_mshr_misses::cpu.data 17003861 # number of overall MSHR misses 863system.cpu.dcache.overall_mshr_misses::total 17003861 # number of overall MSHR misses 864system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354100253000 # number of ReadReq MSHR miss cycles 865system.cpu.dcache.ReadReq_mshr_miss_latency::total 354100253000 # number of ReadReq MSHR miss cycles 866system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121015069211 # number of WriteReq MSHR miss cycles 867system.cpu.dcache.WriteReq_mshr_miss_latency::total 121015069211 # number of WriteReq MSHR miss cycles | 862system.cpu.dcache.demand_mshr_misses::cpu.data 17002313 # number of demand (read+write) MSHR misses 863system.cpu.dcache.demand_mshr_misses::total 17002313 # number of demand (read+write) MSHR misses 864system.cpu.dcache.overall_mshr_misses::cpu.data 17002314 # number of overall MSHR misses 865system.cpu.dcache.overall_mshr_misses::total 17002314 # number of overall MSHR misses 866system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354315671500 # number of ReadReq MSHR miss cycles 867system.cpu.dcache.ReadReq_mshr_miss_latency::total 354315671500 # number of ReadReq MSHR miss cycles 868system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121139018143 # number of WriteReq MSHR miss cycles 869system.cpu.dcache.WriteReq_mshr_miss_latency::total 121139018143 # number of WriteReq MSHR miss cycles |
| 868system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles 869system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles | 870system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles 871system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles |
| 870system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475115322211 # number of demand (read+write) MSHR miss cycles 871system.cpu.dcache.demand_mshr_miss_latency::total 475115322211 # number of demand (read+write) MSHR miss cycles 872system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475115397211 # number of overall MSHR miss cycles 873system.cpu.dcache.overall_mshr_miss_latency::total 475115397211 # number of overall MSHR miss cycles | 872system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475454689643 # number of demand (read+write) MSHR miss cycles 873system.cpu.dcache.demand_mshr_miss_latency::total 475454689643 # number of demand (read+write) MSHR miss cycles 874system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475454764643 # number of overall MSHR miss cycles 875system.cpu.dcache.overall_mshr_miss_latency::total 475454764643 # number of overall MSHR miss cycles |
| 874system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses 875system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses 876system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses 877system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses 878system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses 879system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses 880system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses 881system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses 882system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses 883system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses | 876system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses 877system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses 878system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses 879system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses 880system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses 881system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses 882system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses 883system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses 884system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses 885system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses |
| 884system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24820.778685 # average ReadReq mshr miss latency 885system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24820.778685 # average ReadReq mshr miss latency 886system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44205.174580 # average WriteReq mshr miss latency 887system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44205.174580 # average WriteReq mshr miss latency | 886system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24838.537126 # average ReadReq mshr miss latency 887system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24838.537126 # average ReadReq mshr miss latency 888system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44250.774739 # average WriteReq mshr miss latency 889system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44250.774739 # average WriteReq mshr miss latency |
| 888system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency 889system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency | 890system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency 891system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency |
| 890system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27941.615740 # average overall mshr miss latency 891system.cpu.dcache.demand_avg_mshr_miss_latency::total 27941.615740 # average overall mshr miss latency 892system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27941.618507 # average overall mshr miss latency 893system.cpu.dcache.overall_avg_mshr_miss_latency::total 27941.618507 # average overall mshr miss latency 894system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 895system.cpu.icache.tags.replacements 587 # number of replacements 896system.cpu.icache.tags.tagsinuse 445.528749 # Cycle average of tags in use 897system.cpu.icache.tags.total_refs 656980742 # Total number of references to valid blocks. 898system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. 899system.cpu.icache.tags.avg_refs 611713.912477 # Average number of references to valid blocks. | 892system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27964.118155 # average overall mshr miss latency 893system.cpu.dcache.demand_avg_mshr_miss_latency::total 27964.118155 # average overall mshr miss latency 894system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27964.120922 # average overall mshr miss latency 895system.cpu.dcache.overall_avg_mshr_miss_latency::total 27964.120922 # average overall mshr miss latency 896system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 897system.cpu.icache.tags.replacements 591 # number of replacements 898system.cpu.icache.tags.tagsinuse 443.744305 # Cycle average of tags in use 899system.cpu.icache.tags.total_refs 656904625 # Total number of references to valid blocks. 900system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. 901system.cpu.icache.tags.avg_refs 611074.069767 # Average number of references to valid blocks. |
| 900system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 902system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 901system.cpu.icache.tags.occ_blocks::cpu.inst 445.528749 # Average occupied blocks per requestor 902system.cpu.icache.tags.occ_percent::cpu.inst 0.870173 # Average percentage of cache occupancy 903system.cpu.icache.tags.occ_percent::total 0.870173 # Average percentage of cache occupancy 904system.cpu.icache.tags.occ_task_id_blocks::1024 487 # Occupied blocks per task id 905system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id | 903system.cpu.icache.tags.occ_blocks::cpu.inst 443.744305 # Average occupied blocks per requestor 904system.cpu.icache.tags.occ_percent::cpu.inst 0.866688 # Average percentage of cache occupancy 905system.cpu.icache.tags.occ_percent::total 0.866688 # Average percentage of cache occupancy 906system.cpu.icache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id 907system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id |
| 906system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id | 908system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id |
| 907system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id 908system.cpu.icache.tags.occ_task_id_percent::1024 0.951172 # Percentage of cache occupancy per task id 909system.cpu.icache.tags.tag_accesses 1313965738 # Number of tag accesses 910system.cpu.icache.tags.data_accesses 1313965738 # Number of data accesses 911system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 912system.cpu.icache.ReadReq_hits::cpu.inst 656980742 # number of ReadReq hits 913system.cpu.icache.ReadReq_hits::total 656980742 # number of ReadReq hits 914system.cpu.icache.demand_hits::cpu.inst 656980742 # number of demand (read+write) hits 915system.cpu.icache.demand_hits::total 656980742 # number of demand (read+write) hits 916system.cpu.icache.overall_hits::cpu.inst 656980742 # number of overall hits 917system.cpu.icache.overall_hits::total 656980742 # number of overall hits 918system.cpu.icache.ReadReq_misses::cpu.inst 1590 # number of ReadReq misses 919system.cpu.icache.ReadReq_misses::total 1590 # number of ReadReq misses 920system.cpu.icache.demand_misses::cpu.inst 1590 # number of demand (read+write) misses 921system.cpu.icache.demand_misses::total 1590 # number of demand (read+write) misses 922system.cpu.icache.overall_misses::cpu.inst 1590 # number of overall misses 923system.cpu.icache.overall_misses::total 1590 # number of overall misses 924system.cpu.icache.ReadReq_miss_latency::cpu.inst 127348986 # number of ReadReq miss cycles 925system.cpu.icache.ReadReq_miss_latency::total 127348986 # number of ReadReq miss cycles 926system.cpu.icache.demand_miss_latency::cpu.inst 127348986 # number of demand (read+write) miss cycles 927system.cpu.icache.demand_miss_latency::total 127348986 # number of demand (read+write) miss cycles 928system.cpu.icache.overall_miss_latency::cpu.inst 127348986 # number of overall miss cycles 929system.cpu.icache.overall_miss_latency::total 127348986 # number of overall miss cycles 930system.cpu.icache.ReadReq_accesses::cpu.inst 656982332 # number of ReadReq accesses(hits+misses) 931system.cpu.icache.ReadReq_accesses::total 656982332 # number of ReadReq accesses(hits+misses) 932system.cpu.icache.demand_accesses::cpu.inst 656982332 # number of demand (read+write) accesses 933system.cpu.icache.demand_accesses::total 656982332 # number of demand (read+write) accesses 934system.cpu.icache.overall_accesses::cpu.inst 656982332 # number of overall (read+write) accesses 935system.cpu.icache.overall_accesses::total 656982332 # number of overall (read+write) accesses | 909system.cpu.icache.tags.age_task_id_blocks_1024::4 438 # Occupied blocks per task id 910system.cpu.icache.tags.occ_task_id_percent::1024 0.945312 # Percentage of cache occupancy per task id 911system.cpu.icache.tags.tag_accesses 1313813517 # Number of tag accesses 912system.cpu.icache.tags.data_accesses 1313813517 # Number of data accesses 913system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 914system.cpu.icache.ReadReq_hits::cpu.inst 656904625 # number of ReadReq hits 915system.cpu.icache.ReadReq_hits::total 656904625 # number of ReadReq hits 916system.cpu.icache.demand_hits::cpu.inst 656904625 # number of demand (read+write) hits 917system.cpu.icache.demand_hits::total 656904625 # number of demand (read+write) hits 918system.cpu.icache.overall_hits::cpu.inst 656904625 # number of overall hits 919system.cpu.icache.overall_hits::total 656904625 # number of overall hits 920system.cpu.icache.ReadReq_misses::cpu.inst 1596 # number of ReadReq misses 921system.cpu.icache.ReadReq_misses::total 1596 # number of ReadReq misses 922system.cpu.icache.demand_misses::cpu.inst 1596 # number of demand (read+write) misses 923system.cpu.icache.demand_misses::total 1596 # number of demand (read+write) misses 924system.cpu.icache.overall_misses::cpu.inst 1596 # number of overall misses 925system.cpu.icache.overall_misses::total 1596 # number of overall misses 926system.cpu.icache.ReadReq_miss_latency::cpu.inst 121940986 # number of ReadReq miss cycles 927system.cpu.icache.ReadReq_miss_latency::total 121940986 # number of ReadReq miss cycles 928system.cpu.icache.demand_miss_latency::cpu.inst 121940986 # number of demand (read+write) miss cycles 929system.cpu.icache.demand_miss_latency::total 121940986 # number of demand (read+write) miss cycles 930system.cpu.icache.overall_miss_latency::cpu.inst 121940986 # number of overall miss cycles 931system.cpu.icache.overall_miss_latency::total 121940986 # number of overall miss cycles 932system.cpu.icache.ReadReq_accesses::cpu.inst 656906221 # number of ReadReq accesses(hits+misses) 933system.cpu.icache.ReadReq_accesses::total 656906221 # number of ReadReq accesses(hits+misses) 934system.cpu.icache.demand_accesses::cpu.inst 656906221 # number of demand (read+write) accesses 935system.cpu.icache.demand_accesses::total 656906221 # number of demand (read+write) accesses 936system.cpu.icache.overall_accesses::cpu.inst 656906221 # number of overall (read+write) accesses 937system.cpu.icache.overall_accesses::total 656906221 # number of overall (read+write) accesses |
| 936system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 937system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 938system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 939system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 940system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 941system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses | 938system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 939system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 940system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 941system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 942system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 943system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses |
| 942system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 80093.701887 # average ReadReq miss latency 943system.cpu.icache.ReadReq_avg_miss_latency::total 80093.701887 # average ReadReq miss latency 944system.cpu.icache.demand_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency 945system.cpu.icache.demand_avg_miss_latency::total 80093.701887 # average overall miss latency 946system.cpu.icache.overall_avg_miss_latency::cpu.inst 80093.701887 # average overall miss latency 947system.cpu.icache.overall_avg_miss_latency::total 80093.701887 # average overall miss latency 948system.cpu.icache.blocked_cycles::no_mshrs 20708 # number of cycles access was blocked 949system.cpu.icache.blocked_cycles::no_targets 276 # number of cycles access was blocked | 944system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76404.126566 # average ReadReq miss latency 945system.cpu.icache.ReadReq_avg_miss_latency::total 76404.126566 # average ReadReq miss latency 946system.cpu.icache.demand_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency 947system.cpu.icache.demand_avg_miss_latency::total 76404.126566 # average overall miss latency 948system.cpu.icache.overall_avg_miss_latency::cpu.inst 76404.126566 # average overall miss latency 949system.cpu.icache.overall_avg_miss_latency::total 76404.126566 # average overall miss latency 950system.cpu.icache.blocked_cycles::no_mshrs 19802 # number of cycles access was blocked 951system.cpu.icache.blocked_cycles::no_targets 336 # number of cycles access was blocked |
| 950system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked | 952system.cpu.icache.blocked::no_mshrs 187 # number of cycles access was blocked |
| 951system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked 952system.cpu.icache.avg_blocked_cycles::no_mshrs 110.737968 # average number of cycles each access was blocked 953system.cpu.icache.avg_blocked_cycles::no_targets 30.666667 # average number of cycles each access was blocked 954system.cpu.icache.writebacks::writebacks 587 # number of writebacks 955system.cpu.icache.writebacks::total 587 # number of writebacks 956system.cpu.icache.ReadReq_mshr_hits::cpu.inst 515 # number of ReadReq MSHR hits 957system.cpu.icache.ReadReq_mshr_hits::total 515 # number of ReadReq MSHR hits 958system.cpu.icache.demand_mshr_hits::cpu.inst 515 # number of demand (read+write) MSHR hits 959system.cpu.icache.demand_mshr_hits::total 515 # number of demand (read+write) MSHR hits 960system.cpu.icache.overall_mshr_hits::cpu.inst 515 # number of overall MSHR hits 961system.cpu.icache.overall_mshr_hits::total 515 # number of overall MSHR hits 962system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1075 # number of ReadReq MSHR misses 963system.cpu.icache.ReadReq_mshr_misses::total 1075 # number of ReadReq MSHR misses 964system.cpu.icache.demand_mshr_misses::cpu.inst 1075 # number of demand (read+write) MSHR misses 965system.cpu.icache.demand_mshr_misses::total 1075 # number of demand (read+write) MSHR misses 966system.cpu.icache.overall_mshr_misses::cpu.inst 1075 # number of overall MSHR misses 967system.cpu.icache.overall_mshr_misses::total 1075 # number of overall MSHR misses 968system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 91881989 # number of ReadReq MSHR miss cycles 969system.cpu.icache.ReadReq_mshr_miss_latency::total 91881989 # number of ReadReq MSHR miss cycles 970system.cpu.icache.demand_mshr_miss_latency::cpu.inst 91881989 # number of demand (read+write) MSHR miss cycles 971system.cpu.icache.demand_mshr_miss_latency::total 91881989 # number of demand (read+write) MSHR miss cycles 972system.cpu.icache.overall_mshr_miss_latency::cpu.inst 91881989 # number of overall MSHR miss cycles 973system.cpu.icache.overall_mshr_miss_latency::total 91881989 # number of overall MSHR miss cycles | 953system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked 954system.cpu.icache.avg_blocked_cycles::no_mshrs 105.893048 # average number of cycles each access was blocked 955system.cpu.icache.avg_blocked_cycles::no_targets 33.600000 # average number of cycles each access was blocked 956system.cpu.icache.writebacks::writebacks 591 # number of writebacks 957system.cpu.icache.writebacks::total 591 # number of writebacks 958system.cpu.icache.ReadReq_mshr_hits::cpu.inst 520 # number of ReadReq MSHR hits 959system.cpu.icache.ReadReq_mshr_hits::total 520 # number of ReadReq MSHR hits 960system.cpu.icache.demand_mshr_hits::cpu.inst 520 # number of demand (read+write) MSHR hits 961system.cpu.icache.demand_mshr_hits::total 520 # number of demand (read+write) MSHR hits 962system.cpu.icache.overall_mshr_hits::cpu.inst 520 # number of overall MSHR hits 963system.cpu.icache.overall_mshr_hits::total 520 # number of overall MSHR hits 964system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses 965system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses 966system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses 967system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses 968system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses 969system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses 970system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 89957490 # number of ReadReq MSHR miss cycles 971system.cpu.icache.ReadReq_mshr_miss_latency::total 89957490 # number of ReadReq MSHR miss cycles 972system.cpu.icache.demand_mshr_miss_latency::cpu.inst 89957490 # number of demand (read+write) MSHR miss cycles 973system.cpu.icache.demand_mshr_miss_latency::total 89957490 # number of demand (read+write) MSHR miss cycles 974system.cpu.icache.overall_mshr_miss_latency::cpu.inst 89957490 # number of overall MSHR miss cycles 975system.cpu.icache.overall_mshr_miss_latency::total 89957490 # number of overall MSHR miss cycles |
| 974system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 975system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 976system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 977system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 978system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 979system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses | 976system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 977system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 978system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 979system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 980system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 981system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses |
| 980system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85471.617674 # average ReadReq mshr miss latency 981system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85471.617674 # average ReadReq mshr miss latency 982system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency 983system.cpu.icache.demand_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency 984system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85471.617674 # average overall mshr miss latency 985system.cpu.icache.overall_avg_mshr_miss_latency::total 85471.617674 # average overall mshr miss latency 986system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 987system.cpu.l2cache.prefetcher.num_hwpf_issued 11608007 # number of hwpf issued 988system.cpu.l2cache.prefetcher.pfIdentified 11635645 # number of prefetch candidates identified 989system.cpu.l2cache.prefetcher.pfBufferHit 18478 # number of redundant prefetches already in prefetch queue | 982system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83603.615242 # average ReadReq mshr miss latency 983system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83603.615242 # average ReadReq mshr miss latency 984system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency 985system.cpu.icache.demand_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency 986system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83603.615242 # average overall mshr miss latency 987system.cpu.icache.overall_avg_mshr_miss_latency::total 83603.615242 # average overall mshr miss latency 988system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 989system.cpu.l2cache.prefetcher.num_hwpf_issued 11616550 # number of hwpf issued 990system.cpu.l2cache.prefetcher.pfIdentified 11644306 # number of prefetch candidates identified 991system.cpu.l2cache.prefetcher.pfBufferHit 18561 # number of redundant prefetches already in prefetch queue |
| 990system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped | 992system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped |
| 991system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 992system.cpu.l2cache.prefetcher.pfSpanPage 4655443 # number of prefetches not generated due to page crossing 993system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 994system.cpu.l2cache.tags.replacements 4648753 # number of replacements 995system.cpu.l2cache.tags.tagsinuse 15870.733376 # Cycle average of tags in use 996system.cpu.l2cache.tags.total_refs 13264824 # Total number of references to valid blocks. 997system.cpu.l2cache.tags.sampled_refs 4664667 # Sample count of references to valid blocks. 998system.cpu.l2cache.tags.avg_refs 2.843681 # Average number of references to valid blocks. | 993system.cpu.l2cache.prefetcher.pfRemovedFull 1 # number of prefetches dropped due to prefetch queue size 994system.cpu.l2cache.prefetcher.pfSpanPage 4655502 # number of prefetches not generated due to page crossing 995system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 996system.cpu.l2cache.tags.replacements 4647569 # number of replacements 997system.cpu.l2cache.tags.tagsinuse 15870.791949 # Cycle average of tags in use 998system.cpu.l2cache.tags.total_refs 13265757 # Total number of references to valid blocks. 999system.cpu.l2cache.tags.sampled_refs 4663475 # Sample count of references to valid blocks. 1000system.cpu.l2cache.tags.avg_refs 2.844608 # Average number of references to valid blocks. |
| 999system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 1001system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 1000system.cpu.l2cache.tags.occ_blocks::writebacks 15649.436196 # Average occupied blocks per requestor 1001system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 221.297180 # Average occupied blocks per requestor 1002system.cpu.l2cache.tags.occ_percent::writebacks 0.955166 # Average percentage of cache occupancy 1003system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013507 # Average percentage of cache occupancy 1004system.cpu.l2cache.tags.occ_percent::total 0.968673 # Average percentage of cache occupancy 1005system.cpu.l2cache.tags.occ_task_id_blocks::1022 130 # Occupied blocks per task id 1006system.cpu.l2cache.tags.occ_task_id_blocks::1024 15784 # Occupied blocks per task id 1007system.cpu.l2cache.tags.age_task_id_blocks_1022::0 6 # Occupied blocks per task id 1008system.cpu.l2cache.tags.age_task_id_blocks_1022::1 105 # Occupied blocks per task id 1009system.cpu.l2cache.tags.age_task_id_blocks_1022::3 19 # Occupied blocks per task id 1010system.cpu.l2cache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id 1011system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4048 # Occupied blocks per task id 1012system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7174 # Occupied blocks per task id 1013system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2624 # Occupied blocks per task id 1014system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1515 # Occupied blocks per task id 1015system.cpu.l2cache.tags.occ_task_id_percent::1022 0.007935 # Percentage of cache occupancy per task id 1016system.cpu.l2cache.tags.occ_task_id_percent::1024 0.963379 # Percentage of cache occupancy per task id 1017system.cpu.l2cache.tags.tag_accesses 561782498 # Number of tag accesses 1018system.cpu.l2cache.tags.data_accesses 561782498 # Number of data accesses 1019system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 1020system.cpu.l2cache.WritebackDirty_hits::writebacks 4829115 # number of WritebackDirty hits 1021system.cpu.l2cache.WritebackDirty_hits::total 4829115 # number of WritebackDirty hits 1022system.cpu.l2cache.WritebackClean_hits::writebacks 12153582 # number of WritebackClean hits 1023system.cpu.l2cache.WritebackClean_hits::total 12153582 # number of WritebackClean hits 1024system.cpu.l2cache.ReadExReq_hits::cpu.data 1756982 # number of ReadExReq hits 1025system.cpu.l2cache.ReadExReq_hits::total 1756982 # number of ReadExReq hits 1026system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 57 # number of ReadCleanReq hits 1027system.cpu.l2cache.ReadCleanReq_hits::total 57 # number of ReadCleanReq hits 1028system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11509164 # number of ReadSharedReq hits 1029system.cpu.l2cache.ReadSharedReq_hits::total 11509164 # number of ReadSharedReq hits 1030system.cpu.l2cache.demand_hits::cpu.inst 57 # number of demand (read+write) hits 1031system.cpu.l2cache.demand_hits::cpu.data 13266146 # number of demand (read+write) hits 1032system.cpu.l2cache.demand_hits::total 13266203 # number of demand (read+write) hits 1033system.cpu.l2cache.overall_hits::cpu.inst 57 # number of overall hits 1034system.cpu.l2cache.overall_hits::cpu.data 13266146 # number of overall hits 1035system.cpu.l2cache.overall_hits::total 13266203 # number of overall hits 1036system.cpu.l2cache.UpgradeReq_misses::cpu.data 10 # number of UpgradeReq misses 1037system.cpu.l2cache.UpgradeReq_misses::total 10 # number of UpgradeReq misses 1038system.cpu.l2cache.ReadExReq_misses::cpu.data 980646 # number of ReadExReq misses 1039system.cpu.l2cache.ReadExReq_misses::total 980646 # number of ReadExReq misses 1040system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1018 # number of ReadCleanReq misses 1041system.cpu.l2cache.ReadCleanReq_misses::total 1018 # number of ReadCleanReq misses 1042system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2757059 # number of ReadSharedReq misses 1043system.cpu.l2cache.ReadSharedReq_misses::total 2757059 # number of ReadSharedReq misses 1044system.cpu.l2cache.demand_misses::cpu.inst 1018 # number of demand (read+write) misses 1045system.cpu.l2cache.demand_misses::cpu.data 3737705 # number of demand (read+write) misses 1046system.cpu.l2cache.demand_misses::total 3738723 # number of demand (read+write) misses 1047system.cpu.l2cache.overall_misses::cpu.inst 1018 # number of overall misses 1048system.cpu.l2cache.overall_misses::cpu.data 3737705 # number of overall misses 1049system.cpu.l2cache.overall_misses::total 3738723 # number of overall misses 1050system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 212000 # number of UpgradeReq miss cycles 1051system.cpu.l2cache.UpgradeReq_miss_latency::total 212000 # number of UpgradeReq miss cycles 1052system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104379369500 # number of ReadExReq miss cycles 1053system.cpu.l2cache.ReadExReq_miss_latency::total 104379369500 # number of ReadExReq miss cycles 1054system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90393500 # number of ReadCleanReq miss cycles 1055system.cpu.l2cache.ReadCleanReq_miss_latency::total 90393500 # number of ReadCleanReq miss cycles 1056system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256509677500 # number of ReadSharedReq miss cycles 1057system.cpu.l2cache.ReadSharedReq_miss_latency::total 256509677500 # number of ReadSharedReq miss cycles 1058system.cpu.l2cache.demand_miss_latency::cpu.inst 90393500 # number of demand (read+write) miss cycles 1059system.cpu.l2cache.demand_miss_latency::cpu.data 360889047000 # number of demand (read+write) miss cycles 1060system.cpu.l2cache.demand_miss_latency::total 360979440500 # number of demand (read+write) miss cycles 1061system.cpu.l2cache.overall_miss_latency::cpu.inst 90393500 # number of overall miss cycles 1062system.cpu.l2cache.overall_miss_latency::cpu.data 360889047000 # number of overall miss cycles 1063system.cpu.l2cache.overall_miss_latency::total 360979440500 # number of overall miss cycles 1064system.cpu.l2cache.WritebackDirty_accesses::writebacks 4829115 # number of WritebackDirty accesses(hits+misses) 1065system.cpu.l2cache.WritebackDirty_accesses::total 4829115 # number of WritebackDirty accesses(hits+misses) 1066system.cpu.l2cache.WritebackClean_accesses::writebacks 12153582 # number of WritebackClean accesses(hits+misses) 1067system.cpu.l2cache.WritebackClean_accesses::total 12153582 # number of WritebackClean accesses(hits+misses) 1068system.cpu.l2cache.UpgradeReq_accesses::cpu.data 10 # number of UpgradeReq accesses(hits+misses) 1069system.cpu.l2cache.UpgradeReq_accesses::total 10 # number of UpgradeReq accesses(hits+misses) 1070system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737628 # number of ReadExReq accesses(hits+misses) 1071system.cpu.l2cache.ReadExReq_accesses::total 2737628 # number of ReadExReq accesses(hits+misses) 1072system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1075 # number of ReadCleanReq accesses(hits+misses) 1073system.cpu.l2cache.ReadCleanReq_accesses::total 1075 # number of ReadCleanReq accesses(hits+misses) 1074system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266223 # number of ReadSharedReq accesses(hits+misses) 1075system.cpu.l2cache.ReadSharedReq_accesses::total 14266223 # number of ReadSharedReq accesses(hits+misses) 1076system.cpu.l2cache.demand_accesses::cpu.inst 1075 # number of demand (read+write) accesses 1077system.cpu.l2cache.demand_accesses::cpu.data 17003851 # number of demand (read+write) accesses 1078system.cpu.l2cache.demand_accesses::total 17004926 # number of demand (read+write) accesses 1079system.cpu.l2cache.overall_accesses::cpu.inst 1075 # number of overall (read+write) accesses 1080system.cpu.l2cache.overall_accesses::cpu.data 17003851 # number of overall (read+write) accesses 1081system.cpu.l2cache.overall_accesses::total 17004926 # number of overall (read+write) accesses | 1002system.cpu.l2cache.tags.occ_blocks::writebacks 15652.012265 # Average occupied blocks per requestor 1003system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 218.779684 # Average occupied blocks per requestor 1004system.cpu.l2cache.tags.occ_percent::writebacks 0.955323 # Average percentage of cache occupancy 1005system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013353 # Average percentage of cache occupancy 1006system.cpu.l2cache.tags.occ_percent::total 0.968676 # Average percentage of cache occupancy 1007system.cpu.l2cache.tags.occ_task_id_blocks::1022 135 # Occupied blocks per task id 1008system.cpu.l2cache.tags.occ_task_id_blocks::1024 15771 # Occupied blocks per task id 1009system.cpu.l2cache.tags.age_task_id_blocks_1022::0 3 # Occupied blocks per task id 1010system.cpu.l2cache.tags.age_task_id_blocks_1022::1 109 # Occupied blocks per task id 1011system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id 1012system.cpu.l2cache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id 1013system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4017 # Occupied blocks per task id 1014system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7150 # Occupied blocks per task id 1015system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2693 # Occupied blocks per task id 1016system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1496 # Occupied blocks per task id 1017system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008240 # Percentage of cache occupancy per task id 1018system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962585 # Percentage of cache occupancy per task id 1019system.cpu.l2cache.tags.tag_accesses 561731761 # Number of tag accesses 1020system.cpu.l2cache.tags.data_accesses 561731761 # Number of data accesses 1021system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 1022system.cpu.l2cache.WritebackDirty_hits::writebacks 4837264 # number of WritebackDirty hits 1023system.cpu.l2cache.WritebackDirty_hits::total 4837264 # number of WritebackDirty hits 1024system.cpu.l2cache.WritebackClean_hits::writebacks 12143869 # number of WritebackClean hits 1025system.cpu.l2cache.WritebackClean_hits::total 12143869 # number of WritebackClean hits 1026system.cpu.l2cache.ReadExReq_hits::cpu.data 1756642 # number of ReadExReq hits 1027system.cpu.l2cache.ReadExReq_hits::total 1756642 # number of ReadExReq hits 1028system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 54 # number of ReadCleanReq hits 1029system.cpu.l2cache.ReadCleanReq_hits::total 54 # number of ReadCleanReq hits 1030system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11509702 # number of ReadSharedReq hits 1031system.cpu.l2cache.ReadSharedReq_hits::total 11509702 # number of ReadSharedReq hits 1032system.cpu.l2cache.demand_hits::cpu.inst 54 # number of demand (read+write) hits 1033system.cpu.l2cache.demand_hits::cpu.data 13266344 # number of demand (read+write) hits 1034system.cpu.l2cache.demand_hits::total 13266398 # number of demand (read+write) hits 1035system.cpu.l2cache.overall_hits::cpu.inst 54 # number of overall hits 1036system.cpu.l2cache.overall_hits::cpu.data 13266344 # number of overall hits 1037system.cpu.l2cache.overall_hits::total 13266398 # number of overall hits 1038system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses 1039system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses 1040system.cpu.l2cache.ReadExReq_misses::cpu.data 980963 # number of ReadExReq misses 1041system.cpu.l2cache.ReadExReq_misses::total 980963 # number of ReadExReq misses 1042system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1022 # number of ReadCleanReq misses 1043system.cpu.l2cache.ReadCleanReq_misses::total 1022 # number of ReadCleanReq misses 1044system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2754998 # number of ReadSharedReq misses 1045system.cpu.l2cache.ReadSharedReq_misses::total 2754998 # number of ReadSharedReq misses 1046system.cpu.l2cache.demand_misses::cpu.inst 1022 # number of demand (read+write) misses 1047system.cpu.l2cache.demand_misses::cpu.data 3735961 # number of demand (read+write) misses 1048system.cpu.l2cache.demand_misses::total 3736983 # number of demand (read+write) misses 1049system.cpu.l2cache.overall_misses::cpu.inst 1022 # number of overall misses 1050system.cpu.l2cache.overall_misses::cpu.data 3735961 # number of overall misses 1051system.cpu.l2cache.overall_misses::total 3736983 # number of overall misses 1052system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 191500 # number of UpgradeReq miss cycles 1053system.cpu.l2cache.UpgradeReq_miss_latency::total 191500 # number of UpgradeReq miss cycles 1054system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104504427500 # number of ReadExReq miss cycles 1055system.cpu.l2cache.ReadExReq_miss_latency::total 104504427500 # number of ReadExReq miss cycles 1056system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 88486500 # number of ReadCleanReq miss cycles 1057system.cpu.l2cache.ReadCleanReq_miss_latency::total 88486500 # number of ReadCleanReq miss cycles 1058system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256725449000 # number of ReadSharedReq miss cycles 1059system.cpu.l2cache.ReadSharedReq_miss_latency::total 256725449000 # number of ReadSharedReq miss cycles 1060system.cpu.l2cache.demand_miss_latency::cpu.inst 88486500 # number of demand (read+write) miss cycles 1061system.cpu.l2cache.demand_miss_latency::cpu.data 361229876500 # number of demand (read+write) miss cycles 1062system.cpu.l2cache.demand_miss_latency::total 361318363000 # number of demand (read+write) miss cycles 1063system.cpu.l2cache.overall_miss_latency::cpu.inst 88486500 # number of overall miss cycles 1064system.cpu.l2cache.overall_miss_latency::cpu.data 361229876500 # number of overall miss cycles 1065system.cpu.l2cache.overall_miss_latency::total 361318363000 # number of overall miss cycles 1066system.cpu.l2cache.WritebackDirty_accesses::writebacks 4837264 # number of WritebackDirty accesses(hits+misses) 1067system.cpu.l2cache.WritebackDirty_accesses::total 4837264 # number of WritebackDirty accesses(hits+misses) 1068system.cpu.l2cache.WritebackClean_accesses::writebacks 12143869 # number of WritebackClean accesses(hits+misses) 1069system.cpu.l2cache.WritebackClean_accesses::total 12143869 # number of WritebackClean accesses(hits+misses) 1070system.cpu.l2cache.UpgradeReq_accesses::cpu.data 9 # number of UpgradeReq accesses(hits+misses) 1071system.cpu.l2cache.UpgradeReq_accesses::total 9 # number of UpgradeReq accesses(hits+misses) 1072system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737605 # number of ReadExReq accesses(hits+misses) 1073system.cpu.l2cache.ReadExReq_accesses::total 2737605 # number of ReadExReq accesses(hits+misses) 1074system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) 1075system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) 1076system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14264700 # number of ReadSharedReq accesses(hits+misses) 1077system.cpu.l2cache.ReadSharedReq_accesses::total 14264700 # number of ReadSharedReq accesses(hits+misses) 1078system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses 1079system.cpu.l2cache.demand_accesses::cpu.data 17002305 # number of demand (read+write) accesses 1080system.cpu.l2cache.demand_accesses::total 17003381 # number of demand (read+write) accesses 1081system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses 1082system.cpu.l2cache.overall_accesses::cpu.data 17002305 # number of overall (read+write) accesses 1083system.cpu.l2cache.overall_accesses::total 17003381 # number of overall (read+write) accesses |
| 1082system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1083system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 1084system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1085system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 1084system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358210 # miss rate for ReadExReq accesses 1085system.cpu.l2cache.ReadExReq_miss_rate::total 0.358210 # miss rate for ReadExReq accesses 1086system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.946977 # miss rate for ReadCleanReq accesses 1087system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.946977 # miss rate for ReadCleanReq accesses 1088system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193258 # miss rate for ReadSharedReq accesses 1089system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193258 # miss rate for ReadSharedReq accesses 1090system.cpu.l2cache.demand_miss_rate::cpu.inst 0.946977 # miss rate for demand accesses 1091system.cpu.l2cache.demand_miss_rate::cpu.data 0.219815 # miss rate for demand accesses 1092system.cpu.l2cache.demand_miss_rate::total 0.219861 # miss rate for demand accesses 1093system.cpu.l2cache.overall_miss_rate::cpu.inst 0.946977 # miss rate for overall accesses 1094system.cpu.l2cache.overall_miss_rate::cpu.data 0.219815 # miss rate for overall accesses 1095system.cpu.l2cache.overall_miss_rate::total 0.219861 # miss rate for overall accesses 1096system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21200 # average UpgradeReq miss latency 1097system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21200 # average UpgradeReq miss latency 1098system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106439.397601 # average ReadExReq miss latency 1099system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106439.397601 # average ReadExReq miss latency 1100system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 88795.186640 # average ReadCleanReq miss latency 1101system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 88795.186640 # average ReadCleanReq miss latency 1102system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93037.427745 # average ReadSharedReq miss latency 1103system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93037.427745 # average ReadSharedReq miss latency 1104system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 88795.186640 # average overall miss latency 1105system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96553.646422 # average overall miss latency 1106system.cpu.l2cache.demand_avg_miss_latency::total 96551.533906 # average overall miss latency 1107system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 88795.186640 # average overall miss latency 1108system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96553.646422 # average overall miss latency 1109system.cpu.l2cache.overall_avg_miss_latency::total 96551.533906 # average overall miss latency 1110system.cpu.l2cache.blocked_cycles::no_mshrs 318 # number of cycles access was blocked | 1086system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358329 # miss rate for ReadExReq accesses 1087system.cpu.l2cache.ReadExReq_miss_rate::total 0.358329 # miss rate for ReadExReq accesses 1088system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.949814 # miss rate for ReadCleanReq accesses 1089system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.949814 # miss rate for ReadCleanReq accesses 1090system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193134 # miss rate for ReadSharedReq accesses 1091system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193134 # miss rate for ReadSharedReq accesses 1092system.cpu.l2cache.demand_miss_rate::cpu.inst 0.949814 # miss rate for demand accesses 1093system.cpu.l2cache.demand_miss_rate::cpu.data 0.219733 # miss rate for demand accesses 1094system.cpu.l2cache.demand_miss_rate::total 0.219779 # miss rate for demand accesses 1095system.cpu.l2cache.overall_miss_rate::cpu.inst 0.949814 # miss rate for overall accesses 1096system.cpu.l2cache.overall_miss_rate::cpu.data 0.219733 # miss rate for overall accesses 1097system.cpu.l2cache.overall_miss_rate::total 0.219779 # miss rate for overall accesses 1098system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21277.777778 # average UpgradeReq miss latency 1099system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21277.777778 # average UpgradeReq miss latency 1100system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106532.486444 # average ReadExReq miss latency 1101system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106532.486444 # average ReadExReq miss latency 1102system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 86581.702544 # average ReadCleanReq miss latency 1103system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 86581.702544 # average ReadCleanReq miss latency 1104system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93185.348592 # average ReadSharedReq miss latency 1105system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93185.348592 # average ReadSharedReq miss latency 1106system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 86581.702544 # average overall miss latency 1107system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96689.948450 # average overall miss latency 1108system.cpu.l2cache.demand_avg_miss_latency::total 96687.184020 # average overall miss latency 1109system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 86581.702544 # average overall miss latency 1110system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96689.948450 # average overall miss latency 1111system.cpu.l2cache.overall_avg_miss_latency::total 96687.184020 # average overall miss latency 1112system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 1111system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1113system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1112system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked | 1114system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 1113system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1115system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1114system.cpu.l2cache.avg_blocked_cycles::no_mshrs 159 # average number of cycles each access was blocked | 1116system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 1115system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1117system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1116system.cpu.l2cache.unused_prefetches 58324 # number of HardPF blocks evicted w/o reference 1117system.cpu.l2cache.writebacks::writebacks 1634386 # number of writebacks 1118system.cpu.l2cache.writebacks::total 1634386 # number of writebacks 1119system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3928 # number of ReadExReq MSHR hits 1120system.cpu.l2cache.ReadExReq_mshr_hits::total 3928 # number of ReadExReq MSHR hits | 1118system.cpu.l2cache.unused_prefetches 58080 # number of HardPF blocks evicted w/o reference 1119system.cpu.l2cache.writebacks::writebacks 1634268 # number of writebacks 1120system.cpu.l2cache.writebacks::total 1634268 # number of writebacks 1121system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3942 # number of ReadExReq MSHR hits 1122system.cpu.l2cache.ReadExReq_mshr_hits::total 3942 # number of ReadExReq MSHR hits |
| 1121system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1122system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits | 1123system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1124system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits |
| 1123system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45589 # number of ReadSharedReq MSHR hits 1124system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45589 # number of ReadSharedReq MSHR hits | 1125system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45595 # number of ReadSharedReq MSHR hits 1126system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45595 # number of ReadSharedReq MSHR hits |
| 1125system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits | 1127system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits |
| 1126system.cpu.l2cache.demand_mshr_hits::cpu.data 49517 # number of demand (read+write) MSHR hits 1127system.cpu.l2cache.demand_mshr_hits::total 49518 # number of demand (read+write) MSHR hits | 1128system.cpu.l2cache.demand_mshr_hits::cpu.data 49537 # number of demand (read+write) MSHR hits 1129system.cpu.l2cache.demand_mshr_hits::total 49538 # number of demand (read+write) MSHR hits |
| 1128system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits | 1130system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits |
| 1129system.cpu.l2cache.overall_mshr_hits::cpu.data 49517 # number of overall MSHR hits 1130system.cpu.l2cache.overall_mshr_hits::total 49518 # number of overall MSHR hits 1131system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1196489 # number of HardPFReq MSHR misses 1132system.cpu.l2cache.HardPFReq_mshr_misses::total 1196489 # number of HardPFReq MSHR misses 1133system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 10 # number of UpgradeReq MSHR misses 1134system.cpu.l2cache.UpgradeReq_mshr_misses::total 10 # number of UpgradeReq MSHR misses 1135system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976718 # number of ReadExReq MSHR misses 1136system.cpu.l2cache.ReadExReq_mshr_misses::total 976718 # number of ReadExReq MSHR misses 1137system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1017 # number of ReadCleanReq MSHR misses 1138system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1017 # number of ReadCleanReq MSHR misses 1139system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2711470 # number of ReadSharedReq MSHR misses 1140system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2711470 # number of ReadSharedReq MSHR misses 1141system.cpu.l2cache.demand_mshr_misses::cpu.inst 1017 # number of demand (read+write) MSHR misses 1142system.cpu.l2cache.demand_mshr_misses::cpu.data 3688188 # number of demand (read+write) MSHR misses 1143system.cpu.l2cache.demand_mshr_misses::total 3689205 # number of demand (read+write) MSHR misses 1144system.cpu.l2cache.overall_mshr_misses::cpu.inst 1017 # number of overall MSHR misses 1145system.cpu.l2cache.overall_mshr_misses::cpu.data 3688188 # number of overall MSHR misses 1146system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1196489 # number of overall MSHR misses 1147system.cpu.l2cache.overall_mshr_misses::total 4885694 # number of overall MSHR misses 1148system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84134366845 # number of HardPFReq MSHR miss cycles 1149system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84134366845 # number of HardPFReq MSHR miss cycles 1150system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 152000 # number of UpgradeReq MSHR miss cycles 1151system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 152000 # number of UpgradeReq MSHR miss cycles 1152system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98135216000 # number of ReadExReq MSHR miss cycles 1153system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98135216000 # number of ReadExReq MSHR miss cycles 1154system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 84211500 # number of ReadCleanReq MSHR miss cycles 1155system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 84211500 # number of ReadCleanReq MSHR miss cycles 1156system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237209473000 # number of ReadSharedReq MSHR miss cycles 1157system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237209473000 # number of ReadSharedReq MSHR miss cycles 1158system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 84211500 # number of demand (read+write) MSHR miss cycles 1159system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335344689000 # number of demand (read+write) MSHR miss cycles 1160system.cpu.l2cache.demand_mshr_miss_latency::total 335428900500 # number of demand (read+write) MSHR miss cycles 1161system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 84211500 # number of overall MSHR miss cycles 1162system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335344689000 # number of overall MSHR miss cycles 1163system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84134366845 # number of overall MSHR miss cycles 1164system.cpu.l2cache.overall_mshr_miss_latency::total 419563267345 # number of overall MSHR miss cycles | 1131system.cpu.l2cache.overall_mshr_hits::cpu.data 49537 # number of overall MSHR hits 1132system.cpu.l2cache.overall_mshr_hits::total 49538 # number of overall MSHR hits 1133system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1199044 # number of HardPFReq MSHR misses 1134system.cpu.l2cache.HardPFReq_mshr_misses::total 1199044 # number of HardPFReq MSHR misses 1135system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses 1136system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses 1137system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 977021 # number of ReadExReq MSHR misses 1138system.cpu.l2cache.ReadExReq_mshr_misses::total 977021 # number of ReadExReq MSHR misses 1139system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1021 # number of ReadCleanReq MSHR misses 1140system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1021 # number of ReadCleanReq MSHR misses 1141system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709403 # number of ReadSharedReq MSHR misses 1142system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709403 # number of ReadSharedReq MSHR misses 1143system.cpu.l2cache.demand_mshr_misses::cpu.inst 1021 # number of demand (read+write) MSHR misses 1144system.cpu.l2cache.demand_mshr_misses::cpu.data 3686424 # number of demand (read+write) MSHR misses 1145system.cpu.l2cache.demand_mshr_misses::total 3687445 # number of demand (read+write) MSHR misses 1146system.cpu.l2cache.overall_mshr_misses::cpu.inst 1021 # number of overall MSHR misses 1147system.cpu.l2cache.overall_mshr_misses::cpu.data 3686424 # number of overall MSHR misses 1148system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1199044 # number of overall MSHR misses 1149system.cpu.l2cache.overall_mshr_misses::total 4886489 # number of overall MSHR misses 1150system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of HardPFReq MSHR miss cycles 1151system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84363300436 # number of HardPFReq MSHR miss cycles 1152system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 137500 # number of UpgradeReq MSHR miss cycles 1153system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 137500 # number of UpgradeReq MSHR miss cycles 1154system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98257390500 # number of ReadExReq MSHR miss cycles 1155system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98257390500 # number of ReadExReq MSHR miss cycles 1156system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 82266500 # number of ReadCleanReq MSHR miss cycles 1157system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 82266500 # number of ReadCleanReq MSHR miss cycles 1158system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237433882500 # number of ReadSharedReq MSHR miss cycles 1159system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237433882500 # number of ReadSharedReq MSHR miss cycles 1160system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 82266500 # number of demand (read+write) MSHR miss cycles 1161system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335691273000 # number of demand (read+write) MSHR miss cycles 1162system.cpu.l2cache.demand_mshr_miss_latency::total 335773539500 # number of demand (read+write) MSHR miss cycles 1163system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 82266500 # number of overall MSHR miss cycles 1164system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335691273000 # number of overall MSHR miss cycles 1165system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84363300436 # number of overall MSHR miss cycles 1166system.cpu.l2cache.overall_mshr_miss_latency::total 420136839936 # number of overall MSHR miss cycles |
| 1165system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1166system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1167system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1168system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 1167system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1168system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1169system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1170system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 1169system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356775 # mshr miss rate for ReadExReq accesses 1170system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356775 # mshr miss rate for ReadExReq accesses 1171system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for ReadCleanReq accesses 1172system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.946047 # mshr miss rate for ReadCleanReq accesses 1173system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.190062 # mshr miss rate for ReadSharedReq accesses 1174system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.190062 # mshr miss rate for ReadSharedReq accesses 1175system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for demand accesses 1176system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for demand accesses 1177system.cpu.l2cache.demand_mshr_miss_rate::total 0.216949 # mshr miss rate for demand accesses 1178system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.946047 # mshr miss rate for overall accesses 1179system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216903 # mshr miss rate for overall accesses | 1171system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356889 # mshr miss rate for ReadExReq accesses 1172system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356889 # mshr miss rate for ReadExReq accesses 1173system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for ReadCleanReq accesses 1174system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.948885 # mshr miss rate for ReadCleanReq accesses 1175system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189938 # mshr miss rate for ReadSharedReq accesses 1176system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189938 # mshr miss rate for ReadSharedReq accesses 1177system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for demand accesses 1178system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for demand accesses 1179system.cpu.l2cache.demand_mshr_miss_rate::total 0.216865 # mshr miss rate for demand accesses 1180system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.948885 # mshr miss rate for overall accesses 1181system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216819 # mshr miss rate for overall accesses |
| 1180system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1182system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1181system.cpu.l2cache.overall_mshr_miss_rate::total 0.287311 # mshr miss rate for overall accesses 1182system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average HardPFReq mshr miss latency 1183system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70317.710271 # average HardPFReq mshr miss latency 1184system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15200 # average UpgradeReq mshr miss latency 1185system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15200 # average UpgradeReq mshr miss latency 1186system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100474.462434 # average ReadExReq mshr miss latency 1187system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100474.462434 # average ReadExReq mshr miss latency 1188system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82803.834808 # average ReadCleanReq mshr miss latency 1189system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82803.834808 # average ReadCleanReq mshr miss latency 1190system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87483.716582 # average ReadSharedReq mshr miss latency 1191system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87483.716582 # average ReadSharedReq mshr miss latency 1192system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency 1193system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency 1194system.cpu.l2cache.demand_avg_mshr_miss_latency::total 90921.729885 # average overall mshr miss latency 1195system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82803.834808 # average overall mshr miss latency 1196system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 90923.968355 # average overall mshr miss latency 1197system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70317.710271 # average overall mshr miss latency 1198system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85875.879117 # average overall mshr miss latency 1199system.cpu.toL2Bus.snoop_filter.tot_requests 34008864 # Total number of requests made to the snoop filter. 1200system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003947 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1201system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21229 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1202system.cpu.toL2Bus.snoop_filter.tot_snoops 200156 # Total number of snoops made to the snoop filter. 1203system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200155 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 1183system.cpu.l2cache.overall_mshr_miss_rate::total 0.287383 # mshr miss rate for overall accesses 1184system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average HardPFReq mshr miss latency 1185system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70358.802876 # average HardPFReq mshr miss latency 1186system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency 1187system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency 1188system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100568.350629 # average ReadExReq mshr miss latency 1189system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100568.350629 # average ReadExReq mshr miss latency 1190system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 80574.436827 # average ReadCleanReq mshr miss latency 1191system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 80574.436827 # average ReadCleanReq mshr miss latency 1192system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.283974 # average ReadSharedReq mshr miss latency 1193system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.283974 # average ReadSharedReq mshr miss latency 1194system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency 1195system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency 1196system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91058.589213 # average overall mshr miss latency 1197system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 80574.436827 # average overall mshr miss latency 1198system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91061.492926 # average overall mshr miss latency 1199system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70358.802876 # average overall mshr miss latency 1200system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85979.286956 # average overall mshr miss latency 1201system.cpu.toL2Bus.snoop_filter.tot_requests 34005774 # Total number of requests made to the snoop filter. 1202system.cpu.toL2Bus.snoop_filter.hit_single_requests 17002402 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1203system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21251 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1204system.cpu.toL2Bus.snoop_filter.tot_snoops 202098 # Total number of snoops made to the snoop filter. 1205system.cpu.toL2Bus.snoop_filter.hit_single_snoops 202097 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 1204system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1206system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1205system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 1206system.cpu.toL2Bus.trans_dist::ReadResp 14267297 # Transaction distribution 1207system.cpu.toL2Bus.trans_dist::WritebackDirty 6463501 # Transaction distribution 1208system.cpu.toL2Bus.trans_dist::WritebackClean 12174811 # Transaction distribution 1209system.cpu.toL2Bus.trans_dist::CleanEvict 3014367 # Transaction distribution 1210system.cpu.toL2Bus.trans_dist::HardPFReq 1493474 # Transaction distribution 1211system.cpu.toL2Bus.trans_dist::HardPFResp 16 # Transaction distribution 1212system.cpu.toL2Bus.trans_dist::UpgradeReq 10 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::UpgradeResp 10 # Transaction distribution 1214system.cpu.toL2Bus.trans_dist::ReadExReq 2737628 # Transaction distribution 1215system.cpu.toL2Bus.trans_dist::ReadExResp 2737628 # Transaction distribution 1216system.cpu.toL2Bus.trans_dist::ReadCleanReq 1075 # Transaction distribution 1217system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266223 # Transaction distribution 1218system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2736 # Packet count per connected master and slave (bytes) 1219system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011077 # Packet count per connected master and slave (bytes) 1220system.cpu.toL2Bus.pkt_count::total 51013813 # Packet count per connected master and slave (bytes) 1221system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106304 # Cumulative packet size per connected master and slave (bytes) 1222system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176461184 # Cumulative packet size per connected master and slave (bytes) 1223system.cpu.toL2Bus.pkt_size::total 2176567488 # Cumulative packet size per connected master and slave (bytes) 1224system.cpu.toL2Bus.snoops 6142243 # Total snoops (count) 1225system.cpu.toL2Bus.snoopTraffic 104601728 # Total snoop traffic (bytes) 1226system.cpu.toL2Bus.snoop_fanout::samples 23147163 # Request fanout histogram 1227system.cpu.toL2Bus.snoop_fanout::mean 0.009565 # Request fanout histogram 1228system.cpu.toL2Bus.snoop_fanout::stdev 0.097331 # Request fanout histogram | 1207system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 1208system.cpu.toL2Bus.trans_dist::ReadResp 14265775 # Transaction distribution 1209system.cpu.toL2Bus.trans_dist::WritebackDirty 6471532 # Transaction distribution 1210system.cpu.toL2Bus.trans_dist::WritebackClean 12165120 # Transaction distribution 1211system.cpu.toL2Bus.trans_dist::CleanEvict 3013301 # Transaction distribution 1212system.cpu.toL2Bus.trans_dist::HardPFReq 1495847 # Transaction distribution 1213system.cpu.toL2Bus.trans_dist::HardPFResp 14 # Transaction distribution 1214system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution 1215system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution 1216system.cpu.toL2Bus.trans_dist::ReadExReq 2737605 # Transaction distribution 1217system.cpu.toL2Bus.trans_dist::ReadExResp 2737605 # Transaction distribution 1218system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution 1219system.cpu.toL2Bus.trans_dist::ReadSharedReq 14264700 # Transaction distribution 1220system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes) 1221system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51006435 # Packet count per connected master and slave (bytes) 1222system.cpu.toL2Bus.pkt_count::total 51009177 # Packet count per connected master and slave (bytes) 1223system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106624 # Cumulative packet size per connected master and slave (bytes) 1224system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176263168 # Cumulative packet size per connected master and slave (bytes) 1225system.cpu.toL2Bus.pkt_size::total 2176369792 # Cumulative packet size per connected master and slave (bytes) 1226system.cpu.toL2Bus.snoops 6143430 # Total snoops (count) 1227system.cpu.toL2Bus.snoopTraffic 104594048 # Total snoop traffic (bytes) 1228system.cpu.toL2Bus.snoop_fanout::samples 23146806 # Request fanout histogram 1229system.cpu.toL2Bus.snoop_fanout::mean 0.009650 # Request fanout histogram 1230system.cpu.toL2Bus.snoop_fanout::stdev 0.097758 # Request fanout histogram |
| 1229system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1231system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1230system.cpu.toL2Bus.snoop_fanout::0 22925769 99.04% 99.04% # Request fanout histogram 1231system.cpu.toL2Bus.snoop_fanout::1 221393 0.96% 100.00% # Request fanout histogram | 1232system.cpu.toL2Bus.snoop_fanout::0 22923448 99.04% 99.04% # Request fanout histogram 1233system.cpu.toL2Bus.snoop_fanout::1 223357 0.96% 100.00% # Request fanout histogram |
| 1232system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1233system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1234system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1235system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1234system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram 1235system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1236system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1237system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1236system.cpu.toL2Bus.snoop_fanout::total 23147163 # Request fanout histogram 1237system.cpu.toL2Bus.reqLayer0.occupancy 34008359033 # Layer occupancy (ticks) | 1238system.cpu.toL2Bus.snoop_fanout::total 23146806 # Request fanout histogram 1239system.cpu.toL2Bus.reqLayer0.occupancy 34005271029 # Layer occupancy (ticks) |
| 1238system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) | 1240system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%) |
| 1239system.cpu.toL2Bus.snoopLayer0.occupancy 24049 # Layer occupancy (ticks) | 1241system.cpu.toL2Bus.snoopLayer0.occupancy 21045 # Layer occupancy (ticks) |
| 1240system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1242system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1241system.cpu.toL2Bus.respLayer0.occupancy 1612497 # Layer occupancy (ticks) | 1243system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) |
| 1242system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1244system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1243system.cpu.toL2Bus.respLayer1.occupancy 25505785487 # Layer occupancy (ticks) | 1245system.cpu.toL2Bus.respLayer1.occupancy 25503465992 # Layer occupancy (ticks) |
| 1244system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) | 1246system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%) |
| 1245system.membus.snoop_filter.tot_requests 9335651 # Total number of requests made to the snoop filter. 1246system.membus.snoop_filter.hit_single_requests 4669993 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 1247system.membus.snoop_filter.tot_requests 9333292 # Total number of requests made to the snoop filter. 1248system.membus.snoop_filter.hit_single_requests 4668829 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 1247system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1248system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1249system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1250system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1249system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1250system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1251system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1252system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1251system.membus.pwrStateResidencyTicks::UNDEFINED 787540181500 # Cumulative time (in ticks) in various power states 1252system.membus.trans_dist::ReadResp 3710005 # Transaction distribution 1253system.membus.trans_dist::WritebackDirty 1634386 # Transaction distribution 1254system.membus.trans_dist::CleanEvict 3014367 # Transaction distribution 1255system.membus.trans_dist::UpgradeReq 10 # Transaction distribution 1256system.membus.trans_dist::ReadExReq 976882 # Transaction distribution 1257system.membus.trans_dist::ReadExResp 976882 # Transaction distribution 1258system.membus.trans_dist::ReadSharedReq 3710006 # Transaction distribution 1259system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14022538 # Packet count per connected master and slave (bytes) 1260system.membus.pkt_count::total 14022538 # Packet count per connected master and slave (bytes) 1261system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404561472 # Cumulative packet size per connected master and slave (bytes) 1262system.membus.pkt_size::total 404561472 # Cumulative packet size per connected master and slave (bytes) | 1253system.membus.pwrStateResidencyTicks::UNDEFINED 787835965500 # Cumulative time (in ticks) in various power states 1254system.membus.trans_dist::ReadResp 3708542 # Transaction distribution 1255system.membus.trans_dist::WritebackDirty 1634268 # Transaction distribution 1256system.membus.trans_dist::CleanEvict 3013301 # Transaction distribution 1257system.membus.trans_dist::UpgradeReq 9 # Transaction distribution 1258system.membus.trans_dist::ReadExReq 977171 # Transaction distribution 1259system.membus.trans_dist::ReadExResp 977171 # Transaction distribution 1260system.membus.trans_dist::ReadSharedReq 3708543 # Transaction distribution 1261system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14019005 # Packet count per connected master and slave (bytes) 1262system.membus.pkt_count::total 14019005 # Packet count per connected master and slave (bytes) 1263system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404478784 # Cumulative packet size per connected master and slave (bytes) 1264system.membus.pkt_size::total 404478784 # Cumulative packet size per connected master and slave (bytes) |
| 1263system.membus.snoops 0 # Total snoops (count) 1264system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1265system.membus.snoops 0 # Total snoops (count) 1266system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1265system.membus.snoop_fanout::samples 4686898 # Request fanout histogram | 1267system.membus.snoop_fanout::samples 4685723 # Request fanout histogram |
| 1266system.membus.snoop_fanout::mean 0 # Request fanout histogram 1267system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1268system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1268system.membus.snoop_fanout::mean 0 # Request fanout histogram 1269system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1270system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1269system.membus.snoop_fanout::0 4686898 100.00% 100.00% # Request fanout histogram | 1271system.membus.snoop_fanout::0 4685723 100.00% 100.00% # Request fanout histogram |
| 1270system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1271system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1272system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1273system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1272system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1273system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1274system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1275system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1274system.membus.snoop_fanout::total 4686898 # Request fanout histogram 1275system.membus.reqLayer0.occupancy 17643111757 # Layer occupancy (ticks) | 1276system.membus.snoop_fanout::total 4685723 # Request fanout histogram 1277system.membus.reqLayer0.occupancy 17639856241 # Layer occupancy (ticks) |
| 1276system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) | 1278system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) |
| 1277system.membus.respLayer1.occupancy 25454576781 # Layer occupancy (ticks) | 1279system.membus.respLayer1.occupancy 25447920698 # Layer occupancy (ticks) |
| 1278system.membus.respLayer1.utilization 3.2 # Layer utilization (%) 1279 1280---------- End Simulation Statistics ---------- | 1280system.membus.respLayer1.utilization 3.2 # Layer utilization (%) 1281 1282---------- End Simulation Statistics ---------- |