| stats.txt (11589:af2f7fef4875) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.767804 # Number of seconds simulated 4sim_ticks 767803843500 # Number of ticks simulated 5final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.770752 # Number of seconds simulated 4sim_ticks 770752376500 # Number of ticks simulated 5final_tick 770752376500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 212750 # Simulator instruction rate (inst/s) 8host_op_rate 229206 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 105758139 # Simulator tick rate (ticks/s) 10host_mem_usage 308972 # Number of bytes of host memory used 11host_seconds 7260.00 # Real time elapsed on the host | 7host_inst_rate 147248 # Simulator instruction rate (inst/s) 8host_op_rate 158637 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 73478006 # Simulator tick rate (ticks/s) 10host_mem_usage 329736 # Number of bytes of host memory used 11host_seconds 10489.57 # Real time elapsed on the host |
| 12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory 20system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory 24system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 4673385 # Number of read requests accepted 45system.physmem.writeReqs 1635896 # Number of write requests accepted 46system.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue 50system.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 65664 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 236002624 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 63781504 # Number of bytes read from this memory 20system.physmem.bytes_read::total 299849792 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 65664 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 65664 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 104607936 # Number of bytes written to this memory 24system.physmem.bytes_written::total 104607936 # Number of bytes written to this memory 25system.physmem.num_reads::cpu.inst 1026 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.data 3687541 # Number of read requests responded to by this memory 27system.physmem.num_reads::cpu.l2cache.prefetcher 996586 # Number of read requests responded to by this memory 28system.physmem.num_reads::total 4685153 # Number of read requests responded to by this memory 29system.physmem.num_writes::writebacks 1634499 # Number of write requests responded to by this memory 30system.physmem.num_writes::total 1634499 # Number of write requests responded to by this memory 31system.physmem.bw_read::cpu.inst 85195 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.data 306197725 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::cpu.l2cache.prefetcher 82752264 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_read::total 389035183 # Total read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::cpu.inst 85195 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_inst_read::total 85195 # Instruction read bandwidth from this memory (bytes/s) 37system.physmem.bw_write::writebacks 135721847 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_write::total 135721847 # Write bandwidth from this memory (bytes/s) 39system.physmem.bw_total::writebacks 135721847 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.inst 85195 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.data 306197725 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::cpu.l2cache.prefetcher 82752264 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.bw_total::total 524757030 # Total bandwidth to/from this memory (bytes/s) 44system.physmem.readReqs 4685154 # Number of read requests accepted 45system.physmem.writeReqs 1634499 # Number of write requests accepted 46system.physmem.readBursts 4685154 # Number of DRAM read bursts, including those serviced by the write queue 47system.physmem.writeBursts 1634499 # Number of DRAM write bursts, including those merged in the write queue 48system.physmem.bytesReadDRAM 299347712 # Total number of bytes read from DRAM 49system.physmem.bytesReadWrQ 502144 # Total number of bytes read from write queue 50system.physmem.bytesWritten 104604544 # Total number of bytes written to DRAM 51system.physmem.bytesReadSys 299849856 # Total read bytes from the system interface side 52system.physmem.bytesWrittenSys 104607936 # Total written bytes from the system interface side 53system.physmem.servicedByWrQ 7846 # Number of DRAM read bursts serviced by the write queue |
| 54system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 54system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one 55system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 56system.physmem.perBankRdBursts::0 301126 # Per bank write bursts 57system.physmem.perBankRdBursts::1 298685 # Per bank write bursts 58system.physmem.perBankRdBursts::2 284250 # Per bank write bursts 59system.physmem.perBankRdBursts::3 287696 # Per bank write bursts 60system.physmem.perBankRdBursts::4 287908 # Per bank write bursts 61system.physmem.perBankRdBursts::5 285921 # Per bank write bursts 62system.physmem.perBankRdBursts::6 280645 # Per bank write bursts 63system.physmem.perBankRdBursts::7 277366 # Per bank write bursts 64system.physmem.perBankRdBursts::8 293768 # Per bank write bursts 65system.physmem.perBankRdBursts::9 299240 # Per bank write bursts 66system.physmem.perBankRdBursts::10 292091 # Per bank write bursts 67system.physmem.perBankRdBursts::11 297828 # Per bank write bursts 68system.physmem.perBankRdBursts::12 299005 # Per bank write bursts 69system.physmem.perBankRdBursts::13 298032 # Per bank write bursts 70system.physmem.perBankRdBursts::14 293386 # Per bank write bursts 71system.physmem.perBankRdBursts::15 288652 # Per bank write bursts 72system.physmem.perBankWrBursts::0 103980 # Per bank write bursts 73system.physmem.perBankWrBursts::1 101811 # Per bank write bursts 74system.physmem.perBankWrBursts::2 99205 # Per bank write bursts 75system.physmem.perBankWrBursts::3 99712 # Per bank write bursts 76system.physmem.perBankWrBursts::4 99000 # Per bank write bursts 77system.physmem.perBankWrBursts::5 99026 # Per bank write bursts 78system.physmem.perBankWrBursts::6 102693 # Per bank write bursts 79system.physmem.perBankWrBursts::7 104157 # Per bank write bursts 80system.physmem.perBankWrBursts::8 105172 # Per bank write bursts 81system.physmem.perBankWrBursts::9 104159 # Per bank write bursts 82system.physmem.perBankWrBursts::10 102137 # Per bank write bursts 83system.physmem.perBankWrBursts::11 102620 # Per bank write bursts 84system.physmem.perBankWrBursts::12 102863 # Per bank write bursts 85system.physmem.perBankWrBursts::13 102594 # Per bank write bursts 86system.physmem.perBankWrBursts::14 104213 # Per bank write bursts 87system.physmem.perBankWrBursts::15 102497 # Per bank write bursts | 56system.physmem.perBankRdBursts::0 301314 # Per bank write bursts 57system.physmem.perBankRdBursts::1 301808 # Per bank write bursts 58system.physmem.perBankRdBursts::2 285079 # Per bank write bursts 59system.physmem.perBankRdBursts::3 287721 # Per bank write bursts 60system.physmem.perBankRdBursts::4 288732 # Per bank write bursts 61system.physmem.perBankRdBursts::5 286480 # Per bank write bursts 62system.physmem.perBankRdBursts::6 281880 # Per bank write bursts 63system.physmem.perBankRdBursts::7 278193 # Per bank write bursts 64system.physmem.perBankRdBursts::8 293719 # Per bank write bursts 65system.physmem.perBankRdBursts::9 299847 # Per bank write bursts 66system.physmem.perBankRdBursts::10 291529 # Per bank write bursts 67system.physmem.perBankRdBursts::11 297903 # Per bank write bursts 68system.physmem.perBankRdBursts::12 299405 # Per bank write bursts 69system.physmem.perBankRdBursts::13 299387 # Per bank write bursts 70system.physmem.perBankRdBursts::14 294305 # Per bank write bursts 71system.physmem.perBankRdBursts::15 290006 # Per bank write bursts 72system.physmem.perBankWrBursts::0 103629 # Per bank write bursts 73system.physmem.perBankWrBursts::1 101748 # Per bank write bursts 74system.physmem.perBankWrBursts::2 99222 # Per bank write bursts 75system.physmem.perBankWrBursts::3 99944 # Per bank write bursts 76system.physmem.perBankWrBursts::4 98990 # Per bank write bursts 77system.physmem.perBankWrBursts::5 98822 # Per bank write bursts 78system.physmem.perBankWrBursts::6 102440 # Per bank write bursts 79system.physmem.perBankWrBursts::7 104048 # Per bank write bursts 80system.physmem.perBankWrBursts::8 105134 # Per bank write bursts 81system.physmem.perBankWrBursts::9 103994 # Per bank write bursts 82system.physmem.perBankWrBursts::10 101818 # Per bank write bursts 83system.physmem.perBankWrBursts::11 102570 # Per bank write bursts 84system.physmem.perBankWrBursts::12 102850 # Per bank write bursts 85system.physmem.perBankWrBursts::13 102376 # Per bank write bursts 86system.physmem.perBankWrBursts::14 104237 # Per bank write bursts 87system.physmem.perBankWrBursts::15 102624 # Per bank write bursts |
| 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 88system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 89system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 90system.physmem.totGap 767803802500 # Total gap between requests | 90system.physmem.totGap 770752366000 # Total gap between requests |
| 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) | 91system.physmem.readPktSize::0 0 # Read request sizes (log2) 92system.physmem.readPktSize::1 0 # Read request sizes (log2) 93system.physmem.readPktSize::2 0 # Read request sizes (log2) 94system.physmem.readPktSize::3 0 # Read request sizes (log2) 95system.physmem.readPktSize::4 0 # Read request sizes (log2) 96system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 97system.physmem.readPktSize::6 4673385 # Read request sizes (log2) | 97system.physmem.readPktSize::6 4685154 # Read request sizes (log2) |
| 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) | 98system.physmem.writePktSize::0 0 # Write request sizes (log2) 99system.physmem.writePktSize::1 0 # Write request sizes (log2) 100system.physmem.writePktSize::2 0 # Write request sizes (log2) 101system.physmem.writePktSize::3 0 # Write request sizes (log2) 102system.physmem.writePktSize::4 0 # Write request sizes (log2) 103system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 104system.physmem.writePktSize::6 1635896 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see | 104system.physmem.writePktSize::6 1634499 # Write request sizes (log2) 105system.physmem.rdQLenPdf::0 2776424 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::1 1031022 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::2 327510 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::3 229431 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::4 146630 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::5 80164 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::6 37430 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::7 23802 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::8 17710 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::9 4122 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::10 1619 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::11 771 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::13 239 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see |
| 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 121system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 152system.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see | 152system.physmem.wrQLenPdf::15 25690 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::16 28168 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::17 56471 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::18 73716 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::19 85142 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::20 93999 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::21 100116 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::22 103738 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::23 105456 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::24 106103 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::25 107040 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::26 108147 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::27 109209 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::28 110723 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::29 110766 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::30 103820 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::31 100949 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::32 100270 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::33 2888 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::35 505 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::37 109 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::38 44 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::39 28 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see |
| 182system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 182system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 200system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 201system.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes 233system.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads 252system.physmem.totQLat 128478496877 # Total ticks spent queuing 253system.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM 254system.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers 255system.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst | 201system.physmem.bytesPerActivate::samples 4255173 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::mean 94.931559 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::gmean 78.862227 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::stdev 102.833954 # Bytes accessed per row activation 205system.physmem.bytesPerActivate::0-127 3394354 79.77% 79.77% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::128-255 663703 15.60% 95.37% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::256-383 94226 2.21% 97.58% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::384-511 35436 0.83% 98.41% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::512-639 22765 0.53% 98.95% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::640-767 12171 0.29% 99.24% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::768-895 7342 0.17% 99.41% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.53% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::1024-1151 19831 0.47% 100.00% # Bytes accessed per row activation 214system.physmem.bytesPerActivate::total 4255173 # Bytes accessed per row activation 215system.physmem.rdPerTurnAround::samples 97794 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::mean 47.827914 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 99.473591 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-127 93707 95.82% 95.82% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::128-255 1671 1.71% 97.53% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::256-383 768 0.79% 98.31% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::384-511 406 0.42% 98.73% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::512-639 365 0.37% 99.10% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::640-767 337 0.34% 99.45% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::768-895 234 0.24% 99.69% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::896-1023 165 0.17% 99.86% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::1024-1151 89 0.09% 99.95% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::1152-1279 24 0.02% 99.97% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::1280-1407 12 0.01% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1664-1791 3 0.00% 99.99% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes 235system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes 236system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes 237system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes 238system.physmem.rdPerTurnAround::3968-4095 1 0.00% 100.00% # Reads before turning the bus around for writes 239system.physmem.rdPerTurnAround::total 97794 # Reads before turning the bus around for writes 240system.physmem.wrPerTurnAround::samples 97794 # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::mean 16.713152 # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::gmean 16.671812 # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::stdev 1.223073 # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::16 68724 70.27% 70.27% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::17 1896 1.94% 72.21% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::18 18671 19.09% 91.31% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::19 5634 5.76% 97.07% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::20 1729 1.77% 98.83% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::21 613 0.63% 99.46% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::22 266 0.27% 99.73% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::23 147 0.15% 99.88% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::24 67 0.07% 99.95% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::25 30 0.03% 99.98% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::26 9 0.01% 99.99% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::27 6 0.01% 100.00% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads 257system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads 258system.physmem.wrPerTurnAround::total 97794 # Writes before turning the bus around for reads 259system.physmem.totQLat 128325813562 # Total ticks spent queuing 260system.physmem.totMemAccLat 216025338562 # Total ticks spent from burst creation until serviced by the DRAM 261system.physmem.totBusLat 23386540000 # Total ticks spent in databus transfers 262system.physmem.avgQLat 27435.83 # Average queueing delay per DRAM burst |
| 256system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 263system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 257system.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst 258system.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s 259system.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s 260system.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s 261system.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s | 264system.physmem.avgMemAccLat 46185.83 # Average memory access latency per DRAM burst 265system.physmem.avgRdBW 388.38 # Average DRAM read bandwidth in MiByte/s 266system.physmem.avgWrBW 135.72 # Average achieved write bandwidth in MiByte/s 267system.physmem.avgRdBWSys 389.04 # Average system read bandwidth in MiByte/s 268system.physmem.avgWrBWSys 135.72 # Average system write bandwidth in MiByte/s |
| 262system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 269system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 263system.physmem.busUtil 4.10 # Data bus utilization in percentage 264system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads 265system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes | 270system.physmem.busUtil 4.09 # Data bus utilization in percentage 271system.physmem.busUtilRead 3.03 # Data bus utilization in percentage for reads 272system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes |
| 266system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing | 273system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing |
| 267system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing 268system.physmem.readRowHits 1710736 # Number of row buffer hits during reads 269system.physmem.writeRowHits 347188 # Number of row buffer hits during writes | 274system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing 275system.physmem.readRowHits 1715091 # Number of row buffer hits during reads 276system.physmem.writeRowHits 341475 # Number of row buffer hits during writes |
| 270system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads | 277system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads |
| 271system.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes 272system.physmem.avgGap 121694.34 # Average gap between requests 273system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined 274system.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ) 275system.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ) 276system.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ) 277system.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ) 278system.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) 279system.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ) 280system.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ) 281system.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ) 282system.physmem_0.averagePower 793.947771 # Core power per rank (mW) 283system.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states 284system.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states | 278system.physmem.writeRowHitRate 20.89 # Row buffer hit rate for writes 279system.physmem.avgGap 121961.18 # Average gap between requests 280system.physmem.pageHitRate 32.58 # Row buffer hit rate, read and write combined 281system.physmem_0.actEnergy 15989112720 # Energy for activate commands per rank (pJ) 282system.physmem_0.preEnergy 8724218250 # Energy for precharge commands per rank (pJ) 283system.physmem_0.readEnergy 18025846800 # Energy for read commands per rank (pJ) 284system.physmem_0.writeEnergy 5241069360 # Energy for write commands per rank (pJ) 285system.physmem_0.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) 286system.physmem_0.actBackEnergy 417928675995 # Energy for active background per rank (pJ) 287system.physmem_0.preBackEnergy 95843265750 # Energy for precharge background per rank (pJ) 288system.physmem_0.totalEnergy 612093526155 # Total energy per rank (pJ) 289system.physmem_0.averagePower 794.157652 # Core power per rank (mW) 290system.physmem_0.memoryStateTime::IDLE 156909498029 # Time in different power states 291system.physmem_0.memoryStateTime::REF 25736880000 # Time in different power states |
| 285system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 292system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 286system.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states | 293system.physmem_0.memoryStateTime::ACT 588099785971 # Time in different power states |
| 287system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 294system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 288system.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ) 289system.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ) 290system.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ) 291system.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ) 292system.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) 293system.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ) 294system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) 295system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) 296system.physmem_1.averagePower 794.363055 # Core power per rank (mW) 297system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states 298system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states | 295system.physmem_1.actEnergy 16179556680 # Energy for activate commands per rank (pJ) 296system.physmem_1.preEnergy 8828131125 # Energy for precharge commands per rank (pJ) 297system.physmem_1.readEnergy 18455494200 # Energy for read commands per rank (pJ) 298system.physmem_1.writeEnergy 5349602880 # Energy for write commands per rank (pJ) 299system.physmem_1.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ) 300system.physmem_1.actBackEnergy 412908393870 # Energy for active background per rank (pJ) 301system.physmem_1.preBackEnergy 100247038500 # Energy for precharge background per rank (pJ) 302system.physmem_1.totalEnergy 612309554535 # Total energy per rank (pJ) 303system.physmem_1.averagePower 794.437909 # Core power per rank (mW) 304system.physmem_1.memoryStateTime::IDLE 164276600328 # Time in different power states 305system.physmem_1.memoryStateTime::REF 25736880000 # Time in different power states |
| 299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 306system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 300system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states | 307system.physmem_1.memoryStateTime::ACT 580733308672 # Time in different power states |
| 301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 308system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 302system.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 303system.cpu.branchPred.lookups 286292198 # Number of BP lookups 304system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits | 309system.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 310system.cpu.branchPred.lookups 286275195 # Number of BP lookups 311system.cpu.branchPred.condPredicted 223398341 # Number of conditional branches predicted 312system.cpu.branchPred.condIncorrect 14628424 # Number of conditional branches incorrect 313system.cpu.branchPred.BTBLookups 157667483 # Number of BTB lookups 314system.cpu.branchPred.BTBHits 150349199 # Number of BTB hits |
| 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 315system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 309system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage 310system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. 311system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. 312system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. 313system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. 314system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. 315system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. | 316system.cpu.branchPred.BTBHitPct 95.358406 # BTB Hit Percentage 317system.cpu.branchPred.usedRAS 16643020 # Number of times the RAS was used to get a target. 318system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions. 319system.cpu.branchPred.indirectLookups 3069 # Number of indirect predictor lookups. 320system.cpu.branchPred.indirectHits 1906 # Number of indirect target hits. 321system.cpu.branchPred.indirectMisses 1163 # Number of indirect misses. 322system.cpu.branchPredindirectMispredicted 137 # Number of mispredicted indirect branches. |
| 316system.cpu_clk_domain.clock 500 # Clock period in ticks | 323system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 317system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states | 324system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states |
| 318system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 339system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 340system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 341system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 342system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 343system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 344system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 345system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 346system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 325system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 346system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 347system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states | 354system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states |
| 348system.cpu.dtb.walker.walks 0 # Table walker walks requested 349system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 352system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 353system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 354system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 355system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 369system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 370system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 371system.cpu.dtb.read_accesses 0 # DTB read accesses 372system.cpu.dtb.write_accesses 0 # DTB write accesses 373system.cpu.dtb.inst_accesses 0 # ITB inst accesses 374system.cpu.dtb.hits 0 # DTB hits 375system.cpu.dtb.misses 0 # DTB misses 376system.cpu.dtb.accesses 0 # DTB accesses | 355system.cpu.dtb.walker.walks 0 # Table walker walks requested 356system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 376system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.dtb.read_accesses 0 # DTB read accesses 379system.cpu.dtb.write_accesses 0 # DTB write accesses 380system.cpu.dtb.inst_accesses 0 # ITB inst accesses 381system.cpu.dtb.hits 0 # DTB hits 382system.cpu.dtb.misses 0 # DTB misses 383system.cpu.dtb.accesses 0 # DTB accesses |
| 377system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states | 384system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states |
| 378system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 382system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 383system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 384system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 385system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 399system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 400system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 401system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 402system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 403system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 404system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 405system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 406system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 385system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 386system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 387system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 389system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 390system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 392system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 406system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 407system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 409system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 410system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 411system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 412system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 413system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 407system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states | 414system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states |
| 408system.cpu.itb.walker.walks 0 # Table walker walks requested 409system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 410system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 411system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 412system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 413system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 414system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 415system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 430system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 431system.cpu.itb.read_accesses 0 # DTB read accesses 432system.cpu.itb.write_accesses 0 # DTB write accesses 433system.cpu.itb.inst_accesses 0 # ITB inst accesses 434system.cpu.itb.hits 0 # DTB hits 435system.cpu.itb.misses 0 # DTB misses 436system.cpu.itb.accesses 0 # DTB accesses 437system.cpu.workload.num_syscalls 46 # Number of system calls | 415system.cpu.itb.walker.walks 0 # Table walker walks requested 416system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 417system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 418system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 419system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 420system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 421system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 422system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 437system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 438system.cpu.itb.read_accesses 0 # DTB read accesses 439system.cpu.itb.write_accesses 0 # DTB write accesses 440system.cpu.itb.inst_accesses 0 # ITB inst accesses 441system.cpu.itb.hits 0 # DTB hits 442system.cpu.itb.misses 0 # DTB misses 443system.cpu.itb.accesses 0 # DTB accesses 444system.cpu.workload.num_syscalls 46 # Number of system calls |
| 438system.cpu.pwrStateResidencyTicks::ON 767803843500 # Cumulative time (in ticks) in various power states 439system.cpu.numCycles 1535607688 # number of cpu cycles simulated | 445system.cpu.pwrStateResidencyTicks::ON 770752376500 # Cumulative time (in ticks) in various power states 446system.cpu.numCycles 1541504754 # number of cpu cycles simulated |
| 440system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 441system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 447system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 448system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 442system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss 443system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed 444system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered 445system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken 446system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked 447system.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing 448system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 449system.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR 450system.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched 451system.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed 452system.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total) | 449system.cpu.fetch.icacheStallCycles 13925502 # Number of cycles fetch is stalled on an Icache miss 450system.cpu.fetch.Insts 2067484101 # Number of instructions fetch has processed 451system.cpu.fetch.Branches 286275195 # Number of branches that fetch encountered 452system.cpu.fetch.predictedBranches 166994125 # Number of branches that fetch has predicted taken 453system.cpu.fetch.Cycles 1512857238 # Number of cycles fetch has run and was not squashing or blocked 454system.cpu.fetch.SquashCycles 29281631 # Number of cycles fetch has spent squashing 455system.cpu.fetch.MiscStallCycles 279 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 456system.cpu.fetch.IcacheWaitRetryStallCycles 1018 # Number of stall cycles due to full MSHR 457system.cpu.fetch.CacheLines 656940019 # Number of cache lines fetched 458system.cpu.fetch.IcacheSquashes 946 # Number of outstanding Icache misses that were squashed 459system.cpu.fetch.rateDist::samples 1541424852 # Number of instructions fetched each cycle (Total) 460system.cpu.fetch.rateDist::mean 1.436951 # Number of instructions fetched each cycle (Total) 461system.cpu.fetch.rateDist::stdev 1.229037 # Number of instructions fetched each cycle (Total) |
| 455system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 462system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 456system.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total) 457system.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total) 458system.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total) 459system.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total) | 463system.cpu.fetch.rateDist::0 459011037 29.78% 29.78% # Number of instructions fetched each cycle (Total) 464system.cpu.fetch.rateDist::1 465435057 30.20% 59.97% # Number of instructions fetched each cycle (Total) 465system.cpu.fetch.rateDist::2 101419068 6.58% 66.55% # Number of instructions fetched each cycle (Total) 466system.cpu.fetch.rateDist::3 515559690 33.45% 100.00% # Number of instructions fetched each cycle (Total) |
| 460system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 461system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 462system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 467system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 468system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 469system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 463system.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total) 464system.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle 465system.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle 466system.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle 467system.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked 468system.cpu.decode.RunCycles 849925630 # Number of cycles decode is running 469system.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking 470system.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing 471system.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch 472system.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction 473system.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode 474system.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode 475system.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing 476system.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle 477system.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking 478system.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst 479system.cpu.rename.RunCycles 837854747 # Number of cycles rename is running 480system.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking 481system.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename 482system.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename 483system.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full 484system.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full 485system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full 486system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full 487system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed 488system.cpu.rename.RenameLookups 9128568020 # Number of register rename lookups that rename has made 489system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups 490system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups | 470system.cpu.fetch.rateDist::total 1541424852 # Number of instructions fetched each cycle (Total) 471system.cpu.fetch.branchRate 0.185712 # Number of branch fetches per cycle 472system.cpu.fetch.rate 1.341212 # Number of inst fetches per cycle 473system.cpu.decode.IdleCycles 74709451 # Number of cycles decode is idle 474system.cpu.decode.BlockedCycles 544021839 # Number of cycles decode is blocked 475system.cpu.decode.RunCycles 849845592 # Number of cycles decode is running 476system.cpu.decode.UnblockCycles 58207832 # Number of cycles decode is unblocking 477system.cpu.decode.SquashCycles 14640138 # Number of cycles decode is squashing 478system.cpu.decode.BranchResolved 42201657 # Number of times decode resolved a branch 479system.cpu.decode.BranchMispred 726 # Number of times decode detected a branch misprediction 480system.cpu.decode.DecodedInsts 2037180089 # Number of instructions handled by decode 481system.cpu.decode.SquashedInsts 52484609 # Number of squashed instructions handled by decode 482system.cpu.rename.SquashCycles 14640138 # Number of cycles rename is squashing 483system.cpu.rename.IdleCycles 139806563 # Number of cycles rename is idle 484system.cpu.rename.BlockCycles 462600801 # Number of cycles rename is blocking 485system.cpu.rename.serializeStallCycles 15884 # count of cycles rename stalled for serializing inst 486system.cpu.rename.RunCycles 837785307 # Number of cycles rename is running 487system.cpu.rename.UnblockCycles 86576159 # Number of cycles rename is unblocking 488system.cpu.rename.RenamedInsts 1976384850 # Number of instructions processed by rename 489system.cpu.rename.SquashedInsts 26739549 # Number of squashed instructions processed by rename 490system.cpu.rename.ROBFullEvents 45323653 # Number of times rename has blocked due to ROB full 491system.cpu.rename.IQFullEvents 126929 # Number of times rename has blocked due to IQ full 492system.cpu.rename.LQFullEvents 1602638 # Number of times rename has blocked due to LQ full 493system.cpu.rename.SQFullEvents 25499860 # Number of times rename has blocked due to SQ full 494system.cpu.rename.RenamedOperands 1985860548 # Number of destination operands rename has renamed 495system.cpu.rename.RenameLookups 9128169124 # Number of register rename lookups that rename has made 496system.cpu.rename.int_rename_lookups 2432875929 # Number of integer rename lookups 497system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups |
| 491system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed | 498system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed |
| 492system.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing 493system.cpu.rename.serializingInsts 174 # count of serializing insts renamed | 499system.cpu.rename.UndoneMaps 310961603 # Number of HB maps that are undone due to squashing 500system.cpu.rename.serializingInsts 175 # count of serializing insts renamed |
| 494system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed | 501system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed |
| 495system.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer 496system.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit. 497system.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit. 498system.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads. 499system.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores. 500system.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec) | 502system.cpu.rename.skidInsts 111534180 # count of insts added to the skid buffer 503system.cpu.memDep0.insertedLoads 542566077 # Number of loads inserted to the mem dependence unit. 504system.cpu.memDep0.insertedStores 199303375 # Number of stores inserted to the mem dependence unit. 505system.cpu.memDep0.conflictingLoads 26892889 # Number of conflicting loads. 506system.cpu.memDep0.conflictingStores 29237160 # Number of conflicting stores. 507system.cpu.iq.iqInstsAdded 1947969517 # Number of instructions added to the IQ (excludes non-spec) |
| 501system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ | 508system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ |
| 502system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued 503system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued 504system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling 505system.cpu.iq.iqSquashedOperandsExamined 647584065 # Number of squashed operands that are examined and possibly removed from graph | 509system.cpu.iq.iqInstsIssued 1857492369 # Number of instructions issued 510system.cpu.iq.iqSquashedInstsIssued 13496690 # Number of squashed instructions issued 511system.cpu.iq.iqSquashedInstsExamined 283937332 # Number of squashed instructions iterated over during squash; mainly for profiling 512system.cpu.iq.iqSquashedOperandsExamined 647289356 # Number of squashed operands that are examined and possibly removed from graph |
| 506system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed | 513system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed |
| 507system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle | 514system.cpu.iq.issued_per_cycle::samples 1541424852 # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::mean 1.205049 # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::stdev 1.150817 # Number of insts issued each cycle |
| 510system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 517system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 511system.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle | 518system.cpu.iq.issued_per_cycle::0 588435916 38.17% 38.17% # Number of insts issued each cycle 519system.cpu.iq.issued_per_cycle::1 326131475 21.16% 59.33% # Number of insts issued each cycle 520system.cpu.iq.issued_per_cycle::2 378210554 24.54% 83.87% # Number of insts issued each cycle 521system.cpu.iq.issued_per_cycle::3 219654013 14.25% 98.12% # Number of insts issued each cycle 522system.cpu.iq.issued_per_cycle::4 28986723 1.88% 100.00% # Number of insts issued each cycle 523system.cpu.iq.issued_per_cycle::5 6171 0.00% 100.00% # Number of insts issued each cycle |
| 517system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 518system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 519system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 520system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 521system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 522system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle | 524system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 525system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 526system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 527system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 528system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 529system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle |
| 523system.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle | 530system.cpu.iq.issued_per_cycle::total 1541424852 # Number of insts issued each cycle |
| 524system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 531system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 525system.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available 526system.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available | 532system.cpu.iq.fu_full::IntAlu 166021321 40.99% 40.99% # attempts to use FU when none available 533system.cpu.iq.fu_full::IntMult 1993 0.00% 40.99% # attempts to use FU when none available |
| 527system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available 528system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available 529system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available 530system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available 531system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available 532system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available 533system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 546system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available 547system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available 548system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available 549system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available 550system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available 551system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available 552system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available 553system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available | 534system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available 535system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available 536system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available 537system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available 538system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available 539system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available 540system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available --- 11 unchanged lines hidden (view full) --- 553system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available 554system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available 555system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available 556system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available 557system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available 558system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available 559system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available 560system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available |
| 554system.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available 555system.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available | 561system.cpu.iq.fu_full::MemRead 191489776 47.28% 88.26% # attempts to use FU when none available 562system.cpu.iq.fu_full::MemWrite 47539480 11.74% 100.00% # attempts to use FU when none available |
| 556system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 557system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 558system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 563system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 564system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 565system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 559system.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued 560system.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued | 566system.cpu.iq.FU_type_0::IntAlu 1138243662 61.28% 61.28% # Type of FU issued 567system.cpu.iq.FU_type_0::IntMult 800931 0.04% 61.32% # Type of FU issued |
| 561system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 562system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued 563system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 564system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 565system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 566system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 567system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 574system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued | 568system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 569system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued 570system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 571system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 572system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 573system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 574system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued --- 5 unchanged lines hidden (view full) --- 581system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 582system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 583system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 584system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 585system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 586system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 587system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 588system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued |
| 582system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued | 589system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued |
| 583system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued 584system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued 585system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued 586system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 587system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued | 590system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued 591system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued 592system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued 593system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 594system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued |
| 588system.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued 589system.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued | 595system.cpu.iq.FU_type_0::MemRead 532135699 28.65% 89.97% # Type of FU issued 596system.cpu.iq.FU_type_0::MemWrite 186312026 10.03% 100.00% # Type of FU issued |
| 590system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 591system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 597system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 598system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 592system.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued 593system.cpu.iq.rate 1.209614 # Inst issue rate 594system.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested 595system.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst) 596system.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads 597system.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes 598system.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses 599system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads 600system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes 601system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses 602system.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses 603system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses 604system.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores | 599system.cpu.iq.FU_type_0::total 1857492369 # Type of FU issued 600system.cpu.iq.rate 1.204986 # Inst issue rate 601system.cpu.iq.fu_busy_cnt 405052570 # FU busy when requested 602system.cpu.iq.fu_busy_rate 0.218064 # FU busy rate (busy events/executed inst) 603system.cpu.iq.int_inst_queue_reads 5674958613 # Number of integer instruction queue reads 604system.cpu.iq.int_inst_queue_writes 2231919871 # Number of integer instruction queue writes 605system.cpu.iq.int_inst_queue_wakeup_accesses 1805704142 # Number of integer instruction queue wakeup accesses 606system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads 607system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes 608system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses 609system.cpu.iq.int_alu_accesses 2262544806 # Number of integer alu accesses 610system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses 611system.cpu.iew.lsq.thread0.forwLoads 17811536 # Number of loads that had data forwarded from stores |
| 605system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 612system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 606system.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed 607system.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed 608system.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations 609system.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed | 613system.cpu.iew.lsq.thread0.squashedLoads 84259743 # Number of loads squashed 614system.cpu.iew.lsq.thread0.ignoredResponses 66618 # Number of memory responses ignored because the instruction is squashed 615system.cpu.iew.lsq.thread0.memOrderViolation 13244 # Number of memory ordering violations 616system.cpu.iew.lsq.thread0.squashedStores 24456330 # Number of stores squashed |
| 610system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 611system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 617system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 618system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 612system.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled 613system.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked | 619system.cpu.iew.lsq.thread0.rescheduledLoads 4512030 # Number of loads that were rescheduled 620system.cpu.iew.lsq.thread0.cacheBlocked 4891489 # Number of times an access to memory failed due to the cache being blocked |
| 614system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 621system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 615system.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing 616system.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking 617system.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking 618system.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ | 622system.cpu.iew.iewSquashCycles 14640138 # Number of cycles IEW is squashing 623system.cpu.iew.iewBlockCycles 25364964 # Number of cycles IEW is blocking 624system.cpu.iew.iewUnblockCycles 1346928 # Number of cycles IEW is unblocking 625system.cpu.iew.iewDispatchedInsts 1947969899 # Number of instructions dispatched to IQ |
| 619system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 626system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 620system.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions 621system.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions | 627system.cpu.iew.iewDispLoadInsts 542566077 # Number of dispatched load instructions 628system.cpu.iew.iewDispStoreInsts 199303375 # Number of dispatched store instructions |
| 622system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions | 629system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions |
| 623system.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall 624system.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall 625system.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations 626system.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly 627system.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly 628system.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute 629system.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions 630system.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed 631system.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute | 630system.cpu.iew.iewIQFullEvents 159350 # Number of times the IQ has become full, causing a stall 631system.cpu.iew.iewLSQFullEvents 1186169 # Number of times the LSQ has become full, causing a stall 632system.cpu.iew.memOrderViolationEvents 13244 # Number of memory order violations 633system.cpu.iew.predictedTakenIncorrect 7699482 # Number of branches that were predicted taken incorrectly 634system.cpu.iew.predictedNotTakenIncorrect 8703162 # Number of branches that were predicted not taken incorrectly 635system.cpu.iew.branchMispredicts 16402644 # Number of branch mispredicts detected at execute 636system.cpu.iew.iewExecutedInsts 1827831567 # Number of executed instructions 637system.cpu.iew.iewExecLoadInsts 516957415 # Number of load instructions executed 638system.cpu.iew.iewExecSquashedInsts 29660802 # Number of squashed instructions skipped in execute |
| 632system.cpu.iew.exec_swp 0 # number of swp insts executed | 639system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 633system.cpu.iew.exec_nop 146 # number of nop insts executed 634system.cpu.iew.exec_refs 698692225 # number of memory reference insts executed 635system.cpu.iew.exec_branches 229542687 # Number of branches executed 636system.cpu.iew.exec_stores 181751910 # Number of stores executed 637system.cpu.iew.exec_rate 1.190295 # Inst execution rate 638system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit 639system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back 640system.cpu.iew.wb_producers 1169207800 # num instructions producing a value 641system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value 642system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle | 640system.cpu.iew.exec_nop 151 # number of nop insts executed 641system.cpu.iew.exec_refs 698708795 # number of memory reference insts executed 642system.cpu.iew.exec_branches 229542425 # Number of branches executed 643system.cpu.iew.exec_stores 181751380 # Number of stores executed 644system.cpu.iew.exec_rate 1.185745 # Inst execution rate 645system.cpu.iew.wb_sent 1808736265 # cumulative count of insts sent to commit 646system.cpu.iew.wb_count 1805704212 # cumulative count of insts written-back 647system.cpu.iew.wb_producers 1169174812 # num instructions producing a value 648system.cpu.iew.wb_consumers 1689572222 # num instructions consuming a value 649system.cpu.iew.wb_rate 1.171391 # insts written-back per cycle |
| 643system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back | 650system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back |
| 644system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit | 651system.cpu.commit.commitSquashedInsts 258041892 # The number of squashed insts skipped by commit |
| 645system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards | 652system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards |
| 646system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted 647system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle | 653system.cpu.commit.branchMispredicts 14627747 # The number of times a branch was mispredicted 654system.cpu.commit.committed_per_cycle::samples 1501940299 # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::mean 1.107922 # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::stdev 2.025263 # Number of insts commited each cycle |
| 650system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 657system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 651system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle 658system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle 659system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle | 658system.cpu.commit.committed_per_cycle::0 921653315 61.36% 61.36% # Number of insts commited each cycle 659system.cpu.commit.committed_per_cycle::1 250636600 16.69% 78.05% # Number of insts commited each cycle 660system.cpu.commit.committed_per_cycle::2 110060462 7.33% 85.38% # Number of insts commited each cycle 661system.cpu.commit.committed_per_cycle::3 55269176 3.68% 89.06% # Number of insts commited each cycle 662system.cpu.commit.committed_per_cycle::4 29319156 1.95% 91.01% # Number of insts commited each cycle 663system.cpu.commit.committed_per_cycle::5 34080655 2.27% 93.28% # Number of insts commited each cycle 664system.cpu.commit.committed_per_cycle::6 24723288 1.65% 94.93% # Number of insts commited each cycle 665system.cpu.commit.committed_per_cycle::7 18133421 1.21% 96.13% # Number of insts commited each cycle 666system.cpu.commit.committed_per_cycle::8 58064226 3.87% 100.00% # Number of insts commited each cycle |
| 660system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 661system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 662system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 667system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 668system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 669system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 663system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle | 670system.cpu.commit.committed_per_cycle::total 1501940299 # Number of insts commited each cycle |
| 664system.cpu.commit.committedInsts 1544563042 # Number of instructions committed 665system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed 666system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 667system.cpu.commit.refs 633153379 # Number of memory references committed 668system.cpu.commit.loads 458306334 # Number of loads committed 669system.cpu.commit.membars 62 # Number of memory barriers committed 670system.cpu.commit.branches 213462427 # Number of branches committed 671system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 701system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 702system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 703system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 704system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 705system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction 706system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 707system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 708system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction | 671system.cpu.commit.committedInsts 1544563042 # Number of instructions committed 672system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed 673system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 674system.cpu.commit.refs 633153379 # Number of memory references committed 675system.cpu.commit.loads 458306334 # Number of loads committed 676system.cpu.commit.membars 62 # Number of memory barriers committed 677system.cpu.commit.branches 213462427 # Number of branches committed 678system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 708system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 709system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 710system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 711system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 712system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction 713system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 714system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 715system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction |
| 709system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached 710system.cpu.rob.rob_reads 3360114616 # The number of ROB reads 711system.cpu.rob.rob_writes 3883791528 # The number of ROB writes 712system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself 713system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling | 716system.cpu.commit.bw_lim_events 58064226 # number cycles where commit BW limit reached 717system.cpu.rob.rob_reads 3365949800 # The number of ROB reads 718system.cpu.rob.rob_writes 3883638365 # The number of ROB writes 719system.cpu.timesIdled 837 # Number of times that the entire CPU went into an idle state and unscheduled itself 720system.cpu.idleCycles 79902 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 714system.cpu.committedInsts 1544563024 # Number of Instructions Simulated 715system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated | 721system.cpu.committedInsts 1544563024 # Number of Instructions Simulated 722system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated |
| 716system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction 717system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads 718system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle 719system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads 720system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads 721system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes | 723system.cpu.cpi 0.998020 # CPI: Cycles Per Instruction 724system.cpu.cpi_total 0.998020 # CPI: Total CPI of All Threads 725system.cpu.ipc 1.001984 # IPC: Instructions Per Cycle 726system.cpu.ipc_total 1.001984 # IPC: Total IPC of All Threads 727system.cpu.int_regfile_reads 2175818987 # number of integer regfile reads 728system.cpu.int_regfile_writes 1261576435 # number of integer regfile writes |
| 722system.cpu.fp_regfile_reads 42 # number of floating regfile reads | 729system.cpu.fp_regfile_reads 42 # number of floating regfile reads |
| 723system.cpu.fp_regfile_writes 54 # number of floating regfile writes 724system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads 725system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes 726system.cpu.misc_regfile_reads 675853618 # number of misc regfile reads | 730system.cpu.fp_regfile_writes 52 # number of floating regfile writes 731system.cpu.cc_regfile_reads 6965775009 # number of cc regfile reads 732system.cpu.cc_regfile_writes 551856674 # number of cc regfile writes 733system.cpu.misc_regfile_reads 675846934 # number of misc regfile reads |
| 727system.cpu.misc_regfile_writes 124 # number of misc regfile writes | 734system.cpu.misc_regfile_writes 124 # number of misc regfile writes |
| 728system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 729system.cpu.dcache.tags.replacements 17003710 # number of replacements 730system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use 731system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. 732system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. 733system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. 734system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. 735system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor 736system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy 737system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy | 735system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 736system.cpu.dcache.tags.replacements 17003150 # number of replacements 737system.cpu.dcache.tags.tagsinuse 511.964340 # Cycle average of tags in use 738system.cpu.dcache.tags.total_refs 638065664 # Total number of references to valid blocks. 739system.cpu.dcache.tags.sampled_refs 17003662 # Sample count of references to valid blocks. 740system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks. 741system.cpu.dcache.tags.warmup_cycle 79206500 # Cycle when the warmup percentage was hit. 742system.cpu.dcache.tags.occ_blocks::cpu.data 511.964340 # Average occupied blocks per requestor 743system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy 744system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy |
| 738system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id | 745system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id |
| 739system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id 740system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id | 746system.cpu.dcache.tags.age_task_id_blocks_1024::0 406 # Occupied blocks per task id 747system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id |
| 741system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 748system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 742system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses 743system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses 744system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 745system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits 746system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits 747system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits 748system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits | 749system.cpu.dcache.tags.tag_accesses 1335709608 # Number of tag accesses 750system.cpu.dcache.tags.data_accesses 1335709608 # Number of data accesses 751system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 752system.cpu.dcache.ReadReq_hits::cpu.data 469347574 # number of ReadReq hits 753system.cpu.dcache.ReadReq_hits::total 469347574 # number of ReadReq hits 754system.cpu.dcache.WriteReq_hits::cpu.data 168717937 # number of WriteReq hits 755system.cpu.dcache.WriteReq_hits::total 168717937 # number of WriteReq hits |
| 749system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 750system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 751system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 752system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits | 756system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 757system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 758system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 759system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits |
| 753system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits 754system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits 755system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits 756system.cpu.dcache.overall_hits::total 638076218 # number of overall hits 757system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses 758system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses 759system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses 760system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses | 760system.cpu.dcache.demand_hits::cpu.data 638065511 # number of demand (read+write) hits 761system.cpu.dcache.demand_hits::total 638065511 # number of demand (read+write) hits 762system.cpu.dcache.overall_hits::cpu.data 638065511 # number of overall hits 763system.cpu.dcache.overall_hits::total 638065511 # number of overall hits 764system.cpu.dcache.ReadReq_misses::cpu.data 17419228 # number of ReadReq misses 765system.cpu.dcache.ReadReq_misses::total 17419228 # number of ReadReq misses 766system.cpu.dcache.WriteReq_misses::cpu.data 3868110 # number of WriteReq misses 767system.cpu.dcache.WriteReq_misses::total 3868110 # number of WriteReq misses |
| 761system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 762system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 763system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 764system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses | 768system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 769system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 770system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 771system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses |
| 765system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses 766system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses 767system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses 768system.cpu.dcache.overall_misses::total 21285744 # number of overall misses 769system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles 770system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles 771system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles 772system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles 773system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles 774system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles 775system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles 776system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles 777system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles 778system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles 779system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses) 780system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses) | 772system.cpu.dcache.demand_misses::cpu.data 21287338 # number of demand (read+write) misses 773system.cpu.dcache.demand_misses::total 21287338 # number of demand (read+write) misses 774system.cpu.dcache.overall_misses::cpu.data 21287340 # number of overall misses 775system.cpu.dcache.overall_misses::total 21287340 # number of overall misses 776system.cpu.dcache.ReadReq_miss_latency::cpu.data 416423435500 # number of ReadReq miss cycles 777system.cpu.dcache.ReadReq_miss_latency::total 416423435500 # number of ReadReq miss cycles 778system.cpu.dcache.WriteReq_miss_latency::cpu.data 150253086257 # number of WriteReq miss cycles 779system.cpu.dcache.WriteReq_miss_latency::total 150253086257 # number of WriteReq miss cycles 780system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199500 # number of LoadLockedReq miss cycles 781system.cpu.dcache.LoadLockedReq_miss_latency::total 199500 # number of LoadLockedReq miss cycles 782system.cpu.dcache.demand_miss_latency::cpu.data 566676521757 # number of demand (read+write) miss cycles 783system.cpu.dcache.demand_miss_latency::total 566676521757 # number of demand (read+write) miss cycles 784system.cpu.dcache.overall_miss_latency::cpu.data 566676521757 # number of overall miss cycles 785system.cpu.dcache.overall_miss_latency::total 566676521757 # number of overall miss cycles 786system.cpu.dcache.ReadReq_accesses::cpu.data 486766802 # number of ReadReq accesses(hits+misses) 787system.cpu.dcache.ReadReq_accesses::total 486766802 # number of ReadReq accesses(hits+misses) |
| 781system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 782system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 783system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) 784system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) 785system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 786system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 787system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 788system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) | 788system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 789system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 790system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) 791system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) 792system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 793system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 794system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 795system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) |
| 789system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses 790system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses 791system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses 792system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses 793system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses 794system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses 795system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses 796system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses | 796system.cpu.dcache.demand_accesses::cpu.data 659352849 # number of demand (read+write) accesses 797system.cpu.dcache.demand_accesses::total 659352849 # number of demand (read+write) accesses 798system.cpu.dcache.overall_accesses::cpu.data 659352851 # number of overall (read+write) accesses 799system.cpu.dcache.overall_accesses::total 659352851 # number of overall (read+write) accesses 800system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses 801system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses 802system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022413 # miss rate for WriteReq accesses 803system.cpu.dcache.WriteReq_miss_rate::total 0.022413 # miss rate for WriteReq accesses |
| 797system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 798system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 799system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses 800system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses | 804system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 805system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 806system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses 807system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses |
| 801system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses 802system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses 803system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses 804system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses 805system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency 806system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency 807system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency 808system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency 809system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency 810system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency 811system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency 812system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency 813system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency 814system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency 815system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked 816system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked 817system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked 818system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked 819system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked 820system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked 821system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks 822system.cpu.dcache.writebacks::total 17003710 # number of writebacks 823system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits 824system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits 825system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits 826system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits | 808system.cpu.dcache.demand_miss_rate::cpu.data 0.032285 # miss rate for demand accesses 809system.cpu.dcache.demand_miss_rate::total 0.032285 # miss rate for demand accesses 810system.cpu.dcache.overall_miss_rate::cpu.data 0.032285 # miss rate for overall accesses 811system.cpu.dcache.overall_miss_rate::total 0.032285 # miss rate for overall accesses 812system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23905.963887 # average ReadReq miss latency 813system.cpu.dcache.ReadReq_avg_miss_latency::total 23905.963887 # average ReadReq miss latency 814system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38844.057242 # average WriteReq miss latency 815system.cpu.dcache.WriteReq_avg_miss_latency::total 38844.057242 # average WriteReq miss latency 816system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49875 # average LoadLockedReq miss latency 817system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49875 # average LoadLockedReq miss latency 818system.cpu.dcache.demand_avg_miss_latency::cpu.data 26620.356277 # average overall miss latency 819system.cpu.dcache.demand_avg_miss_latency::total 26620.356277 # average overall miss latency 820system.cpu.dcache.overall_avg_miss_latency::cpu.data 26620.353776 # average overall miss latency 821system.cpu.dcache.overall_avg_miss_latency::total 26620.353776 # average overall miss latency 822system.cpu.dcache.blocked_cycles::no_mshrs 20685246 # number of cycles access was blocked 823system.cpu.dcache.blocked_cycles::no_targets 3452781 # number of cycles access was blocked 824system.cpu.dcache.blocked::no_mshrs 946049 # number of cycles access was blocked 825system.cpu.dcache.blocked::no_targets 67233 # number of cycles access was blocked 826system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.864878 # average number of cycles each access was blocked 827system.cpu.dcache.avg_blocked_cycles::no_targets 51.355450 # average number of cycles each access was blocked 828system.cpu.dcache.writebacks::writebacks 17003150 # number of writebacks 829system.cpu.dcache.writebacks::total 17003150 # number of writebacks 830system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3153076 # number of ReadReq MSHR hits 831system.cpu.dcache.ReadReq_mshr_hits::total 3153076 # number of ReadReq MSHR hits 832system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130592 # number of WriteReq MSHR hits 833system.cpu.dcache.WriteReq_mshr_hits::total 1130592 # number of WriteReq MSHR hits |
| 827system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 828system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits | 834system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 835system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits |
| 829system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits 830system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits 831system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits 832system.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits 833system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses 834system.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses 835system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses 836system.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses | 836system.cpu.dcache.demand_mshr_hits::cpu.data 4283668 # number of demand (read+write) MSHR hits 837system.cpu.dcache.demand_mshr_hits::total 4283668 # number of demand (read+write) MSHR hits 838system.cpu.dcache.overall_mshr_hits::cpu.data 4283668 # number of overall MSHR hits 839system.cpu.dcache.overall_mshr_hits::total 4283668 # number of overall MSHR hits 840system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266152 # number of ReadReq MSHR misses 841system.cpu.dcache.ReadReq_mshr_misses::total 14266152 # number of ReadReq MSHR misses 842system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737518 # number of WriteReq MSHR misses 843system.cpu.dcache.WriteReq_mshr_misses::total 2737518 # number of WriteReq MSHR misses |
| 837system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 838system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses | 844system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 845system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses |
| 839system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses 840system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses 841system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses 842system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses 843system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles 844system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles 845system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles 846system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles 847system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles 848system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles 849system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles 850system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles 851system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles 852system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles | 846system.cpu.dcache.demand_mshr_misses::cpu.data 17003670 # number of demand (read+write) MSHR misses 847system.cpu.dcache.demand_mshr_misses::total 17003670 # number of demand (read+write) MSHR misses 848system.cpu.dcache.overall_mshr_misses::cpu.data 17003671 # number of overall MSHR misses 849system.cpu.dcache.overall_mshr_misses::total 17003671 # number of overall MSHR misses 850system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335207977500 # number of ReadReq MSHR miss cycles 851system.cpu.dcache.ReadReq_mshr_miss_latency::total 335207977500 # number of ReadReq MSHR miss cycles 852system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116679674033 # number of WriteReq MSHR miss cycles 853system.cpu.dcache.WriteReq_mshr_miss_latency::total 116679674033 # number of WriteReq MSHR miss cycles 854system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69000 # number of SoftPFReq MSHR miss cycles 855system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69000 # number of SoftPFReq MSHR miss cycles 856system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451887651533 # number of demand (read+write) MSHR miss cycles 857system.cpu.dcache.demand_mshr_miss_latency::total 451887651533 # number of demand (read+write) MSHR miss cycles 858system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451887720533 # number of overall MSHR miss cycles 859system.cpu.dcache.overall_mshr_miss_latency::total 451887720533 # number of overall MSHR miss cycles |
| 853system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses 854system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses 855system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses 856system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses 857system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses 858system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses | 860system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses 861system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses 862system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses 863system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses 864system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses 865system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses |
| 859system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses 860system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses 861system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses 862system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses 863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency 864system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency 866system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency 867system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency 868system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency 869system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency 870system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency 871system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency 872system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency 873system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 874system.cpu.icache.tags.replacements 589 # number of replacements 875system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use 876system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. 877system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. 878system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. | 866system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for demand accesses 867system.cpu.dcache.demand_mshr_miss_rate::total 0.025788 # mshr miss rate for demand accesses 868system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for overall accesses 869system.cpu.dcache.overall_mshr_miss_rate::total 0.025788 # mshr miss rate for overall accesses 870system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23496.733913 # average ReadReq mshr miss latency 871system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23496.733913 # average ReadReq mshr miss latency 872system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42622.431718 # average WriteReq mshr miss latency 873system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42622.431718 # average WriteReq mshr miss latency 874system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69000 # average SoftPFReq mshr miss latency 875system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69000 # average SoftPFReq mshr miss latency 876system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26575.889295 # average overall mshr miss latency 877system.cpu.dcache.demand_avg_mshr_miss_latency::total 26575.889295 # average overall mshr miss latency 878system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26575.891790 # average overall mshr miss latency 879system.cpu.dcache.overall_avg_mshr_miss_latency::total 26575.891790 # average overall mshr miss latency 880system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 881system.cpu.icache.tags.replacements 588 # number of replacements 882system.cpu.icache.tags.tagsinuse 444.874436 # Cycle average of tags in use 883system.cpu.icache.tags.total_refs 656938405 # Total number of references to valid blocks. 884system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks. 885system.cpu.icache.tags.avg_refs 611674.492551 # Average number of references to valid blocks. |
| 879system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 886system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 880system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor 881system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy 882system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy | 887system.cpu.icache.tags.occ_blocks::cpu.inst 444.874436 # Average occupied blocks per requestor 888system.cpu.icache.tags.occ_percent::cpu.inst 0.868895 # Average percentage of cache occupancy 889system.cpu.icache.tags.occ_percent::total 0.868895 # Average percentage of cache occupancy |
| 883system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id | 890system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id |
| 884system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id | 891system.cpu.icache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id |
| 885system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id | 892system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id |
| 886system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id | 893system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id |
| 887system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id | 894system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id |
| 888system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses 889system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses 890system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 891system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits 892system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits 893system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits 894system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits 895system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits 896system.cpu.icache.overall_hits::total 656966815 # number of overall hits 897system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses 898system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses 899system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses 900system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses 901system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses 902system.cpu.icache.overall_misses::total 1620 # number of overall misses 903system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles 904system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles 905system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles 906system.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles 907system.cpu.icache.overall_miss_latency::cpu.inst 98788987 # number of overall miss cycles 908system.cpu.icache.overall_miss_latency::total 98788987 # number of overall miss cycles 909system.cpu.icache.ReadReq_accesses::cpu.inst 656968435 # number of ReadReq accesses(hits+misses) 910system.cpu.icache.ReadReq_accesses::total 656968435 # number of ReadReq accesses(hits+misses) 911system.cpu.icache.demand_accesses::cpu.inst 656968435 # number of demand (read+write) accesses 912system.cpu.icache.demand_accesses::total 656968435 # number of demand (read+write) accesses 913system.cpu.icache.overall_accesses::cpu.inst 656968435 # number of overall (read+write) accesses 914system.cpu.icache.overall_accesses::total 656968435 # number of overall (read+write) accesses | 895system.cpu.icache.tags.tag_accesses 1313881106 # Number of tag accesses 896system.cpu.icache.tags.data_accesses 1313881106 # Number of data accesses 897system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 898system.cpu.icache.ReadReq_hits::cpu.inst 656938405 # number of ReadReq hits 899system.cpu.icache.ReadReq_hits::total 656938405 # number of ReadReq hits 900system.cpu.icache.demand_hits::cpu.inst 656938405 # number of demand (read+write) hits 901system.cpu.icache.demand_hits::total 656938405 # number of demand (read+write) hits 902system.cpu.icache.overall_hits::cpu.inst 656938405 # number of overall hits 903system.cpu.icache.overall_hits::total 656938405 # number of overall hits 904system.cpu.icache.ReadReq_misses::cpu.inst 1611 # number of ReadReq misses 905system.cpu.icache.ReadReq_misses::total 1611 # number of ReadReq misses 906system.cpu.icache.demand_misses::cpu.inst 1611 # number of demand (read+write) misses 907system.cpu.icache.demand_misses::total 1611 # number of demand (read+write) misses 908system.cpu.icache.overall_misses::cpu.inst 1611 # number of overall misses 909system.cpu.icache.overall_misses::total 1611 # number of overall misses 910system.cpu.icache.ReadReq_miss_latency::cpu.inst 103785485 # number of ReadReq miss cycles 911system.cpu.icache.ReadReq_miss_latency::total 103785485 # number of ReadReq miss cycles 912system.cpu.icache.demand_miss_latency::cpu.inst 103785485 # number of demand (read+write) miss cycles 913system.cpu.icache.demand_miss_latency::total 103785485 # number of demand (read+write) miss cycles 914system.cpu.icache.overall_miss_latency::cpu.inst 103785485 # number of overall miss cycles 915system.cpu.icache.overall_miss_latency::total 103785485 # number of overall miss cycles 916system.cpu.icache.ReadReq_accesses::cpu.inst 656940016 # number of ReadReq accesses(hits+misses) 917system.cpu.icache.ReadReq_accesses::total 656940016 # number of ReadReq accesses(hits+misses) 918system.cpu.icache.demand_accesses::cpu.inst 656940016 # number of demand (read+write) accesses 919system.cpu.icache.demand_accesses::total 656940016 # number of demand (read+write) accesses 920system.cpu.icache.overall_accesses::cpu.inst 656940016 # number of overall (read+write) accesses 921system.cpu.icache.overall_accesses::total 656940016 # number of overall (read+write) accesses |
| 915system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 916system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 917system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 918system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 919system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 920system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses | 922system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 923system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 924system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 925system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 926system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 927system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses |
| 921system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173 # average ReadReq miss latency 922system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173 # average ReadReq miss latency 923system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency 924system.cpu.icache.demand_avg_miss_latency::total 60980.856173 # average overall miss latency 925system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency 926system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency 927system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked 928system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked 929system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked 930system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked 931system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked 932system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked 933system.cpu.icache.writebacks::writebacks 589 # number of writebacks 934system.cpu.icache.writebacks::total 589 # number of writebacks 935system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits 936system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits 937system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits 938system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits 939system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits 940system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits | 928system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64423.019863 # average ReadReq miss latency 929system.cpu.icache.ReadReq_avg_miss_latency::total 64423.019863 # average ReadReq miss latency 930system.cpu.icache.demand_avg_miss_latency::cpu.inst 64423.019863 # average overall miss latency 931system.cpu.icache.demand_avg_miss_latency::total 64423.019863 # average overall miss latency 932system.cpu.icache.overall_avg_miss_latency::cpu.inst 64423.019863 # average overall miss latency 933system.cpu.icache.overall_avg_miss_latency::total 64423.019863 # average overall miss latency 934system.cpu.icache.blocked_cycles::no_mshrs 16825 # number of cycles access was blocked 935system.cpu.icache.blocked_cycles::no_targets 586 # number of cycles access was blocked 936system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked 937system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked 938system.cpu.icache.avg_blocked_cycles::no_mshrs 90.945946 # average number of cycles each access was blocked 939system.cpu.icache.avg_blocked_cycles::no_targets 58.600000 # average number of cycles each access was blocked 940system.cpu.icache.writebacks::writebacks 588 # number of writebacks 941system.cpu.icache.writebacks::total 588 # number of writebacks 942system.cpu.icache.ReadReq_mshr_hits::cpu.inst 535 # number of ReadReq MSHR hits 943system.cpu.icache.ReadReq_mshr_hits::total 535 # number of ReadReq MSHR hits 944system.cpu.icache.demand_mshr_hits::cpu.inst 535 # number of demand (read+write) MSHR hits 945system.cpu.icache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits 946system.cpu.icache.overall_mshr_hits::cpu.inst 535 # number of overall MSHR hits 947system.cpu.icache.overall_mshr_hits::total 535 # number of overall MSHR hits |
| 941system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses 942system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses 943system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses 944system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses 945system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses 946system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses | 948system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses 949system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses 950system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses 951system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses 952system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses 953system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses |
| 947system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73759491 # number of ReadReq MSHR miss cycles 948system.cpu.icache.ReadReq_mshr_miss_latency::total 73759491 # number of ReadReq MSHR miss cycles 949system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73759491 # number of demand (read+write) MSHR miss cycles 950system.cpu.icache.demand_mshr_miss_latency::total 73759491 # number of demand (read+write) MSHR miss cycles 951system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73759491 # number of overall MSHR miss cycles 952system.cpu.icache.overall_mshr_miss_latency::total 73759491 # number of overall MSHR miss cycles | 954system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75943989 # number of ReadReq MSHR miss cycles 955system.cpu.icache.ReadReq_mshr_miss_latency::total 75943989 # number of ReadReq MSHR miss cycles 956system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75943989 # number of demand (read+write) MSHR miss cycles 957system.cpu.icache.demand_mshr_miss_latency::total 75943989 # number of demand (read+write) MSHR miss cycles 958system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75943989 # number of overall MSHR miss cycles 959system.cpu.icache.overall_mshr_miss_latency::total 75943989 # number of overall MSHR miss cycles |
| 953system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 954system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 955system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 956system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 957system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 958system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses | 960system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 961system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 962system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 963system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 964system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 965system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses |
| 959system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency 960system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency 961system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 962system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency 963system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 964system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency 965system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 966system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued 967system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified 968system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue | 966system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70579.915428 # average ReadReq mshr miss latency 967system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70579.915428 # average ReadReq mshr miss latency 968system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70579.915428 # average overall mshr miss latency 969system.cpu.icache.demand_avg_mshr_miss_latency::total 70579.915428 # average overall mshr miss latency 970system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70579.915428 # average overall mshr miss latency 971system.cpu.icache.overall_avg_mshr_miss_latency::total 70579.915428 # average overall mshr miss latency 972system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 973system.cpu.l2cache.prefetcher.num_hwpf_issued 11612917 # number of hwpf issued 974system.cpu.l2cache.prefetcher.pfIdentified 11641367 # number of prefetch candidates identified 975system.cpu.l2cache.prefetcher.pfBufferHit 19112 # number of redundant prefetches already in prefetch queue |
| 969system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 970system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size | 976system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 977system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size |
| 971system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing 972system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 973system.cpu.l2cache.tags.replacements 4706089 # number of replacements 974system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use 975system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. 976system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks. 977system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks. 978system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit. 979system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor 980system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor 981system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.119162 # Average occupied blocks per requestor 982system.cpu.l2cache.tags.occ_percent::writebacks 0.799460 # Average percentage of cache occupancy 983system.cpu.l2cache.tags.occ_percent::cpu.data 0.000140 # Average percentage of cache occupancy 984system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183052 # Average percentage of cache occupancy 985system.cpu.l2cache.tags.occ_percent::total 0.982651 # Average percentage of cache occupancy 986system.cpu.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id 987system.cpu.l2cache.tags.occ_task_id_blocks::1024 15097 # Occupied blocks per task id 988system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1022::1 636 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1022::3 191 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id 995system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id 996system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id 997system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id 998system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses 999system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses 1000system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 1001system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits 1002system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits 1003system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits 1004system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits 1005system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits 1006system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits 1007system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits 1008system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits 1009system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11522367 # number of ReadSharedReq hits 1010system.cpu.l2cache.ReadSharedReq_hits::total 11522367 # number of ReadSharedReq hits 1011system.cpu.l2cache.demand_hits::cpu.inst 56 # number of demand (read+write) hits 1012system.cpu.l2cache.demand_hits::cpu.data 13279454 # number of demand (read+write) hits 1013system.cpu.l2cache.demand_hits::total 13279510 # number of demand (read+write) hits 1014system.cpu.l2cache.overall_hits::cpu.inst 56 # number of overall hits 1015system.cpu.l2cache.overall_hits::cpu.data 13279454 # number of overall hits 1016system.cpu.l2cache.overall_hits::total 13279510 # number of overall hits 1017system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 1018system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 1019system.cpu.l2cache.ReadExReq_misses::cpu.data 980546 # number of ReadExReq misses 1020system.cpu.l2cache.ReadExReq_misses::total 980546 # number of ReadExReq misses 1021system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1020 # number of ReadCleanReq misses 1022system.cpu.l2cache.ReadCleanReq_misses::total 1020 # number of ReadCleanReq misses 1023system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2744222 # number of ReadSharedReq misses 1024system.cpu.l2cache.ReadSharedReq_misses::total 2744222 # number of ReadSharedReq misses 1025system.cpu.l2cache.demand_misses::cpu.inst 1020 # number of demand (read+write) misses 1026system.cpu.l2cache.demand_misses::cpu.data 3724768 # number of demand (read+write) misses 1027system.cpu.l2cache.demand_misses::total 3725788 # number of demand (read+write) misses 1028system.cpu.l2cache.overall_misses::cpu.inst 1020 # number of overall misses 1029system.cpu.l2cache.overall_misses::cpu.data 3724768 # number of overall misses 1030system.cpu.l2cache.overall_misses::total 3725788 # number of overall misses 1031system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 121000 # number of UpgradeReq miss cycles 1032system.cpu.l2cache.UpgradeReq_miss_latency::total 121000 # number of UpgradeReq miss cycles 1033system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99083213500 # number of ReadExReq miss cycles 1034system.cpu.l2cache.ReadExReq_miss_latency::total 99083213500 # number of ReadExReq miss cycles 1035system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72272000 # number of ReadCleanReq miss cycles 1036system.cpu.l2cache.ReadCleanReq_miss_latency::total 72272000 # number of ReadCleanReq miss cycles 1037system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000 # number of ReadSharedReq miss cycles 1038system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000 # number of ReadSharedReq miss cycles 1039system.cpu.l2cache.demand_miss_latency::cpu.inst 72272000 # number of demand (read+write) miss cycles 1040system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500 # number of demand (read+write) miss cycles 1041system.cpu.l2cache.demand_miss_latency::total 333235195500 # number of demand (read+write) miss cycles 1042system.cpu.l2cache.overall_miss_latency::cpu.inst 72272000 # number of overall miss cycles 1043system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500 # number of overall miss cycles 1044system.cpu.l2cache.overall_miss_latency::total 333235195500 # number of overall miss cycles 1045system.cpu.l2cache.WritebackDirty_accesses::writebacks 4833112 # number of WritebackDirty accesses(hits+misses) 1046system.cpu.l2cache.WritebackDirty_accesses::total 4833112 # number of WritebackDirty accesses(hits+misses) 1047system.cpu.l2cache.WritebackClean_accesses::writebacks 12149903 # number of WritebackClean accesses(hits+misses) 1048system.cpu.l2cache.WritebackClean_accesses::total 12149903 # number of WritebackClean accesses(hits+misses) 1049system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses) 1050system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses) 1051system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737633 # number of ReadExReq accesses(hits+misses) 1052system.cpu.l2cache.ReadExReq_accesses::total 2737633 # number of ReadExReq accesses(hits+misses) | 978system.cpu.l2cache.prefetcher.pfSpanPage 4655505 # number of prefetches not generated due to page crossing 979system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 980system.cpu.l2cache.tags.replacements 4647068 # number of replacements 981system.cpu.l2cache.tags.tagsinuse 15866.736257 # Cycle average of tags in use 982system.cpu.l2cache.tags.total_refs 13267029 # Total number of references to valid blocks. 983system.cpu.l2cache.tags.sampled_refs 4662976 # Sample count of references to valid blocks. 984system.cpu.l2cache.tags.avg_refs 2.845185 # Average number of references to valid blocks. 985system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 986system.cpu.l2cache.tags.occ_blocks::writebacks 15646.626307 # Average occupied blocks per requestor 987system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 220.109950 # Average occupied blocks per requestor 988system.cpu.l2cache.tags.occ_percent::writebacks 0.954994 # Average percentage of cache occupancy 989system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013434 # Average percentage of cache occupancy 990system.cpu.l2cache.tags.occ_percent::total 0.968429 # Average percentage of cache occupancy 991system.cpu.l2cache.tags.occ_task_id_blocks::1022 143 # Occupied blocks per task id 992system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1022::1 115 # Occupied blocks per task id 995system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id 996system.cpu.l2cache.tags.age_task_id_blocks_1024::0 463 # Occupied blocks per task id 997system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4068 # Occupied blocks per task id 998system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7095 # Occupied blocks per task id 999system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2886 # Occupied blocks per task id 1000system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1253 # Occupied blocks per task id 1001system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008728 # Percentage of cache occupancy per task id 1002system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id 1003system.cpu.l2cache.tags.tag_accesses 561777243 # Number of tag accesses 1004system.cpu.l2cache.tags.data_accesses 561777243 # Number of data accesses 1005system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 1006system.cpu.l2cache.WritebackDirty_hits::writebacks 4835234 # number of WritebackDirty hits 1007system.cpu.l2cache.WritebackDirty_hits::total 4835234 # number of WritebackDirty hits 1008system.cpu.l2cache.WritebackClean_hits::writebacks 12147319 # number of WritebackClean hits 1009system.cpu.l2cache.WritebackClean_hits::total 12147319 # number of WritebackClean hits 1010system.cpu.l2cache.ReadExReq_hits::cpu.data 1756866 # number of ReadExReq hits 1011system.cpu.l2cache.ReadExReq_hits::total 1756866 # number of ReadExReq hits 1012system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 49 # number of ReadCleanReq hits 1013system.cpu.l2cache.ReadCleanReq_hits::total 49 # number of ReadCleanReq hits 1014system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11510992 # number of ReadSharedReq hits 1015system.cpu.l2cache.ReadSharedReq_hits::total 11510992 # number of ReadSharedReq hits 1016system.cpu.l2cache.demand_hits::cpu.inst 49 # number of demand (read+write) hits 1017system.cpu.l2cache.demand_hits::cpu.data 13267858 # number of demand (read+write) hits 1018system.cpu.l2cache.demand_hits::total 13267907 # number of demand (read+write) hits 1019system.cpu.l2cache.overall_hits::cpu.inst 49 # number of overall hits 1020system.cpu.l2cache.overall_hits::cpu.data 13267858 # number of overall hits 1021system.cpu.l2cache.overall_hits::total 13267907 # number of overall hits 1022system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses 1023system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses 1024system.cpu.l2cache.ReadExReq_misses::cpu.data 980689 # number of ReadExReq misses 1025system.cpu.l2cache.ReadExReq_misses::total 980689 # number of ReadExReq misses 1026system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1027 # number of ReadCleanReq misses 1027system.cpu.l2cache.ReadCleanReq_misses::total 1027 # number of ReadCleanReq misses 1028system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2755115 # number of ReadSharedReq misses 1029system.cpu.l2cache.ReadSharedReq_misses::total 2755115 # number of ReadSharedReq misses 1030system.cpu.l2cache.demand_misses::cpu.inst 1027 # number of demand (read+write) misses 1031system.cpu.l2cache.demand_misses::cpu.data 3735804 # number of demand (read+write) misses 1032system.cpu.l2cache.demand_misses::total 3736831 # number of demand (read+write) misses 1033system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses 1034system.cpu.l2cache.overall_misses::cpu.data 3735804 # number of overall misses 1035system.cpu.l2cache.overall_misses::total 3736831 # number of overall misses 1036system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 191500 # number of UpgradeReq miss cycles 1037system.cpu.l2cache.UpgradeReq_miss_latency::total 191500 # number of UpgradeReq miss cycles 1038system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100034737999 # number of ReadExReq miss cycles 1039system.cpu.l2cache.ReadExReq_miss_latency::total 100034737999 # number of ReadExReq miss cycles 1040system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 74500500 # number of ReadCleanReq miss cycles 1041system.cpu.l2cache.ReadCleanReq_miss_latency::total 74500500 # number of ReadCleanReq miss cycles 1042system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 237611587999 # number of ReadSharedReq miss cycles 1043system.cpu.l2cache.ReadSharedReq_miss_latency::total 237611587999 # number of ReadSharedReq miss cycles 1044system.cpu.l2cache.demand_miss_latency::cpu.inst 74500500 # number of demand (read+write) miss cycles 1045system.cpu.l2cache.demand_miss_latency::cpu.data 337646325998 # number of demand (read+write) miss cycles 1046system.cpu.l2cache.demand_miss_latency::total 337720826498 # number of demand (read+write) miss cycles 1047system.cpu.l2cache.overall_miss_latency::cpu.inst 74500500 # number of overall miss cycles 1048system.cpu.l2cache.overall_miss_latency::cpu.data 337646325998 # number of overall miss cycles 1049system.cpu.l2cache.overall_miss_latency::total 337720826498 # number of overall miss cycles 1050system.cpu.l2cache.WritebackDirty_accesses::writebacks 4835234 # number of WritebackDirty accesses(hits+misses) 1051system.cpu.l2cache.WritebackDirty_accesses::total 4835234 # number of WritebackDirty accesses(hits+misses) 1052system.cpu.l2cache.WritebackClean_accesses::writebacks 12147319 # number of WritebackClean accesses(hits+misses) 1053system.cpu.l2cache.WritebackClean_accesses::total 12147319 # number of WritebackClean accesses(hits+misses) 1054system.cpu.l2cache.UpgradeReq_accesses::cpu.data 9 # number of UpgradeReq accesses(hits+misses) 1055system.cpu.l2cache.UpgradeReq_accesses::total 9 # number of UpgradeReq accesses(hits+misses) 1056system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737555 # number of ReadExReq accesses(hits+misses) 1057system.cpu.l2cache.ReadExReq_accesses::total 2737555 # number of ReadExReq accesses(hits+misses) |
| 1053system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) 1054system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) | 1058system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) 1059system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) |
| 1055system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266589 # number of ReadSharedReq accesses(hits+misses) 1056system.cpu.l2cache.ReadSharedReq_accesses::total 14266589 # number of ReadSharedReq accesses(hits+misses) | 1060system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266107 # number of ReadSharedReq accesses(hits+misses) 1061system.cpu.l2cache.ReadSharedReq_accesses::total 14266107 # number of ReadSharedReq accesses(hits+misses) |
| 1057system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses | 1062system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses |
| 1058system.cpu.l2cache.demand_accesses::cpu.data 17004222 # number of demand (read+write) accesses 1059system.cpu.l2cache.demand_accesses::total 17005298 # number of demand (read+write) accesses | 1063system.cpu.l2cache.demand_accesses::cpu.data 17003662 # number of demand (read+write) accesses 1064system.cpu.l2cache.demand_accesses::total 17004738 # number of demand (read+write) accesses |
| 1060system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses | 1065system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses |
| 1061system.cpu.l2cache.overall_accesses::cpu.data 17004222 # number of overall (read+write) accesses 1062system.cpu.l2cache.overall_accesses::total 17005298 # number of overall (read+write) accesses | 1066system.cpu.l2cache.overall_accesses::cpu.data 17003662 # number of overall (read+write) accesses 1067system.cpu.l2cache.overall_accesses::total 17004738 # number of overall (read+write) accesses |
| 1063system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1064system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses | 1068system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1069system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses |
| 1065system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358173 # miss rate for ReadExReq accesses 1066system.cpu.l2cache.ReadExReq_miss_rate::total 0.358173 # miss rate for ReadExReq accesses 1067system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947955 # miss rate for ReadCleanReq accesses 1068system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947955 # miss rate for ReadCleanReq accesses 1069system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192353 # miss rate for ReadSharedReq accesses 1070system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192353 # miss rate for ReadSharedReq accesses 1071system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947955 # miss rate for demand accesses 1072system.cpu.l2cache.demand_miss_rate::cpu.data 0.219050 # miss rate for demand accesses 1073system.cpu.l2cache.demand_miss_rate::total 0.219096 # miss rate for demand accesses 1074system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947955 # miss rate for overall accesses 1075system.cpu.l2cache.overall_miss_rate::cpu.data 0.219050 # miss rate for overall accesses 1076system.cpu.l2cache.overall_miss_rate::total 0.219096 # miss rate for overall accesses 1077system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency 1078system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency 1079system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158 # average ReadExReq miss latency 1080system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158 # average ReadExReq miss latency 1081system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961 # average ReadCleanReq miss latency 1082system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961 # average ReadCleanReq miss latency 1083system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742 # average ReadSharedReq miss latency 1084system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742 # average ReadSharedReq miss latency 1085system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency 1086system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency 1087system.cpu.l2cache.demand_avg_miss_latency::total 89440.192383 # average overall miss latency 1088system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency 1089system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency 1090system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency 1091system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked | 1070system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358235 # miss rate for ReadExReq accesses 1071system.cpu.l2cache.ReadExReq_miss_rate::total 0.358235 # miss rate for ReadExReq accesses 1072system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954461 # miss rate for ReadCleanReq accesses 1073system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954461 # miss rate for ReadCleanReq accesses 1074system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193123 # miss rate for ReadSharedReq accesses 1075system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193123 # miss rate for ReadSharedReq accesses 1076system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954461 # miss rate for demand accesses 1077system.cpu.l2cache.demand_miss_rate::cpu.data 0.219706 # miss rate for demand accesses 1078system.cpu.l2cache.demand_miss_rate::total 0.219752 # miss rate for demand accesses 1079system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954461 # miss rate for overall accesses 1080system.cpu.l2cache.overall_miss_rate::cpu.data 0.219706 # miss rate for overall accesses 1081system.cpu.l2cache.overall_miss_rate::total 0.219752 # miss rate for overall accesses 1082system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21277.777778 # average UpgradeReq miss latency 1083system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21277.777778 # average UpgradeReq miss latency 1084system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102004.547822 # average ReadExReq miss latency 1085system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102004.547822 # average ReadExReq miss latency 1086system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72541.869523 # average ReadCleanReq miss latency 1087system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72541.869523 # average ReadCleanReq miss latency 1088system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86243.800349 # average ReadSharedReq miss latency 1089system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86243.800349 # average ReadSharedReq miss latency 1090system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72541.869523 # average overall miss latency 1091system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90381.167213 # average overall miss latency 1092system.cpu.l2cache.demand_avg_miss_latency::total 90376.264406 # average overall miss latency 1093system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72541.869523 # average overall miss latency 1094system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90381.167213 # average overall miss latency 1095system.cpu.l2cache.overall_avg_miss_latency::total 90376.264406 # average overall miss latency 1096system.cpu.l2cache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked |
| 1092system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 1097system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 1093system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked | 1098system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked |
| 1094system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 1099system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 1095system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked | 1100system.cpu.l2cache.avg_blocked_cycles::no_mshrs 70.200000 # average number of cycles each access was blocked |
| 1096system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1101system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1097system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference 1098system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks 1099system.cpu.l2cache.writebacks::total 1635896 # number of writebacks 1100system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits 1101system.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits 1102system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1103system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1104system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits 1105system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45253 # number of ReadSharedReq MSHR hits 1106system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1107system.cpu.l2cache.demand_mshr_hits::cpu.data 49168 # number of demand (read+write) MSHR hits 1108system.cpu.l2cache.demand_mshr_hits::total 49169 # number of demand (read+write) MSHR hits 1109system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1110system.cpu.l2cache.overall_mshr_hits::cpu.data 49168 # number of overall MSHR hits 1111system.cpu.l2cache.overall_mshr_hits::total 49169 # number of overall MSHR hits 1112system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of HardPFReq MSHR misses 1113system.cpu.l2cache.HardPFReq_mshr_misses::total 1145204 # number of HardPFReq MSHR misses 1114system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 1115system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 1116system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976631 # number of ReadExReq MSHR misses 1117system.cpu.l2cache.ReadExReq_mshr_misses::total 976631 # number of ReadExReq MSHR misses 1118system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1019 # number of ReadCleanReq MSHR misses 1119system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1019 # number of ReadCleanReq MSHR misses 1120system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2698969 # number of ReadSharedReq MSHR misses 1121system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2698969 # number of ReadSharedReq MSHR misses 1122system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses 1123system.cpu.l2cache.demand_mshr_misses::cpu.data 3675600 # number of demand (read+write) MSHR misses 1124system.cpu.l2cache.demand_mshr_misses::total 3676619 # number of demand (read+write) MSHR misses 1125system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses 1126system.cpu.l2cache.overall_mshr_misses::cpu.data 3675600 # number of overall MSHR misses 1127system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of overall MSHR misses 1128system.cpu.l2cache.overall_mshr_misses::total 4821823 # number of overall MSHR misses 1129system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of HardPFReq MSHR miss cycles 1130system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72434619378 # number of HardPFReq MSHR miss cycles 1131system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 85000 # number of UpgradeReq MSHR miss cycles 1132system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 85000 # number of UpgradeReq MSHR miss cycles 1133system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92854351000 # number of ReadExReq MSHR miss cycles 1134system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92854351000 # number of ReadExReq MSHR miss cycles 1135system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66085000 # number of ReadCleanReq MSHR miss cycles 1136system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66085000 # number of ReadCleanReq MSHR miss cycles 1137system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500 # number of ReadSharedReq MSHR miss cycles 1138system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500 # number of ReadSharedReq MSHR miss cycles 1139system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66085000 # number of demand (read+write) MSHR miss cycles 1140system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500 # number of demand (read+write) MSHR miss cycles 1141system.cpu.l2cache.demand_mshr_miss_latency::total 308011949500 # number of demand (read+write) MSHR miss cycles 1142system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66085000 # number of overall MSHR miss cycles 1143system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500 # number of overall MSHR miss cycles 1144system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of overall MSHR miss cycles 1145system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878 # number of overall MSHR miss cycles | 1102system.cpu.l2cache.unused_prefetches 58014 # number of HardPF blocks evicted w/o reference 1103system.cpu.l2cache.writebacks::writebacks 1634499 # number of writebacks 1104system.cpu.l2cache.writebacks::total 1634499 # number of writebacks 1105system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3902 # number of ReadExReq MSHR hits 1106system.cpu.l2cache.ReadExReq_mshr_hits::total 3902 # number of ReadExReq MSHR hits 1107system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45668 # number of ReadSharedReq MSHR hits 1108system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45668 # number of ReadSharedReq MSHR hits 1109system.cpu.l2cache.demand_mshr_hits::cpu.data 49570 # number of demand (read+write) MSHR hits 1110system.cpu.l2cache.demand_mshr_hits::total 49570 # number of demand (read+write) MSHR hits 1111system.cpu.l2cache.overall_mshr_hits::cpu.data 49570 # number of overall MSHR hits 1112system.cpu.l2cache.overall_mshr_hits::total 49570 # number of overall MSHR hits 1113system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1198249 # number of HardPFReq MSHR misses 1114system.cpu.l2cache.HardPFReq_mshr_misses::total 1198249 # number of HardPFReq MSHR misses 1115system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses 1116system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses 1117system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976787 # number of ReadExReq MSHR misses 1118system.cpu.l2cache.ReadExReq_mshr_misses::total 976787 # number of ReadExReq MSHR misses 1119system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1027 # number of ReadCleanReq MSHR misses 1120system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1027 # number of ReadCleanReq MSHR misses 1121system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709447 # number of ReadSharedReq MSHR misses 1122system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709447 # number of ReadSharedReq MSHR misses 1123system.cpu.l2cache.demand_mshr_misses::cpu.inst 1027 # number of demand (read+write) MSHR misses 1124system.cpu.l2cache.demand_mshr_misses::cpu.data 3686234 # number of demand (read+write) MSHR misses 1125system.cpu.l2cache.demand_mshr_misses::total 3687261 # number of demand (read+write) MSHR misses 1126system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses 1127system.cpu.l2cache.overall_mshr_misses::cpu.data 3686234 # number of overall MSHR misses 1128system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1198249 # number of overall MSHR misses 1129system.cpu.l2cache.overall_mshr_misses::total 4885510 # number of overall MSHR misses 1130system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 73218164638 # number of HardPFReq MSHR miss cycles 1131system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 73218164638 # number of HardPFReq MSHR miss cycles 1132system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 137500 # number of UpgradeReq MSHR miss cycles 1133system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 137500 # number of UpgradeReq MSHR miss cycles 1134system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93806338999 # number of ReadExReq MSHR miss cycles 1135system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93806338999 # number of ReadExReq MSHR miss cycles 1136system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68350500 # number of ReadCleanReq MSHR miss cycles 1137system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68350500 # number of ReadCleanReq MSHR miss cycles 1138system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 218529981999 # number of ReadSharedReq MSHR miss cycles 1139system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 218529981999 # number of ReadSharedReq MSHR miss cycles 1140system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68350500 # number of demand (read+write) MSHR miss cycles 1141system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312336320998 # number of demand (read+write) MSHR miss cycles 1142system.cpu.l2cache.demand_mshr_miss_latency::total 312404671498 # number of demand (read+write) MSHR miss cycles 1143system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68350500 # number of overall MSHR miss cycles 1144system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312336320998 # number of overall MSHR miss cycles 1145system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 73218164638 # number of overall MSHR miss cycles 1146system.cpu.l2cache.overall_mshr_miss_latency::total 385622836136 # number of overall MSHR miss cycles |
| 1146system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1147system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1148system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1149system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses | 1147system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1148system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1149system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1150system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses |
| 1150system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses 1151system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses 1152system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses 1153system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses 1154system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses 1155system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses 1156system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses 1158system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses 1159system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses 1160system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses | 1151system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356810 # mshr miss rate for ReadExReq accesses 1152system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356810 # mshr miss rate for ReadExReq accesses 1153system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for ReadCleanReq accesses 1154system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954461 # mshr miss rate for ReadCleanReq accesses 1155system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189922 # mshr miss rate for ReadSharedReq accesses 1156system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189922 # mshr miss rate for ReadSharedReq accesses 1157system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for demand accesses 1158system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for demand accesses 1159system.cpu.l2cache.demand_mshr_miss_rate::total 0.216837 # mshr miss rate for demand accesses 1160system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for overall accesses 1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for overall accesses |
| 1161system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1162system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1162system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses 1163system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency 1164system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency 1165system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency 1166system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency 1167system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency 1168system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency 1169system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency 1170system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency 1171system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency 1172system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency 1173system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency 1174system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency 1176system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency 1180system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. 1181system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1182system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1183system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. 1184system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1185system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1186system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 1187system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution | 1163system.cpu.l2cache.overall_mshr_miss_rate::total 0.287303 # mshr miss rate for overall accesses 1164system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average HardPFReq mshr miss latency 1165system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61104.298554 # average HardPFReq mshr miss latency 1166system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency 1167system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency 1168system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96035.613700 # average ReadExReq mshr miss latency 1169system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96035.613700 # average ReadExReq mshr miss latency 1170system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66553.554041 # average ReadCleanReq mshr miss latency 1171system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66553.554041 # average ReadCleanReq mshr miss latency 1172system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80654.828088 # average ReadSharedReq mshr miss latency 1173system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80654.828088 # average ReadSharedReq mshr miss latency 1174system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency 1175system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency 1176system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84725.402270 # average overall mshr miss latency 1177system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average overall mshr miss latency 1180system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78931.951042 # average overall mshr miss latency 1181system.cpu.toL2Bus.snoop_filter.tot_requests 34008488 # Total number of requests made to the snoop filter. 1182system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003756 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1183system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1184system.cpu.toL2Bus.snoop_filter.tot_snoops 201663 # Total number of snoops made to the snoop filter. 1185system.cpu.toL2Bus.snoop_filter.hit_single_snoops 201662 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1186system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1187system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 1188system.cpu.toL2Bus.trans_dist::ReadResp 14267181 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::WritebackDirty 6469733 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::WritebackClean 12168504 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::CleanEvict 3012569 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::HardPFReq 1490485 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution 1195system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution 1196system.cpu.toL2Bus.trans_dist::ReadExReq 2737555 # Transaction distribution 1197system.cpu.toL2Bus.trans_dist::ReadExResp 2737555 # Transaction distribution |
| 1197system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution | 1198system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution |
| 1198system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution 1199system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes) 1200system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes) 1201system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes) 1202system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes) 1203system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes) 1204system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes) 1205system.cpu.toL2Bus.snoops 8842499 # Total snoops (count) 1206system.cpu.toL2Bus.snoopTraffic 104697920 # Total snoop traffic (bytes) 1207system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram 1208system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram | 1199system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266107 # Transaction distribution 1200system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2738 # Packet count per connected master and slave (bytes) 1201system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51010503 # Packet count per connected master and slave (bytes) 1202system.cpu.toL2Bus.pkt_count::total 51013241 # Packet count per connected master and slave (bytes) 1203system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106368 # Cumulative packet size per connected master and slave (bytes) 1204system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176436672 # Cumulative packet size per connected master and slave (bytes) 1205system.cpu.toL2Bus.pkt_size::total 2176543040 # Cumulative packet size per connected master and slave (bytes) 1206system.cpu.toL2Bus.snoops 6137564 # Total snoops (count) 1207system.cpu.toL2Bus.snoopTraffic 104608640 # Total snoop traffic (bytes) 1208system.cpu.toL2Bus.snoop_fanout::samples 23142303 # Request fanout histogram 1209system.cpu.toL2Bus.snoop_fanout::mean 0.009630 # Request fanout histogram 1210system.cpu.toL2Bus.snoop_fanout::stdev 0.097659 # Request fanout histogram |
| 1210system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1211system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1211system.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram 1212system.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram | 1212system.cpu.toL2Bus.snoop_fanout::0 22919446 99.04% 99.04% # Request fanout histogram 1213system.cpu.toL2Bus.snoop_fanout::1 222856 0.96% 100.00% # Request fanout histogram 1214system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram |
| 1214system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1215system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1216system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1215system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1216system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1217system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1217system.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram 1218system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) | 1218system.cpu.toL2Bus.snoop_fanout::total 23142303 # Request fanout histogram 1219system.cpu.toL2Bus.reqLayer0.occupancy 34007983525 # Layer occupancy (ticks) |
| 1219system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) | 1220system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) |
| 1220system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) | 1221system.cpu.toL2Bus.snoopLayer0.occupancy 16538 # Layer occupancy (ticks) |
| 1221system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) | 1222system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) |
| 1222system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) | 1223system.cpu.toL2Bus.respLayer0.occupancy 1611000 # Layer occupancy (ticks) |
| 1223system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 1224system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 1224system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) | 1225system.cpu.toL2Bus.respLayer1.occupancy 25505500994 # Layer occupancy (ticks) |
| 1225system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) | 1226system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) |
| 1226system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states 1227system.membus.trans_dist::ReadResp 3696594 # Transaction distribution 1228system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution 1229system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution 1230system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 1231system.membus.trans_dist::ReadExReq 976790 # Transaction distribution 1232system.membus.trans_dist::ReadExResp 976790 # Transaction distribution 1233system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution 1234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) 1235system.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes) 1236system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes) 1237system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes) | 1227system.membus.snoop_filter.tot_requests 9332231 # Total number of requests made to the snoop filter. 1228system.membus.snoop_filter.hit_single_requests 4668264 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1229system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1230system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1231system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1232system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1233system.membus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states 1234system.membus.trans_dist::ReadResp 3708204 # Transaction distribution 1235system.membus.trans_dist::WritebackDirty 1634499 # Transaction distribution 1236system.membus.trans_dist::CleanEvict 3012569 # Transaction distribution 1237system.membus.trans_dist::UpgradeReq 9 # Transaction distribution 1238system.membus.trans_dist::ReadExReq 976948 # Transaction distribution 1239system.membus.trans_dist::ReadExResp 976948 # Transaction distribution 1240system.membus.trans_dist::ReadSharedReq 3708206 # Transaction distribution 1241system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14017383 # Packet count per connected master and slave (bytes) 1242system.membus.pkt_count::total 14017383 # Packet count per connected master and slave (bytes) 1243system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404457664 # Cumulative packet size per connected master and slave (bytes) 1244system.membus.pkt_size::total 404457664 # Cumulative packet size per connected master and slave (bytes) |
| 1238system.membus.snoops 0 # Total snoops (count) 1239system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1245system.membus.snoops 0 # Total snoops (count) 1246system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1240system.membus.snoop_fanout::samples 9311100 # Request fanout histogram | 1247system.membus.snoop_fanout::samples 4685163 # Request fanout histogram |
| 1241system.membus.snoop_fanout::mean 0 # Request fanout histogram 1242system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1243system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1248system.membus.snoop_fanout::mean 0 # Request fanout histogram 1249system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1250system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1244system.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram | 1251system.membus.snoop_fanout::0 4685163 100.00% 100.00% # Request fanout histogram |
| 1245system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1246system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1247system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1248system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1252system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1253system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1254system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1255system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1249system.membus.snoop_fanout::total 9311100 # Request fanout histogram 1250system.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks) | 1256system.membus.snoop_fanout::total 4685163 # Request fanout histogram 1257system.membus.reqLayer0.occupancy 17662405597 # Layer occupancy (ticks) |
| 1251system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) | 1258system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) |
| 1252system.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks) | 1259system.membus.respLayer1.occupancy 25476549560 # Layer occupancy (ticks) |
| 1253system.membus.respLayer1.utilization 3.3 # Layer utilization (%) 1254 1255---------- End Simulation Statistics ---------- | 1260system.membus.respLayer1.utilization 3.3 # Layer utilization (%) 1261 1262---------- End Simulation Statistics ---------- |