| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.767804 # Number of seconds simulated 4sim_ticks 767803843500 # Number of ticks simulated 5final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.767804 # Number of seconds simulated 4sim_ticks 767803843500 # Number of ticks simulated 5final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 232866 # Simulator instruction rate (inst/s) 8host_op_rate 250878 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 115757951 # Simulator tick rate (ticks/s) 10host_mem_usage 355612 # Number of bytes of host memory used 11host_seconds 6632.84 # Real time elapsed on the host | 7host_inst_rate 232978 # Simulator instruction rate (inst/s) 8host_op_rate 250999 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 115813638 # Simulator tick rate (ticks/s) 10host_mem_usage 356264 # Number of bytes of host memory used 11host_seconds 6629.65 # Real time elapsed on the host |
| 12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory 19system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory 23system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory --- 269 unchanged lines hidden (view full) --- 293system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) 294system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) 295system.physmem_1.averagePower 794.363055 # Core power per rank (mW) 296system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states 297system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states 298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states 300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory 20system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory 23system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory 24system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory --- 269 unchanged lines hidden (view full) --- 294system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) 295system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) 296system.physmem_1.averagePower 794.363055 # Core power per rank (mW) 297system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states 298system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states 299system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 300system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states 301system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 302system.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 301system.cpu.branchPred.lookups 286292198 # Number of BP lookups 302system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted 303system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect 304system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups 305system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits 306system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 307system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage 308system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. 309system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. 310system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. 311system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. 312system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. 313system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. 314system.cpu_clk_domain.clock 500 # Clock period in ticks | 303system.cpu.branchPred.lookups 286292198 # Number of BP lookups 304system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted 305system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect 306system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups 307system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits 308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 309system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage 310system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. 311system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. 312system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. 313system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. 314system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. 315system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. 316system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 317system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 315system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 336system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 337system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 338system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 339system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 340system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 341system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 342system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 343system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 318system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 339system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 340system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 341system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 342system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 343system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 344system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 345system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 346system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 347system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 344system.cpu.dtb.walker.walks 0 # Table walker walks requested 345system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 351system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 365system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 366system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 367system.cpu.dtb.read_accesses 0 # DTB read accesses 368system.cpu.dtb.write_accesses 0 # DTB write accesses 369system.cpu.dtb.inst_accesses 0 # ITB inst accesses 370system.cpu.dtb.hits 0 # DTB hits 371system.cpu.dtb.misses 0 # DTB misses 372system.cpu.dtb.accesses 0 # DTB accesses | 348system.cpu.dtb.walker.walks 0 # Table walker walks requested 349system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 351system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 352system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 353system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 354system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 355system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 369system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 370system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 371system.cpu.dtb.read_accesses 0 # DTB read accesses 372system.cpu.dtb.write_accesses 0 # DTB write accesses 373system.cpu.dtb.inst_accesses 0 # ITB inst accesses 374system.cpu.dtb.hits 0 # DTB hits 375system.cpu.dtb.misses 0 # DTB misses 376system.cpu.dtb.accesses 0 # DTB accesses |
| 377system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 373system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 394system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 395system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 397system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 398system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 399system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 400system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 401system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 378system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 382system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 383system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 384system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 385system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 399system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 400system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 401system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 402system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 403system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 404system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 405system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 406system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 407system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 402system.cpu.itb.walker.walks 0 # Table walker walks requested 403system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 409system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 424system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 425system.cpu.itb.read_accesses 0 # DTB read accesses 426system.cpu.itb.write_accesses 0 # DTB write accesses 427system.cpu.itb.inst_accesses 0 # ITB inst accesses 428system.cpu.itb.hits 0 # DTB hits 429system.cpu.itb.misses 0 # DTB misses 430system.cpu.itb.accesses 0 # DTB accesses 431system.cpu.workload.num_syscalls 46 # Number of system calls | 408system.cpu.itb.walker.walks 0 # Table walker walks requested 409system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 410system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 411system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 412system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 413system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 414system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 415system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 430system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 431system.cpu.itb.read_accesses 0 # DTB read accesses 432system.cpu.itb.write_accesses 0 # DTB write accesses 433system.cpu.itb.inst_accesses 0 # ITB inst accesses 434system.cpu.itb.hits 0 # DTB hits 435system.cpu.itb.misses 0 # DTB misses 436system.cpu.itb.accesses 0 # DTB accesses 437system.cpu.workload.num_syscalls 46 # Number of system calls |
| 438system.cpu.pwrStateResidencyTicks::ON 767803843500 # Cumulative time (in ticks) in various power states |
|
| 432system.cpu.numCycles 1535607688 # number of cpu cycles simulated 433system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 434system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 435system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss 436system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed 437system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered 438system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken 439system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 713system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads 714system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes 715system.cpu.fp_regfile_reads 42 # number of floating regfile reads 716system.cpu.fp_regfile_writes 54 # number of floating regfile writes 717system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads 718system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes 719system.cpu.misc_regfile_reads 675853616 # number of misc regfile reads 720system.cpu.misc_regfile_writes 124 # number of misc regfile writes | 439system.cpu.numCycles 1535607688 # number of cpu cycles simulated 440system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 441system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 442system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss 443system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed 444system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered 445system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken 446system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 720system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads 721system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes 722system.cpu.fp_regfile_reads 42 # number of floating regfile reads 723system.cpu.fp_regfile_writes 54 # number of floating regfile writes 724system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads 725system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes 726system.cpu.misc_regfile_reads 675853616 # number of misc regfile reads 727system.cpu.misc_regfile_writes 124 # number of misc regfile writes |
| 728system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 721system.cpu.dcache.tags.replacements 17003710 # number of replacements 722system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use 723system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. 724system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. 725system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. 726system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. 727system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor 728system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy 729system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy 730system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 731system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id 732system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 733system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 734system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses 735system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses | 729system.cpu.dcache.tags.replacements 17003710 # number of replacements 730system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use 731system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. 732system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. 733system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. 734system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. 735system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor 736system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy 737system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy 738system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 739system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id 740system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 741system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 742system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses 743system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses |
| 744system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 736system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits 737system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits 738system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits 739system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits 740system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 741system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 742system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 743system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits --- 112 unchanged lines hidden (view full) --- 856system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency 857system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency 858system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency 859system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency 860system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency 861system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency 862system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency 863system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency | 745system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits 746system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits 747system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits 748system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits 749system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 750system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 751system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 752system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits --- 112 unchanged lines hidden (view full) --- 865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency 866system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency 867system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency 868system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency 869system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency 870system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency 871system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency 872system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency |
| 873system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 864system.cpu.icache.tags.replacements 589 # number of replacements 865system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use 866system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. 867system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. 868system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. 869system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 870system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor 871system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy 872system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy 873system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id 874system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 875system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 876system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id 877system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id 878system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses 879system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses | 874system.cpu.icache.tags.replacements 589 # number of replacements 875system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use 876system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. 877system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. 878system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. 879system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 880system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor 881system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy 882system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy 883system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id 884system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 885system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 886system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id 887system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id 888system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses 889system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses |
| 890system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 880system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits 881system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits 882system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits 883system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits 884system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits 885system.cpu.icache.overall_hits::total 656966815 # number of overall hits 886system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses 887system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 946system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 947system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 948system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency 949system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency 950system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 951system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency 952system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 953system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency | 891system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits 892system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits 893system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits 894system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits 895system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits 896system.cpu.icache.overall_hits::total 656966815 # number of overall hits 897system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses 898system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 957system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 958system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 959system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency 960system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency 961system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 962system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency 963system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 964system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency |
| 965system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 954system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued 955system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified 956system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue 957system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 958system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 959system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing | 966system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued 967system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified 968system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue 969system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 970system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 971system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing |
| 972system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 960system.cpu.l2cache.tags.replacements 4706089 # number of replacements 961system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use 962system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. 963system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks. 964system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks. 965system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit. 966system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor 967system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor --- 11 unchanged lines hidden (view full) --- 979system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id 983system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id 984system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id 985system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses 986system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses | 973system.cpu.l2cache.tags.replacements 4706089 # number of replacements 974system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use 975system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. 976system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks. 977system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks. 978system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit. 979system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor 980system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor --- 11 unchanged lines hidden (view full) --- 992system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id 993system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id 994system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id 995system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id 996system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id 997system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id 998system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses 999system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses |
| 1000system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 987system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits 988system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits 989system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits 990system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits 991system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits 992system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits 993system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits 994system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits --- 169 unchanged lines hidden (view full) --- 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency 1166system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. 1167system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1168system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1169system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. 1170system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1171system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1001system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits 1002system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits 1003system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits 1004system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits 1005system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits 1006system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits 1007system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits 1008system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits --- 169 unchanged lines hidden (view full) --- 1178system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency 1179system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency 1180system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. 1181system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1182system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1183system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. 1184system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1185system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1186system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 1172system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution --- 22 unchanged lines hidden (view full) --- 1202system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) 1203system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) 1204system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) 1205system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1206system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) 1207system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1208system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) 1209system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) | 1187system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution 1188system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution 1189system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution 1190system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution 1191system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution 1192system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution 1193system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution 1194system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution --- 22 unchanged lines hidden (view full) --- 1217system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) 1218system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) 1219system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) 1220system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1221system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) 1222system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1223system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) 1224system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) |
| 1225system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states |
|
| 1210system.membus.trans_dist::ReadResp 3696594 # Transaction distribution 1211system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution 1212system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution 1213system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 1214system.membus.trans_dist::ReadExReq 976790 # Transaction distribution 1215system.membus.trans_dist::ReadExResp 976790 # Transaction distribution 1216system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution 1217system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- | 1226system.membus.trans_dist::ReadResp 3696594 # Transaction distribution 1227system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution 1228system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution 1229system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 1230system.membus.trans_dist::ReadExReq 976790 # Transaction distribution 1231system.membus.trans_dist::ReadExResp 976790 # Transaction distribution 1232system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution 1233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) --- 20 unchanged lines hidden --- |