Cross Reference: /gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

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stats.txt (11456:c0fb4435b80f)	stats.txt (11502:e273e86a873d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.767804 # Number of seconds simulated 4sim_ticks 767803843500 # Number of ticks simulated 5final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 224780 # Simulator instruction rate (inst/s) 8host_op_rate 242166 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 111738196 # Simulator tick rate (ticks/s) 10host_mem_usage 312364 # Number of bytes of host memory used 11host_seconds 6871.45 # Real time elapsed on the host 12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory 19system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory 23system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 4673385 # Number of read requests accepted 44system.physmem.writeReqs 1635896 # Number of write requests accepted 45system.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue 49system.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 301126 # Per bank write bursts 56system.physmem.perBankRdBursts::1 298685 # Per bank write bursts 57system.physmem.perBankRdBursts::2 284250 # Per bank write bursts 58system.physmem.perBankRdBursts::3 287696 # Per bank write bursts 59system.physmem.perBankRdBursts::4 287908 # Per bank write bursts 60system.physmem.perBankRdBursts::5 285921 # Per bank write bursts 61system.physmem.perBankRdBursts::6 280645 # Per bank write bursts 62system.physmem.perBankRdBursts::7 277366 # Per bank write bursts 63system.physmem.perBankRdBursts::8 293768 # Per bank write bursts 64system.physmem.perBankRdBursts::9 299240 # Per bank write bursts 65system.physmem.perBankRdBursts::10 292091 # Per bank write bursts 66system.physmem.perBankRdBursts::11 297828 # Per bank write bursts 67system.physmem.perBankRdBursts::12 299005 # Per bank write bursts 68system.physmem.perBankRdBursts::13 298032 # Per bank write bursts 69system.physmem.perBankRdBursts::14 293386 # Per bank write bursts 70system.physmem.perBankRdBursts::15 288652 # Per bank write bursts 71system.physmem.perBankWrBursts::0 103980 # Per bank write bursts 72system.physmem.perBankWrBursts::1 101811 # Per bank write bursts 73system.physmem.perBankWrBursts::2 99205 # Per bank write bursts 74system.physmem.perBankWrBursts::3 99712 # Per bank write bursts 75system.physmem.perBankWrBursts::4 99000 # Per bank write bursts 76system.physmem.perBankWrBursts::5 99026 # Per bank write bursts 77system.physmem.perBankWrBursts::6 102693 # Per bank write bursts 78system.physmem.perBankWrBursts::7 104157 # Per bank write bursts 79system.physmem.perBankWrBursts::8 105172 # Per bank write bursts 80system.physmem.perBankWrBursts::9 104159 # Per bank write bursts 81system.physmem.perBankWrBursts::10 102137 # Per bank write bursts 82system.physmem.perBankWrBursts::11 102620 # Per bank write bursts 83system.physmem.perBankWrBursts::12 102863 # Per bank write bursts 84system.physmem.perBankWrBursts::13 102594 # Per bank write bursts 85system.physmem.perBankWrBursts::14 104213 # Per bank write bursts 86system.physmem.perBankWrBursts::15 102497 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 767803802500 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 4673385 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 1635896 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes 232system.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads 238system.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads 239system.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads 251system.physmem.totQLat 128478496877 # Total ticks spent queuing 252system.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM 253system.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers 254system.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst 255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 256system.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst 257system.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s 258system.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s 259system.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s 260system.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s 261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 262system.physmem.busUtil 4.10 # Data bus utilization in percentage 263system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads 264system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes 265system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing 266system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing 267system.physmem.readRowHits 1710736 # Number of row buffer hits during reads 268system.physmem.writeRowHits 347188 # Number of row buffer hits during writes 269system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads 270system.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes 271system.physmem.avgGap 121694.34 # Average gap between requests 272system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined 273system.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ) 274system.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ) 275system.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ) 276system.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ) 277system.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) 278system.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ) 279system.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ) 280system.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ) 281system.physmem_0.averagePower 793.947771 # Core power per rank (mW) 282system.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states 283system.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states 284system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states 286system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 287system.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ) 288system.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ) 289system.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ) 290system.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ) 291system.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ) 292system.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ) 293system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ) 294system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ) 295system.physmem_1.averagePower 794.363055 # Core power per rank (mW) 296system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states 297system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states 298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 299system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states 300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 301system.cpu.branchPred.lookups 286292198 # Number of BP lookups 302system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted 303system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect 304system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups 305system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits 306system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 307system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage 308system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target. 309system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions. 310system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups. 311system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits. 312system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses. 313system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches. 314system.cpu_clk_domain.clock 500 # Clock period in ticks 315system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 323system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 324system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 325system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 326system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 327system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 328system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 329system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 330system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 331system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 332system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 333system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 334system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 335system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 336system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 337system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 338system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 339system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 340system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 341system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 342system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 343system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 344system.cpu.dtb.walker.walks 0 # Table walker walks requested 345system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 351system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 352system.cpu.dtb.inst_hits 0 # ITB inst hits 353system.cpu.dtb.inst_misses 0 # ITB inst misses 354system.cpu.dtb.read_hits 0 # DTB read hits 355system.cpu.dtb.read_misses 0 # DTB read misses 356system.cpu.dtb.write_hits 0 # DTB write hits 357system.cpu.dtb.write_misses 0 # DTB write misses 358system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 359system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 360system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 361system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 362system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 363system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 364system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 365system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 366system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 367system.cpu.dtb.read_accesses 0 # DTB read accesses 368system.cpu.dtb.write_accesses 0 # DTB write accesses 369system.cpu.dtb.inst_accesses 0 # ITB inst accesses 370system.cpu.dtb.hits 0 # DTB hits 371system.cpu.dtb.misses 0 # DTB misses 372system.cpu.dtb.accesses 0 # DTB accesses 373system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 381system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 382system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 383system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 384system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 385system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 386system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 387system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 388system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 389system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 390system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 391system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 392system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 393system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 394system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 395system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 397system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 398system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 399system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 400system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 401system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 402system.cpu.itb.walker.walks 0 # Table walker walks requested 403system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 404system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 409system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 410system.cpu.itb.inst_hits 0 # ITB inst hits 411system.cpu.itb.inst_misses 0 # ITB inst misses 412system.cpu.itb.read_hits 0 # DTB read hits 413system.cpu.itb.read_misses 0 # DTB read misses 414system.cpu.itb.write_hits 0 # DTB write hits 415system.cpu.itb.write_misses 0 # DTB write misses 416system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 417system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 418system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 419system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 420system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 421system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 422system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 423system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 424system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 425system.cpu.itb.read_accesses 0 # DTB read accesses 426system.cpu.itb.write_accesses 0 # DTB write accesses 427system.cpu.itb.inst_accesses 0 # ITB inst accesses 428system.cpu.itb.hits 0 # DTB hits 429system.cpu.itb.misses 0 # DTB misses 430system.cpu.itb.accesses 0 # DTB accesses 431system.cpu.workload.num_syscalls 46 # Number of system calls 432system.cpu.numCycles 1535607688 # number of cpu cycles simulated 433system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 434system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 435system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss 436system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed 437system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered 438system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken 439system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked 440system.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing 441system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 442system.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR 443system.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched 444system.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed 445system.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total) 446system.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total) 447system.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total) 457system.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle 458system.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle 459system.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle 460system.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked 461system.cpu.decode.RunCycles 849925630 # Number of cycles decode is running 462system.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking 463system.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing 464system.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch 465system.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction 466system.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode 467system.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode 468system.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing 469system.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle 470system.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking 471system.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst 472system.cpu.rename.RunCycles 837854747 # Number of cycles rename is running 473system.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking 474system.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename 475system.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename 476system.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full 477system.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full 478system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full 479system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full 480system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed 481system.cpu.rename.RenameLookups 9128568325 # Number of register rename lookups that rename has made 482system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups 483system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups 484system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed 485system.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing 486system.cpu.rename.serializingInsts 174 # count of serializing insts renamed 487system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed 488system.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer 489system.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit. 490system.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit. 491system.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads. 492system.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores. 493system.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec) 494system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ 495system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued 496system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued 497system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling 498system.cpu.iq.iqSquashedOperandsExamined 647584155 # Number of squashed operands that are examined and possibly removed from graph 499system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed 500system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle 501system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle 502system.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle 517system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 518system.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available 519system.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available 520system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available 521system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available 522system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available 524system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available 525system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available 526system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 527system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available 528system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available 546system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 547system.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available 548system.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available 549system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 550system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 551system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 552system.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued 553system.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued 554system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 555system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued 556system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 560system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued 561system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued 562system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued 581system.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued 582system.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued 583system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 584system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 585system.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued 586system.cpu.iq.rate 1.209614 # Inst issue rate 587system.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested 588system.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst) 589system.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads 590system.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes 591system.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses 592system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads 593system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes 594system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses 595system.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses 596system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses 597system.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores 598system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 599system.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed 600system.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed 601system.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations 602system.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed 603system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 604system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 605system.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled 606system.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked 607system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 608system.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing 609system.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking 610system.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking 611system.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ 612system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 613system.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions 614system.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions 615system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions 616system.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall 617system.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall 618system.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations 619system.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly 620system.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly 621system.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute 622system.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions 623system.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed 624system.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute 625system.cpu.iew.exec_swp 0 # number of swp insts executed 626system.cpu.iew.exec_nop 146 # number of nop insts executed 627system.cpu.iew.exec_refs 698692225 # number of memory reference insts executed 628system.cpu.iew.exec_branches 229542687 # Number of branches executed 629system.cpu.iew.exec_stores 181751910 # Number of stores executed 630system.cpu.iew.exec_rate 1.190295 # Inst execution rate 631system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit 632system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back 633system.cpu.iew.wb_producers 1169207800 # num instructions producing a value 634system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value 635system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle 636system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back 637system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit 638system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards 639system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted 640system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle 641system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle 642system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle 643system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 644system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle 657system.cpu.commit.committedInsts 1544563042 # Number of instructions committed 658system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed 659system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 660system.cpu.commit.refs 633153379 # Number of memory references committed 661system.cpu.commit.loads 458306334 # Number of loads committed 662system.cpu.commit.membars 62 # Number of memory barriers committed 663system.cpu.commit.branches 213462427 # Number of branches committed 664system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 665system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. 666system.cpu.commit.function_calls 13665177 # Number of function calls committed. 667system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 668system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction 669system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 670system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 671system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 672system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 673system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 674system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction 676system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction 677system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction 678system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction 679system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction 680system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 696system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 697system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 698system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction 699system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 700system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 701system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction 702system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached 703system.cpu.rob.rob_reads 3360114616 # The number of ROB reads 704system.cpu.rob.rob_writes 3883791528 # The number of ROB writes 705system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself 706system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling 707system.cpu.committedInsts 1544563024 # Number of Instructions Simulated 708system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated 709system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction 710system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads 711system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle 712system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads 713system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads 714system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes 715system.cpu.fp_regfile_reads 42 # number of floating regfile reads 716system.cpu.fp_regfile_writes 54 # number of floating regfile writes 717system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads 718system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes 719system.cpu.misc_regfile_reads 675853701 # number of misc regfile reads 720system.cpu.misc_regfile_writes 124 # number of misc regfile writes 721system.cpu.dcache.tags.replacements 17003710 # number of replacements 722system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use 723system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks. 724system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks. 725system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks. 726system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit. 727system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor 728system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy 729system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy 730system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 731system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id 732system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id 733system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 734system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses 735system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses 736system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits 737system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits 738system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits 739system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits 740system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 741system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 742system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 743system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 744system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits 745system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits 746system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits 747system.cpu.dcache.overall_hits::total 638076218 # number of overall hits 748system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses 749system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses 750system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses 751system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses 752system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 753system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 754system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 755system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses 756system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses 757system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses 758system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses 759system.cpu.dcache.overall_misses::total 21285744 # number of overall misses 760system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles 761system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles 762system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles 763system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles 764system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles 765system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles 766system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles 767system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles 768system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles 769system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles 770system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses) 771system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses) 772system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 773system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 774system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) 775system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) 776system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 777system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 778system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 779system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 780system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses 781system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses 782system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses 783system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses 784system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses 785system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses 786system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses 787system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses 788system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 789system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 790system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses 791system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses 792system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses 793system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses 794system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses 795system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses 796system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency 797system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency 798system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency 799system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency 800system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency 801system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency 802system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency 803system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency 804system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency 805system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency 806system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked 807system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked 808system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked 809system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked 810system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked 811system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked 812system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks 813system.cpu.dcache.writebacks::total 17003710 # number of writebacks 814system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits 815system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits 816system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits 817system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits 818system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 819system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits 820system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits 821system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits 822system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits 823system.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits 824system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses 825system.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses 826system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses 827system.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses 828system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 829system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 830system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses 831system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses 832system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses 833system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses 834system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles 835system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles 836system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles 837system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles 838system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles 839system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles 840system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles 841system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles 842system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles 843system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles 844system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses 845system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses 846system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses 847system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses 848system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses 849system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses 850system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses 851system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses 852system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses 853system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses 854system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency 855system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency 856system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency 857system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency 858system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency 859system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency 860system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency 861system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency 862system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency 863system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency 864system.cpu.icache.tags.replacements 589 # number of replacements 865system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use 866system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. 867system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. 868system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. 869system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 870system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor 871system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy 872system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy 873system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id 874system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 875system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id 876system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id 877system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id 878system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses 879system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses 880system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits 881system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits 882system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits 883system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits 884system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits 885system.cpu.icache.overall_hits::total 656966815 # number of overall hits 886system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses 887system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses 888system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses 889system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses 890system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses 891system.cpu.icache.overall_misses::total 1620 # number of overall misses 892system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles 893system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles 894system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles 895system.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles 896system.cpu.icache.overall_miss_latency::cpu.inst 98788987 # number of overall miss cycles 897system.cpu.icache.overall_miss_latency::total 98788987 # number of overall miss cycles 898system.cpu.icache.ReadReq_accesses::cpu.inst 656968435 # number of ReadReq accesses(hits+misses) 899system.cpu.icache.ReadReq_accesses::total 656968435 # number of ReadReq accesses(hits+misses) 900system.cpu.icache.demand_accesses::cpu.inst 656968435 # number of demand (read+write) accesses 901system.cpu.icache.demand_accesses::total 656968435 # number of demand (read+write) accesses 902system.cpu.icache.overall_accesses::cpu.inst 656968435 # number of overall (read+write) accesses 903system.cpu.icache.overall_accesses::total 656968435 # number of overall (read+write) accesses 904system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 905system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 906system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 907system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 908system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 909system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 910system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173 # average ReadReq miss latency 911system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173 # average ReadReq miss latency 912system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency 913system.cpu.icache.demand_avg_miss_latency::total 60980.856173 # average overall miss latency 914system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency 915system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency 916system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked 917system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked 918system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked 919system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked 920system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked 921system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked 922system.cpu.icache.writebacks::writebacks 589 # number of writebacks 923system.cpu.icache.writebacks::total 589 # number of writebacks 924system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits 925system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits 926system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits 927system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits 928system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits 929system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits 930system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses 931system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses 932system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses 933system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses 934system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses 935system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses 936system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73759491 # number of ReadReq MSHR miss cycles 937system.cpu.icache.ReadReq_mshr_miss_latency::total 73759491 # number of ReadReq MSHR miss cycles 938system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73759491 # number of demand (read+write) MSHR miss cycles 939system.cpu.icache.demand_mshr_miss_latency::total 73759491 # number of demand (read+write) MSHR miss cycles 940system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73759491 # number of overall MSHR miss cycles 941system.cpu.icache.overall_mshr_miss_latency::total 73759491 # number of overall MSHR miss cycles 942system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 943system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 944system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 945system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 946system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 947system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 948system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency 949system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency 950system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 951system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency 952system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 953system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency 954system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued 955system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified 956system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue 957system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 958system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 959system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing 960system.cpu.l2cache.tags.replacements 4706089 # number of replacements 961system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use 962system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks. 963system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks. 964system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks. 965system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit. 966system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor 967system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor 968system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.119162 # Average occupied blocks per requestor 969system.cpu.l2cache.tags.occ_percent::writebacks 0.799460 # Average percentage of cache occupancy 970system.cpu.l2cache.tags.occ_percent::cpu.data 0.000140 # Average percentage of cache occupancy 971system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183052 # Average percentage of cache occupancy 972system.cpu.l2cache.tags.occ_percent::total 0.982651 # Average percentage of cache occupancy 973system.cpu.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id 974system.cpu.l2cache.tags.occ_task_id_blocks::1024 15097 # Occupied blocks per task id 975system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id 976system.cpu.l2cache.tags.age_task_id_blocks_1022::1 636 # Occupied blocks per task id 977system.cpu.l2cache.tags.age_task_id_blocks_1022::3 191 # Occupied blocks per task id 978system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id 979system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id 980system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id 981system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id 982system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id 983system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id 984system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id 985system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses 986system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses 987system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits 988system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits 989system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits 990system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits 991system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits 992system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits 993system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits 994system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits 995system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11522367 # number of ReadSharedReq hits 996system.cpu.l2cache.ReadSharedReq_hits::total 11522367 # number of ReadSharedReq hits 997system.cpu.l2cache.demand_hits::cpu.inst 56 # number of demand (read+write) hits 998system.cpu.l2cache.demand_hits::cpu.data 13279454 # number of demand (read+write) hits 999system.cpu.l2cache.demand_hits::total 13279510 # number of demand (read+write) hits 1000system.cpu.l2cache.overall_hits::cpu.inst 56 # number of overall hits 1001system.cpu.l2cache.overall_hits::cpu.data 13279454 # number of overall hits 1002system.cpu.l2cache.overall_hits::total 13279510 # number of overall hits 1003system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses 1004system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses 1005system.cpu.l2cache.ReadExReq_misses::cpu.data 980546 # number of ReadExReq misses 1006system.cpu.l2cache.ReadExReq_misses::total 980546 # number of ReadExReq misses 1007system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1020 # number of ReadCleanReq misses 1008system.cpu.l2cache.ReadCleanReq_misses::total 1020 # number of ReadCleanReq misses 1009system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2744222 # number of ReadSharedReq misses 1010system.cpu.l2cache.ReadSharedReq_misses::total 2744222 # number of ReadSharedReq misses 1011system.cpu.l2cache.demand_misses::cpu.inst 1020 # number of demand (read+write) misses 1012system.cpu.l2cache.demand_misses::cpu.data 3724768 # number of demand (read+write) misses 1013system.cpu.l2cache.demand_misses::total 3725788 # number of demand (read+write) misses 1014system.cpu.l2cache.overall_misses::cpu.inst 1020 # number of overall misses 1015system.cpu.l2cache.overall_misses::cpu.data 3724768 # number of overall misses 1016system.cpu.l2cache.overall_misses::total 3725788 # number of overall misses 1017system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 121000 # number of UpgradeReq miss cycles 1018system.cpu.l2cache.UpgradeReq_miss_latency::total 121000 # number of UpgradeReq miss cycles 1019system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99083213500 # number of ReadExReq miss cycles 1020system.cpu.l2cache.ReadExReq_miss_latency::total 99083213500 # number of ReadExReq miss cycles 1021system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72272000 # number of ReadCleanReq miss cycles 1022system.cpu.l2cache.ReadCleanReq_miss_latency::total 72272000 # number of ReadCleanReq miss cycles 1023system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000 # number of ReadSharedReq miss cycles 1024system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000 # number of ReadSharedReq miss cycles 1025system.cpu.l2cache.demand_miss_latency::cpu.inst 72272000 # number of demand (read+write) miss cycles 1026system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500 # number of demand (read+write) miss cycles 1027system.cpu.l2cache.demand_miss_latency::total 333235195500 # number of demand (read+write) miss cycles 1028system.cpu.l2cache.overall_miss_latency::cpu.inst 72272000 # number of overall miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::total 333235195500 # number of overall miss cycles 1031system.cpu.l2cache.WritebackDirty_accesses::writebacks 4833112 # number of WritebackDirty accesses(hits+misses) 1032system.cpu.l2cache.WritebackDirty_accesses::total 4833112 # number of WritebackDirty accesses(hits+misses) 1033system.cpu.l2cache.WritebackClean_accesses::writebacks 12149903 # number of WritebackClean accesses(hits+misses) 1034system.cpu.l2cache.WritebackClean_accesses::total 12149903 # number of WritebackClean accesses(hits+misses) 1035system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses) 1036system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses) 1037system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737633 # number of ReadExReq accesses(hits+misses) 1038system.cpu.l2cache.ReadExReq_accesses::total 2737633 # number of ReadExReq accesses(hits+misses) 1039system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses) 1040system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses) 1041system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266589 # number of ReadSharedReq accesses(hits+misses) 1042system.cpu.l2cache.ReadSharedReq_accesses::total 14266589 # number of ReadSharedReq accesses(hits+misses) 1043system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses 1044system.cpu.l2cache.demand_accesses::cpu.data 17004222 # number of demand (read+write) accesses 1045system.cpu.l2cache.demand_accesses::total 17005298 # number of demand (read+write) accesses 1046system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses 1047system.cpu.l2cache.overall_accesses::cpu.data 17004222 # number of overall (read+write) accesses 1048system.cpu.l2cache.overall_accesses::total 17005298 # number of overall (read+write) accesses 1049system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses 1050system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses 1051system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358173 # miss rate for ReadExReq accesses 1052system.cpu.l2cache.ReadExReq_miss_rate::total 0.358173 # miss rate for ReadExReq accesses 1053system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947955 # miss rate for ReadCleanReq accesses 1054system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947955 # miss rate for ReadCleanReq accesses 1055system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192353 # miss rate for ReadSharedReq accesses 1056system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192353 # miss rate for ReadSharedReq accesses 1057system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947955 # miss rate for demand accesses 1058system.cpu.l2cache.demand_miss_rate::cpu.data 0.219050 # miss rate for demand accesses 1059system.cpu.l2cache.demand_miss_rate::total 0.219096 # miss rate for demand accesses 1060system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947955 # miss rate for overall accesses 1061system.cpu.l2cache.overall_miss_rate::cpu.data 0.219050 # miss rate for overall accesses 1062system.cpu.l2cache.overall_miss_rate::total 0.219096 # miss rate for overall accesses 1063system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency 1064system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency 1065system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158 # average ReadExReq miss latency 1066system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158 # average ReadExReq miss latency 1067system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961 # average ReadCleanReq miss latency 1068system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961 # average ReadCleanReq miss latency 1069system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742 # average ReadSharedReq miss latency 1070system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742 # average ReadSharedReq miss latency 1071system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency 1072system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency 1073system.cpu.l2cache.demand_avg_miss_latency::total 89440.192383 # average overall miss latency 1074system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency 1075system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency 1076system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency 1077system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked 1078system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1080system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked 1082system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1083system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference 1084system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks 1085system.cpu.l2cache.writebacks::total 1635896 # number of writebacks 1086system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits 1087system.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits 1088system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1089system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1090system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits 1091system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45253 # number of ReadSharedReq MSHR hits 1092system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1093system.cpu.l2cache.demand_mshr_hits::cpu.data 49168 # number of demand (read+write) MSHR hits 1094system.cpu.l2cache.demand_mshr_hits::total 49169 # number of demand (read+write) MSHR hits 1095system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1096system.cpu.l2cache.overall_mshr_hits::cpu.data 49168 # number of overall MSHR hits 1097system.cpu.l2cache.overall_mshr_hits::total 49169 # number of overall MSHR hits 1098system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of HardPFReq MSHR misses 1099system.cpu.l2cache.HardPFReq_mshr_misses::total 1145204 # number of HardPFReq MSHR misses 1100system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses 1101system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses 1102system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976631 # number of ReadExReq MSHR misses 1103system.cpu.l2cache.ReadExReq_mshr_misses::total 976631 # number of ReadExReq MSHR misses 1104system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1019 # number of ReadCleanReq MSHR misses 1105system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1019 # number of ReadCleanReq MSHR misses 1106system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2698969 # number of ReadSharedReq MSHR misses 1107system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2698969 # number of ReadSharedReq MSHR misses 1108system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses 1109system.cpu.l2cache.demand_mshr_misses::cpu.data 3675600 # number of demand (read+write) MSHR misses 1110system.cpu.l2cache.demand_mshr_misses::total 3676619 # number of demand (read+write) MSHR misses 1111system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses 1112system.cpu.l2cache.overall_mshr_misses::cpu.data 3675600 # number of overall MSHR misses 1113system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of overall MSHR misses 1114system.cpu.l2cache.overall_mshr_misses::total 4821823 # number of overall MSHR misses 1115system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of HardPFReq MSHR miss cycles 1116system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72434619378 # number of HardPFReq MSHR miss cycles 1117system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 85000 # number of UpgradeReq MSHR miss cycles 1118system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 85000 # number of UpgradeReq MSHR miss cycles 1119system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92854351000 # number of ReadExReq MSHR miss cycles 1120system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92854351000 # number of ReadExReq MSHR miss cycles 1121system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66085000 # number of ReadCleanReq MSHR miss cycles 1122system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66085000 # number of ReadCleanReq MSHR miss cycles 1123system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500 # number of ReadSharedReq MSHR miss cycles 1124system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500 # number of ReadSharedReq MSHR miss cycles 1125system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66085000 # number of demand (read+write) MSHR miss cycles 1126system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500 # number of demand (read+write) MSHR miss cycles 1127system.cpu.l2cache.demand_mshr_miss_latency::total 308011949500 # number of demand (read+write) MSHR miss cycles 1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66085000 # number of overall MSHR miss cycles 1129system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500 # number of overall MSHR miss cycles 1130system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of overall MSHR miss cycles 1131system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878 # number of overall MSHR miss cycles 1132system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1133system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1134system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses 1135system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses 1136system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses 1137system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses 1138system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses 1139system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses 1140system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses 1141system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses 1142system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses 1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses 1144system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses 1145system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses 1146system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses 1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1148system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses 1149system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency 1150system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency 1151system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency 1152system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency 1153system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency 1154system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency 1155system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency 1156system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency 1157system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency 1158system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency 1166system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. 1167system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1168system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1169system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. 1170system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1171system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1172system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution 1174system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution 1175system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution 1176system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution 1177system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution 1178system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution 1179system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution 1180system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution 1181system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution 1183system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution 1184system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes) 1185system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes) 1186system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes) 1187system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes) 1188system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes) 1189system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes) 1190system.cpu.toL2Bus.snoops 8842499 # Total snoops (count) 1191system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram 1192system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram 1193system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram 1194system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1195system.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram 1196system.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram 1197system.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram 1198system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1199system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1200system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1201system.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram 1202system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks) 1203system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%) 1204system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks) 1205system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) 1206system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks) 1207system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1208system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks) 1209system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%) 1210system.membus.trans_dist::ReadResp 3696594 # Transaction distribution 1211system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution 1212system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution 1213system.membus.trans_dist::UpgradeReq 6 # Transaction distribution 1214system.membus.trans_dist::ReadExReq 976790 # Transaction distribution 1215system.membus.trans_dist::ReadExResp 976790 # Transaction distribution 1216system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution 1217system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes) 1218system.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes) 1219system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes) 1220system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes) 1221system.membus.snoops 0 # Total snoops (count) 1222system.membus.snoop_fanout::samples 9311100 # Request fanout histogram 1223system.membus.snoop_fanout::mean 0 # Request fanout histogram 1224system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1225system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1226system.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram 1227system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1228system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1229system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1230system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1231system.membus.snoop_fanout::total 9311100 # Request fanout histogram 1232system.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks) 1233system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) 1234system.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks) 1235system.membus.respLayer1.utilization 3.3 # Layer utilization (%) 1236 1237---------- End Simulation Statistics ----------

stats.txt (11456:c0fb4435b80f)

stats.txt (11502:e273e86a873d)

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.767804 # Number of seconds simulated
4sim_ticks 767803843500 # Number of ticks simulated
5final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 224780 # Simulator instruction rate (inst/s)
8host_op_rate 242166 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 111738196 # Simulator tick rate (ticks/s)
10host_mem_usage 312364 # Number of bytes of host memory used
11host_seconds 6871.45 # Real time elapsed on the host
12sim_insts 1544563024 # Number of instructions simulated
13sim_ops 1664032416 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory
19system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory
23system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 4673385 # Number of read requests accepted
44system.physmem.writeReqs 1635896 # Number of write requests accepted
45system.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue
49system.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 301126 # Per bank write bursts
56system.physmem.perBankRdBursts::1 298685 # Per bank write bursts
57system.physmem.perBankRdBursts::2 284250 # Per bank write bursts
58system.physmem.perBankRdBursts::3 287696 # Per bank write bursts
59system.physmem.perBankRdBursts::4 287908 # Per bank write bursts
60system.physmem.perBankRdBursts::5 285921 # Per bank write bursts
61system.physmem.perBankRdBursts::6 280645 # Per bank write bursts
62system.physmem.perBankRdBursts::7 277366 # Per bank write bursts
63system.physmem.perBankRdBursts::8 293768 # Per bank write bursts
64system.physmem.perBankRdBursts::9 299240 # Per bank write bursts
65system.physmem.perBankRdBursts::10 292091 # Per bank write bursts
66system.physmem.perBankRdBursts::11 297828 # Per bank write bursts
67system.physmem.perBankRdBursts::12 299005 # Per bank write bursts
68system.physmem.perBankRdBursts::13 298032 # Per bank write bursts
69system.physmem.perBankRdBursts::14 293386 # Per bank write bursts
70system.physmem.perBankRdBursts::15 288652 # Per bank write bursts
71system.physmem.perBankWrBursts::0 103980 # Per bank write bursts
72system.physmem.perBankWrBursts::1 101811 # Per bank write bursts
73system.physmem.perBankWrBursts::2 99205 # Per bank write bursts
74system.physmem.perBankWrBursts::3 99712 # Per bank write bursts
75system.physmem.perBankWrBursts::4 99000 # Per bank write bursts
76system.physmem.perBankWrBursts::5 99026 # Per bank write bursts
77system.physmem.perBankWrBursts::6 102693 # Per bank write bursts
78system.physmem.perBankWrBursts::7 104157 # Per bank write bursts
79system.physmem.perBankWrBursts::8 105172 # Per bank write bursts
80system.physmem.perBankWrBursts::9 104159 # Per bank write bursts
81system.physmem.perBankWrBursts::10 102137 # Per bank write bursts
82system.physmem.perBankWrBursts::11 102620 # Per bank write bursts
83system.physmem.perBankWrBursts::12 102863 # Per bank write bursts
84system.physmem.perBankWrBursts::13 102594 # Per bank write bursts
85system.physmem.perBankWrBursts::14 104213 # Per bank write bursts
86system.physmem.perBankWrBursts::15 102497 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89system.physmem.totGap 767803802500 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 4673385 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 1635896 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes
222system.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes
223system.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes
224system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes
232system.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads
251system.physmem.totQLat 128478496877 # Total ticks spent queuing
252system.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM
253system.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers
254system.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst
255system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
256system.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst
257system.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s
258system.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s
259system.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s
260system.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s
261system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
262system.physmem.busUtil 4.10 # Data bus utilization in percentage
263system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads
264system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes
265system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing
266system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing
267system.physmem.readRowHits 1710736 # Number of row buffer hits during reads
268system.physmem.writeRowHits 347188 # Number of row buffer hits during writes
269system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads
270system.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes
271system.physmem.avgGap 121694.34 # Average gap between requests
272system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined
273system.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ)
274system.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ)
275system.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ)
276system.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ)
277system.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ)
278system.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ)
279system.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ)
280system.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ)
281system.physmem_0.averagePower 793.947771 # Core power per rank (mW)
282system.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states
283system.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states
284system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
285system.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states
286system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
287system.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ)
288system.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ)
289system.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ)
290system.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ)
291system.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ)
292system.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ)
293system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ)
294system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ)
295system.physmem_1.averagePower 794.363055 # Core power per rank (mW)
296system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states
297system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states
298system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
299system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states
300system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
301system.cpu.branchPred.lookups 286292198 # Number of BP lookups
302system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted
303system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect
304system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups
305system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits
306system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
307system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage
308system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target.
309system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions.
310system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups.
311system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits.
312system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses.
313system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches.
314system.cpu_clk_domain.clock 500 # Clock period in ticks
315system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
323system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
324system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
325system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
326system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
327system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
328system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
329system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
330system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
331system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
332system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
333system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
334system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
335system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
336system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
337system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
338system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
339system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
340system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
341system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
342system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
343system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
344system.cpu.dtb.walker.walks 0 # Table walker walks requested
345system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
346system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
347system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
348system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
349system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
350system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
351system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
352system.cpu.dtb.inst_hits 0 # ITB inst hits
353system.cpu.dtb.inst_misses 0 # ITB inst misses
354system.cpu.dtb.read_hits 0 # DTB read hits
355system.cpu.dtb.read_misses 0 # DTB read misses
356system.cpu.dtb.write_hits 0 # DTB write hits
357system.cpu.dtb.write_misses 0 # DTB write misses
358system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
359system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
360system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
361system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
362system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
363system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
364system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
365system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
366system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
367system.cpu.dtb.read_accesses 0 # DTB read accesses
368system.cpu.dtb.write_accesses 0 # DTB write accesses
369system.cpu.dtb.inst_accesses 0 # ITB inst accesses
370system.cpu.dtb.hits 0 # DTB hits
371system.cpu.dtb.misses 0 # DTB misses
372system.cpu.dtb.accesses 0 # DTB accesses
373system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
381system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
382system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
383system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
384system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
385system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
386system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
387system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
388system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
389system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
390system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
391system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
392system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
393system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
394system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
395system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
396system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
397system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
398system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
399system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
400system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
401system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
402system.cpu.itb.walker.walks 0 # Table walker walks requested
403system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
404system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
405system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
406system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
407system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
408system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
409system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
410system.cpu.itb.inst_hits 0 # ITB inst hits
411system.cpu.itb.inst_misses 0 # ITB inst misses
412system.cpu.itb.read_hits 0 # DTB read hits
413system.cpu.itb.read_misses 0 # DTB read misses
414system.cpu.itb.write_hits 0 # DTB write hits
415system.cpu.itb.write_misses 0 # DTB write misses
416system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
417system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
418system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
419system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
420system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
421system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
422system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
423system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
424system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
425system.cpu.itb.read_accesses 0 # DTB read accesses
426system.cpu.itb.write_accesses 0 # DTB write accesses
427system.cpu.itb.inst_accesses 0 # ITB inst accesses
428system.cpu.itb.hits 0 # DTB hits
429system.cpu.itb.misses 0 # DTB misses
430system.cpu.itb.accesses 0 # DTB accesses
431system.cpu.workload.num_syscalls 46 # Number of system calls
432system.cpu.numCycles 1535607688 # number of cpu cycles simulated
433system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
434system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
435system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss
436system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed
437system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered
438system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken
439system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked
440system.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing
441system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
442system.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR
443system.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched
444system.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed
445system.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total)
446system.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total)
447system.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total)
448system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
449system.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total)
450system.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total)
451system.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total)
452system.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total)
453system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
454system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
455system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
456system.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total)
457system.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle
458system.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle
459system.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle
460system.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked
461system.cpu.decode.RunCycles 849925630 # Number of cycles decode is running
462system.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking
463system.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing
464system.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch
465system.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction
466system.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode
467system.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode
468system.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing
469system.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle
470system.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking
471system.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst
472system.cpu.rename.RunCycles 837854747 # Number of cycles rename is running
473system.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking
474system.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename
475system.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename
476system.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full
477system.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full
478system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full
479system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full
480system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed
481system.cpu.rename.RenameLookups 9128568325 # Number of register rename lookups that rename has made
482system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups
483system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups
484system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
485system.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing
486system.cpu.rename.serializingInsts 174 # count of serializing insts renamed
487system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed
488system.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer
489system.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit.
490system.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit.
491system.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads.
492system.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores.
493system.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec)
494system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ
495system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued
496system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued
497system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling
498system.cpu.iq.iqSquashedOperandsExamined 647584155 # Number of squashed operands that are examined and possibly removed from graph
499system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed
500system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle
501system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle
502system.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle
503system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
504system.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle
505system.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle
506system.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle
507system.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle
508system.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle
509system.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle
510system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
511system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
512system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
513system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
514system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
515system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
516system.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle
517system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
518system.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available
519system.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available
520system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available
521system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available
522system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available
523system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available
524system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available
525system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available
526system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
527system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available
528system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available
529system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available
530system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available
531system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available
532system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available
533system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available
534system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available
535system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available
536system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available
537system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available
538system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available
539system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available
540system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available
541system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available
542system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available
543system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available
544system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available
545system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available
546system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
547system.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available
548system.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available
549system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
550system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
551system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
552system.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued
553system.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued
554system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
555system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
556system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
557system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
558system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
559system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
560system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
561system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
562system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
563system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
564system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
565system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
566system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
567system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
568system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
569system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
570system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
571system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
572system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
573system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
574system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
575system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued
576system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
577system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
578system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
579system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
580system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
581system.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued
582system.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued
583system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
584system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
585system.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued
586system.cpu.iq.rate 1.209614 # Inst issue rate
587system.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested
588system.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst)
589system.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads
590system.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes
591system.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses
592system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads
593system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes
594system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses
595system.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses
596system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses
597system.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores
598system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
599system.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed
600system.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed
601system.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations
602system.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed
603system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
604system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
605system.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled
606system.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked
607system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
608system.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing
609system.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking
610system.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking
611system.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ
612system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
613system.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions
614system.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions
615system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions
616system.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall
617system.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall
618system.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations
619system.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly
620system.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly
621system.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute
622system.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions
623system.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed
624system.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute
625system.cpu.iew.exec_swp 0 # number of swp insts executed
626system.cpu.iew.exec_nop 146 # number of nop insts executed
627system.cpu.iew.exec_refs 698692225 # number of memory reference insts executed
628system.cpu.iew.exec_branches 229542687 # Number of branches executed
629system.cpu.iew.exec_stores 181751910 # Number of stores executed
630system.cpu.iew.exec_rate 1.190295 # Inst execution rate
631system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit
632system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back
633system.cpu.iew.wb_producers 1169207800 # num instructions producing a value
634system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value
635system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle
636system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back
637system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit
638system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
639system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted
640system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle
641system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle
642system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle
643system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
644system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle
645system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle
646system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle
647system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle
648system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle
649system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle
650system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle
651system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle
652system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle
653system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
654system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
655system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
656system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle
657system.cpu.commit.committedInsts 1544563042 # Number of instructions committed
658system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed
659system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
660system.cpu.commit.refs 633153379 # Number of memory references committed
661system.cpu.commit.loads 458306334 # Number of loads committed
662system.cpu.commit.membars 62 # Number of memory barriers committed
663system.cpu.commit.branches 213462427 # Number of branches committed
664system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
665system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
666system.cpu.commit.function_calls 13665177 # Number of function calls committed.
667system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
668system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction
669system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
670system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
671system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
672system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
673system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
674system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
675system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
676system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
677system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
678system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
679system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
680system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
681system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
682system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
683system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
684system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
685system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
686system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
687system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
688system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
689system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
690system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
691system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
692system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
693system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
694system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
695system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
696system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
697system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
698system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
699system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
700system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
701system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction
702system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached
703system.cpu.rob.rob_reads 3360114616 # The number of ROB reads
704system.cpu.rob.rob_writes 3883791528 # The number of ROB writes
705system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself
706system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling
707system.cpu.committedInsts 1544563024 # Number of Instructions Simulated
708system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated
709system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction
710system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads
711system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle
712system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads
713system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads
714system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes
715system.cpu.fp_regfile_reads 42 # number of floating regfile reads
716system.cpu.fp_regfile_writes 54 # number of floating regfile writes
717system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads
718system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes
719system.cpu.misc_regfile_reads 675853701 # number of misc regfile reads
720system.cpu.misc_regfile_writes 124 # number of misc regfile writes
721system.cpu.dcache.tags.replacements 17003710 # number of replacements
722system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use
723system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks.
724system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks.
725system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks.
726system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit.
727system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor
728system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy
729system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy
730system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
731system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id
732system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
733system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
734system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses
735system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses
736system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits
737system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits
738system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits
739system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits
740system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
741system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
742system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
743system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
744system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits
745system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits
746system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits
747system.cpu.dcache.overall_hits::total 638076218 # number of overall hits
748system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses
749system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses
750system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses
751system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses
752system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
753system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
754system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
755system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
756system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses
757system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses
758system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses
759system.cpu.dcache.overall_misses::total 21285744 # number of overall misses
760system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles
761system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles
762system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles
763system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles
764system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles
765system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles
766system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles
767system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles
768system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles
769system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles
770system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses)
771system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses)
772system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
773system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
774system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
775system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
776system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
777system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
778system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
779system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
780system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses
781system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses
782system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses
783system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses
784system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses
785system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses
786system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses
787system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses
788system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
789system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
790system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
791system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
792system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses
793system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses
794system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses
795system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses
796system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency
797system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency
798system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency
799system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency
800system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency
801system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency
802system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency
803system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency
804system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency
805system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency
806system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked
807system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked
808system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked
809system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked
810system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked
811system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked
812system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks
813system.cpu.dcache.writebacks::total 17003710 # number of writebacks
814system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits
815system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits
816system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits
817system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits
818system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
819system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
820system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits
821system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits
822system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits
823system.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits
824system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses
825system.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses
826system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses
827system.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses
828system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
829system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
830system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses
831system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses
832system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses
833system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses
834system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles
835system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles
836system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles
837system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles
838system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles
839system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles
840system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles
841system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles
842system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles
843system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles
844system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses
845system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses
846system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
847system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
848system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
849system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
850system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses
851system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses
852system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses
853system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses
854system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency
855system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency
856system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency
857system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency
858system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency
859system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency
860system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency
861system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency
862system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency
863system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency
864system.cpu.icache.tags.replacements 589 # number of replacements
865system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use
866system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks.
867system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks.
868system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks.
869system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
870system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor
871system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy
872system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy
873system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id
874system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
875system.cpu.icache.tags.age_task_id_blocks_1024::1 14 # Occupied blocks per task id
876system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id
877system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id
878system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses
879system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses
880system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits
881system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits
882system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits
883system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits
884system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits
885system.cpu.icache.overall_hits::total 656966815 # number of overall hits
886system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses
887system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses
888system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses
889system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses
890system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses
891system.cpu.icache.overall_misses::total 1620 # number of overall misses
892system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles
893system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles
894system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles
895system.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles
896system.cpu.icache.overall_miss_latency::cpu.inst 98788987 # number of overall miss cycles
897system.cpu.icache.overall_miss_latency::total 98788987 # number of overall miss cycles
898system.cpu.icache.ReadReq_accesses::cpu.inst 656968435 # number of ReadReq accesses(hits+misses)
899system.cpu.icache.ReadReq_accesses::total 656968435 # number of ReadReq accesses(hits+misses)
900system.cpu.icache.demand_accesses::cpu.inst 656968435 # number of demand (read+write) accesses
901system.cpu.icache.demand_accesses::total 656968435 # number of demand (read+write) accesses
902system.cpu.icache.overall_accesses::cpu.inst 656968435 # number of overall (read+write) accesses
903system.cpu.icache.overall_accesses::total 656968435 # number of overall (read+write) accesses
904system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
905system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
906system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
907system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
908system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
909system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
910system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173 # average ReadReq miss latency
911system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173 # average ReadReq miss latency
912system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency
913system.cpu.icache.demand_avg_miss_latency::total 60980.856173 # average overall miss latency
914system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency
915system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency
916system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked
917system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked
918system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked
919system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
920system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked
921system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked
922system.cpu.icache.writebacks::writebacks 589 # number of writebacks
923system.cpu.icache.writebacks::total 589 # number of writebacks
924system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits
925system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits
926system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits
927system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits
928system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits
929system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits
930system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses
931system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses
932system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses
933system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses
934system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses
935system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses
936system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73759491 # number of ReadReq MSHR miss cycles
937system.cpu.icache.ReadReq_mshr_miss_latency::total 73759491 # number of ReadReq MSHR miss cycles
938system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73759491 # number of demand (read+write) MSHR miss cycles
939system.cpu.icache.demand_mshr_miss_latency::total 73759491 # number of demand (read+write) MSHR miss cycles
940system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73759491 # number of overall MSHR miss cycles
941system.cpu.icache.overall_mshr_miss_latency::total 73759491 # number of overall MSHR miss cycles
942system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
943system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
944system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
945system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
946system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
947system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
948system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency
949system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency
950system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency
951system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency
952system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency
953system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency
954system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued
955system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified
956system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue
957system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
958system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
959system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing
960system.cpu.l2cache.tags.replacements 4706089 # number of replacements
961system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use
962system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks.
963system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks.
964system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks.
965system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit.
966system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor
967system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor
968system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.119162 # Average occupied blocks per requestor
969system.cpu.l2cache.tags.occ_percent::writebacks 0.799460 # Average percentage of cache occupancy
970system.cpu.l2cache.tags.occ_percent::cpu.data 0.000140 # Average percentage of cache occupancy
971system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183052 # Average percentage of cache occupancy
972system.cpu.l2cache.tags.occ_percent::total 0.982651 # Average percentage of cache occupancy
973system.cpu.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id
974system.cpu.l2cache.tags.occ_task_id_blocks::1024 15097 # Occupied blocks per task id
975system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
976system.cpu.l2cache.tags.age_task_id_blocks_1022::1 636 # Occupied blocks per task id
977system.cpu.l2cache.tags.age_task_id_blocks_1022::3 191 # Occupied blocks per task id
978system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id
979system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id
980system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id
981system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id
982system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id
983system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id
984system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id
985system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses
986system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses
987system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits
988system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits
989system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits
990system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits
991system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits
992system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits
993system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits
994system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits
995system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11522367 # number of ReadSharedReq hits
996system.cpu.l2cache.ReadSharedReq_hits::total 11522367 # number of ReadSharedReq hits
997system.cpu.l2cache.demand_hits::cpu.inst 56 # number of demand (read+write) hits
998system.cpu.l2cache.demand_hits::cpu.data 13279454 # number of demand (read+write) hits
999system.cpu.l2cache.demand_hits::total 13279510 # number of demand (read+write) hits
1000system.cpu.l2cache.overall_hits::cpu.inst 56 # number of overall hits
1001system.cpu.l2cache.overall_hits::cpu.data 13279454 # number of overall hits
1002system.cpu.l2cache.overall_hits::total 13279510 # number of overall hits
1003system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
1004system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
1005system.cpu.l2cache.ReadExReq_misses::cpu.data 980546 # number of ReadExReq misses
1006system.cpu.l2cache.ReadExReq_misses::total 980546 # number of ReadExReq misses
1007system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1020 # number of ReadCleanReq misses
1008system.cpu.l2cache.ReadCleanReq_misses::total 1020 # number of ReadCleanReq misses
1009system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2744222 # number of ReadSharedReq misses
1010system.cpu.l2cache.ReadSharedReq_misses::total 2744222 # number of ReadSharedReq misses
1011system.cpu.l2cache.demand_misses::cpu.inst 1020 # number of demand (read+write) misses
1012system.cpu.l2cache.demand_misses::cpu.data 3724768 # number of demand (read+write) misses
1013system.cpu.l2cache.demand_misses::total 3725788 # number of demand (read+write) misses
1014system.cpu.l2cache.overall_misses::cpu.inst 1020 # number of overall misses
1015system.cpu.l2cache.overall_misses::cpu.data 3724768 # number of overall misses
1016system.cpu.l2cache.overall_misses::total 3725788 # number of overall misses
1017system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 121000 # number of UpgradeReq miss cycles
1018system.cpu.l2cache.UpgradeReq_miss_latency::total 121000 # number of UpgradeReq miss cycles
1019system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99083213500 # number of ReadExReq miss cycles
1020system.cpu.l2cache.ReadExReq_miss_latency::total 99083213500 # number of ReadExReq miss cycles
1021system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72272000 # number of ReadCleanReq miss cycles
1022system.cpu.l2cache.ReadCleanReq_miss_latency::total 72272000 # number of ReadCleanReq miss cycles
1023system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000 # number of ReadSharedReq miss cycles
1024system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000 # number of ReadSharedReq miss cycles
1025system.cpu.l2cache.demand_miss_latency::cpu.inst 72272000 # number of demand (read+write) miss cycles
1026system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500 # number of demand (read+write) miss cycles
1027system.cpu.l2cache.demand_miss_latency::total 333235195500 # number of demand (read+write) miss cycles
1028system.cpu.l2cache.overall_miss_latency::cpu.inst 72272000 # number of overall miss cycles
1029system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500 # number of overall miss cycles
1030system.cpu.l2cache.overall_miss_latency::total 333235195500 # number of overall miss cycles
1031system.cpu.l2cache.WritebackDirty_accesses::writebacks 4833112 # number of WritebackDirty accesses(hits+misses)
1032system.cpu.l2cache.WritebackDirty_accesses::total 4833112 # number of WritebackDirty accesses(hits+misses)
1033system.cpu.l2cache.WritebackClean_accesses::writebacks 12149903 # number of WritebackClean accesses(hits+misses)
1034system.cpu.l2cache.WritebackClean_accesses::total 12149903 # number of WritebackClean accesses(hits+misses)
1035system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses)
1036system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses)
1037system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737633 # number of ReadExReq accesses(hits+misses)
1038system.cpu.l2cache.ReadExReq_accesses::total 2737633 # number of ReadExReq accesses(hits+misses)
1039system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses)
1040system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses)
1041system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266589 # number of ReadSharedReq accesses(hits+misses)
1042system.cpu.l2cache.ReadSharedReq_accesses::total 14266589 # number of ReadSharedReq accesses(hits+misses)
1043system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses
1044system.cpu.l2cache.demand_accesses::cpu.data 17004222 # number of demand (read+write) accesses
1045system.cpu.l2cache.demand_accesses::total 17005298 # number of demand (read+write) accesses
1046system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses
1047system.cpu.l2cache.overall_accesses::cpu.data 17004222 # number of overall (read+write) accesses
1048system.cpu.l2cache.overall_accesses::total 17005298 # number of overall (read+write) accesses
1049system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
1050system.cpu.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses
1051system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358173 # miss rate for ReadExReq accesses
1052system.cpu.l2cache.ReadExReq_miss_rate::total 0.358173 # miss rate for ReadExReq accesses
1053system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947955 # miss rate for ReadCleanReq accesses
1054system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947955 # miss rate for ReadCleanReq accesses
1055system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192353 # miss rate for ReadSharedReq accesses
1056system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192353 # miss rate for ReadSharedReq accesses
1057system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947955 # miss rate for demand accesses
1058system.cpu.l2cache.demand_miss_rate::cpu.data 0.219050 # miss rate for demand accesses
1059system.cpu.l2cache.demand_miss_rate::total 0.219096 # miss rate for demand accesses
1060system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947955 # miss rate for overall accesses
1061system.cpu.l2cache.overall_miss_rate::cpu.data 0.219050 # miss rate for overall accesses
1062system.cpu.l2cache.overall_miss_rate::total 0.219096 # miss rate for overall accesses
1063system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency
1064system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency
1065system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158 # average ReadExReq miss latency
1066system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158 # average ReadExReq miss latency
1067system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961 # average ReadCleanReq miss latency
1068system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961 # average ReadCleanReq miss latency
1069system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742 # average ReadSharedReq miss latency
1070system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742 # average ReadSharedReq miss latency
1071system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency
1072system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency
1073system.cpu.l2cache.demand_avg_miss_latency::total 89440.192383 # average overall miss latency
1074system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency
1075system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency
1076system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency
1077system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked
1078system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1079system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1080system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1081system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked
1082system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1083system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference
1084system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks
1085system.cpu.l2cache.writebacks::total 1635896 # number of writebacks
1086system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits
1087system.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits
1088system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
1089system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
1090system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits
1091system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45253 # number of ReadSharedReq MSHR hits
1092system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
1093system.cpu.l2cache.demand_mshr_hits::cpu.data 49168 # number of demand (read+write) MSHR hits
1094system.cpu.l2cache.demand_mshr_hits::total 49169 # number of demand (read+write) MSHR hits
1095system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
1096system.cpu.l2cache.overall_mshr_hits::cpu.data 49168 # number of overall MSHR hits
1097system.cpu.l2cache.overall_mshr_hits::total 49169 # number of overall MSHR hits
1098system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of HardPFReq MSHR misses
1099system.cpu.l2cache.HardPFReq_mshr_misses::total 1145204 # number of HardPFReq MSHR misses
1100system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
1101system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
1102system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976631 # number of ReadExReq MSHR misses
1103system.cpu.l2cache.ReadExReq_mshr_misses::total 976631 # number of ReadExReq MSHR misses
1104system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1019 # number of ReadCleanReq MSHR misses
1105system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1019 # number of ReadCleanReq MSHR misses
1106system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2698969 # number of ReadSharedReq MSHR misses
1107system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2698969 # number of ReadSharedReq MSHR misses
1108system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses
1109system.cpu.l2cache.demand_mshr_misses::cpu.data 3675600 # number of demand (read+write) MSHR misses
1110system.cpu.l2cache.demand_mshr_misses::total 3676619 # number of demand (read+write) MSHR misses
1111system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses
1112system.cpu.l2cache.overall_mshr_misses::cpu.data 3675600 # number of overall MSHR misses
1113system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of overall MSHR misses
1114system.cpu.l2cache.overall_mshr_misses::total 4821823 # number of overall MSHR misses
1115system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of HardPFReq MSHR miss cycles
1116system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72434619378 # number of HardPFReq MSHR miss cycles
1117system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 85000 # number of UpgradeReq MSHR miss cycles
1118system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 85000 # number of UpgradeReq MSHR miss cycles
1119system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92854351000 # number of ReadExReq MSHR miss cycles
1120system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92854351000 # number of ReadExReq MSHR miss cycles
1121system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66085000 # number of ReadCleanReq MSHR miss cycles
1122system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66085000 # number of ReadCleanReq MSHR miss cycles
1123system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500 # number of ReadSharedReq MSHR miss cycles
1124system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500 # number of ReadSharedReq MSHR miss cycles
1125system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66085000 # number of demand (read+write) MSHR miss cycles
1126system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500 # number of demand (read+write) MSHR miss cycles
1127system.cpu.l2cache.demand_mshr_miss_latency::total 308011949500 # number of demand (read+write) MSHR miss cycles
1128system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66085000 # number of overall MSHR miss cycles
1129system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500 # number of overall MSHR miss cycles
1130system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of overall MSHR miss cycles
1131system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878 # number of overall MSHR miss cycles
1132system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1133system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1134system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
1135system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses
1136system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses
1137system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses
1138system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses
1139system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses
1140system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses
1141system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses
1142system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses
1143system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses
1144system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses
1145system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses
1146system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses
1147system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1148system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses
1149system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency
1150system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency
1151system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency
1152system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency
1153system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency
1154system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency
1155system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency
1156system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency
1157system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency
1158system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency
1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency
1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency
1161system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency
1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency
1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency
1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency
1165system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency
1166system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter.
1167system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1168system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
1169system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter.
1170system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1171system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
1172system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution
1173system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution
1174system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution
1175system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution
1176system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution
1177system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
1178system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution
1179system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution
1180system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution
1181system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution
1182system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution
1183system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution
1184system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes)
1185system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes)
1186system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes)
1187system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes)
1188system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes)
1189system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes)
1190system.cpu.toL2Bus.snoops 8842499 # Total snoops (count)
1191system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram
1192system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram
1193system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram
1194system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1195system.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram
1196system.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram
1197system.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram
1198system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1199system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
1200system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1201system.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram
1202system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks)
1203system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%)
1204system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks)
1205system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
1206system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks)
1207system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1208system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks)
1209system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%)
1210system.membus.trans_dist::ReadResp 3696594 # Transaction distribution
1211system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution
1212system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution
1213system.membus.trans_dist::UpgradeReq 6 # Transaction distribution
1214system.membus.trans_dist::ReadExReq 976790 # Transaction distribution
1215system.membus.trans_dist::ReadExResp 976790 # Transaction distribution
1216system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution
1217system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes)
1218system.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes)
1219system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes)
1220system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes)
1221system.membus.snoops 0 # Total snoops (count)
1222system.membus.snoop_fanout::samples 9311100 # Request fanout histogram
1223system.membus.snoop_fanout::mean 0 # Request fanout histogram
1224system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1225system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1226system.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram
1227system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1228system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1229system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1230system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1231system.membus.snoop_fanout::total 9311100 # Request fanout histogram
1232system.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks)
1233system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
1234system.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks)
1235system.membus.respLayer1.utilization 3.3 # Layer utilization (%)
1236
1237---------- End Simulation Statistics ----------