| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.767804 # Number of seconds simulated 4sim_ticks 767803843500 # Number of ticks simulated 5final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.767804 # Number of seconds simulated 4sim_ticks 767803843500 # Number of ticks simulated 5final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 188017 # Simulator instruction rate (inst/s) 8host_op_rate 202560 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 93463451 # Simulator tick rate (ticks/s) 10host_mem_usage 313392 # Number of bytes of host memory used 11host_seconds 8215.02 # Real time elapsed on the host | 7host_inst_rate 224780 # Simulator instruction rate (inst/s) 8host_op_rate 242166 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 111738196 # Simulator tick rate (ticks/s) 10host_mem_usage 312364 # Number of bytes of host memory used 11host_seconds 6871.45 # Real time elapsed on the host |
| 12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory 19system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory --- 784 unchanged lines hidden (view full) --- 804system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency 805system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency 806system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked 807system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked 808system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked 809system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked 810system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked 811system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked | 12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory 19system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory --- 784 unchanged lines hidden (view full) --- 804system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency 805system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency 806system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked 807system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked 808system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked 809system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked 810system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked 811system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked |
| 812system.cpu.dcache.fast_writes 0 # number of fast writes performed 813system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 814system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks 815system.cpu.dcache.writebacks::total 17003710 # number of writebacks 816system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits 817system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits 818system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits 819system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits 820system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 821system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 858system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency 859system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency 860system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency 861system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency 862system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency 863system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency 864system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency 865system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency | 812system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks 813system.cpu.dcache.writebacks::total 17003710 # number of writebacks 814system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits 815system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits 816system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits 817system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits 818system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 819system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits --- 36 unchanged lines hidden (view full) --- 856system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency 857system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency 858system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency 859system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency 860system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency 861system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency 862system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency 863system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency |
| 866system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 867system.cpu.icache.tags.replacements 589 # number of replacements 868system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use 869system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. 870system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. 871system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. 872system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 873system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor 874system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 917system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency 918system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency 919system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked 920system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked 921system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked 922system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked 923system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked 924system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked | 864system.cpu.icache.tags.replacements 589 # number of replacements 865system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use 866system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks. 867system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks. 868system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks. 869system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 870system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor 871system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 914system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency 915system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency 916system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked 917system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked 918system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked 919system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked 920system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked 921system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked |
| 925system.cpu.icache.fast_writes 0 # number of fast writes performed 926system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 927system.cpu.icache.writebacks::writebacks 589 # number of writebacks 928system.cpu.icache.writebacks::total 589 # number of writebacks 929system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits 930system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits 931system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits 932system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits 933system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits 934system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 951system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 952system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 953system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency 954system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency 955system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 956system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency 957system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 958system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency | 922system.cpu.icache.writebacks::writebacks 589 # number of writebacks 923system.cpu.icache.writebacks::total 589 # number of writebacks 924system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits 925system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits 926system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits 927system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits 928system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits 929system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 946system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 947system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 948system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency 949system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency 950system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 951system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency 952system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency 953system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency |
| 959system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 960system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued 961system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified 962system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue 963system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 964system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 965system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing 966system.cpu.l2cache.tags.replacements 4706089 # number of replacements 967system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use --- 113 unchanged lines hidden (view full) --- 1081system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency 1082system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency 1083system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked 1084system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1085system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1086system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1087system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked 1088system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 954system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued 955system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified 956system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue 957system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 958system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 959system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing 960system.cpu.l2cache.tags.replacements 4706089 # number of replacements 961system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use --- 113 unchanged lines hidden (view full) --- 1075system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency 1076system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency 1077system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked 1078system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1079system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked 1080system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1081system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked 1082system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1089system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1090system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1091system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference 1092system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks 1093system.cpu.l2cache.writebacks::total 1635896 # number of writebacks 1094system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits 1095system.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits 1096system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1097system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1098system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits --- 67 unchanged lines hidden (view full) --- 1166system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency 1167system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency 1168system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency 1169system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency 1170system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency 1171system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency 1172system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency 1173system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency | 1083system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference 1084system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks 1085system.cpu.l2cache.writebacks::total 1635896 # number of writebacks 1086system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits 1087system.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits 1088system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1089system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1090system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits --- 67 unchanged lines hidden (view full) --- 1158system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency 1159system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency 1160system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency 1161system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency 1162system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency 1163system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency 1164system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency 1165system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency |
| 1174system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1175system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. 1176system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1177system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1178system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. 1179system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1180system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1181system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution 1182system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution --- 64 unchanged lines hidden --- | 1166system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter. 1167system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1168system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1169system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter. 1170system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1171system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1172system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution 1173system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution --- 64 unchanged lines hidden --- |