| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.771783 # Number of seconds simulated 4sim_ticks 771782683000 # Number of ticks simulated 5final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 141348 # Simulator instruction rate (inst/s) 8host_op_rate 152281 # Simulator op (including micro ops) rate (op/s) --- 689 unchanged lines hidden (view full) --- 698system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 699system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 700system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 701system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction 702system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 703system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 704system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction 705system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.771783 # Number of seconds simulated 4sim_ticks 771782683000 # Number of ticks simulated 5final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 141348 # Simulator instruction rate (inst/s) 8host_op_rate 152281 # Simulator op (including micro ops) rate (op/s) --- 689 unchanged lines hidden (view full) --- 698system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 699system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 700system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 701system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction 702system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 703system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 704system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction 705system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached |
| 706system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 707system.cpu.rob.rob_reads 3367926925 # The number of ROB reads 708system.cpu.rob.rob_writes 3883468057 # The number of ROB writes 709system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself 710system.cpu.idleCycles 78604 # Total number of cycles that the CPU has spent unscheduled due to idling 711system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 712system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated 713system.cpu.cpi 0.999354 # CPI: Cycles Per Instruction 714system.cpu.cpi_total 0.999354 # CPI: Total CPI of All Threads --- 485 unchanged lines hidden --- | 706system.cpu.rob.rob_reads 3367926925 # The number of ROB reads 707system.cpu.rob.rob_writes 3883468057 # The number of ROB writes 708system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself 709system.cpu.idleCycles 78604 # Total number of cycles that the CPU has spent unscheduled due to idling 710system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 711system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated 712system.cpu.cpi 0.999354 # CPI: Cycles Per Instruction 713system.cpu.cpi_total 0.999354 # CPI: Total CPI of All Threads --- 485 unchanged lines hidden --- |