1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.528386 # Number of seconds simulated 4sim_ticks 528386107000 # Number of ticks simulated 5final_tick 528386107000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 123376 # Simulator instruction rate (inst/s) 8host_op_rate 137635 # Simulator op (including micro ops) rate (op/s) --- 653 unchanged lines hidden (view full) --- 662system.cpu.commit.bw_lim_events 106144682 # number cycles where commit BW limit reached 663system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 664system.cpu.rob.rob_reads 2991567190 # The number of ROB reads 665system.cpu.rob.rob_writes 4472170576 # The number of ROB writes 666system.cpu.timesIdled 1153872 # Number of times that the entire CPU went into an idle state and unscheduled itself 667system.cpu.idleCycles 90540825 # Total number of cycles that the CPU has spent unscheduled due to idling 668system.cpu.committedInsts 1544563023 # Number of Instructions Simulated 669system.cpu.committedOps 1723073835 # Number of Ops (including micro ops) Simulated |
670system.cpu.cpi 0.684188 # CPI: Cycles Per Instruction 671system.cpu.cpi_total 0.684188 # CPI: Total CPI of All Threads 672system.cpu.ipc 1.461586 # IPC: Instructions Per Cycle 673system.cpu.ipc_total 1.461586 # IPC: Total IPC of All Threads 674system.cpu.int_regfile_reads 9954183829 # number of integer regfile reads 675system.cpu.int_regfile_writes 1937102211 # number of integer regfile writes 676system.cpu.fp_regfile_reads 137 # number of floating regfile reads 677system.cpu.fp_regfile_writes 142 # number of floating regfile writes --- 406 unchanged lines hidden --- |