3,5c3,5
< sim_seconds 0.483300 # Number of seconds simulated
< sim_ticks 483300356500 # Number of ticks simulated
< final_tick 483300356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.464073 # Number of seconds simulated
> sim_ticks 464073050000 # Number of ticks simulated
> final_tick 464073050000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,18c7,18
< host_inst_rate 175200 # Simulator instruction rate (inst/s)
< host_op_rate 195449 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 54820940 # Simulator tick rate (ticks/s)
< host_mem_usage 223460 # Number of bytes of host memory used
< host_seconds 8815.98 # Real time elapsed on the host
< sim_insts 1544563036 # Number of instructions simulated
< sim_ops 1723073849 # Number of ops (including micro ops) simulated
< system.physmem.bytes_read 188191232 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 45952 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 77928320 # Number of bytes written to this memory
< system.physmem.num_reads 2940488 # Number of read requests responded to by this memory
< system.physmem.num_writes 1217630 # Number of write requests responded to by this memory
---
> host_inst_rate 176271 # Simulator instruction rate (inst/s)
> host_op_rate 196643 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 52961695 # Simulator tick rate (ticks/s)
> host_mem_usage 223676 # Number of bytes of host memory used
> host_seconds 8762.43 # Real time elapsed on the host
> sim_insts 1544563056 # Number of instructions simulated
> sim_ops 1723073869 # Number of ops (including micro ops) simulated
> system.physmem.bytes_read 189754368 # Number of bytes read from this memory
> system.physmem.bytes_inst_read 48448 # Number of instructions bytes read from this memory
> system.physmem.bytes_written 78230272 # Number of bytes written to this memory
> system.physmem.num_reads 2964912 # Number of read requests responded to by this memory
> system.physmem.num_writes 1222348 # Number of write requests responded to by this memory
20,23c20,23
< system.physmem.bw_read 389387737 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 95080 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write 161242008 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total 550629745 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read 408889006 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read 104397 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write 168573185 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total 577462190 # Total bandwidth to/from this memory (bytes/s)
67c67
< system.cpu.numCycles 966600714 # number of cpu cycles simulated
---
> system.cpu.numCycles 928146101 # number of cpu cycles simulated
70,74c70,74
< system.cpu.BPredUnit.lookups 298802813 # Number of BP lookups
< system.cpu.BPredUnit.condPredicted 243899992 # Number of conditional branches predicted
< system.cpu.BPredUnit.condIncorrect 18315213 # Number of conditional branches incorrect
< system.cpu.BPredUnit.BTBLookups 264194846 # Number of BTB lookups
< system.cpu.BPredUnit.BTBHits 238628617 # Number of BTB hits
---
> system.cpu.BPredUnit.lookups 300566019 # Number of BP lookups
> system.cpu.BPredUnit.condPredicted 246342426 # Number of conditional branches predicted
> system.cpu.BPredUnit.condIncorrect 16106991 # Number of conditional branches incorrect
> system.cpu.BPredUnit.BTBLookups 172736235 # Number of BTB lookups
> system.cpu.BPredUnit.BTBHits 156347078 # Number of BTB hits
76,91c76,91
< system.cpu.BPredUnit.usedRAS 17678661 # Number of times the RAS was used to get a target.
< system.cpu.BPredUnit.RASInCorrect 3338 # Number of incorrect RAS predictions.
< system.cpu.fetch.icacheStallCycles 296004888 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 2174228266 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 298802813 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 256307278 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 484507329 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 86919023 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 107617273 # Number of cycles fetch has spent blocked
< system.cpu.fetch.MiscStallCycles 8 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.PendingTrapStallCycles 140 # Number of stall cycles due to pending traps
< system.cpu.fetch.CacheLines 285078339 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 5300000 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 956319158 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.521362 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.026261 # Number of instructions fetched each cycle (Total)
---
> system.cpu.BPredUnit.usedRAS 18335765 # Number of times the RAS was used to get a target.
> system.cpu.BPredUnit.RASInCorrect 410 # Number of incorrect RAS predictions.
> system.cpu.fetch.icacheStallCycles 292802110 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 2158556881 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 300566019 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 174682843 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 429264774 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 83785432 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 129176492 # Number of cycles fetch has spent blocked
> system.cpu.fetch.MiscStallCycles 6 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.PendingTrapStallCycles 309 # Number of stall cycles due to pending traps
> system.cpu.fetch.CacheLines 283792946 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 5380579 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 918501449 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.613879 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.238743 # Number of instructions fetched each cycle (Total)
93,101c93,101
< system.cpu.fetch.rateDist::0 471811881 49.34% 49.34% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 35281645 3.69% 53.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 65131283 6.81% 59.84% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 66854544 6.99% 66.83% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 46816923 4.90% 71.72% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 59777101 6.25% 77.97% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 54237422 5.67% 83.64% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 17725648 1.85% 85.50% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 138682711 14.50% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 489236723 53.26% 53.26% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 23024875 2.51% 55.77% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 38786234 4.22% 59.99% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 47824320 5.21% 65.20% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 40756189 4.44% 69.64% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 46964078 5.11% 74.75% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 39095628 4.26% 79.01% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 18144974 1.98% 80.98% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 174668428 19.02% 100.00% # Number of instructions fetched each cycle (Total)
105,150c105,150
< system.cpu.fetch.rateDist::total 956319158 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.309127 # Number of branch fetches per cycle
< system.cpu.fetch.rate 2.249355 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 322991638 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 92138952 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 459388324 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 13611363 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 68188881 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 46868404 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 664 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 2351885426 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 2233 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 68188881 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 343108382 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 46584354 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 25758 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 451644595 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 46767188 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 2295012184 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 19840 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 2699078 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 37731214 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 3 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 2263685405 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 10601312044 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 10601310861 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 1183 # Number of floating rename lookups
< system.cpu.rename.CommittedMaps 1706319951 # Number of HB maps that are committed
< system.cpu.rename.UndoneMaps 557365454 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 9613 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 9609 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 98574159 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 618665433 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 221947140 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 73974093 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 60832432 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 2187079584 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 2062 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 2018219576 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 3314512 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 457863024 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 1047846495 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1559 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 956319158 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.110404 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.840875 # Number of insts issued each cycle
---
> system.cpu.fetch.rateDist::total 918501449 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.323835 # Number of branch fetches per cycle
> system.cpu.fetch.rate 2.325665 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 322112975 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 109206216 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 403275742 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 16649458 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 67257058 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 46176709 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 759 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 2347040926 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 2511 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 67257058 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 343744693 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 50775772 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 22198 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 397120131 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 59581597 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 2290149919 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 23251 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 4667919 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 46275027 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 2264746735 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 10570831770 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 10570827064 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 4706 # Number of floating rename lookups
> system.cpu.rename.CommittedMaps 1706319983 # Number of HB maps that are committed
> system.cpu.rename.UndoneMaps 558426752 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 5769 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 5766 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 136911238 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 624866711 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 218769389 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 86004799 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 66542105 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 2190647855 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 1856 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 2016093744 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 4890618 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 462875235 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 1075025866 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 1349 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 918501449 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.194982 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.923350 # Number of insts issued each cycle
152,160c152,160
< system.cpu.iq.issued_per_cycle::0 261846751 27.38% 27.38% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 150992981 15.79% 43.17% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 168342829 17.60% 60.77% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 136328017 14.26% 75.03% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 124939866 13.06% 88.09% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 73493141 7.69% 95.78% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 29213551 3.05% 98.83% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 10245765 1.07% 99.90% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 916257 0.10% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 251234212 27.35% 27.35% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 138874484 15.12% 42.47% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 158306173 17.24% 59.71% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 116338081 12.67% 72.37% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 125703968 13.69% 86.06% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 75541719 8.22% 94.28% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 39131512 4.26% 98.54% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 10691268 1.16% 99.71% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 2680032 0.29% 100.00% # Number of insts issued each cycle
164c164
< system.cpu.iq.issued_per_cycle::total 956319158 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 918501449 # Number of insts issued each cycle
166,196c166,196
< system.cpu.iq.fu_full::IntAlu 899945 3.67% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 187 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.67% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 19005921 77.47% 81.14% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 4627423 18.86% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 823704 3.29% 3.29% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 4653 0.02% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.30% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 18995164 75.78% 79.08% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 5243478 20.92% 100.00% # attempts to use FU when none available
200,230c200,230
< system.cpu.iq.FU_type_0::IntAlu 1238740250 61.38% 61.38% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 1017622 0.05% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 6 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 7 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.43% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 583895352 28.93% 90.36% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 194566336 9.64% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 1234318257 61.22% 61.22% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 931291 0.05% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 86 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 1 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 19 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 587032832 29.12% 90.39% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 193811220 9.61% 100.00% # Type of FU issued
233,245c233,245
< system.cpu.iq.FU_type_0::total 2018219576 # Type of FU issued
< system.cpu.iq.rate 2.087956 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 24533476 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.012156 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 5020606045 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 2645122896 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1958251270 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 253 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 238 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 108 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 2042752922 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 130 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 55694024 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 2016093744 # Type of FU issued
> system.cpu.iq.rate 2.172173 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 25066999 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.012433 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 4980646050 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 2653710289 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1958144552 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 504 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 870 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 197 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 2041160488 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 255 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 63652463 # Number of loads that had data forwarded from stores
247,250c247,250
< system.cpu.iew.lsq.thread0.squashedLoads 132738662 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 211257 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 180594 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 47100094 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 138939936 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 281971 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 189096 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 43922339 # Number of stores squashed
253,254c253,254
< system.cpu.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 451914 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 450534 # Number of times an access to memory failed due to the cache being blocked
256,272c256,272
< system.cpu.iew.iewSquashCycles 68188881 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 22161421 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1213363 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 2187099355 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 7278228 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 618665433 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 221947140 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 1999 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 219629 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 61218 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 180594 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 18897487 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 1819209 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 20716696 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1985947715 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 570245268 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 32271861 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 67257058 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 23170910 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1317099 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 2190657684 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 5590225 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 624866711 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 218769389 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 1789 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 207758 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 50528 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 189096 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 8640354 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 10202609 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 18842963 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1986590916 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 572448085 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 29502828 # Number of squashed instructions skipped in execute
274,282c274,282
< system.cpu.iew.exec_nop 17709 # number of nop insts executed
< system.cpu.iew.exec_refs 761448250 # number of memory reference insts executed
< system.cpu.iew.exec_branches 238637230 # Number of branches executed
< system.cpu.iew.exec_stores 191202982 # Number of stores executed
< system.cpu.iew.exec_rate 2.054569 # Inst execution rate
< system.cpu.iew.wb_sent 1967185295 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1958251378 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 1288041557 # num instructions producing a value
< system.cpu.iew.wb_consumers 2036752533 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 7973 # number of nop insts executed
> system.cpu.iew.exec_refs 763288309 # number of memory reference insts executed
> system.cpu.iew.exec_branches 238204396 # Number of branches executed
> system.cpu.iew.exec_stores 190840224 # Number of stores executed
> system.cpu.iew.exec_rate 2.140386 # Inst execution rate
> system.cpu.iew.wb_sent 1967133110 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1958144749 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 1296172102 # num instructions producing a value
> system.cpu.iew.wb_consumers 2068722659 # num instructions consuming a value
284,285c284,285
< system.cpu.iew.wb_rate 2.025916 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.632400 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 2.109738 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.626557 # average fanout of values written-back
287,294c287,294
< system.cpu.commit.commitCommittedInsts 1544563054 # The number of committed instructions
< system.cpu.commit.commitCommittedOps 1723073867 # The number of committed instructions
< system.cpu.commit.commitSquashedInsts 464107908 # The number of squashed insts skipped by commit
< system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards
< system.cpu.commit.branchMispredicts 18315306 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 888130278 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.940114 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.672278 # Number of insts commited each cycle
---
> system.cpu.commit.commitCommittedInsts 1544563074 # The number of committed instructions
> system.cpu.commit.commitCommittedOps 1723073887 # The number of committed instructions
> system.cpu.commit.commitSquashedInsts 467651163 # The number of squashed insts skipped by commit
> system.cpu.commit.commitNonSpecStalls 507 # The number of times commit has been forced to stall to communicate backwards
> system.cpu.commit.branchMispredicts 16106465 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 851244392 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 2.024182 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.756273 # Number of insts commited each cycle
296,304c296,304
< system.cpu.commit.committed_per_cycle::0 382955223 43.12% 43.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 200739073 22.60% 65.72% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 81923550 9.22% 74.95% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 38679338 4.36% 79.30% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 19675426 2.22% 81.52% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 30976281 3.49% 85.00% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 22277703 2.51% 87.51% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 12029119 1.35% 88.87% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 98874565 11.13% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 363008407 42.64% 42.64% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 192701589 22.64% 65.28% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 73550522 8.64% 73.92% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 35106838 4.12% 78.05% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 18707332 2.20% 80.24% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 30658705 3.60% 83.85% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 19651115 2.31% 86.15% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 10957875 1.29% 87.44% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 106902009 12.56% 100.00% # Number of insts commited each cycle
308,310c308,310
< system.cpu.commit.committed_per_cycle::total 888130278 # Number of insts commited each cycle
< system.cpu.commit.committedInsts 1544563054 # Number of instructions committed
< system.cpu.commit.committedOps 1723073867 # Number of ops (including micro ops) committed
---
> system.cpu.commit.committed_per_cycle::total 851244392 # Number of insts commited each cycle
> system.cpu.commit.committedInsts 1544563074 # Number of instructions committed
> system.cpu.commit.committedOps 1723073887 # Number of ops (including micro ops) committed
312,313c312,313
< system.cpu.commit.refs 660773817 # Number of memory references committed
< system.cpu.commit.loads 485926771 # Number of loads committed
---
> system.cpu.commit.refs 660773825 # Number of memory references committed
> system.cpu.commit.loads 485926775 # Number of loads committed
315c315
< system.cpu.commit.branches 213462365 # Number of branches committed
---
> system.cpu.commit.branches 213462369 # Number of branches committed
317c317
< system.cpu.commit.int_insts 1536941853 # Number of committed integer instructions.
---
> system.cpu.commit.int_insts 1536941869 # Number of committed integer instructions.
319c319
< system.cpu.commit.bw_lim_events 98874565 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 106902009 # number cycles where commit BW limit reached
321,342c321,342
< system.cpu.rob.rob_reads 2976436889 # The number of ROB reads
< system.cpu.rob.rob_writes 4442782654 # The number of ROB writes
< system.cpu.timesIdled 920078 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 10281556 # Total number of cycles that the CPU has spent unscheduled due to idling
< system.cpu.committedInsts 1544563036 # Number of Instructions Simulated
< system.cpu.committedOps 1723073849 # Number of Ops (including micro ops) Simulated
< system.cpu.committedInsts_total 1544563036 # Number of Instructions Simulated
< system.cpu.cpi 0.625809 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.625809 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.597933 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.597933 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 9941434858 # number of integer regfile reads
< system.cpu.int_regfile_writes 1939754373 # number of integer regfile writes
< system.cpu.fp_regfile_reads 96 # number of floating regfile reads
< system.cpu.fp_regfile_writes 31 # number of floating regfile writes
< system.cpu.misc_regfile_reads 2912823996 # number of misc regfile reads
< system.cpu.misc_regfile_writes 126 # number of misc regfile writes
< system.cpu.icache.replacements 10 # number of replacements
< system.cpu.icache.tagsinuse 609.966952 # Cycle average of tags in use
< system.cpu.icache.total_refs 285077321 # Total number of references to valid blocks.
< system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks.
< system.cpu.icache.avg_refs 382141.180965 # Average number of references to valid blocks.
---
> system.cpu.rob.rob_reads 2935066834 # The number of ROB reads
> system.cpu.rob.rob_writes 4448881416 # The number of ROB writes
> system.cpu.timesIdled 899412 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 9644652 # Total number of cycles that the CPU has spent unscheduled due to idling
> system.cpu.committedInsts 1544563056 # Number of Instructions Simulated
> system.cpu.committedOps 1723073869 # Number of Ops (including micro ops) Simulated
> system.cpu.committedInsts_total 1544563056 # Number of Instructions Simulated
> system.cpu.cpi 0.600912 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.600912 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.664138 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.664138 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 9951907737 # number of integer regfile reads
> system.cpu.int_regfile_writes 1938294940 # number of integer regfile writes
> system.cpu.fp_regfile_reads 210 # number of floating regfile reads
> system.cpu.fp_regfile_writes 230 # number of floating regfile writes
> system.cpu.misc_regfile_reads 2898206993 # number of misc regfile reads
> system.cpu.misc_regfile_writes 134 # number of misc regfile writes
> system.cpu.icache.replacements 22 # number of replacements
> system.cpu.icache.tagsinuse 634.912102 # Cycle average of tags in use
> system.cpu.icache.total_refs 283791788 # Total number of references to valid blocks.
> system.cpu.icache.sampled_refs 786 # Sample count of references to valid blocks.
> system.cpu.icache.avg_refs 361058.254453 # Average number of references to valid blocks.
344,370c344,370
< system.cpu.icache.occ_blocks::cpu.inst 609.966952 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.297835 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.297835 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 285077321 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 285077321 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 285077321 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 285077321 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 285077321 # number of overall hits
< system.cpu.icache.overall_hits::total 285077321 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1018 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1018 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1018 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1018 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1018 # number of overall misses
< system.cpu.icache.overall_misses::total 1018 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 35270500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 35270500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 35270500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 35270500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 35270500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 35270500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 285078339 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 285078339 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 285078339 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 285078339 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 285078339 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 285078339 # number of overall (read+write) accesses
---
> system.cpu.icache.occ_blocks::cpu.inst 634.912102 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.310016 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.310016 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 283791788 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 283791788 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 283791788 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 283791788 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 283791788 # number of overall hits
> system.cpu.icache.overall_hits::total 283791788 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1158 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1158 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1158 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1158 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1158 # number of overall misses
> system.cpu.icache.overall_misses::total 1158 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 38624000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 38624000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 38624000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 38624000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 38624000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 38624000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 283792946 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 283792946 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 283792946 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 283792946 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 283792946 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 283792946 # number of overall (read+write) accesses
374,376c374,376
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34646.856582 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 34646.856582 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 34646.856582 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33354.058722 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 33354.058722 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 33354.058722 # average overall miss latency
385,402c385,402
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 272 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 272 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 272 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 272 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 272 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 272 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 746 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 746 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 746 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 746 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 746 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 746 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25653000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 25653000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25653000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 25653000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25653000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 25653000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 372 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 372 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 372 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 372 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 372 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 786 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 786 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 786 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 786 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 786 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 786 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27049500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 27049500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27049500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 27049500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27049500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 27049500 # number of overall MSHR miss cycles
406,408c406,408
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34387.399464 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34387.399464 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34387.399464 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34414.122137 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34414.122137 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34414.122137 # average overall mshr miss latency
410,452c410,452
< system.cpu.dcache.replacements 9570609 # number of replacements
< system.cpu.dcache.tagsinuse 4087.729265 # Cycle average of tags in use
< system.cpu.dcache.total_refs 666885051 # Total number of references to valid blocks.
< system.cpu.dcache.sampled_refs 9574705 # Sample count of references to valid blocks.
< system.cpu.dcache.avg_refs 69.650715 # Average number of references to valid blocks.
< system.cpu.dcache.warmup_cycle 3484295000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.occ_blocks::cpu.data 4087.729265 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.997981 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.997981 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 499489564 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 499489564 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 167395365 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 167395365 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 60 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 60 # number of LoadLockedReq hits
< system.cpu.dcache.StoreCondReq_hits::cpu.data 62 # number of StoreCondReq hits
< system.cpu.dcache.StoreCondReq_hits::total 62 # number of StoreCondReq hits
< system.cpu.dcache.demand_hits::cpu.data 666884929 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 666884929 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 666884929 # number of overall hits
< system.cpu.dcache.overall_hits::total 666884929 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 10445560 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 10445560 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 5190682 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5190682 # number of WriteReq misses
< system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
< system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
< system.cpu.dcache.demand_misses::cpu.data 15636242 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 15636242 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 15636242 # number of overall misses
< system.cpu.dcache.overall_misses::total 15636242 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 184478558500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 184478558500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 128511717246 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 128511717246 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 113500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 113500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 312990275746 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 312990275746 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 312990275746 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 312990275746 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 509935124 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 509935124 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.replacements 9618384 # number of replacements
> system.cpu.dcache.tagsinuse 4087.732309 # Cycle average of tags in use
> system.cpu.dcache.total_refs 660741585 # Total number of references to valid blocks.
> system.cpu.dcache.sampled_refs 9622480 # Sample count of references to valid blocks.
> system.cpu.dcache.avg_refs 68.666454 # Average number of references to valid blocks.
> system.cpu.dcache.warmup_cycle 3347848000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.occ_blocks::cpu.data 4087.732309 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.997982 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.997982 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 493363105 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 493363105 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 167378321 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 167378321 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 93 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 93 # number of LoadLockedReq hits
> system.cpu.dcache.StoreCondReq_hits::cpu.data 66 # number of StoreCondReq hits
> system.cpu.dcache.StoreCondReq_hits::total 66 # number of StoreCondReq hits
> system.cpu.dcache.demand_hits::cpu.data 660741426 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 660741426 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 660741426 # number of overall hits
> system.cpu.dcache.overall_hits::total 660741426 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 10695472 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 10695472 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 5207726 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5207726 # number of WriteReq misses
> system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
> system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
> system.cpu.dcache.demand_misses::cpu.data 15903198 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 15903198 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 15903198 # number of overall misses
> system.cpu.dcache.overall_misses::total 15903198 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 189107739500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 189107739500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 129597679387 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 129597679387 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 148000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 148000 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 318705418887 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 318705418887 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 318705418887 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 318705418887 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 504058577 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 504058577 # number of ReadReq accesses(hits+misses)
455,478c455,478
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 63 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 63 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::cpu.data 62 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.StoreCondReq_accesses::total 62 # number of StoreCondReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 682521171 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 682521171 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 682521171 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 682521171 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.020484 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030076 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.047619 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.022910 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.022910 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17660.954367 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24758.156490 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 20016.975674 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 20016.975674 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 266779202 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 225500 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 90534 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 14 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.729428 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 16107.142857 # average number of cycles each access was blocked
---
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 97 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 97 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::cpu.data 66 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.StoreCondReq_accesses::total 66 # number of StoreCondReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 676644624 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 676644624 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 676644624 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 676644624 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.021219 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.030175 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.041237 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.023503 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.023503 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17681.102760 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24885.656309 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37000 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 20040.335214 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 270494777 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 161000 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 91798 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 10 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 2946.630395 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 16100 # average number of cycles each access was blocked
481,516c481,516
< system.cpu.dcache.writebacks::writebacks 3128454 # number of writebacks
< system.cpu.dcache.writebacks::total 3128454 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2763491 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2763491 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3298046 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 3298046 # number of WriteReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 6061537 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 6061537 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 6061537 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 6061537 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7682069 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 7682069 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1892636 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1892636 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 9574705 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 9574705 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 9574705 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9574705 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 92052400500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 92052400500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45263240996 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 45263240996 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137315641496 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 137315641496 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137315641496 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 137315641496 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015065 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010966 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014028 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014028 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11982.761480 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23915.449667 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14341.501017 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14341.501017 # average overall mshr miss latency
---
> system.cpu.dcache.writebacks::writebacks 3133951 # number of writebacks
> system.cpu.dcache.writebacks::total 3133951 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2966989 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 2966989 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3313729 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 3313729 # number of WriteReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 6280718 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 6280718 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 6280718 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 6280718 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7728483 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 7728483 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893997 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1893997 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 9622480 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 9622480 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9622480 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9622480 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 93034311000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 93034311000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 45389589120 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 45389589120 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 138423900120 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 138423900120 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 138423900120 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 138423900120 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015333 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010974 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014221 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12037.848954 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23964.974137 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14385.470286 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14385.470286 # average overall mshr miss latency
518,593c518,593
< system.cpu.l2cache.replacements 2928111 # number of replacements
< system.cpu.l2cache.tagsinuse 26779.513847 # Cycle average of tags in use
< system.cpu.l2cache.total_refs 7850665 # Total number of references to valid blocks.
< system.cpu.l2cache.sampled_refs 2955434 # Sample count of references to valid blocks.
< system.cpu.l2cache.avg_refs 2.656349 # Average number of references to valid blocks.
< system.cpu.l2cache.warmup_cycle 102043879500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.occ_blocks::writebacks 10799.372069 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.inst 11.094827 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 15969.046951 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::writebacks 0.329571 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.inst 0.000339 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.487337 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.817246 # Average percentage of cache occupancy
< system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 5654817 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 5654844 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 3128454 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 3128454 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 980108 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 980108 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 6634925 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 6634952 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 6634925 # number of overall hits
< system.cpu.l2cache.overall_hits::total 6634952 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 719 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 2027251 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 2027970 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 912529 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 912529 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 719 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 2939780 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 2940499 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 719 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 2939780 # number of overall misses
< system.cpu.l2cache.overall_misses::total 2940499 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24699000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 69597988500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 69622687500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31651212500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 31651212500 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 24699000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 101249201000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 101273900000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 24699000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 101249201000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 101273900000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 746 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 7682068 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 7682814 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 3128454 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 3128454 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 1892637 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 1892637 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 746 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 9574705 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 9575451 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 746 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 9574705 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 9575451 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963807 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.263894 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.482147 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963807 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.307036 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963807 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.307036 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34351.877608 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34331.214290 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34685.157951 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 56425000 # number of cycles access was blocked
---
> system.cpu.l2cache.replacements 2952443 # number of replacements
> system.cpu.l2cache.tagsinuse 26872.767236 # Cycle average of tags in use
> system.cpu.l2cache.total_refs 7878289 # Total number of references to valid blocks.
> system.cpu.l2cache.sampled_refs 2979766 # Sample count of references to valid blocks.
> system.cpu.l2cache.avg_refs 2.643929 # Average number of references to valid blocks.
> system.cpu.l2cache.warmup_cycle 101003264500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.occ_blocks::writebacks 10760.518963 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.inst 11.047760 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 16101.200513 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::writebacks 0.328385 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.inst 0.000337 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.491370 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.820092 # Average percentage of cache occupancy
> system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 5679969 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 5679997 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 3133951 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 3133951 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 978347 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 978347 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 6658316 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 6658344 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 6658316 # number of overall hits
> system.cpu.l2cache.overall_hits::total 6658344 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 758 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 2048513 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 2049271 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 915651 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 915651 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 758 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 2964164 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 2964922 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 758 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 2964164 # number of overall misses
> system.cpu.l2cache.overall_misses::total 2964922 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26043500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 70322097500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 70348141000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 31765624000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 31765624000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 26043500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 102087721500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 102113765000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 26043500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 102087721500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 102113765000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 786 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 7728482 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 7729268 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 3133951 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 3133951 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893998 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 1893998 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 786 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 9622480 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 9623266 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 786 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 9622480 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 9623266 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964377 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.265060 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.483449 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964377 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.308046 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964377 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.308046 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.179420 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.362817 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34691.846566 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.179420 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.645491 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.179420 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.645491 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 57298000 # number of cycles access was blocked
595c595
< system.cpu.l2cache.blocked::no_mshrs 6634 # number of cycles access was blocked
---
> system.cpu.l2cache.blocked::no_mshrs 6751 # number of cycles access was blocked
597c597
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8505.426590 # average number of cycles each access was blocked
---
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs 8487.335210 # average number of cycles each access was blocked
601,602c601,602
< system.cpu.l2cache.writebacks::writebacks 1217630 # number of writebacks
< system.cpu.l2cache.writebacks::total 1217630 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 1222348 # number of writebacks
> system.cpu.l2cache.writebacks::total 1222348 # number of writebacks
604,605c604,605
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 11 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
607,608c607,608
< system.cpu.l2cache.demand_mshr_hits::cpu.data 10 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 11 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
610,647c610,647
< system.cpu.l2cache.overall_mshr_hits::cpu.data 10 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 11 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 718 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2027241 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 2027959 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 912529 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 912529 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 718 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 2939770 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 2940488 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 718 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 2939770 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 2940488 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22382500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63220880000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63243262500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28812389000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28812389000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22382500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92033269000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 92055651500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22382500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92033269000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 92055651500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.263893 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.482147 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.307035 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962466 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.307035 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31173.398329 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31185.675507 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31574.217367 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31173.398329 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31173.398329 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 757 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2048504 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 2049261 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 915651 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 915651 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 757 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 2964155 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 2964912 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 757 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 2964155 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 2964912 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23603500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 63886529000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 63910132500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 28922104500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 28922104500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23603500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 92808633500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 92832237000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23603500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 92808633500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 92832237000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.265059 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.483449 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963104 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.308045 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31180.317041 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31186.919332 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31586.384441 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31180.317041 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31310.317274 # average overall mshr miss latency