3,5c3,5
< sim_seconds 0.770752 # Number of seconds simulated
< sim_ticks 770752376500 # Number of ticks simulated
< final_tick 770752376500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.787742 # Number of seconds simulated
> sim_ticks 787742202500 # Number of ticks simulated
> final_tick 787742202500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 147248 # Simulator instruction rate (inst/s)
< host_op_rate 158637 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 73478006 # Simulator tick rate (ticks/s)
< host_mem_usage 329736 # Number of bytes of host memory used
< host_seconds 10489.57 # Real time elapsed on the host
---
> host_inst_rate 201500 # Simulator instruction rate (inst/s)
> host_op_rate 217086 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 102767126 # Simulator tick rate (ticks/s)
> host_mem_usage 327820 # Number of bytes of host memory used
> host_seconds 7665.31 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
18,20c18,20
< system.physmem.bytes_read::cpu.data 236002624 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 63781504 # Number of bytes read from this memory
< system.physmem.bytes_read::total 299849792 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 236035776 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 63780672 # Number of bytes read from this memory
> system.physmem.bytes_read::total 299882112 # Number of bytes read from this memory
23,24c23,24
< system.physmem.bytes_written::writebacks 104607936 # Number of bytes written to this memory
< system.physmem.bytes_written::total 104607936 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 104579136 # Number of bytes written to this memory
> system.physmem.bytes_written::total 104579136 # Number of bytes written to this memory
26,54c26,54
< system.physmem.num_reads::cpu.data 3687541 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 996586 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 4685153 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1634499 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1634499 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 85195 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 306197725 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 82752264 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 389035183 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 85195 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 85195 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 135721847 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 135721847 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 135721847 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 85195 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 306197725 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 82752264 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 524757030 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 4685154 # Number of read requests accepted
< system.physmem.writeReqs 1634499 # Number of write requests accepted
< system.physmem.readBursts 4685154 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1634499 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 299347712 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 502144 # Total number of bytes read from write queue
< system.physmem.bytesWritten 104604544 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 299849856 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 104607936 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 7846 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 26 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.num_reads::cpu.data 3688059 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 996573 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 4685658 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1634049 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1634049 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 83357 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 299635814 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 80966428 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 380685599 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 83357 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 83357 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 132758072 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 132758072 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 132758072 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 83357 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 299635814 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 80966428 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 513443671 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 4685658 # Number of read requests accepted
> system.physmem.writeReqs 1634049 # Number of write requests accepted
> system.physmem.readBursts 4685658 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1634049 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 299378880 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 503232 # Total number of bytes read from write queue
> system.physmem.bytesWritten 104576512 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 299882112 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 104579136 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 7863 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 17 # Number of DRAM write bursts merged with an existing one
56,87c56,87
< system.physmem.perBankRdBursts::0 301314 # Per bank write bursts
< system.physmem.perBankRdBursts::1 301808 # Per bank write bursts
< system.physmem.perBankRdBursts::2 285079 # Per bank write bursts
< system.physmem.perBankRdBursts::3 287721 # Per bank write bursts
< system.physmem.perBankRdBursts::4 288732 # Per bank write bursts
< system.physmem.perBankRdBursts::5 286480 # Per bank write bursts
< system.physmem.perBankRdBursts::6 281880 # Per bank write bursts
< system.physmem.perBankRdBursts::7 278193 # Per bank write bursts
< system.physmem.perBankRdBursts::8 293719 # Per bank write bursts
< system.physmem.perBankRdBursts::9 299847 # Per bank write bursts
< system.physmem.perBankRdBursts::10 291529 # Per bank write bursts
< system.physmem.perBankRdBursts::11 297903 # Per bank write bursts
< system.physmem.perBankRdBursts::12 299405 # Per bank write bursts
< system.physmem.perBankRdBursts::13 299387 # Per bank write bursts
< system.physmem.perBankRdBursts::14 294305 # Per bank write bursts
< system.physmem.perBankRdBursts::15 290006 # Per bank write bursts
< system.physmem.perBankWrBursts::0 103629 # Per bank write bursts
< system.physmem.perBankWrBursts::1 101748 # Per bank write bursts
< system.physmem.perBankWrBursts::2 99222 # Per bank write bursts
< system.physmem.perBankWrBursts::3 99944 # Per bank write bursts
< system.physmem.perBankWrBursts::4 98990 # Per bank write bursts
< system.physmem.perBankWrBursts::5 98822 # Per bank write bursts
< system.physmem.perBankWrBursts::6 102440 # Per bank write bursts
< system.physmem.perBankWrBursts::7 104048 # Per bank write bursts
< system.physmem.perBankWrBursts::8 105134 # Per bank write bursts
< system.physmem.perBankWrBursts::9 103994 # Per bank write bursts
< system.physmem.perBankWrBursts::10 101818 # Per bank write bursts
< system.physmem.perBankWrBursts::11 102570 # Per bank write bursts
< system.physmem.perBankWrBursts::12 102850 # Per bank write bursts
< system.physmem.perBankWrBursts::13 102376 # Per bank write bursts
< system.physmem.perBankWrBursts::14 104237 # Per bank write bursts
< system.physmem.perBankWrBursts::15 102624 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 301431 # Per bank write bursts
> system.physmem.perBankRdBursts::1 301123 # Per bank write bursts
> system.physmem.perBankRdBursts::2 285299 # Per bank write bursts
> system.physmem.perBankRdBursts::3 287676 # Per bank write bursts
> system.physmem.perBankRdBursts::4 288751 # Per bank write bursts
> system.physmem.perBankRdBursts::5 286469 # Per bank write bursts
> system.physmem.perBankRdBursts::6 281133 # Per bank write bursts
> system.physmem.perBankRdBursts::7 278330 # Per bank write bursts
> system.physmem.perBankRdBursts::8 294107 # Per bank write bursts
> system.physmem.perBankRdBursts::9 299584 # Per bank write bursts
> system.physmem.perBankRdBursts::10 292343 # Per bank write bursts
> system.physmem.perBankRdBursts::11 297976 # Per bank write bursts
> system.physmem.perBankRdBursts::12 299704 # Per bank write bursts
> system.physmem.perBankRdBursts::13 299189 # Per bank write bursts
> system.physmem.perBankRdBursts::14 294388 # Per bank write bursts
> system.physmem.perBankRdBursts::15 290292 # Per bank write bursts
> system.physmem.perBankWrBursts::0 103694 # Per bank write bursts
> system.physmem.perBankWrBursts::1 101682 # Per bank write bursts
> system.physmem.perBankWrBursts::2 99052 # Per bank write bursts
> system.physmem.perBankWrBursts::3 99844 # Per bank write bursts
> system.physmem.perBankWrBursts::4 99095 # Per bank write bursts
> system.physmem.perBankWrBursts::5 98699 # Per bank write bursts
> system.physmem.perBankWrBursts::6 102473 # Per bank write bursts
> system.physmem.perBankWrBursts::7 104090 # Per bank write bursts
> system.physmem.perBankWrBursts::8 105068 # Per bank write bursts
> system.physmem.perBankWrBursts::9 104102 # Per bank write bursts
> system.physmem.perBankWrBursts::10 101990 # Per bank write bursts
> system.physmem.perBankWrBursts::11 102510 # Per bank write bursts
> system.physmem.perBankWrBursts::12 102612 # Per bank write bursts
> system.physmem.perBankWrBursts::13 102296 # Per bank write bursts
> system.physmem.perBankWrBursts::14 104281 # Per bank write bursts
> system.physmem.perBankWrBursts::15 102520 # Per bank write bursts
90c90
< system.physmem.totGap 770752366000 # Total gap between requests
---
> system.physmem.totGap 787742161500 # Total gap between requests
97c97
< system.physmem.readPktSize::6 4685154 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 4685658 # Read request sizes (log2)
104,120c104,120
< system.physmem.writePktSize::6 1634499 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 2776424 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 1031022 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 327510 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 229431 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 146630 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 80164 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 37430 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 23802 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 17710 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 4122 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1619 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 771 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 239 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1634049 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 2727854 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1051064 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 327817 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 232993 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 158136 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 89940 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 39970 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 24320 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 17966 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 4404 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1761 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 825 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 484 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see
152,185c152,185
< system.physmem.wrQLenPdf::15 25690 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 28168 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 56471 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 73716 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 85142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 93999 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 100116 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 103738 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 105456 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 106103 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 107040 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 108147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 109209 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 110723 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 110766 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 103820 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 100949 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 100270 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 2888 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 505 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 109 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 44 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 28 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 24393 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 26784 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 55742 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 73104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 84746 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 93459 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 99625 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 103284 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 105129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 105804 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 106233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 107403 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 108454 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 109545 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 110077 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 108778 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 102213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 101052 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 4490 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1853 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 898 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 461 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 229 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 132 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 59 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 32 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 19 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::47 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::48 2 # What write queue length does an incoming req see
201,262c201,255
< system.physmem.bytesPerActivate::samples 4255173 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 94.931559 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 78.862227 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 102.833954 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 3394354 79.77% 79.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 663703 15.60% 95.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 94226 2.21% 97.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 35436 0.83% 98.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 22765 0.53% 98.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 12171 0.29% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 7342 0.17% 99.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.53% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 19831 0.47% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 4255173 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 97794 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 47.827914 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 99.473591 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-127 93707 95.82% 95.82% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::128-255 1671 1.71% 97.53% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::256-383 768 0.79% 98.31% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::384-511 406 0.42% 98.73% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-639 365 0.37% 99.10% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::640-767 337 0.34% 99.45% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::768-895 234 0.24% 99.69% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::896-1023 165 0.17% 99.86% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-1151 89 0.09% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1152-1279 24 0.02% 99.97% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1280-1407 12 0.01% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1664-1791 3 0.00% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::3968-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 97794 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 97794 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.713152 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.671812 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.223073 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 68724 70.27% 70.27% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 1896 1.94% 72.21% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 18671 19.09% 91.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 5634 5.76% 97.07% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 1729 1.77% 98.83% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 613 0.63% 99.46% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 266 0.27% 99.73% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 147 0.15% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 67 0.07% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 30 0.03% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 9 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::27 6 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 97794 # Writes before turning the bus around for reads
< system.physmem.totQLat 128325813562 # Total ticks spent queuing
< system.physmem.totMemAccLat 216025338562 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 23386540000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 27435.83 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 4258602 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 94.856263 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 78.818587 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 102.740363 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 3399214 79.82% 79.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 662534 15.56% 95.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 94110 2.21% 97.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 35203 0.83% 98.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 22640 0.53% 98.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 12473 0.29% 99.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 7407 0.17% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5223 0.12% 99.54% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 19798 0.46% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 4258602 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 97968 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 47.747867 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 99.462080 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-255 95523 97.50% 97.50% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::256-511 1197 1.22% 98.73% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-767 705 0.72% 99.45% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::768-1023 407 0.42% 99.86% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-1279 106 0.11% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1280-1535 17 0.02% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1536-1791 4 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1792-2047 4 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2048-2303 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2304-2559 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::3584-3839 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::4352-4607 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::4608-4863 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 97968 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 97968 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.678997 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.638691 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.208217 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 70313 71.77% 71.77% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 1920 1.96% 73.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 17565 17.93% 91.66% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 5314 5.42% 97.08% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 1711 1.75% 98.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 637 0.65% 99.48% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 262 0.27% 99.75% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 130 0.13% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 63 0.06% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 33 0.03% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 13 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::27 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 97968 # Writes before turning the bus around for reads
> system.physmem.totQLat 162666982970 # Total ticks spent queuing
> system.physmem.totMemAccLat 250375639220 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 23388975000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 34774.29 # Average queueing delay per DRAM burst
264,268c257,261
< system.physmem.avgMemAccLat 46185.83 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 388.38 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 135.72 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 389.04 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 135.72 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 53524.29 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 380.05 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 132.75 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 380.69 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 132.76 # Average system write bandwidth in MiByte/s
270,314c263,317
< system.physmem.busUtil 4.09 # Data bus utilization in percentage
< system.physmem.busUtilRead 3.03 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes
< system.physmem.avgRdQLen 1.42 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing
< system.physmem.readRowHits 1715091 # Number of row buffer hits during reads
< system.physmem.writeRowHits 341475 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 36.67 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 20.89 # Row buffer hit rate for writes
< system.physmem.avgGap 121961.18 # Average gap between requests
< system.physmem.pageHitRate 32.58 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 15989112720 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 8724218250 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 18025846800 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 5241069360 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 417928675995 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 95843265750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 612093526155 # Total energy per rank (pJ)
< system.physmem_0.averagePower 794.157652 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 156909498029 # Time in different power states
< system.physmem_0.memoryStateTime::REF 25736880000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 588099785971 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 16179556680 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 8828131125 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 18455494200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 5349602880 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 412908393870 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 100247038500 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 612309554535 # Total energy per rank (pJ)
< system.physmem_1.averagePower 794.437909 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 164276600328 # Time in different power states
< system.physmem_1.memoryStateTime::REF 25736880000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 580733308672 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 286275195 # Number of BP lookups
< system.cpu.branchPred.condPredicted 223398341 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 14628424 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 157667483 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 150349199 # Number of BTB hits
---
> system.physmem.busUtil 4.01 # Data bus utilization in percentage
> system.physmem.busUtilRead 2.97 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 1.04 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.91 # Average write queue length when enqueuing
> system.physmem.readRowHits 1712898 # Number of row buffer hits during reads
> system.physmem.writeRowHits 340301 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 36.62 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 20.83 # Row buffer hit rate for writes
> system.physmem.avgGap 124648.53 # Average gap between requests
> system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 15106540680 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 8029309200 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 16494913680 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 4221043380 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 59407414560.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 64582002630 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1606944480 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 223006056720 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 35875852320 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 16122239730 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 444464207160 # Total energy per rank (pJ)
> system.physmem_0.averagePower 564.225454 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 641904162368 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 1401750889 # Time in different power states
> system.physmem_0.memoryStateTime::REF 25151370000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 59428702250 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 93425472309 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 119284909993 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 489049997059 # Time in different power states
> system.physmem_1.actEnergy 15299891880 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 8132085390 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 16904542620 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 4308478380 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 58934141760.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 64765265610 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 1612336320 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 219700492200 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 35552759520 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 18091245240 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 443312102310 # Total energy per rank (pJ)
> system.physmem_1.averagePower 562.762917 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 641480248383 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 1450220904 # Time in different power states
> system.physmem_1.memoryStateTime::REF 24952394000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 67105561000 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 92583809905 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 119858377963 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 481791838728 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 286283098 # Number of BP lookups
> system.cpu.branchPred.condPredicted 223408244 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 14630421 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 158004936 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 150354998 # Number of BTB hits
316,322c319,325
< system.cpu.branchPred.BTBHitPct 95.358406 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 16643020 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 3069 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 1906 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 1163 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 137 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 95.158418 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 16643073 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 3065 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 1898 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 1167 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 134 # Number of mispredicted indirect branches.
324c327
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
354c357
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
384c387
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
414c417
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
445,446c448,449
< system.cpu.pwrStateResidencyTicks::ON 770752376500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1541504754 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 787742202500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1575484406 # number of cpu cycles simulated
449,461c452,464
< system.cpu.fetch.icacheStallCycles 13925502 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 2067484101 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 286275195 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 166994125 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 1512857238 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 29281631 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 279 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.IcacheWaitRetryStallCycles 1018 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 656940019 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 946 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 1541424852 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.436951 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.229037 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 13928690 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 2067537239 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 286283098 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 166999969 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 1546809233 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 29285745 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 303 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.IcacheWaitRetryStallCycles 986 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 656964714 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 1575382084 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.406011 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.233492 # Number of instructions fetched each cycle (Total)
463,466c466,469
< system.cpu.fetch.rateDist::0 459011037 29.78% 29.78% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 465435057 30.20% 59.97% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 101419068 6.58% 66.55% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 515559690 33.45% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 492942163 31.29% 31.29% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 465443083 29.54% 60.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 101428647 6.44% 67.27% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 515568191 32.73% 100.00% # Number of instructions fetched each cycle (Total)
470,497c473,500
< system.cpu.fetch.rateDist::total 1541424852 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.185712 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.341212 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 74709451 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 544021839 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 849845592 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 58207832 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 14640138 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 42201657 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 726 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 2037180089 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 52484609 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 14640138 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 139806563 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 462600801 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 15884 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 837785307 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 86576159 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 1976384850 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 26739549 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 45323653 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 126929 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1602638 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 25499860 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 1985860548 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 9128169124 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 2432875929 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 1575382084 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.181711 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.312318 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 74686824 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 577980395 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 849907031 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 58165638 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 14642196 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 42200734 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 724 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 2037196735 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 52499519 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 14642196 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 139768268 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 492678513 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 15538 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 837819054 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 90458515 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 1976393108 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 26740093 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 45400307 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 126273 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1723349 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 29315109 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 1985867653 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 9128208959 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 2432891999 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 131 # Number of floating rename lookups
499,516c502,519
< system.cpu.rename.UndoneMaps 310961603 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 175 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 175 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 111534180 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 542566077 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 199303375 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 26892889 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 29237160 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 1947969517 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 231 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 1857492369 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 13496690 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 283937332 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 647289356 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 61 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 1541424852 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.205049 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.150817 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 310968708 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 177 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 176 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 111448171 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 542564068 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 199306440 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 26831952 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 28868587 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 1947979256 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 230 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 1857513748 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 13517148 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 283947070 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 647252748 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 60 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 1575382084 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.179088 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.151868 # Number of insts issued each cycle
518,523c521,526
< system.cpu.iq.issued_per_cycle::0 588435916 38.17% 38.17% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 326131475 21.16% 59.33% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 378210554 24.54% 83.87% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 219654013 14.25% 98.12% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 28986723 1.88% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 6171 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 622503864 39.51% 39.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 326012726 20.69% 60.21% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 378121823 24.00% 84.21% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 219723484 13.95% 98.16% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 29014011 1.84% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle
530c533
< system.cpu.iq.issued_per_cycle::total 1541424852 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1575382084 # Number of insts issued each cycle
532,562c535,565
< system.cpu.iq.fu_full::IntAlu 166021321 40.99% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 1993 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 191489776 47.28% 88.26% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 47539480 11.74% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 166098751 40.96% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 2024 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.96% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 191460462 47.22% 88.18% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 47920671 11.82% 100.00% # attempts to use FU when none available
566,567c569,570
< system.cpu.iq.FU_type_0::IntAlu 1138243662 61.28% 61.28% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 800931 0.04% 61.32% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 1138250302 61.28% 61.28% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 801028 0.04% 61.32% # Type of FU issued
595,596c598,599
< system.cpu.iq.FU_type_0::MemRead 532135699 28.65% 89.97% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 186312026 10.03% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 532139540 28.65% 89.97% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 186322827 10.03% 100.00% # Type of FU issued
599,605c602,608
< system.cpu.iq.FU_type_0::total 1857492369 # Type of FU issued
< system.cpu.iq.rate 1.204986 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 405052570 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.218064 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 5674958613 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 2231919871 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1805704142 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 1857513748 # Type of FU issued
> system.cpu.iq.rate 1.179011 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 405481908 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.218293 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 5709408399 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 2231939413 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1805717250 # Number of integer instruction queue wakeup accesses
607,609c610,612
< system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 2262544806 # Number of integer alu accesses
---
> system.cpu.iq.fp_inst_queue_writes 228 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 2262995523 # Number of integer alu accesses
611c614
< system.cpu.iew.lsq.thread0.forwLoads 17811536 # Number of loads that had data forwarded from stores
---
> system.cpu.iew.lsq.thread0.forwLoads 17822173 # Number of loads that had data forwarded from stores
613,616c616,619
< system.cpu.iew.lsq.thread0.squashedLoads 84259743 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 66618 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 13244 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 24456330 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 84257734 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 66715 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 13309 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 24459395 # Number of stores squashed
619,620c622,623
< system.cpu.iew.lsq.thread0.rescheduledLoads 4512030 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 4891489 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 4550351 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 4849996 # Number of times an access to memory failed due to the cache being blocked
622,625c625,628
< system.cpu.iew.iewSquashCycles 14640138 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 25364964 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1346928 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 1947969899 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 14642196 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 25436916 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1454941 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 1947979633 # Number of instructions dispatched to IQ
627,638c630,641
< system.cpu.iew.iewDispLoadInsts 542566077 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 199303375 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 169 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 159350 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 1186169 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 13244 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 7699482 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 8703162 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 16402644 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1827831567 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 516957415 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 29660802 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 542564068 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 199306440 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 168 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 159182 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 1294449 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 13309 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 7700831 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 8703764 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 16404595 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1827842620 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 516961097 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 29671128 # Number of squashed instructions skipped in execute
640,651c643,654
< system.cpu.iew.exec_nop 151 # number of nop insts executed
< system.cpu.iew.exec_refs 698708795 # number of memory reference insts executed
< system.cpu.iew.exec_branches 229542425 # Number of branches executed
< system.cpu.iew.exec_stores 181751380 # Number of stores executed
< system.cpu.iew.exec_rate 1.185745 # Inst execution rate
< system.cpu.iew.wb_sent 1808736265 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1805704212 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 1169174812 # num instructions producing a value
< system.cpu.iew.wb_consumers 1689572222 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.171391 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.691995 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 258041892 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_nop 147 # number of nop insts executed
> system.cpu.iew.exec_refs 698716504 # number of memory reference insts executed
> system.cpu.iew.exec_branches 229543654 # Number of branches executed
> system.cpu.iew.exec_stores 181755407 # Number of stores executed
> system.cpu.iew.exec_rate 1.160178 # Inst execution rate
> system.cpu.iew.wb_sent 1808745333 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1805717319 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 1169202335 # num instructions producing a value
> system.cpu.iew.wb_consumers 1689603795 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.146135 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.691998 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 258049766 # The number of squashed insts skipped by commit
653,656c656,659
< system.cpu.commit.branchMispredicts 14627747 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 1501940299 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.107922 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.025263 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 14629745 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 1535892995 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.083430 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.009496 # Number of insts commited each cycle
658,666c661,669
< system.cpu.commit.committed_per_cycle::0 921653315 61.36% 61.36% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 250636600 16.69% 78.05% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 110060462 7.33% 85.38% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 55269176 3.68% 89.06% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 29319156 1.95% 91.01% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 34080655 2.27% 93.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 24723288 1.65% 94.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 18133421 1.21% 96.13% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 58064226 3.87% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 955612705 62.22% 62.22% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 250634240 16.32% 78.54% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 110090472 7.17% 85.71% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 55300497 3.60% 89.31% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 29246766 1.90% 91.21% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 34056030 2.22% 93.43% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 24731317 1.61% 95.04% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 18107101 1.18% 96.22% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 58113867 3.78% 100.00% # Number of insts commited each cycle
670c673
< system.cpu.commit.committed_per_cycle::total 1501940299 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 1535892995 # Number of insts commited each cycle
716,720c719,723
< system.cpu.commit.bw_lim_events 58064226 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 3365949800 # The number of ROB reads
< system.cpu.rob.rob_writes 3883638365 # The number of ROB writes
< system.cpu.timesIdled 837 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 79902 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 58113867 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 3399860729 # The number of ROB reads
> system.cpu.rob.rob_writes 3883658641 # The number of ROB writes
> system.cpu.timesIdled 841 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 102322 # Total number of cycles that the CPU has spent unscheduled due to idling
723,733c726,736
< system.cpu.cpi 0.998020 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.998020 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.001984 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.001984 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 2175818987 # number of integer regfile reads
< system.cpu.int_regfile_writes 1261576435 # number of integer regfile writes
< system.cpu.fp_regfile_reads 42 # number of floating regfile reads
< system.cpu.fp_regfile_writes 52 # number of floating regfile writes
< system.cpu.cc_regfile_reads 6965775009 # number of cc regfile reads
< system.cpu.cc_regfile_writes 551856674 # number of cc regfile writes
< system.cpu.misc_regfile_reads 675846934 # number of misc regfile reads
---
> system.cpu.cpi 1.020020 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 1.020020 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.980373 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.980373 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 2175838440 # number of integer regfile reads
> system.cpu.int_regfile_writes 1261579513 # number of integer regfile writes
> system.cpu.fp_regfile_reads 40 # number of floating regfile reads
> system.cpu.fp_regfile_writes 51 # number of floating regfile writes
> system.cpu.cc_regfile_reads 6965813253 # number of cc regfile reads
> system.cpu.cc_regfile_writes 551861987 # number of cc regfile writes
> system.cpu.misc_regfile_reads 675852638 # number of misc regfile reads
735,744c738,747
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 17003150 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.964340 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 638065664 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 17003662 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 79206500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.964340 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 17003360 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.963277 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 638058665 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 17003872 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 37.524316 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 83293500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.963277 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999928 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999928 # Average percentage of cache occupancy
746,747c749,750
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 406 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 382 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
749,755c752,758
< system.cpu.dcache.tags.tag_accesses 1335709608 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1335709608 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 469347574 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 469347574 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 168717937 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 168717937 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 1335696042 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1335696042 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 469342719 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 469342719 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 168715791 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 168715791 # number of WriteReq hits
760,767c763,770
< system.cpu.dcache.demand_hits::cpu.data 638065511 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 638065511 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 638065511 # number of overall hits
< system.cpu.dcache.overall_hits::total 638065511 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 17419228 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 17419228 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3868110 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3868110 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 638058510 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 638058510 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 638058510 # number of overall hits
> system.cpu.dcache.overall_hits::total 638058510 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 17417195 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 17417195 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3870256 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3870256 # number of WriteReq misses
772,787c775,790
< system.cpu.dcache.demand_misses::cpu.data 21287338 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 21287338 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 21287340 # number of overall misses
< system.cpu.dcache.overall_misses::total 21287340 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 416423435500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 416423435500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 150253086257 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 150253086257 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 199500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 566676521757 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 566676521757 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 566676521757 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 566676521757 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 486766802 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 486766802 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 21287451 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 21287451 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 21287453 # number of overall misses
> system.cpu.dcache.overall_misses::total 21287453 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 440618340000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 440618340000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 157333375444 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 157333375444 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 245500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 245500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 597951715444 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 597951715444 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 597951715444 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 597951715444 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 486759914 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 486759914 # number of ReadReq accesses(hits+misses)
796,803c799,806
< system.cpu.dcache.demand_accesses::cpu.data 659352849 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 659352849 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 659352851 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 659352851 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022413 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.022413 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 659345961 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 659345961 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 659345963 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 659345963 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035782 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.035782 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022425 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.022425 # miss rate for WriteReq accesses
808,833c811,836
< system.cpu.dcache.demand_miss_rate::cpu.data 0.032285 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.032285 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.032285 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.032285 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23905.963887 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 23905.963887 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38844.057242 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38844.057242 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49875 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49875 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 26620.356277 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 26620.356277 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 26620.353776 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 26620.353776 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 20685246 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 3452781 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 946049 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 67233 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.864878 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 51.355450 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 17003150 # number of writebacks
< system.cpu.dcache.writebacks::total 17003150 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3153076 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 3153076 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130592 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1130592 # number of WriteReq MSHR hits
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.032286 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.032286 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.032286 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.032286 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25297.893260 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 25297.893260 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40651.929858 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 40651.929858 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 61375 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 61375 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 28089.399499 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 28089.399499 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 28089.396859 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 28089.396859 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 21254267 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 3791320 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 940376 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 67438 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 22.601882 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 56.219342 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 17003360 # number of writebacks
> system.cpu.dcache.writebacks::total 17003360 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3150878 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 3150878 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1132695 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1132695 # number of WriteReq MSHR hits
836,843c839,846
< system.cpu.dcache.demand_mshr_hits::cpu.data 4283668 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 4283668 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 4283668 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 4283668 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266152 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 14266152 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737518 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2737518 # number of WriteReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 4283573 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 4283573 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 4283573 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 4283573 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266317 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 14266317 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737561 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2737561 # number of WriteReq MSHR misses
846,861c849,864
< system.cpu.dcache.demand_mshr_misses::cpu.data 17003670 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 17003670 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 17003671 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 17003671 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335207977500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 335207977500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116679674033 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 116679674033 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451887651533 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 451887651533 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451887720533 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 451887720533 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029308 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029308 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 17003878 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 17003878 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 17003879 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 17003879 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 354302060000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 354302060000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 121168074300 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 121168074300 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 475470134300 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 475470134300 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 475470209300 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 475470209300 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029309 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029309 # mshr miss rate for ReadReq accesses
866,885c869,888
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.025788 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.025788 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23496.733913 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23496.733913 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42622.431718 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42622.431718 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26575.889295 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26575.889295 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26575.891790 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26575.891790 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 588 # number of replacements
< system.cpu.icache.tags.tagsinuse 444.874436 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 656938405 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 611674.492551 # Average number of references to valid blocks.
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24834.865228 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24834.865228 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44261.323967 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44261.323967 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 27962.452700 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 27962.452700 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 27962.455467 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 27962.455467 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 589 # number of replacements
> system.cpu.icache.tags.tagsinuse 445.623702 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 656963104 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 610560.505576 # Average number of references to valid blocks.
887,891c890,894
< system.cpu.icache.tags.occ_blocks::cpu.inst 444.874436 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.868895 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.868895 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 486 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 445.623702 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.870359 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.870359 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 487 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id
893,921c896,925
< system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.949219 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 1313881106 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 1313881106 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 656938405 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 656938405 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 656938405 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 656938405 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 656938405 # number of overall hits
< system.cpu.icache.overall_hits::total 656938405 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1611 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1611 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1611 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1611 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1611 # number of overall misses
< system.cpu.icache.overall_misses::total 1611 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 103785485 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 103785485 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 103785485 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 103785485 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 103785485 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 103785485 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 656940016 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 656940016 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 656940016 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 656940016 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 656940016 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 656940016 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.951172 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 1313930500 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 1313930500 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 656963104 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 656963104 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 656963104 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 656963104 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 656963104 # number of overall hits
> system.cpu.icache.overall_hits::total 656963104 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1608 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1608 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1608 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1608 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1608 # number of overall misses
> system.cpu.icache.overall_misses::total 1608 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 127367486 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 127367486 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 127367486 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 127367486 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 127367486 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 127367486 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 656964712 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 656964712 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 656964712 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 656964712 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 656964712 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 656964712 # number of overall (read+write) accesses
928,959c932,963
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64423.019863 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 64423.019863 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 64423.019863 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 64423.019863 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 64423.019863 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 64423.019863 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 16825 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 586 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 90.945946 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 58.600000 # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 588 # number of writebacks
< system.cpu.icache.writebacks::total 588 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 535 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 535 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 535 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 535 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 535 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75943989 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 75943989 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75943989 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 75943989 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75943989 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 75943989 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 79208.635572 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 79208.635572 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 79208.635572 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 79208.635572 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 79208.635572 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 79208.635572 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 21110 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 318 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 109.378238 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 35.333333 # average number of cycles each access was blocked
> system.cpu.icache.writebacks::writebacks 589 # number of writebacks
> system.cpu.icache.writebacks::total 589 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 531 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 531 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 531 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 531 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 531 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 531 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 92273990 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 92273990 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 92273990 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 92273990 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 92273990 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 92273990 # number of overall MSHR miss cycles
966,975c970,979
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70579.915428 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70579.915428 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70579.915428 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 70579.915428 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70579.915428 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 70579.915428 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 11612917 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 11641367 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 19112 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 85676.870938 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 85676.870938 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 85676.870938 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 85676.870938 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 85676.870938 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 85676.870938 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 11610963 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 11639700 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 19388 # number of redundant prefetches already in prefetch queue
978,984c982,988
< system.cpu.l2cache.prefetcher.pfSpanPage 4655505 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 4647068 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 15866.736257 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 13267029 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 4662976 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 2.845185 # Average number of references to valid blocks.
---
> system.cpu.l2cache.prefetcher.pfSpanPage 4657940 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 4647528 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 15870.760193 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 13267468 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 4663442 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 2.844995 # Average number of references to valid blocks.
986,1025c990,1029
< system.cpu.l2cache.tags.occ_blocks::writebacks 15646.626307 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 220.109950 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.954994 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013434 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.968429 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 143 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::1 115 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 463 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4068 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7095 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2886 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1253 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008728 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 561777243 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 561777243 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 4835234 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 4835234 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 12147319 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 12147319 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1756866 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1756866 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 49 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 49 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11510992 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 11510992 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 49 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 13267858 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 13267907 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 49 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 13267858 # number of overall hits
< system.cpu.l2cache.overall_hits::total 13267907 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 980689 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 980689 # number of ReadExReq misses
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 15649.753914 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 221.006278 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.955185 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013489 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.968674 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 144 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15770 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 116 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 27 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 430 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4072 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7121 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2569 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1578 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008789 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962524 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 561783529 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 561783529 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 4825740 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 4825740 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 12156985 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 12156985 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1756408 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1756408 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 50 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 50 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11511753 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 11511753 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 50 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 13268161 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 13268211 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 50 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 13268161 # number of overall hits
> system.cpu.l2cache.overall_hits::total 13268211 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 7 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 7 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 981196 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 981196 # number of ReadExReq misses
1028,1029c1032,1033
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2755115 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 2755115 # number of ReadSharedReq misses
---
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2754515 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 2754515 # number of ReadSharedReq misses
1031,1032c1035,1036
< system.cpu.l2cache.demand_misses::cpu.data 3735804 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 3736831 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 3735711 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 3736738 # number of demand (read+write) misses
1034,1067c1038,1071
< system.cpu.l2cache.overall_misses::cpu.data 3735804 # number of overall misses
< system.cpu.l2cache.overall_misses::total 3736831 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 191500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 191500 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100034737999 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 100034737999 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 74500500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 74500500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 237611587999 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 237611587999 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 74500500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 337646325998 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 337720826498 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 74500500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 337646325998 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 337720826498 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 4835234 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 4835234 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 12147319 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 12147319 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 9 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 9 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737555 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2737555 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1076 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadCleanReq_accesses::total 1076 # number of ReadCleanReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266107 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 14266107 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 17003662 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 17004738 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 17003662 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 17004738 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_misses::cpu.data 3735711 # number of overall misses
> system.cpu.l2cache.overall_misses::total 3736738 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 148500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 148500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 104535366500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 104535366500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 90830000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 90830000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 256701151000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 256701151000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 90830000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 361236517500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 361327347500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 90830000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 361236517500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 361327347500 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 4825740 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 4825740 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 12156985 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 12156985 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 7 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 7 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737604 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 2737604 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1077 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadCleanReq_accesses::total 1077 # number of ReadCleanReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266268 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 14266268 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1077 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 17003872 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 17004949 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1077 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 17003872 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 17004949 # number of overall (read+write) accesses
1070,1096c1074,1100
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358235 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.358235 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954461 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954461 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193123 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193123 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954461 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.219706 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.219752 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954461 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.219706 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.219752 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21277.777778 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21277.777778 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102004.547822 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102004.547822 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72541.869523 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72541.869523 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86243.800349 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86243.800349 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72541.869523 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90381.167213 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 90376.264406 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72541.869523 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90381.167213 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 90376.264406 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358414 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.358414 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.953575 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.953575 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193079 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193079 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.953575 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.219698 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.219744 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.953575 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.219698 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.219744 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21214.285714 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21214.285714 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 106538.720602 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 106538.720602 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 88442.064265 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 88442.064265 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 93192.867347 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 93192.867347 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 88442.064265 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 96698.196809 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 96695.927705 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 88442.064265 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 96698.196809 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 96695.927705 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 541 # number of cycles access was blocked
1098c1102
< system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
---
> system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
1100c1104
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs 70.200000 # average number of cycles each access was blocked
---
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs 135.250000 # average number of cycles each access was blocked
1102,1146c1106,1154
< system.cpu.l2cache.unused_prefetches 58014 # number of HardPF blocks evicted w/o reference
< system.cpu.l2cache.writebacks::writebacks 1634499 # number of writebacks
< system.cpu.l2cache.writebacks::total 1634499 # number of writebacks
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3902 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 3902 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45668 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45668 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 49570 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 49570 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 49570 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 49570 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1198249 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 1198249 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976787 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 976787 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1027 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1027 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709447 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709447 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 1027 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 3686234 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 3687261 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 3686234 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1198249 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 4885510 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 73218164638 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 73218164638 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 137500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 137500 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93806338999 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93806338999 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68350500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68350500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 218529981999 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 218529981999 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68350500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312336320998 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 312404671498 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68350500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312336320998 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 73218164638 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 385622836136 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.unused_prefetches 58311 # number of HardPF blocks evicted w/o reference
> system.cpu.l2cache.writebacks::writebacks 1634049 # number of writebacks
> system.cpu.l2cache.writebacks::total 1634049 # number of writebacks
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3931 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 3931 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45060 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45060 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 48991 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 48992 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 48991 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 48992 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1197394 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 1197394 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 7 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 7 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 977265 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 977265 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1026 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1026 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709455 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709455 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 1026 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 3686720 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 3687746 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 1026 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 3686720 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1197394 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 4885140 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 84175133455 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 84175133455 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 106500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 106500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98289203000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98289203000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 84580000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 84580000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 237438885500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 237438885500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 84580000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 335728088500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 335812668500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 84580000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 335728088500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 84175133455 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 419987801955 # number of overall MSHR miss cycles
1151,1161c1159,1169
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356810 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356810 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954461 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189922 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189922 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.216837 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356978 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356978 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.952646 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189920 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189920 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216816 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.216863 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.952646 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216816 # mshr miss rate for overall accesses
1163,1185c1171,1193
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.287303 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61104.298554 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96035.613700 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96035.613700 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66553.554041 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66553.554041 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80654.828088 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80654.828088 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84725.402270 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78931.951042 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 34008488 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003756 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 201663 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 201662 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.287278 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 70298.609693 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15214.285714 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15214.285714 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 100575.793669 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 100575.793669 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82436.647173 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82436.647173 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 87633.448609 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 87633.448609 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82436.647173 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 91064.167743 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 91061.767405 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82436.647173 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 91064.167743 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 70298.609693 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 85972.521147 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 34008905 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003965 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21224 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 200821 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 200820 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
1187,1192c1195,1200
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 14267181 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 6469733 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 12168504 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 3012569 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 1490485 # Transaction distribution
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 14267344 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 6459789 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 12178209 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 3013479 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 1493524 # Transaction distribution
1194,1210c1202,1218
< system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2737555 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2737555 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadCleanReq 1076 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266107 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2738 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51010503 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 51013241 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106368 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176436672 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 2176543040 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 6137564 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 104608640 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 23142303 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.009630 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.097659 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::UpgradeReq 7 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 7 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 2737604 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 2737604 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadCleanReq 1077 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266268 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2742 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51011129 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 51013871 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106560 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176463552 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 2176570112 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 6141063 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 104579840 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 23146008 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.009594 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.097477 # Request fanout histogram
1212,1213c1220,1221
< system.cpu.toL2Bus.snoop_fanout::0 22919446 99.04% 99.04% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 222856 0.96% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 22923954 99.04% 99.04% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 222053 0.96% 100.00% # Request fanout histogram
1218,1221c1226,1229
< system.cpu.toL2Bus.snoop_fanout::total 23142303 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 34007983525 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 4.4 # Layer utilization (%)
< system.cpu.toL2Bus.snoopLayer0.occupancy 16538 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 23146008 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 34008401540 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 4.3 # Layer utilization (%)
> system.cpu.toL2Bus.snoopLayer0.occupancy 16551 # Layer occupancy (ticks)
1223c1231
< system.cpu.toL2Bus.respLayer0.occupancy 1611000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1614499 # Layer occupancy (ticks)
1225,1228c1233,1236
< system.cpu.toL2Bus.respLayer1.occupancy 25505500994 # Layer occupancy (ticks)
< system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%)
< system.membus.snoop_filter.tot_requests 9332231 # Total number of requests made to the snoop filter.
< system.membus.snoop_filter.hit_single_requests 4668264 # Number of requests hitting in the snoop filter with a single holder of the requested data.
---
> system.cpu.toL2Bus.respLayer1.occupancy 25505814993 # Layer occupancy (ticks)
> system.cpu.toL2Bus.respLayer1.utilization 3.2 # Layer utilization (%)
> system.membus.snoop_filter.tot_requests 9333193 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 4668760 # Number of requests hitting in the snoop filter with a single holder of the requested data.
1233,1244c1241,1252
< system.membus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 3708204 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1634499 # Transaction distribution
< system.membus.trans_dist::CleanEvict 3012569 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 9 # Transaction distribution
< system.membus.trans_dist::ReadExReq 976948 # Transaction distribution
< system.membus.trans_dist::ReadExResp 976948 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 3708206 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14017383 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 14017383 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404457664 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 404457664 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 787742202500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 3708223 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1634049 # Transaction distribution
> system.membus.trans_dist::CleanEvict 3013479 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 7 # Transaction distribution
> system.membus.trans_dist::ReadExReq 977434 # Transaction distribution
> system.membus.trans_dist::ReadExResp 977434 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 3708224 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14018850 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 14018850 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404461184 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 404461184 # Cumulative packet size per connected master and slave (bytes)
1247c1255
< system.membus.snoop_fanout::samples 4685163 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 4685665 # Request fanout histogram
1251c1259
< system.membus.snoop_fanout::0 4685163 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 4685665 100.00% 100.00% # Request fanout histogram
1256,1260c1264,1268
< system.membus.snoop_fanout::total 4685163 # Request fanout histogram
< system.membus.reqLayer0.occupancy 17662405597 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
< system.membus.respLayer1.occupancy 25476549560 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 3.3 # Layer utilization (%)
---
> system.membus.snoop_fanout::total 4685665 # Request fanout histogram
> system.membus.reqLayer0.occupancy 17659262741 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
> system.membus.respLayer1.occupancy 25448696800 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 3.2 # Layer utilization (%)