3,5c3,5
< sim_seconds 0.767804 # Number of seconds simulated
< sim_ticks 767803843500 # Number of ticks simulated
< final_tick 767803843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.770752 # Number of seconds simulated
> sim_ticks 770752376500 # Number of ticks simulated
> final_tick 770752376500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 212750 # Simulator instruction rate (inst/s)
< host_op_rate 229206 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 105758139 # Simulator tick rate (ticks/s)
< host_mem_usage 308972 # Number of bytes of host memory used
< host_seconds 7260.00 # Real time elapsed on the host
---
> host_inst_rate 147248 # Simulator instruction rate (inst/s)
> host_op_rate 158637 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 73478006 # Simulator tick rate (ticks/s)
> host_mem_usage 329736 # Number of bytes of host memory used
> host_seconds 10489.57 # Real time elapsed on the host
16,53c16,53
< system.physmem.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.physmem.bytes_read::cpu.inst 65216 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 235320384 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 63711040 # Number of bytes read from this memory
< system.physmem.bytes_read::total 299096640 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 65216 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 65216 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 104697344 # Number of bytes written to this memory
< system.physmem.bytes_written::total 104697344 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 1019 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 3676881 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 995485 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 4673385 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1635896 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1635896 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 84938 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 306485030 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 82978277 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 389548245 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 84938 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 84938 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 136359495 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 136359495 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 136359495 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 84938 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 306485030 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 82978277 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 525907740 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 4673385 # Number of read requests accepted
< system.physmem.writeReqs 1635896 # Number of write requests accepted
< system.physmem.readBursts 4673385 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1635896 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 298598336 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 498304 # Total number of bytes read from write queue
< system.physmem.bytesWritten 104693696 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 299096640 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 104697344 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 7786 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.physmem.bytes_read::cpu.inst 65664 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 236002624 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 63781504 # Number of bytes read from this memory
> system.physmem.bytes_read::total 299849792 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 65664 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 65664 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 104607936 # Number of bytes written to this memory
> system.physmem.bytes_written::total 104607936 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 1026 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 3687541 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 996586 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 4685153 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1634499 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1634499 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 85195 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 306197725 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 82752264 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 389035183 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 85195 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 85195 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 135721847 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 135721847 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 135721847 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 85195 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 306197725 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 82752264 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 524757030 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 4685154 # Number of read requests accepted
> system.physmem.writeReqs 1634499 # Number of write requests accepted
> system.physmem.readBursts 4685154 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1634499 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 299347712 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 502144 # Total number of bytes read from write queue
> system.physmem.bytesWritten 104604544 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 299849856 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 104607936 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 7846 # Number of DRAM read bursts serviced by the write queue
56,87c56,87
< system.physmem.perBankRdBursts::0 301126 # Per bank write bursts
< system.physmem.perBankRdBursts::1 298685 # Per bank write bursts
< system.physmem.perBankRdBursts::2 284250 # Per bank write bursts
< system.physmem.perBankRdBursts::3 287696 # Per bank write bursts
< system.physmem.perBankRdBursts::4 287908 # Per bank write bursts
< system.physmem.perBankRdBursts::5 285921 # Per bank write bursts
< system.physmem.perBankRdBursts::6 280645 # Per bank write bursts
< system.physmem.perBankRdBursts::7 277366 # Per bank write bursts
< system.physmem.perBankRdBursts::8 293768 # Per bank write bursts
< system.physmem.perBankRdBursts::9 299240 # Per bank write bursts
< system.physmem.perBankRdBursts::10 292091 # Per bank write bursts
< system.physmem.perBankRdBursts::11 297828 # Per bank write bursts
< system.physmem.perBankRdBursts::12 299005 # Per bank write bursts
< system.physmem.perBankRdBursts::13 298032 # Per bank write bursts
< system.physmem.perBankRdBursts::14 293386 # Per bank write bursts
< system.physmem.perBankRdBursts::15 288652 # Per bank write bursts
< system.physmem.perBankWrBursts::0 103980 # Per bank write bursts
< system.physmem.perBankWrBursts::1 101811 # Per bank write bursts
< system.physmem.perBankWrBursts::2 99205 # Per bank write bursts
< system.physmem.perBankWrBursts::3 99712 # Per bank write bursts
< system.physmem.perBankWrBursts::4 99000 # Per bank write bursts
< system.physmem.perBankWrBursts::5 99026 # Per bank write bursts
< system.physmem.perBankWrBursts::6 102693 # Per bank write bursts
< system.physmem.perBankWrBursts::7 104157 # Per bank write bursts
< system.physmem.perBankWrBursts::8 105172 # Per bank write bursts
< system.physmem.perBankWrBursts::9 104159 # Per bank write bursts
< system.physmem.perBankWrBursts::10 102137 # Per bank write bursts
< system.physmem.perBankWrBursts::11 102620 # Per bank write bursts
< system.physmem.perBankWrBursts::12 102863 # Per bank write bursts
< system.physmem.perBankWrBursts::13 102594 # Per bank write bursts
< system.physmem.perBankWrBursts::14 104213 # Per bank write bursts
< system.physmem.perBankWrBursts::15 102497 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 301314 # Per bank write bursts
> system.physmem.perBankRdBursts::1 301808 # Per bank write bursts
> system.physmem.perBankRdBursts::2 285079 # Per bank write bursts
> system.physmem.perBankRdBursts::3 287721 # Per bank write bursts
> system.physmem.perBankRdBursts::4 288732 # Per bank write bursts
> system.physmem.perBankRdBursts::5 286480 # Per bank write bursts
> system.physmem.perBankRdBursts::6 281880 # Per bank write bursts
> system.physmem.perBankRdBursts::7 278193 # Per bank write bursts
> system.physmem.perBankRdBursts::8 293719 # Per bank write bursts
> system.physmem.perBankRdBursts::9 299847 # Per bank write bursts
> system.physmem.perBankRdBursts::10 291529 # Per bank write bursts
> system.physmem.perBankRdBursts::11 297903 # Per bank write bursts
> system.physmem.perBankRdBursts::12 299405 # Per bank write bursts
> system.physmem.perBankRdBursts::13 299387 # Per bank write bursts
> system.physmem.perBankRdBursts::14 294305 # Per bank write bursts
> system.physmem.perBankRdBursts::15 290006 # Per bank write bursts
> system.physmem.perBankWrBursts::0 103629 # Per bank write bursts
> system.physmem.perBankWrBursts::1 101748 # Per bank write bursts
> system.physmem.perBankWrBursts::2 99222 # Per bank write bursts
> system.physmem.perBankWrBursts::3 99944 # Per bank write bursts
> system.physmem.perBankWrBursts::4 98990 # Per bank write bursts
> system.physmem.perBankWrBursts::5 98822 # Per bank write bursts
> system.physmem.perBankWrBursts::6 102440 # Per bank write bursts
> system.physmem.perBankWrBursts::7 104048 # Per bank write bursts
> system.physmem.perBankWrBursts::8 105134 # Per bank write bursts
> system.physmem.perBankWrBursts::9 103994 # Per bank write bursts
> system.physmem.perBankWrBursts::10 101818 # Per bank write bursts
> system.physmem.perBankWrBursts::11 102570 # Per bank write bursts
> system.physmem.perBankWrBursts::12 102850 # Per bank write bursts
> system.physmem.perBankWrBursts::13 102376 # Per bank write bursts
> system.physmem.perBankWrBursts::14 104237 # Per bank write bursts
> system.physmem.perBankWrBursts::15 102624 # Per bank write bursts
90c90
< system.physmem.totGap 767803802500 # Total gap between requests
---
> system.physmem.totGap 770752366000 # Total gap between requests
97c97
< system.physmem.readPktSize::6 4673385 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 4685154 # Read request sizes (log2)
104,120c104,120
< system.physmem.writePktSize::6 1635896 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 2761676 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 1029435 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 325938 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 231496 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 148985 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 81565 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 37573 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 23615 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 17937 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 4209 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1691 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 802 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 456 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 219 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1634499 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 2776424 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1031022 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 327510 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 229431 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 146630 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 80164 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 37430 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 23802 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 17710 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 4122 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1619 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 771 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 426 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 239 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 7 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
152,181c152,181
< system.physmem.wrQLenPdf::15 25842 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 28487 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 55926 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 73202 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 85102 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 93551 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 100017 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 103625 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 105684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 106315 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 107141 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 108142 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 109489 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 111392 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 111204 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 103853 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 101152 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 100444 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 3026 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1226 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 559 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 257 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 52 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 23 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 15 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 5 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 25690 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 28168 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 56471 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 73716 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 85142 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 93999 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 100116 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 103738 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 105456 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 106103 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 107040 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 108147 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 109209 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 110723 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 110766 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 103820 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 100949 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 100270 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 2888 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1126 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 505 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 211 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 109 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 44 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 28 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 14 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
201,255c201,262
< system.physmem.bytesPerActivate::samples 4243508 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 95.037234 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 78.939445 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 102.771916 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 3380789 79.67% 79.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 664864 15.67% 95.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 95298 2.25% 97.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 35170 0.83% 98.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 22966 0.54% 98.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 12163 0.29% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 7344 0.17% 99.41% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 19569 0.46% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 4243508 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 97753 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 47.727814 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 100.001834 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-255 95363 97.56% 97.56% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::256-511 1154 1.18% 98.74% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-767 681 0.70% 99.43% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::768-1023 412 0.42% 99.85% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-1279 112 0.11% 99.97% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1280-1535 14 0.01% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1536-1791 8 0.01% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1792-2047 2 0.00% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2048-2303 1 0.00% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2560-2815 2 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2816-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::3328-3583 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::3840-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::4096-4351 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 97753 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 97753 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.734412 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.690766 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.259650 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 68350 69.92% 69.92% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 1981 2.03% 71.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 18352 18.77% 90.72% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 5702 5.83% 96.55% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 2016 2.06% 98.62% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 741 0.76% 99.37% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 311 0.32% 99.69% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 155 0.16% 99.85% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 75 0.08% 99.93% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 43 0.04% 99.97% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 16 0.02% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::27 8 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::29 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::35 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 97753 # Writes before turning the bus around for reads
< system.physmem.totQLat 128478496877 # Total ticks spent queuing
< system.physmem.totMemAccLat 215958478127 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 23327995000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 27537.41 # Average queueing delay per DRAM burst
---
> system.physmem.bytesPerActivate::samples 4255173 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 94.931559 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 78.862227 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 102.833954 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 3394354 79.77% 79.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 663703 15.60% 95.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 94226 2.21% 97.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 35436 0.83% 98.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 22765 0.53% 98.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 12171 0.29% 99.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 7342 0.17% 99.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5345 0.13% 99.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 19831 0.47% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 4255173 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 97794 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 47.827914 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 99.473591 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-127 93707 95.82% 95.82% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::128-255 1671 1.71% 97.53% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::256-383 768 0.79% 98.31% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::384-511 406 0.42% 98.73% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-639 365 0.37% 99.10% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::640-767 337 0.34% 99.45% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::768-895 234 0.24% 99.69% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::896-1023 165 0.17% 99.86% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-1151 89 0.09% 99.95% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1152-1279 24 0.02% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1280-1407 12 0.01% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1664-1791 3 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::3968-4095 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 97794 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 97794 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.713152 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.671812 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.223073 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 68724 70.27% 70.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 1896 1.94% 72.21% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 18671 19.09% 91.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 5634 5.76% 97.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 1729 1.77% 98.83% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 613 0.63% 99.46% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 266 0.27% 99.73% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 147 0.15% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 67 0.07% 99.95% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 30 0.03% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 9 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::27 6 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::38 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 97794 # Writes before turning the bus around for reads
> system.physmem.totQLat 128325813562 # Total ticks spent queuing
> system.physmem.totMemAccLat 216025338562 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 23386540000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 27435.83 # Average queueing delay per DRAM burst
257,261c264,268
< system.physmem.avgMemAccLat 46287.41 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 388.90 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 136.35 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 389.55 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 136.36 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 46185.83 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 388.38 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 135.72 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 389.04 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 135.72 # Average system write bandwidth in MiByte/s
263,265c270,272
< system.physmem.busUtil 4.10 # Data bus utilization in percentage
< system.physmem.busUtilRead 3.04 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 1.07 # Data bus utilization in percentage for writes
---
> system.physmem.busUtil 4.09 # Data bus utilization in percentage
> system.physmem.busUtilRead 3.03 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes
267,269c274,276
< system.physmem.avgWrQLen 24.85 # Average write queue length when enqueuing
< system.physmem.readRowHits 1710736 # Number of row buffer hits during reads
< system.physmem.writeRowHits 347188 # Number of row buffer hits during writes
---
> system.physmem.avgWrQLen 24.86 # Average write queue length when enqueuing
> system.physmem.readRowHits 1715091 # Number of row buffer hits during reads
> system.physmem.writeRowHits 341475 # Number of row buffer hits during writes
271,284c278,291
< system.physmem.writeRowHitRate 21.22 # Row buffer hit rate for writes
< system.physmem.avgGap 121694.34 # Average gap between requests
< system.physmem.pageHitRate 32.66 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 15941658600 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 8698325625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 17967846000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 5246104320 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 414557114310 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 97034832000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 609594982455 # Total energy per rank (pJ)
< system.physmem_0.averagePower 793.947771 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 158900831773 # Time in different power states
< system.physmem_0.memoryStateTime::REF 25638600000 # Time in different power states
---
> system.physmem.writeRowHitRate 20.89 # Row buffer hit rate for writes
> system.physmem.avgGap 121961.18 # Average gap between requests
> system.physmem.pageHitRate 32.58 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 15989112720 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 8724218250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 18025846800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 5241069360 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 417928675995 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 95843265750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 612093526155 # Total energy per rank (pJ)
> system.physmem_0.averagePower 794.157652 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 156909498029 # Time in different power states
> system.physmem_0.memoryStateTime::REF 25736880000 # Time in different power states
286c293
< system.physmem_0.memoryStateTime::ACT 583262954477 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 588099785971 # Time in different power states
288,298c295,305
< system.physmem_1.actEnergy 16139254320 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 8806140750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 18423607800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 5354132400 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 50149101600 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 410075734410 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 100965867000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 609913838280 # Total energy per rank (pJ)
< system.physmem_1.averagePower 794.363055 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 165472936005 # Time in different power states
< system.physmem_1.memoryStateTime::REF 25638600000 # Time in different power states
---
> system.physmem_1.actEnergy 16179556680 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 8828131125 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 18455494200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 5349602880 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 50341337280 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 412908393870 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 100247038500 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 612309554535 # Total energy per rank (pJ)
> system.physmem_1.averagePower 794.437909 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 164276600328 # Time in different power states
> system.physmem_1.memoryStateTime::REF 25736880000 # Time in different power states
300c307
< system.physmem_1.memoryStateTime::ACT 576690946995 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 580733308672 # Time in different power states
302,307c309,314
< system.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 286292198 # Number of BP lookups
< system.cpu.branchPred.condPredicted 223415085 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 14631198 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 158639381 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 150355883 # Number of BTB hits
---
> system.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 286275195 # Number of BP lookups
> system.cpu.branchPred.condPredicted 223398341 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 14628424 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 157667483 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 150349199 # Number of BTB hits
309,315c316,322
< system.cpu.branchPred.BTBHitPct 94.778410 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 16642674 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 61 # Number of incorrect RAS predictions.
< system.cpu.branchPred.indirectLookups 3027 # Number of indirect predictor lookups.
< system.cpu.branchPred.indirectHits 1888 # Number of indirect target hits.
< system.cpu.branchPred.indirectMisses 1139 # Number of indirect misses.
< system.cpu.branchPredindirectMispredicted 136 # Number of mispredicted indirect branches.
---
> system.cpu.branchPred.BTBHitPct 95.358406 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 16643020 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 63 # Number of incorrect RAS predictions.
> system.cpu.branchPred.indirectLookups 3069 # Number of indirect predictor lookups.
> system.cpu.branchPred.indirectHits 1906 # Number of indirect target hits.
> system.cpu.branchPred.indirectMisses 1163 # Number of indirect misses.
> system.cpu.branchPredindirectMispredicted 137 # Number of mispredicted indirect branches.
317c324
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
347c354
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
377c384
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
407c414
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
438,439c445,446
< system.cpu.pwrStateResidencyTicks::ON 767803843500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 1535607688 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 770752376500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 1541504754 # number of cpu cycles simulated
442,454c449,461
< system.cpu.fetch.icacheStallCycles 13928755 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 2067573004 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 286292198 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 167000445 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 1506957925 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 29287239 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.IcacheWaitRetryStallCycles 992 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 656968436 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 958 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 1535531474 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.442524 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.228151 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 13925502 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 2067484101 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 286275195 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 166994125 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 1512857238 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 29281631 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 279 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.IcacheWaitRetryStallCycles 1018 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 656940019 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 946 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 1541424852 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.436951 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.229037 # Number of instructions fetched each cycle (Total)
456,459c463,466
< system.cpu.fetch.rateDist::0 453078112 29.51% 29.51% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 465445913 30.31% 59.82% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 101427094 6.61% 66.42% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 515580355 33.58% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 459011037 29.78% 29.78% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 465435057 30.20% 59.97% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 101419068 6.58% 66.55% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 515559690 33.45% 100.00% # Number of instructions fetched each cycle (Total)
463,490c470,497
< system.cpu.fetch.rateDist::total 1535531474 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.186436 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.346420 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 74706893 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 538056624 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 849925630 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 58199384 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 14642943 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 42203258 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 730 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 2037275151 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 52500118 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 14642943 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 139803593 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 457092273 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 13624 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 837854747 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 86124294 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 1976468269 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 26746953 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 45300136 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 126625 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1588286 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 25069373 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 1985943496 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 9128568020 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 2432995559 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 145 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 1541424852 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.185712 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.341212 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 74709451 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 544021839 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 849845592 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 58207832 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 14640138 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 42201657 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 726 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 2037180089 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 52484609 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 14640138 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 139806563 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 462600801 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 15884 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 837785307 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 86576159 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 1976384850 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 26739549 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 45323653 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 126929 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1602638 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 25499860 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 1985860548 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 9128169124 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 2432875929 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups
492,493c499,500
< system.cpu.rename.UndoneMaps 311044551 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 174 # count of serializing insts renamed
---
> system.cpu.rename.UndoneMaps 310961603 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 175 # count of serializing insts renamed
495,500c502,507
< system.cpu.rename.skidInsts 111502635 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 542585286 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 199312070 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 26927303 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 29234152 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 1948047142 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.rename.skidInsts 111534180 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 542566077 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 199303375 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 26892889 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 29237160 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 1947969517 # Number of instructions added to the IQ (excludes non-spec)
502,505c509,512
< system.cpu.iq.iqInstsIssued 1857492479 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 13497229 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 284014957 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 647584065 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqInstsIssued 1857492369 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 13496690 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 283937332 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 647289356 # Number of squashed operands that are examined and possibly removed from graph
507,509c514,516
< system.cpu.iq.issued_per_cycle::samples 1535531474 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.209674 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.150607 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 1541424852 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.205049 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.150817 # Number of insts issued each cycle
511,516c518,523
< system.cpu.iq.issued_per_cycle::0 582548107 37.94% 37.94% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 326134076 21.24% 59.18% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 378190631 24.63% 83.81% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 219663672 14.31% 98.11% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 28988815 1.89% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 6173 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 588435916 38.17% 38.17% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 326131475 21.16% 59.33% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 378210554 24.54% 83.87% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 219654013 14.25% 98.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 28986723 1.88% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 6171 0.00% 100.00% # Number of insts issued each cycle
523c530
< system.cpu.iq.issued_per_cycle::total 1535531474 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1541424852 # Number of insts issued each cycle
525,526c532,533
< system.cpu.iq.fu_full::IntAlu 166038532 40.99% 40.99% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 1976 0.00% 40.99% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 166021321 40.99% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 1993 0.00% 40.99% # attempts to use FU when none available
554,555c561,562
< system.cpu.iq.fu_full::MemRead 191466165 47.27% 88.26% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 47567904 11.74% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::MemRead 191489776 47.28% 88.26% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 47539480 11.74% 100.00% # attempts to use FU when none available
559,560c566,567
< system.cpu.iq.FU_type_0::IntAlu 1138257084 61.28% 61.28% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 800920 0.04% 61.32% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 1138243662 61.28% 61.28% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 800931 0.04% 61.32% # Type of FU issued
582c589
< system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued
588,589c595,596
< system.cpu.iq.FU_type_0::MemRead 532121986 28.65% 89.97% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 186312436 10.03% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 532135699 28.65% 89.97% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 186312026 10.03% 100.00% # Type of FU issued
592,604c599,611
< system.cpu.iq.FU_type_0::total 1857492479 # Type of FU issued
< system.cpu.iq.rate 1.209614 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 405074577 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.218076 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 5669087998 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 2232075127 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1805719723 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 240 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 252 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 72 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 2262566922 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 17809734 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 1857492369 # Type of FU issued
> system.cpu.iq.rate 1.204986 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 405052570 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.218064 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 5674958613 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 2231919871 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1805704142 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 2262544806 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 133 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 17811536 # Number of loads that had data forwarded from stores
606,609c613,616
< system.cpu.iew.lsq.thread0.squashedLoads 84278952 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 66732 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 13280 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 24465025 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 84259743 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 66618 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 13244 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 24456330 # Number of stores squashed
612,613c619,620
< system.cpu.iew.lsq.thread0.rescheduledLoads 4505677 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 4870984 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 4512030 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 4891489 # Number of times an access to memory failed due to the cache being blocked
615,618c622,625
< system.cpu.iew.iewSquashCycles 14642943 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 25375759 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1295309 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 1948047519 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 14640138 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 25364964 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1346928 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 1947969899 # Number of instructions dispatched to IQ
620,621c627,628
< system.cpu.iew.iewDispLoadInsts 542585286 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 199312070 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 542566077 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 199303375 # Number of dispatched store instructions
623,631c630,638
< system.cpu.iew.iewIQFullEvents 159534 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 1134383 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 13280 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 7701154 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 8705181 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 16406335 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1827826675 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 516940315 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 29665804 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewIQFullEvents 159350 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 1186169 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 13244 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 7699482 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 8703162 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 16402644 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1827831567 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 516957415 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 29660802 # Number of squashed instructions skipped in execute
633,642c640,649
< system.cpu.iew.exec_nop 146 # number of nop insts executed
< system.cpu.iew.exec_refs 698692225 # number of memory reference insts executed
< system.cpu.iew.exec_branches 229542687 # Number of branches executed
< system.cpu.iew.exec_stores 181751910 # Number of stores executed
< system.cpu.iew.exec_rate 1.190295 # Inst execution rate
< system.cpu.iew.wb_sent 1808754463 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1805719795 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 1169207800 # num instructions producing a value
< system.cpu.iew.wb_consumers 1689618799 # num instructions consuming a value
< system.cpu.iew.wb_rate 1.175899 # insts written-back per cycle
---
> system.cpu.iew.exec_nop 151 # number of nop insts executed
> system.cpu.iew.exec_refs 698708795 # number of memory reference insts executed
> system.cpu.iew.exec_branches 229542425 # Number of branches executed
> system.cpu.iew.exec_stores 181751380 # Number of stores executed
> system.cpu.iew.exec_rate 1.185745 # Inst execution rate
> system.cpu.iew.wb_sent 1808736265 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1805704212 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 1169174812 # num instructions producing a value
> system.cpu.iew.wb_consumers 1689572222 # num instructions consuming a value
> system.cpu.iew.wb_rate 1.171391 # insts written-back per cycle
644c651
< system.cpu.commit.commitSquashedInsts 258113026 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 258041892 # The number of squashed insts skipped by commit
646,649c653,656
< system.cpu.commit.branchMispredicts 14630522 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 1496036001 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.112294 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.028030 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 14627747 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 1501940299 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.107922 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.025263 # Number of insts commited each cycle
651,659c658,666
< system.cpu.commit.committed_per_cycle::0 915722932 61.21% 61.21% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 250663462 16.76% 77.97% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 110062832 7.36% 85.32% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 55282207 3.70% 89.02% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 29306686 1.96% 90.98% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 34079757 2.28% 93.25% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 24721963 1.65% 94.91% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 18129916 1.21% 96.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 58066246 3.88% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 921653315 61.36% 61.36% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 250636600 16.69% 78.05% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 110060462 7.33% 85.38% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 55269176 3.68% 89.06% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 29319156 1.95% 91.01% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 34080655 2.27% 93.28% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 24723288 1.65% 94.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 18133421 1.21% 96.13% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 58064226 3.87% 100.00% # Number of insts commited each cycle
663c670
< system.cpu.commit.committed_per_cycle::total 1496036001 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 1501940299 # Number of insts commited each cycle
709,713c716,720
< system.cpu.commit.bw_lim_events 58066246 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 3360114616 # The number of ROB reads
< system.cpu.rob.rob_writes 3883791528 # The number of ROB writes
< system.cpu.timesIdled 840 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 76214 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.commit.bw_lim_events 58064226 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 3365949800 # The number of ROB reads
> system.cpu.rob.rob_writes 3883638365 # The number of ROB writes
> system.cpu.timesIdled 837 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 79902 # Total number of cycles that the CPU has spent unscheduled due to idling
716,721c723,728
< system.cpu.cpi 0.994202 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.994202 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.005832 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.005832 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 2175815840 # number of integer regfile reads
< system.cpu.int_regfile_writes 1261595611 # number of integer regfile writes
---
> system.cpu.cpi 0.998020 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.998020 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.001984 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.001984 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 2175818987 # number of integer regfile reads
> system.cpu.int_regfile_writes 1261576435 # number of integer regfile writes
723,726c730,733
< system.cpu.fp_regfile_writes 54 # number of floating regfile writes
< system.cpu.cc_regfile_reads 6965778765 # number of cc regfile reads
< system.cpu.cc_regfile_writes 551854660 # number of cc regfile writes
< system.cpu.misc_regfile_reads 675853618 # number of misc regfile reads
---
> system.cpu.fp_regfile_writes 52 # number of floating regfile writes
> system.cpu.cc_regfile_reads 6965775009 # number of cc regfile reads
> system.cpu.cc_regfile_writes 551856674 # number of cc regfile writes
> system.cpu.misc_regfile_reads 675846934 # number of misc regfile reads
728,737c735,744
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.tags.replacements 17003710 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.964650 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 638076364 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 17004222 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 37.524584 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 78426500 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.964650 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.tags.replacements 17003150 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.964340 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 638065664 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 17003662 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 37.525191 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 79206500 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.964340 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999930 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999930 # Average percentage of cache occupancy
739,740c746,747
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 395 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 117 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 406 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id
742,748c749,755
< system.cpu.dcache.tags.tag_accesses 1335728390 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1335728390 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 469357603 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 469357603 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 168718615 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 168718615 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 1335709608 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1335709608 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 469347574 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 469347574 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 168717937 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 168717937 # number of WriteReq hits
753,760c760,767
< system.cpu.dcache.demand_hits::cpu.data 638076218 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 638076218 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 638076218 # number of overall hits
< system.cpu.dcache.overall_hits::total 638076218 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 17418310 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 17418310 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3867432 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3867432 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 638065511 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 638065511 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 638065511 # number of overall hits
> system.cpu.dcache.overall_hits::total 638065511 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 17419228 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 17419228 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3868110 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3868110 # number of WriteReq misses
765,780c772,787
< system.cpu.dcache.demand_misses::cpu.data 21285742 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 21285742 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 21285744 # number of overall misses
< system.cpu.dcache.overall_misses::total 21285744 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 411945425500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 411945425500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 148954509432 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 148954509432 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 196500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 196500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 560899934932 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 560899934932 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 560899934932 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 560899934932 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 486775913 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 486775913 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 21287338 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 21287338 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 21287340 # number of overall misses
> system.cpu.dcache.overall_misses::total 21287340 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 416423435500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 416423435500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 150253086257 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 150253086257 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 199500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 199500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 566676521757 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 566676521757 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 566676521757 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 566676521757 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 486766802 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 486766802 # number of ReadReq accesses(hits+misses)
789,796c796,803
< system.cpu.dcache.demand_accesses::cpu.data 659361960 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 659361960 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 659361962 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 659361962 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035783 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.035783 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022409 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.022409 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 659352849 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 659352849 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 659352851 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 659352851 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022413 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.022413 # miss rate for WriteReq accesses
801,826c808,833
< system.cpu.dcache.demand_miss_rate::cpu.data 0.032282 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.032282 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.032282 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.032282 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23650.137442 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 23650.137442 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38515.094624 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 38515.094624 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49125 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49125 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 26350.969345 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 26350.969345 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 26350.966869 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 26350.966869 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 20530392 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 3397643 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 943594 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 67194 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.757654 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 50.564678 # average number of cycles each access was blocked
< system.cpu.dcache.writebacks::writebacks 17003710 # number of writebacks
< system.cpu.dcache.writebacks::total 17003710 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151672 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 3151672 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129843 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1129843 # number of WriteReq MSHR hits
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.032285 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.032285 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.032285 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.032285 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23905.963887 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 23905.963887 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38844.057242 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 38844.057242 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 49875 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 49875 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 26620.356277 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 26620.356277 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 26620.353776 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 26620.353776 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 20685246 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 3452781 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 946049 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 67233 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.864878 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 51.355450 # average number of cycles each access was blocked
> system.cpu.dcache.writebacks::writebacks 17003150 # number of writebacks
> system.cpu.dcache.writebacks::total 17003150 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3153076 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 3153076 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1130592 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1130592 # number of WriteReq MSHR hits
829,836c836,843
< system.cpu.dcache.demand_mshr_hits::cpu.data 4281515 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 4281515 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 4281515 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 4281515 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266638 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 14266638 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737589 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2737589 # number of WriteReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 4283668 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 4283668 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 4283668 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 4283668 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14266152 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 14266152 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737518 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2737518 # number of WriteReq MSHR misses
839,852c846,859
< system.cpu.dcache.demand_mshr_misses::cpu.data 17004227 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 17004227 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 17004228 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 17004228 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 331755520500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 331755520500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115729212265 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 115729212265 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 447484732765 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 447484732765 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 447484800765 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 447484800765 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 17003670 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 17003670 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 17003671 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 17003671 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335207977500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 335207977500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116679674033 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 116679674033 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69000 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451887651533 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 451887651533 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451887720533 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 451887720533 # number of overall MSHR miss cycles
859,878c866,885
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.025789 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025789 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.025789 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23253.938349 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23253.938349 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42274.136938 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42274.136938 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26316.087921 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26316.087921 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26316.090373 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26316.090373 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.tags.replacements 589 # number of replacements
< system.cpu.icache.tags.tagsinuse 444.836642 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 656966815 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1075 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 611131.920930 # Average number of references to valid blocks.
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.025788 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025788 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.025788 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23496.733913 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23496.733913 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42622.431718 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42622.431718 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69000 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26575.889295 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26575.889295 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26575.891790 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26575.891790 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.tags.replacements 588 # number of replacements
> system.cpu.icache.tags.tagsinuse 444.874436 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 656938405 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1074 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 611674.492551 # Average number of references to valid blocks.
880,882c887,889
< system.cpu.icache.tags.occ_blocks::cpu.inst 444.836642 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.868822 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.868822 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 444.874436 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.868895 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.868895 # Average percentage of cache occupancy
884c891
< system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 29 # Occupied blocks per task id
886c893
< system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::4 443 # Occupied blocks per task id
888,914c895,921
< system.cpu.icache.tags.tag_accesses 1313937945 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 1313937945 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 656966815 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 656966815 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 656966815 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 656966815 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 656966815 # number of overall hits
< system.cpu.icache.overall_hits::total 656966815 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1620 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1620 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1620 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1620 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1620 # number of overall misses
< system.cpu.icache.overall_misses::total 1620 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 98788987 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 98788987 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 98788987 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 98788987 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 98788987 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 98788987 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 656968435 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 656968435 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 656968435 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 656968435 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 656968435 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 656968435 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 1313881106 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 1313881106 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 656938405 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 656938405 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 656938405 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 656938405 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 656938405 # number of overall hits
> system.cpu.icache.overall_hits::total 656938405 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1611 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1611 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1611 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1611 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1611 # number of overall misses
> system.cpu.icache.overall_misses::total 1611 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 103785485 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 103785485 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 103785485 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 103785485 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 103785485 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 103785485 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 656940016 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 656940016 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 656940016 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 656940016 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 656940016 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 656940016 # number of overall (read+write) accesses
921,940c928,947
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 60980.856173 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 60980.856173 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 60980.856173 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 60980.856173 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 60980.856173 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 17260 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 439 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 183 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 94.316940 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 54.875000 # average number of cycles each access was blocked
< system.cpu.icache.writebacks::writebacks 589 # number of writebacks
< system.cpu.icache.writebacks::total 589 # number of writebacks
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 544 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 544 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 544 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 544 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 544 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 544 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64423.019863 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 64423.019863 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 64423.019863 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 64423.019863 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 64423.019863 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 64423.019863 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 16825 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 586 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 185 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 10 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 90.945946 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 58.600000 # average number of cycles each access was blocked
> system.cpu.icache.writebacks::writebacks 588 # number of writebacks
> system.cpu.icache.writebacks::total 588 # number of writebacks
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 535 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 535 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 535 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 535 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 535 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 535 # number of overall MSHR hits
947,952c954,959
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 73759491 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 73759491 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 73759491 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 73759491 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 73759491 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 73759491 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 75943989 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 75943989 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 75943989 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 75943989 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 75943989 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 75943989 # number of overall MSHR miss cycles
959,968c966,975
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68549.712825 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68549.712825 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68549.712825 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 68549.712825 # average overall mshr miss latency
< system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.prefetcher.num_hwpf_issued 11611376 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 11640224 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 19566 # number of redundant prefetches already in prefetch queue
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70579.915428 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70579.915428 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70579.915428 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 70579.915428 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70579.915428 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 70579.915428 # average overall mshr miss latency
> system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.prefetcher.num_hwpf_issued 11612917 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 11641367 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 19112 # number of redundant prefetches already in prefetch queue
971,1052c978,1057
< system.cpu.l2cache.prefetcher.pfSpanPage 4656640 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.tags.replacements 4706089 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 16099.754607 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 22829126 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 4722015 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.834615 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 54111720000 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 13098.345143 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 2.290302 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 2999.119162 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.799460 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.000140 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.183052 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.982651 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 829 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15097 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::1 636 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 191 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 453 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2943 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 4353 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 5523 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1825 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.050598 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.921448 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 552242422 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 552242422 # Number of data accesses
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.cpu.l2cache.WritebackDirty_hits::writebacks 4833112 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackDirty_hits::total 4833112 # number of WritebackDirty hits
< system.cpu.l2cache.WritebackClean_hits::writebacks 12149903 # number of WritebackClean hits
< system.cpu.l2cache.WritebackClean_hits::total 12149903 # number of WritebackClean hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1757087 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1757087 # number of ReadExReq hits
< system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 56 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadCleanReq_hits::total 56 # number of ReadCleanReq hits
< system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11522367 # number of ReadSharedReq hits
< system.cpu.l2cache.ReadSharedReq_hits::total 11522367 # number of ReadSharedReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 56 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 13279454 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 13279510 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 56 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 13279454 # number of overall hits
< system.cpu.l2cache.overall_hits::total 13279510 # number of overall hits
< system.cpu.l2cache.UpgradeReq_misses::cpu.data 6 # number of UpgradeReq misses
< system.cpu.l2cache.UpgradeReq_misses::total 6 # number of UpgradeReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 980546 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 980546 # number of ReadExReq misses
< system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1020 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadCleanReq_misses::total 1020 # number of ReadCleanReq misses
< system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2744222 # number of ReadSharedReq misses
< system.cpu.l2cache.ReadSharedReq_misses::total 2744222 # number of ReadSharedReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 1020 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 3724768 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 3725788 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 1020 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 3724768 # number of overall misses
< system.cpu.l2cache.overall_misses::total 3725788 # number of overall misses
< system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 121000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.UpgradeReq_miss_latency::total 121000 # number of UpgradeReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99083213500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 99083213500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72272000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 72272000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 234079710000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 234079710000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 72272000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 333162923500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 333235195500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 72272000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 333162923500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 333235195500 # number of overall miss cycles
< system.cpu.l2cache.WritebackDirty_accesses::writebacks 4833112 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackDirty_accesses::total 4833112 # number of WritebackDirty accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::writebacks 12149903 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.WritebackClean_accesses::total 12149903 # number of WritebackClean accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::cpu.data 6 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.UpgradeReq_accesses::total 6 # number of UpgradeReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737633 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2737633 # number of ReadExReq accesses(hits+misses)
---
> system.cpu.l2cache.prefetcher.pfSpanPage 4655505 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.tags.replacements 4647068 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 15866.736257 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 13267029 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 4662976 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 2.845185 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 15646.626307 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 220.109950 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.954994 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.013434 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.968429 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 143 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15765 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 115 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 23 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 463 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4068 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 7095 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2886 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1253 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.008728 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.962219 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 561777243 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 561777243 # Number of data accesses
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.cpu.l2cache.WritebackDirty_hits::writebacks 4835234 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackDirty_hits::total 4835234 # number of WritebackDirty hits
> system.cpu.l2cache.WritebackClean_hits::writebacks 12147319 # number of WritebackClean hits
> system.cpu.l2cache.WritebackClean_hits::total 12147319 # number of WritebackClean hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1756866 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1756866 # number of ReadExReq hits
> system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 49 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadCleanReq_hits::total 49 # number of ReadCleanReq hits
> system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11510992 # number of ReadSharedReq hits
> system.cpu.l2cache.ReadSharedReq_hits::total 11510992 # number of ReadSharedReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 49 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 13267858 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 13267907 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 49 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 13267858 # number of overall hits
> system.cpu.l2cache.overall_hits::total 13267907 # number of overall hits
> system.cpu.l2cache.UpgradeReq_misses::cpu.data 9 # number of UpgradeReq misses
> system.cpu.l2cache.UpgradeReq_misses::total 9 # number of UpgradeReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 980689 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 980689 # number of ReadExReq misses
> system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1027 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadCleanReq_misses::total 1027 # number of ReadCleanReq misses
> system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2755115 # number of ReadSharedReq misses
> system.cpu.l2cache.ReadSharedReq_misses::total 2755115 # number of ReadSharedReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 1027 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 3735804 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 3736831 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 1027 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 3735804 # number of overall misses
> system.cpu.l2cache.overall_misses::total 3736831 # number of overall misses
> system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 191500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.UpgradeReq_miss_latency::total 191500 # number of UpgradeReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100034737999 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 100034737999 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 74500500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 74500500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 237611587999 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 237611587999 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 74500500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 337646325998 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 337720826498 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 74500500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 337646325998 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 337720826498 # number of overall miss cycles
> system.cpu.l2cache.WritebackDirty_accesses::writebacks 4835234 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackDirty_accesses::total 4835234 # number of WritebackDirty accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::writebacks 12147319 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.WritebackClean_accesses::total 12147319 # number of WritebackClean accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::cpu.data 9 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.UpgradeReq_accesses::total 9 # number of UpgradeReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737555 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 2737555 # number of ReadExReq accesses(hits+misses)
1055,1056c1060,1061
< system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266589 # number of ReadSharedReq accesses(hits+misses)
< system.cpu.l2cache.ReadSharedReq_accesses::total 14266589 # number of ReadSharedReq accesses(hits+misses)
---
> system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14266107 # number of ReadSharedReq accesses(hits+misses)
> system.cpu.l2cache.ReadSharedReq_accesses::total 14266107 # number of ReadSharedReq accesses(hits+misses)
1058,1059c1063,1064
< system.cpu.l2cache.demand_accesses::cpu.data 17004222 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 17005298 # number of demand (read+write) accesses
---
> system.cpu.l2cache.demand_accesses::cpu.data 17003662 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 17004738 # number of demand (read+write) accesses
1061,1062c1066,1067
< system.cpu.l2cache.overall_accesses::cpu.data 17004222 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 17005298 # number of overall (read+write) accesses
---
> system.cpu.l2cache.overall_accesses::cpu.data 17003662 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 17004738 # number of overall (read+write) accesses
1065,1091c1070,1096
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358173 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.358173 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.947955 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.947955 # miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.192353 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.192353 # miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.947955 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.219050 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.219096 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947955 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.219050 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.219096 # miss rate for overall accesses
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 20166.666667 # average UpgradeReq miss latency
< system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 20166.666667 # average UpgradeReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101049.021158 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101049.021158 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 70854.901961 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 70854.901961 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85299.115742 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85299.115742 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 89440.192383 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70854.901961 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89445.281827 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 89440.192383 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked
---
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.358235 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.358235 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954461 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954461 # miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.193123 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.193123 # miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954461 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.219706 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.219752 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954461 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.219706 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.219752 # miss rate for overall accesses
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 21277.777778 # average UpgradeReq miss latency
> system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 21277.777778 # average UpgradeReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 102004.547822 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 102004.547822 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 72541.869523 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 72541.869523 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86243.800349 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86243.800349 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72541.869523 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 90381.167213 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 90376.264406 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72541.869523 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 90381.167213 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 90376.264406 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked
1093c1098
< system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
---
> system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
1095c1100
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs 53 # average number of cycles each access was blocked
---
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs 70.200000 # average number of cycles each access was blocked
1097,1145c1102,1146
< system.cpu.l2cache.unused_prefetches 56900 # number of HardPF blocks evicted w/o reference
< system.cpu.l2cache.writebacks::writebacks 1635896 # number of writebacks
< system.cpu.l2cache.writebacks::total 1635896 # number of writebacks
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3915 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 3915 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45253 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45253 # number of ReadSharedReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 49168 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 49169 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 49168 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 49169 # number of overall MSHR hits
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 1145204 # number of HardPFReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 6 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.UpgradeReq_mshr_misses::total 6 # number of UpgradeReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976631 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 976631 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1019 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1019 # number of ReadCleanReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2698969 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2698969 # number of ReadSharedReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 1019 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 3675600 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 3676619 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 1019 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 3675600 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1145204 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 4821823 # number of overall MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72434619378 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 85000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 85000 # number of UpgradeReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 92854351000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 92854351000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 66085000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 66085000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 215091513500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 215091513500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66085000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 307945864500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 308011949500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66085000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 307945864500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72434619378 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 380446568878 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.unused_prefetches 58014 # number of HardPF blocks evicted w/o reference
> system.cpu.l2cache.writebacks::writebacks 1634499 # number of writebacks
> system.cpu.l2cache.writebacks::total 1634499 # number of writebacks
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3902 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 3902 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 45668 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.ReadSharedReq_mshr_hits::total 45668 # number of ReadSharedReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 49570 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 49570 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 49570 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 49570 # number of overall MSHR hits
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 1198249 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 1198249 # number of HardPFReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 9 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.UpgradeReq_mshr_misses::total 9 # number of UpgradeReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 976787 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 976787 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1027 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1027 # number of ReadCleanReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2709447 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2709447 # number of ReadSharedReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 1027 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 3686234 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 3687261 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 1027 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 3686234 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 1198249 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 4885510 # number of overall MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 73218164638 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 73218164638 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 137500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 137500 # number of UpgradeReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93806338999 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93806338999 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 68350500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 68350500 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 218529981999 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 218529981999 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 68350500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 312336320998 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 312404671498 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 68350500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 312336320998 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 73218164638 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 385622836136 # number of overall MSHR miss cycles
1150,1160c1151,1161
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356743 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356743 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.947026 # mshr miss rate for ReadCleanReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189181 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189181 # mshr miss rate for ReadSharedReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.216204 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947026 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216158 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.356810 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.356810 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954461 # mshr miss rate for ReadCleanReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.189922 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189922 # mshr miss rate for ReadSharedReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.216837 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954461 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.216791 # mshr miss rate for overall accesses
1162,1196c1163,1197
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.283548 # mshr miss rate for overall accesses
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 63250.407244 # average HardPFReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 14166.666667 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14166.666667 # average UpgradeReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95076.186400 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95076.186400 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 64852.796860 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 64852.796860 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79693.954803 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79693.954803 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83775.868400 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64852.796860 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83781.114512 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 63250.407244 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78900.981823 # average overall mshr miss latency
< system.cpu.toL2Bus.snoop_filter.tot_requests 34009604 # Total number of requests made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_requests 17004315 # Number of requests hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.snoop_filter.tot_snoops 2918086 # Total number of snoops made to the snoop filter.
< system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2899299 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
< system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 18787 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.cpu.toL2Bus.trans_dist::ReadResp 14267664 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackDirty 6469008 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::WritebackClean 12171187 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::CleanEvict 5770180 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 1436414 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFResp 9 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeReq 6 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::UpgradeResp 6 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2737633 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2737633 # Transaction distribution
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.287303 # mshr miss rate for overall accesses
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 61104.298554 # average HardPFReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 15277.777778 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15277.777778 # average UpgradeReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 96035.613700 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 96035.613700 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66553.554041 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66553.554041 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 80654.828088 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 80654.828088 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 84725.402270 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66553.554041 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 84730.465021 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 61104.298554 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78931.951042 # average overall mshr miss latency
> system.cpu.toL2Bus.snoop_filter.tot_requests 34008488 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 17003756 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 21185 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 201663 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 201662 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 1 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.cpu.toL2Bus.trans_dist::ReadResp 14267181 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackDirty 6469733 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::WritebackClean 12168504 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::CleanEvict 3012569 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 1490485 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFResp 11 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeReq 9 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::UpgradeResp 9 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 2737555 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 2737555 # Transaction distribution
1198,1209c1199,1210
< system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266589 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2740 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51012175 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 51014915 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106496 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176508224 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 2176614720 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 8842499 # Total snoops (count)
< system.cpu.toL2Bus.snoopTraffic 104697920 # Total snoop traffic (bytes)
< system.cpu.toL2Bus.snoop_fanout::samples 25847794 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 0.114446 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.320627 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadSharedReq 14266107 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2738 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 51010503 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 51013241 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 106368 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2176436672 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 2176543040 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 6137564 # Total snoops (count)
> system.cpu.toL2Bus.snoopTraffic 104608640 # Total snoop traffic (bytes)
> system.cpu.toL2Bus.snoop_fanout::samples 23142303 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.009630 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.097659 # Request fanout histogram
1211,1213c1212,1214
< system.cpu.toL2Bus.snoop_fanout::0 22908415 88.63% 88.63% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 2920592 11.30% 99.93% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 18787 0.07% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 22919446 99.04% 99.04% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 222856 0.96% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 1 0.00% 100.00% # Request fanout histogram
1217,1218c1218,1219
< system.cpu.toL2Bus.snoop_fanout::total 25847794 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 34009101529 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 23142303 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 34007983525 # Layer occupancy (ticks)
1220c1221
< system.cpu.toL2Bus.snoopLayer0.occupancy 13538 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoopLayer0.occupancy 16538 # Layer occupancy (ticks)
1222c1223
< system.cpu.toL2Bus.respLayer0.occupancy 1613498 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1611000 # Layer occupancy (ticks)
1224c1225
< system.cpu.toL2Bus.respLayer1.occupancy 25506339992 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 25505500994 # Layer occupancy (ticks)
1226,1237c1227,1244
< system.membus.pwrStateResidencyTicks::UNDEFINED 767803843500 # Cumulative time (in ticks) in various power states
< system.membus.trans_dist::ReadResp 3696594 # Transaction distribution
< system.membus.trans_dist::WritebackDirty 1635896 # Transaction distribution
< system.membus.trans_dist::CleanEvict 3001813 # Transaction distribution
< system.membus.trans_dist::UpgradeReq 6 # Transaction distribution
< system.membus.trans_dist::ReadExReq 976790 # Transaction distribution
< system.membus.trans_dist::ReadExResp 976790 # Transaction distribution
< system.membus.trans_dist::ReadSharedReq 3696595 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 13984484 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 13984484 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 403793920 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 403793920 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.snoop_filter.tot_requests 9332231 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 4668264 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 770752376500 # Cumulative time (in ticks) in various power states
> system.membus.trans_dist::ReadResp 3708204 # Transaction distribution
> system.membus.trans_dist::WritebackDirty 1634499 # Transaction distribution
> system.membus.trans_dist::CleanEvict 3012569 # Transaction distribution
> system.membus.trans_dist::UpgradeReq 9 # Transaction distribution
> system.membus.trans_dist::ReadExReq 976948 # Transaction distribution
> system.membus.trans_dist::ReadExResp 976948 # Transaction distribution
> system.membus.trans_dist::ReadSharedReq 3708206 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14017383 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 14017383 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 404457664 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 404457664 # Cumulative packet size per connected master and slave (bytes)
1240c1247
< system.membus.snoop_fanout::samples 9311100 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 4685163 # Request fanout histogram
1244c1251
< system.membus.snoop_fanout::0 9311100 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 4685163 100.00% 100.00% # Request fanout histogram
1249,1250c1256,1257
< system.membus.snoop_fanout::total 9311100 # Request fanout histogram
< system.membus.reqLayer0.occupancy 17657610874 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 4685163 # Request fanout histogram
> system.membus.reqLayer0.occupancy 17662405597 # Layer occupancy (ticks)
1252c1259
< system.membus.respLayer1.occupancy 25413256779 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 25476549560 # Layer occupancy (ticks)