3,5c3,5
< sim_seconds 0.756343 # Number of seconds simulated
< sim_ticks 756342731500 # Number of ticks simulated
< final_tick 756342731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.771783 # Number of seconds simulated
> sim_ticks 771782683000 # Number of ticks simulated
> final_tick 771782683000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 137786 # Simulator instruction rate (inst/s)
< host_op_rate 148444 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 67471289 # Simulator tick rate (ticks/s)
< host_mem_usage 311496 # Number of bytes of host memory used
< host_seconds 11209.85 # Real time elapsed on the host
---
> host_inst_rate 141348 # Simulator instruction rate (inst/s)
> host_op_rate 152281 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 70628369 # Simulator tick rate (ticks/s)
> host_mem_usage 310548 # Number of bytes of host memory used
> host_seconds 10927.38 # Real time elapsed on the host
16,53c16,53
< system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 238887296 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.l2cache.prefetcher 63148480 # Number of bytes read from this memory
< system.physmem.bytes_read::total 302102080 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 104863424 # Number of bytes written to this memory
< system.physmem.bytes_written::total 104863424 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 3732614 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.l2cache.prefetcher 986695 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 4720345 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1638491 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1638491 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 87664 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 315845299 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.l2cache.prefetcher 83491885 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 399424847 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 87664 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 87664 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 138645378 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 138645378 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 138645378 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 87664 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 315845299 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.l2cache.prefetcher 83491885 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 538070225 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 4720345 # Number of read requests accepted
< system.physmem.writeReqs 1638491 # Number of write requests accepted
< system.physmem.readBursts 4720345 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1638491 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 301644480 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 457600 # Total number of bytes read from write queue
< system.physmem.bytesWritten 104860480 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 302102080 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 104863424 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 7150 # Number of DRAM read bursts serviced by the write queue
< system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one
---
> system.physmem.bytes_read::cpu.inst 66112 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 238756480 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.l2cache.prefetcher 63336128 # Number of bytes read from this memory
> system.physmem.bytes_read::total 302158720 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 66112 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 66112 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 104900608 # Number of bytes written to this memory
> system.physmem.bytes_written::total 104900608 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 1033 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 3730570 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.l2cache.prefetcher 989627 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 4721230 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1639072 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1639072 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 85661 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 309357135 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.l2cache.prefetcher 82064718 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 391507515 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 85661 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 85661 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 135919878 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 135919878 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 135919878 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 85661 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 309357135 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.l2cache.prefetcher 82064718 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 527427392 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 4721230 # Number of read requests accepted
> system.physmem.writeReqs 1639072 # Number of write requests accepted
> system.physmem.readBursts 4721230 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1639072 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 301708544 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 450176 # Total number of bytes read from write queue
> system.physmem.bytesWritten 104898432 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 302158720 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 104900608 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 7034 # Number of DRAM read bursts serviced by the write queue
> system.physmem.mergedWrBursts 11 # Number of DRAM write bursts merged with an existing one
55,86c55,86
< system.physmem.perBankRdBursts::0 296862 # Per bank write bursts
< system.physmem.perBankRdBursts::1 294626 # Per bank write bursts
< system.physmem.perBankRdBursts::2 288270 # Per bank write bursts
< system.physmem.perBankRdBursts::3 292812 # Per bank write bursts
< system.physmem.perBankRdBursts::4 290199 # Per bank write bursts
< system.physmem.perBankRdBursts::5 289793 # Per bank write bursts
< system.physmem.perBankRdBursts::6 284872 # Per bank write bursts
< system.physmem.perBankRdBursts::7 281493 # Per bank write bursts
< system.physmem.perBankRdBursts::8 297311 # Per bank write bursts
< system.physmem.perBankRdBursts::9 303290 # Per bank write bursts
< system.physmem.perBankRdBursts::10 295469 # Per bank write bursts
< system.physmem.perBankRdBursts::11 301855 # Per bank write bursts
< system.physmem.perBankRdBursts::12 303298 # Per bank write bursts
< system.physmem.perBankRdBursts::13 302373 # Per bank write bursts
< system.physmem.perBankRdBursts::14 297652 # Per bank write bursts
< system.physmem.perBankRdBursts::15 293020 # Per bank write bursts
< system.physmem.perBankWrBursts::0 104131 # Per bank write bursts
< system.physmem.perBankWrBursts::1 101826 # Per bank write bursts
< system.physmem.perBankWrBursts::2 99098 # Per bank write bursts
< system.physmem.perBankWrBursts::3 99979 # Per bank write bursts
< system.physmem.perBankWrBursts::4 99438 # Per bank write bursts
< system.physmem.perBankWrBursts::5 99115 # Per bank write bursts
< system.physmem.perBankWrBursts::6 102674 # Per bank write bursts
< system.physmem.perBankWrBursts::7 104427 # Per bank write bursts
< system.physmem.perBankWrBursts::8 105209 # Per bank write bursts
< system.physmem.perBankWrBursts::9 104570 # Per bank write bursts
< system.physmem.perBankWrBursts::10 102342 # Per bank write bursts
< system.physmem.perBankWrBursts::11 102683 # Per bank write bursts
< system.physmem.perBankWrBursts::12 102787 # Per bank write bursts
< system.physmem.perBankWrBursts::13 102808 # Per bank write bursts
< system.physmem.perBankWrBursts::14 104630 # Per bank write bursts
< system.physmem.perBankWrBursts::15 102728 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 296496 # Per bank write bursts
> system.physmem.perBankRdBursts::1 294922 # Per bank write bursts
> system.physmem.perBankRdBursts::2 288553 # Per bank write bursts
> system.physmem.perBankRdBursts::3 293200 # Per bank write bursts
> system.physmem.perBankRdBursts::4 290519 # Per bank write bursts
> system.physmem.perBankRdBursts::5 289057 # Per bank write bursts
> system.physmem.perBankRdBursts::6 284695 # Per bank write bursts
> system.physmem.perBankRdBursts::7 280747 # Per bank write bursts
> system.physmem.perBankRdBursts::8 297891 # Per bank write bursts
> system.physmem.perBankRdBursts::9 303659 # Per bank write bursts
> system.physmem.perBankRdBursts::10 295750 # Per bank write bursts
> system.physmem.perBankRdBursts::11 302488 # Per bank write bursts
> system.physmem.perBankRdBursts::12 303486 # Per bank write bursts
> system.physmem.perBankRdBursts::13 302338 # Per bank write bursts
> system.physmem.perBankRdBursts::14 297681 # Per bank write bursts
> system.physmem.perBankRdBursts::15 292714 # Per bank write bursts
> system.physmem.perBankWrBursts::0 104090 # Per bank write bursts
> system.physmem.perBankWrBursts::1 102136 # Per bank write bursts
> system.physmem.perBankWrBursts::2 99204 # Per bank write bursts
> system.physmem.perBankWrBursts::3 100079 # Per bank write bursts
> system.physmem.perBankWrBursts::4 99319 # Per bank write bursts
> system.physmem.perBankWrBursts::5 99058 # Per bank write bursts
> system.physmem.perBankWrBursts::6 102867 # Per bank write bursts
> system.physmem.perBankWrBursts::7 104266 # Per bank write bursts
> system.physmem.perBankWrBursts::8 105488 # Per bank write bursts
> system.physmem.perBankWrBursts::9 104503 # Per bank write bursts
> system.physmem.perBankWrBursts::10 102301 # Per bank write bursts
> system.physmem.perBankWrBursts::11 102956 # Per bank write bursts
> system.physmem.perBankWrBursts::12 103260 # Per bank write bursts
> system.physmem.perBankWrBursts::13 102520 # Per bank write bursts
> system.physmem.perBankWrBursts::14 104484 # Per bank write bursts
> system.physmem.perBankWrBursts::15 102507 # Per bank write bursts
89c89
< system.physmem.totGap 756342591500 # Total gap between requests
---
> system.physmem.totGap 771782536000 # Total gap between requests
96c96
< system.physmem.readPktSize::6 4720345 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 4721230 # Read request sizes (log2)
103,119c103,119
< system.physmem.writePktSize::6 1638491 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 2764600 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 1036830 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 329452 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 239558 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 162691 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::5 91104 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::6 40419 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::7 23320 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::8 17706 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::9 4471 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::10 1653 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::11 733 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::12 418 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::13 229 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1639072 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 2775597 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 1044443 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 331745 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 234202 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 153941 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::5 85295 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::6 39428 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::7 23872 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::8 18360 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::9 4183 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::10 1645 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::11 788 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::12 434 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::13 248 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::14 11 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see
151,182c151,182
< system.physmem.wrQLenPdf::15 22698 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 24488 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 59650 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 74848 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 84172 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 91913 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 98459 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 103044 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 106253 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 107840 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 108834 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 109988 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 110978 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 113431 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 107071 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 104798 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 103128 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 101631 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 3003 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 1224 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 572 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::39 18 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 22873 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 24573 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 60114 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 75847 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 85447 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 93235 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 99435 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 103341 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 105611 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 106420 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 106485 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 107133 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 108359 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 110847 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 113228 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 106323 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 103422 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 101669 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 2755 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 1061 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 485 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 198 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 99 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 50 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::39 22 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::40 10 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
200,230c200,231
< system.physmem.bytesPerActivate::samples 4285614 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 94.853108 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 78.948636 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 101.693693 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 3410667 79.58% 79.58% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 676414 15.78% 95.37% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 97051 2.26% 97.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 35005 0.82% 98.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 22710 0.53% 98.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 12276 0.29% 99.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 7200 0.17% 99.43% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5155 0.12% 99.55% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 19136 0.45% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 4285614 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 98802 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 47.703225 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 32.303831 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 97.301104 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-127 94981 96.13% 96.13% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::128-255 1362 1.38% 97.51% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::256-383 759 0.77% 98.28% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::384-511 434 0.44% 98.72% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::512-639 380 0.38% 99.10% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::640-767 348 0.35% 99.46% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::768-895 273 0.28% 99.73% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::896-1023 148 0.15% 99.88% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-1151 67 0.07% 99.95% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1152-1279 20 0.02% 99.97% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1280-1407 9 0.01% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1408-1535 8 0.01% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1536-1663 4 0.00% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 4289012 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 94.801701 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 78.923105 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 101.558340 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 3414847 79.62% 79.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 675748 15.76% 95.37% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 96615 2.25% 97.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 35482 0.83% 98.45% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 22807 0.53% 98.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 12154 0.28% 99.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 7173 0.17% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5164 0.12% 99.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 19022 0.44% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 4289012 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 98837 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 47.696531 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 32.309771 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 98.301255 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-127 95044 96.16% 96.16% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::128-255 1344 1.36% 97.52% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::384-511 419 0.42% 98.73% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::512-639 374 0.38% 99.10% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::640-767 356 0.36% 99.46% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::768-895 254 0.26% 99.72% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::896-1023 146 0.15% 99.87% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-1151 62 0.06% 99.93% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1152-1279 41 0.04% 99.97% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1280-1407 8 0.01% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1408-1535 7 0.01% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1536-1663 2 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes
232,261c233,259
< system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2560-2687 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2816-2943 2 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::total 98802 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 98802 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 16.583116 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 16.550078 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.089696 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 73349 74.24% 74.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 1793 1.81% 76.05% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 18295 18.52% 94.57% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 3696 3.74% 98.31% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 920 0.93% 99.24% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 398 0.40% 99.64% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 161 0.16% 99.81% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 94 0.10% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::24 50 0.05% 99.95% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::25 24 0.02% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::26 14 0.01% 99.99% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::27 5 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 98802 # Writes before turning the bus around for reads
< system.physmem.totQLat 132475907765 # Total ticks spent queuing
< system.physmem.totMemAccLat 220848314015 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 23565975000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 28107.45 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::2304-2431 1 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2560-2687 3 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2944-3071 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::3200-3327 2 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::3584-3711 1 0.00% 100.00% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::total 98837 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 98837 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 16.583243 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 16.550199 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.089458 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 73410 74.27% 74.27% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 1674 1.69% 75.97% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 18461 18.68% 94.65% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 3603 3.65% 98.29% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 928 0.94% 99.23% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 388 0.39% 99.62% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 174 0.18% 99.80% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 100 0.10% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 61 0.06% 99.96% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::25 27 0.03% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 7 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::27 4 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 98837 # Writes before turning the bus around for reads
> system.physmem.totQLat 132409571838 # Total ticks spent queuing
> system.physmem.totMemAccLat 220800746838 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 23570980000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 28087.41 # Average queueing delay per DRAM burst
263,267c261,265
< system.physmem.avgMemAccLat 46857.45 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 398.82 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 138.64 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 399.42 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 138.65 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 46837.41 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 390.92 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 135.92 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 391.51 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 135.92 # Average system write bandwidth in MiByte/s
269,290c267,288
< system.physmem.busUtil 4.20 # Data bus utilization in percentage
< system.physmem.busUtilRead 3.12 # Data bus utilization in percentage for reads
< system.physmem.busUtilWrite 1.08 # Data bus utilization in percentage for writes
< system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing
< system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing
< system.physmem.readRowHits 1712938 # Number of row buffer hits during reads
< system.physmem.writeRowHits 353078 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 36.34 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 21.55 # Row buffer hit rate for writes
< system.physmem.avgGap 118943.56 # Average gap between requests
< system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 16066436400 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 8766408750 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 18087404400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 5253193440 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 400853320515 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 102178887750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 600606152535 # Total energy per rank (pJ)
< system.physmem_0.averagePower 794.094387 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 167492103071 # Time in different power states
< system.physmem_0.memoryStateTime::REF 25255880000 # Time in different power states
---
> system.physmem.busUtil 4.12 # Data bus utilization in percentage
> system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads
> system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes
> system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
> system.physmem.avgWrQLen 24.98 # Average write queue length when enqueuing
> system.physmem.readRowHits 1710867 # Number of row buffer hits during reads
> system.physmem.writeRowHits 353347 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 36.29 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 21.56 # Row buffer hit rate for writes
> system.physmem.avgGap 121343.69 # Average gap between requests
> system.physmem.pageHitRate 32.49 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 16078381200 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 8772926250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 18081671400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 5255351280 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 410988240855 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 102552687000 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 612138233745 # Total energy per rank (pJ)
> system.physmem_0.averagePower 793.150023 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 168058001250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 25771460000 # Time in different power states
292c290
< system.physmem_0.memoryStateTime::ACT 563593117929 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 577951698750 # Time in different power states
294,304c292,302
< system.physmem_1.actEnergy 16332729840 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 8911707750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 18675259200 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 5363826480 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 402415744095 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 100808340750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 601908109395 # Total energy per rank (pJ)
< system.physmem_1.averagePower 795.815775 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 165215512876 # Time in different power states
< system.physmem_1.memoryStateTime::REF 25255880000 # Time in different power states
---
> system.physmem_1.actEnergy 16346489040 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 8919215250 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 18688846800 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 5365504800 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 50408975760 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 412404849315 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 101310048000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 613443928965 # Total energy per rank (pJ)
> system.physmem_1.averagePower 794.841817 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 165993972457 # Time in different power states
> system.physmem_1.memoryStateTime::REF 25771460000 # Time in different power states
306c304
< system.physmem_1.memoryStateTime::ACT 565869633374 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 580015821043 # Time in different power states
308,312c306,310
< system.cpu.branchPred.lookups 286251205 # Number of BP lookups
< system.cpu.branchPred.condPredicted 223383370 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 14630986 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 158738952 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 150334108 # Number of BTB hits
---
> system.cpu.branchPred.lookups 286268512 # Number of BP lookups
> system.cpu.branchPred.condPredicted 223399208 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 14631885 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 157652290 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 150341382 # Number of BTB hits
314,316c312,314
< system.cpu.branchPred.BTBHitPct 94.705242 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 16640646 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 95.362638 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 16641174 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions.
435c433
< system.cpu.numCycles 1512685464 # number of cpu cycles simulated
---
> system.cpu.numCycles 1543565367 # number of cpu cycles simulated
438,450c436,448
< system.cpu.fetch.icacheStallCycles 13925295 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 2067334861 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 286251205 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 166974754 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 1484044715 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 29286501 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
< system.cpu.fetch.IcacheWaitRetryStallCycles 1090 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 656878260 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 961 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 1512614520 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 1.464203 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.224459 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 13925779 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 2067423618 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 286268512 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 166982556 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 1514915602 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 29288421 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 253 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
> system.cpu.fetch.IcacheWaitRetryStallCycles 919 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 656914213 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 942 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 1543486763 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 1.434983 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.229356 # Number of instructions fetched each cycle (Total)
452,455c450,453
< system.cpu.fetch.rateDist::0 430302331 28.45% 28.45% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 465370544 30.77% 59.21% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 101420857 6.71% 65.92% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 515520788 34.08% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 461116597 29.87% 29.87% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 465422138 30.15% 60.03% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 101389056 6.57% 66.60% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 515558972 33.40% 100.00% # Number of instructions fetched each cycle (Total)
459,486c457,484
< system.cpu.fetch.rateDist::total 1512614520 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.189234 # Number of branch fetches per cycle
< system.cpu.fetch.rate 1.366665 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 74740374 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 515177494 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 849893259 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 58160845 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 14642548 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 42195150 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 2036986769 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 52385989 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 14642548 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 139815435 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 436624028 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 12701 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 837804287 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 83715521 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 1976173031 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 26689335 # Number of squashed instructions processed by rename
< system.cpu.rename.ROBFullEvents 45146280 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 125414 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LQFullEvents 1394915 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 22818803 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 1985649062 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 9127137269 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 2432583454 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 143 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 1543486763 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.185459 # Number of branch fetches per cycle
> system.cpu.fetch.rate 1.339382 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 74615169 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 546131714 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 850052649 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 58043724 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 14643507 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 42202613 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 760 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 2037139109 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 52472329 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 14643507 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 139680975 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 464946049 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 14177 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 837873228 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 86328827 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 1976320354 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 26732336 # Number of squashed instructions processed by rename
> system.cpu.rename.ROBFullEvents 45128593 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 125639 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LQFullEvents 1500891 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 25518898 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 1985788047 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 9127865226 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 2432787425 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 124 # Number of floating rename lookups
488,505c486,503
< system.cpu.rename.UndoneMaps 310750117 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 155 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 111721700 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 542489680 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 199288909 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 26826914 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 28715919 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 1947778041 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 1857580897 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 13541153 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 279193675 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 645796508 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 1512614520 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 1.228060 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.150014 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 310889102 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 151 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 141 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 111344488 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 542536301 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 199301557 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 26908887 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 29198248 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 1947883742 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 210 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 1857409514 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 13500100 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 279518916 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 646881302 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 40 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 1543486763 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 1.203385 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.151093 # Number of insts issued each cycle
507,512c505,510
< system.cpu.iq.issued_per_cycle::0 560160519 37.03% 37.03% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 325201183 21.50% 58.53% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 378431439 25.02% 83.55% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 219774852 14.53% 98.08% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 29040355 1.92% 100.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 6172 0.00% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 590762659 38.27% 38.27% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 325764931 21.11% 59.38% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 378272466 24.51% 83.89% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 219653351 14.23% 98.12% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 29027182 1.88% 100.00% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 6174 0.00% 100.00% # Number of insts issued each cycle
519c517
< system.cpu.iq.issued_per_cycle::total 1512614520 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 1543486763 # Number of insts issued each cycle
521,551c519,549
< system.cpu.iq.fu_full::IntAlu 166509117 41.02% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 1974 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 191277328 47.12% 88.14% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 48123931 11.86% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 166053840 40.99% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 1992 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 191416352 47.25% 88.24% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 47630536 11.76% 100.00% # attempts to use FU when none available
555,585c553,583
< system.cpu.iq.FU_type_0::IntAlu 1138363415 61.28% 61.28% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 801029 0.04% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 532094788 28.64% 89.97% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 186321614 10.03% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 1138248479 61.28% 61.28% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 801009 0.04% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 26 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 532044411 28.64% 89.97% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 186315567 10.03% 100.00% # Type of FU issued
588,600c586,598
< system.cpu.iq.FU_type_0::total 1857580897 # Type of FU issued
< system.cpu.iq.rate 1.228002 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 405912350 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.218517 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 5647229580 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 2226984572 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1805831958 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 2263493115 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 17832338 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 1857409514 # Type of FU issued
> system.cpu.iq.rate 1.203324 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 405102720 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.218101 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 5676908390 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 2227415601 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1805707256 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 221 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 208 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 66 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 2262512110 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 124 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 17814082 # Number of loads that had data forwarded from stores
602,605c600,603
< system.cpu.iew.lsq.thread0.squashedLoads 84183346 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 66238 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 13114 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 24441864 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 84229967 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 66402 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 24454512 # Number of stores squashed
608,609c606,607
< system.cpu.iew.lsq.thread0.rescheduledLoads 4579390 # Number of loads that were rescheduled
< system.cpu.iew.lsq.thread0.cacheBlocked 4849629 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.rescheduledLoads 4520775 # Number of loads that were rescheduled
> system.cpu.iew.lsq.thread0.cacheBlocked 4802645 # Number of times an access to memory failed due to the cache being blocked
611,614c609,612
< system.cpu.iew.iewSquashCycles 14642548 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 25281228 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1183865 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 1947778336 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewSquashCycles 14643507 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 25316113 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1330365 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 1947884031 # Number of instructions dispatched to IQ
616,627c614,625
< system.cpu.iew.iewDispLoadInsts 542489680 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 199288909 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 158613 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 1024253 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 13114 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 7709445 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 8723908 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 16433353 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1827918594 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 516926976 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 29662303 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewDispLoadInsts 542536301 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 199301557 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 148 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 158933 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 1170467 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 7700956 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 8705023 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 16405979 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1827745758 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 516865735 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 29663756 # Number of squashed instructions skipped in execute
629,637c627,635
< system.cpu.iew.exec_nop 81 # number of nop insts executed
< system.cpu.iew.exec_refs 698686621 # number of memory reference insts executed
< system.cpu.iew.exec_branches 229598858 # Number of branches executed
< system.cpu.iew.exec_stores 181759645 # Number of stores executed
< system.cpu.iew.exec_rate 1.208393 # Inst execution rate
< system.cpu.iew.wb_sent 1808851456 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1805832027 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 1169265268 # num instructions producing a value
< system.cpu.iew.wb_consumers 1689455879 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 79 # number of nop insts executed
> system.cpu.iew.exec_refs 698617938 # number of memory reference insts executed
> system.cpu.iew.exec_branches 229554698 # Number of branches executed
> system.cpu.iew.exec_stores 181752203 # Number of stores executed
> system.cpu.iew.exec_rate 1.184106 # Inst execution rate
> system.cpu.iew.wb_sent 1808737138 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1805707322 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 1169287953 # num instructions producing a value
> system.cpu.iew.wb_consumers 1689671414 # num instructions consuming a value
639,640c637,638
< system.cpu.iew.wb_rate 1.193792 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.169829 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.692021 # average fanout of values written-back
642c640
< system.cpu.commit.commitSquashedInsts 257820227 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 257958644 # The number of squashed insts skipped by commit
644,647c642,645
< system.cpu.commit.branchMispredicts 14630284 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 1473146552 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.129577 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.040655 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 14631182 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 1504006174 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.106400 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.024308 # Number of insts commited each cycle
649,657c647,655
< system.cpu.commit.committed_per_cycle::0 893288218 60.64% 60.64% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 250810214 17.03% 77.66% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 109558722 7.44% 85.10% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 55058301 3.74% 88.84% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 29206870 1.98% 90.82% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 33934631 2.30% 93.12% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 24884814 1.69% 94.81% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 18117903 1.23% 96.04% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 58286879 3.96% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 923727407 61.42% 61.42% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 250637926 16.66% 78.08% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 110048306 7.32% 85.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 55269063 3.67% 89.07% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 29308073 1.95% 91.02% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 34102690 2.27% 93.29% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 24713726 1.64% 94.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 18129256 1.21% 96.14% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 58069727 3.86% 100.00% # Number of insts commited each cycle
661c659
< system.cpu.commit.committed_per_cycle::total 1473146552 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 1504006174 # Number of insts commited each cycle
707c705
< system.cpu.commit.bw_lim_events 58286879 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 58069727 # number cycles where commit BW limit reached
709,712c707,710
< system.cpu.rob.rob_reads 3336711734 # The number of ROB reads
< system.cpu.rob.rob_writes 3883178493 # The number of ROB writes
< system.cpu.timesIdled 871 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 70944 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 3367926925 # The number of ROB reads
> system.cpu.rob.rob_writes 3883468057 # The number of ROB writes
> system.cpu.timesIdled 846 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 78604 # Total number of cycles that the CPU has spent unscheduled due to idling
715,720c713,718
< system.cpu.cpi 0.979361 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.979361 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.021073 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.021073 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 2175874054 # number of integer regfile reads
< system.cpu.int_regfile_writes 1261590215 # number of integer regfile writes
---
> system.cpu.cpi 0.999354 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.999354 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.000646 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.000646 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 2175695472 # number of integer regfile reads
> system.cpu.int_regfile_writes 1261559121 # number of integer regfile writes
722,725c720,723
< system.cpu.fp_regfile_writes 51 # number of floating regfile writes
< system.cpu.cc_regfile_reads 6966029517 # number of cc regfile reads
< system.cpu.cc_regfile_writes 551971474 # number of cc regfile writes
< system.cpu.misc_regfile_reads 675853074 # number of misc regfile reads
---
> system.cpu.fp_regfile_writes 48 # number of floating regfile writes
> system.cpu.cc_regfile_reads 6965502930 # number of cc regfile reads
> system.cpu.cc_regfile_writes 551873305 # number of cc regfile writes
> system.cpu.misc_regfile_reads 675842878 # number of misc regfile reads
727,735c725,733
< system.cpu.dcache.tags.replacements 17007297 # number of replacements
< system.cpu.dcache.tags.tagsinuse 511.963762 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 638259274 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 17007809 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 37.527425 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 79888000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 511.963762 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.replacements 17005493 # number of replacements
> system.cpu.dcache.tags.tagsinuse 511.964646 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 638183172 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 17006005 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 37.526931 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 79063000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 511.964646 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.999931 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.999931 # Average percentage of cache occupancy
737,738c735,736
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 392 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id
740,745c738,743
< system.cpu.dcache.tags.tag_accesses 1335624835 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1335624835 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 469463783 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 469463783 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 168795373 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 168795373 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 1335677307 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1335677307 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 469397613 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 469397613 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 168785441 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 168785441 # number of WriteReq hits
750,757c748,755
< system.cpu.dcache.demand_hits::cpu.data 638259156 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 638259156 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 638259156 # number of overall hits
< system.cpu.dcache.overall_hits::total 638259156 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 17258559 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 17258559 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 3790674 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 3790674 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 638183054 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 638183054 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 638183054 # number of overall hits
> system.cpu.dcache.overall_hits::total 638183054 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 17351867 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 17351867 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 3800606 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 3800606 # number of WriteReq misses
762,777c760,775
< system.cpu.dcache.demand_misses::cpu.data 21049233 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 21049233 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 21049235 # number of overall misses
< system.cpu.dcache.overall_misses::total 21049235 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 392276819281 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 392276819281 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 143202458834 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 143202458834 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 535479278115 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 535479278115 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 535479278115 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 535479278115 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 486722342 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 486722342 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 21152473 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 21152473 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 21152475 # number of overall misses
> system.cpu.dcache.overall_misses::total 21152475 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 417182903209 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 417182903209 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 149917932873 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 149917932873 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 358750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 358750 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 567100836082 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 567100836082 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 567100836082 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 567100836082 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 486749480 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 486749480 # number of ReadReq accesses(hits+misses)
786,793c784,791
< system.cpu.dcache.demand_accesses::cpu.data 659308389 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 659308389 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 659308391 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 659308391 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035459 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.035459 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021964 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.021964 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 659335527 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 659335527 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 659335529 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 659335529 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035648 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.035648 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022022 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.022022 # miss rate for WriteReq accesses
798,817c796,815
< system.cpu.dcache.demand_miss_rate::cpu.data 0.031926 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.031926 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.031926 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.031926 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22729.407437 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 22729.407437 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37777.571702 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 37777.571702 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 25439.372452 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 25439.372452 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 25439.370035 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 25439.370035 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 19976216 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 2938205 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 1014245 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 66761 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.695651 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 44.010800 # average number of cycles each access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.032082 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.032082 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.032082 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.032082 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24042.536933 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 24042.536933 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39445.797032 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 39445.797032 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 89687.500000 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 89687.500000 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 26810.143480 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 26810.143480 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 26810.140945 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 26810.140945 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 20723795 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 3315809 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 944207 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 67033 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.948360 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 49.465323 # average number of cycles each access was blocked
820,825c818,823
< system.cpu.dcache.writebacks::writebacks 4837992 # number of writebacks
< system.cpu.dcache.writebacks::total 4837992 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2988204 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 2988204 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1053221 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 1053221 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 4835251 # number of writebacks
> system.cpu.dcache.writebacks::total 4835251 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3083373 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 3083373 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1063096 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 1063096 # number of WriteReq MSHR hits
828,835c826,833
< system.cpu.dcache.demand_mshr_hits::cpu.data 4041425 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 4041425 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 4041425 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 4041425 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270355 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 14270355 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737453 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 2737453 # number of WriteReq MSHR misses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 4146469 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 4146469 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 4146469 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 4146469 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268494 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 14268494 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737510 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 2737510 # number of WriteReq MSHR misses
838,855c836,853
< system.cpu.dcache.demand_mshr_misses::cpu.data 17007808 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 17007808 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 17007809 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 17007809 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 303479537034 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 303479537034 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 110174073244 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 110174073244 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 413653610278 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 413653610278 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 413653672278 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 413653672278 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029319 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029319 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015861 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015861 # mshr miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 17006004 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 17006004 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 17006005 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 17006005 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 329072767985 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 329072767985 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115107857313 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 115107857313 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444180625298 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 444180625298 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444180693048 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 444180693048 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
858,871c856,869
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.025796 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.025796 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21266.432197 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21266.432197 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40246.927799 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40246.927799 # average WriteReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24321.394637 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 24321.394637 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24321.396852 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 24321.396852 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23062.894233 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23062.894233 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42048.378750 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42048.378750 # average WriteReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency
> system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26119.047443 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26119.047443 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26119.049891 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26119.049891 # average overall mshr miss latency
873,877c871,875
< system.cpu.icache.tags.replacements 591 # number of replacements
< system.cpu.icache.tags.tagsinuse 445.749905 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 656876635 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 1079 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 608782.794254 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 588 # number of replacements
> system.cpu.icache.tags.tagsinuse 446.068543 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 656912599 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 1076 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 610513.567844 # Average number of references to valid blocks.
879,881c877,879
< system.cpu.icache.tags.occ_blocks::cpu.inst 445.749905 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.870605 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.870605 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 446.068543 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.871228 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.871228 # Average percentage of cache occupancy
883c881
< system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
885c883
< system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id
887,912c885,910
< system.cpu.icache.tags.tag_accesses 1313757597 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 1313757597 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 656876635 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 656876635 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 656876635 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 656876635 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 656876635 # number of overall hits
< system.cpu.icache.overall_hits::total 656876635 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1624 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1624 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1624 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1624 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1624 # number of overall misses
< system.cpu.icache.overall_misses::total 1624 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 95182738 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 95182738 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 95182738 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 95182738 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 95182738 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 95182738 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 656878259 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 656878259 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 656878259 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 656878259 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 656878259 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 656878259 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 1313829498 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 1313829498 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 656912599 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 656912599 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 656912599 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 656912599 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 656912599 # number of overall hits
> system.cpu.icache.overall_hits::total 656912599 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1612 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1612 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1612 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1612 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1612 # number of overall misses
> system.cpu.icache.overall_misses::total 1612 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 102924516 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 102924516 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 102924516 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 102924516 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 102924516 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 102924516 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 656914211 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 656914211 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 656914211 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 656914211 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 656914211 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 656914211 # number of overall (read+write) accesses
919,930c917,928
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58610.060345 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 58610.060345 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 58610.060345 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 58610.060345 # average overall miss latency
< system.cpu.icache.blocked_cycles::no_mshrs 15932 # number of cycles access was blocked
< system.cpu.icache.blocked_cycles::no_targets 279 # number of cycles access was blocked
< system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked
< system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked
< system.cpu.icache.avg_blocked_cycles::no_mshrs 82.549223 # average number of cycles each access was blocked
< system.cpu.icache.avg_blocked_cycles::no_targets 39.857143 # average number of cycles each access was blocked
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63848.955335 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 63848.955335 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 63848.955335 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 63848.955335 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 63848.955335 # average overall miss latency
> system.cpu.icache.blocked_cycles::no_mshrs 17306 # number of cycles access was blocked
> system.cpu.icache.blocked_cycles::no_targets 307 # number of cycles access was blocked
> system.cpu.icache.blocked::no_mshrs 186 # number of cycles access was blocked
> system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
> system.cpu.icache.avg_blocked_cycles::no_mshrs 93.043011 # average number of cycles each access was blocked
> system.cpu.icache.avg_blocked_cycles::no_targets 38.375000 # average number of cycles each access was blocked
933,950c931,948
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 545 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 545 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 545 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 545 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 545 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 545 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1079 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 1079 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 1079 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 1079 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 1079 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 1079 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69657739 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 69657739 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69657739 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 69657739 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69657739 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 69657739 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 536 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 536 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 536 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 536 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 536 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 536 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1076 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 1076 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 1076 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 1076 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 1076 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 1076 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76203217 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 76203217 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76203217 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 76203217 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76203217 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 76203217 # number of overall MSHR miss cycles
957,962c955,960
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64557.682113 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64557.682113 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70820.833643 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70820.833643 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70820.833643 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 70820.833643 # average overall mshr miss latency
964,966c962,964
< system.cpu.l2cache.prefetcher.num_hwpf_issued 10957108 # number of hwpf issued
< system.cpu.l2cache.prefetcher.pfIdentified 11640584 # number of prefetch candidates identified
< system.cpu.l2cache.prefetcher.pfBufferHit 428597 # number of redundant prefetches already in prefetch queue
---
> system.cpu.l2cache.prefetcher.num_hwpf_issued 10941726 # number of hwpf issued
> system.cpu.l2cache.prefetcher.pfIdentified 11630409 # number of prefetch candidates identified
> system.cpu.l2cache.prefetcher.pfBufferHit 431114 # number of redundant prefetches already in prefetch queue
969,998c967,996
< system.cpu.l2cache.prefetcher.pfSpanPage 4655192 # number of prefetches not generated due to page crossing
< system.cpu.l2cache.tags.replacements 4712285 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 16126.126522 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 15322460 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 4728219 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 3.240641 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 29457635500 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 5257.920148 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.981837 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 7532.490537 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3316.734000 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.320918 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001159 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.459747 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.202437 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.984261 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1022 762 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 15172 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::1 562 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1022::3 192 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 487 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2381 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1270 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9338 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1696 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1022 0.046509 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.926025 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 357015786 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 357015786 # Number of data accesses
---
> system.cpu.l2cache.prefetcher.pfSpanPage 4654951 # number of prefetches not generated due to page crossing
> system.cpu.l2cache.tags.replacements 4713207 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 16130.406064 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 15325447 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 4729134 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 3.240646 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 29468558500 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 5233.732135 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.908605 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 7574.796716 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3302.968608 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.319442 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001154 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.462329 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.201597 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.984522 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1022 731 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 15196 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::1 525 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1022::3 201 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 466 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2455 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1253 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9206 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1816 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1022 0.044617 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927490 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 356943997 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 356943997 # Number of data accesses
1000,1005c998,1003
< system.cpu.l2cache.ReadReq_hits::cpu.data 11478119 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 11478162 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 4837992 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 4837992 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1752292 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1752292 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.data 11484174 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 11484217 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 4835251 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 4835251 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1752141 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1752141 # number of ReadExReq hits
1007,1008c1005,1006
< system.cpu.l2cache.demand_hits::cpu.data 13230411 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 13230454 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 13236315 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 13236358 # number of demand (read+write) hits
1010,1069c1008,1067
< system.cpu.l2cache.overall_hits::cpu.data 13230411 # number of overall hits
< system.cpu.l2cache.overall_hits::total 13230454 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 1036 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 2792203 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 2793239 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 985195 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 985195 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 1036 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 3777398 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 3778434 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 1036 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 3777398 # number of overall misses
< system.cpu.l2cache.overall_misses::total 3778434 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68850750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 219170127718 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 219238978468 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95974587720 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 95974587720 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 68850750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 315144715438 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 315213566188 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 68850750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 315144715438 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 315213566188 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 1079 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 14270322 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 14271401 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 4837992 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 4837992 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737487 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 2737487 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 1079 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 17007809 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 17008888 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 1079 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 17007809 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 17008888 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960148 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195665 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.195723 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359890 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.359890 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960148 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.222098 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.222145 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960148 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.222098 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.222145 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66458.252896 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78493.622318 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 78489.158453 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97416.844097 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97416.844097 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66458.252896 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83429.047042 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 83424.393859 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66458.252896 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83429.047042 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 83424.393859 # average overall miss latency
< system.cpu.l2cache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked
---
> system.cpu.l2cache.overall_hits::cpu.data 13236315 # number of overall hits
> system.cpu.l2cache.overall_hits::total 13236358 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 1033 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 2784280 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 2785313 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 985410 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 985410 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 1033 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 3769690 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 3770723 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 1033 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 3769690 # number of overall misses
> system.cpu.l2cache.overall_misses::total 3770723 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 75372729 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 239047213138 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 239122585867 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100142345987 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 100142345987 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 75372729 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 339189559125 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 339264931854 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 75372729 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 339189559125 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 339264931854 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 1076 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 14268454 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 14269530 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 4835251 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 4835251 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737551 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 2737551 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 1076 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 17006005 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 17007081 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 1076 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 17006005 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 17007081 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960037 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195135 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.195193 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359960 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.359960 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960037 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.221668 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.221715 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960037 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.221668 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.221715 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72964.887706 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.024946 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.243960 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101625.055547 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101625.055547 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 89973.443251 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72964.887706 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89978.104068 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 89973.443251 # average overall miss latency
> system.cpu.l2cache.blocked_cycles::no_mshrs 846 # number of cycles access was blocked
1071c1069
< system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
---
> system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
1073c1071
< system.cpu.l2cache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked
---
> system.cpu.l2cache.avg_blocked_cycles::no_mshrs 211.500000 # average number of cycles each access was blocked
1077,1117c1075,1115
< system.cpu.l2cache.writebacks::writebacks 1638491 # number of writebacks
< system.cpu.l2cache.writebacks::total 1638491 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43338 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadReq_mshr_hits::total 43338 # number of ReadReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3740 # number of ReadExReq MSHR hits
< system.cpu.l2cache.ReadExReq_mshr_hits::total 3740 # number of ReadExReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.data 47078 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.demand_mshr_hits::total 47078 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.data 47078 # number of overall MSHR hits
< system.cpu.l2cache.overall_mshr_hits::total 47078 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1036 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748865 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 2749901 # number of ReadReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993225 # number of HardPFReq MSHR misses
< system.cpu.l2cache.HardPFReq_mshr_misses::total 993225 # number of HardPFReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981455 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 981455 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 1036 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 3730320 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 3731356 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 1036 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 3730320 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993225 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 4724581 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59969750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 193568757616 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 193628727366 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68540364307 # number of HardPFReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87429015038 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87429015038 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59969750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 280997772654 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 281057742404 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59969750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 280997772654 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 349598106711 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192628 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192686 # mshr miss rate for ReadReq accesses
---
> system.cpu.l2cache.writebacks::writebacks 1639072 # number of writebacks
> system.cpu.l2cache.writebacks::total 1639072 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 36084 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadReq_mshr_hits::total 36084 # number of ReadReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3647 # number of ReadExReq MSHR hits
> system.cpu.l2cache.ReadExReq_mshr_hits::total 3647 # number of ReadExReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.data 39731 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.demand_mshr_hits::total 39731 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.data 39731 # number of overall MSHR hits
> system.cpu.l2cache.overall_mshr_hits::total 39731 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1033 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748196 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 2749229 # number of ReadReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993723 # number of HardPFReq MSHR misses
> system.cpu.l2cache.HardPFReq_mshr_misses::total 993723 # number of HardPFReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981763 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 981763 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 1033 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 3729959 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 3730992 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 1033 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 3729959 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993723 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 4724715 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66585771 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212846915589 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212913501360 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 71046693133 # number of HardPFReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91372170669 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91372170669 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66585771 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304219086258 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 304285672029 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66585771 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304219086258 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 71046693133 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 375332365162 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192606 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192664 # mshr miss rate for ReadReq accesses
1120,1126c1118,1124
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358524 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358524 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.219377 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for overall accesses
---
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358628 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358628 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.219379 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960037 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219332 # mshr miss rate for overall accesses
1128,1142c1126,1140
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.277771 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57885.859073 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70417.702439 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70412.981182 # average ReadReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average HardPFReq mshr miss latency
< system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69007.892781 # average HardPFReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89081.022602 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89081.022602 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75323.218263 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73995.579018 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.277809 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64458.636012 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77449.685390 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77444.804111 # average ReadReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average HardPFReq mshr miss latency
> system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71495.470199 # average HardPFReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93069.478753 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93069.478753 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81556.238134 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64458.636012 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81560.973259 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71495.470199 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79440.212830 # average overall mshr miss latency
1144,1159c1142,1157
< system.cpu.toL2Bus.trans_dist::ReadReq 14271401 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 14271401 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 4837992 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::HardPFReq 1352607 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 2737487 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 2737487 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2158 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38853610 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 38855768 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69056 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398131264 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 1398200320 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.snoops 1352607 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 23199492 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5.058303 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.234316 # Request fanout histogram
---
> system.cpu.toL2Bus.trans_dist::ReadReq 14269530 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 14269530 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 4835251 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::HardPFReq 1300143 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 2737551 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 2737551 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2152 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38847261 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 38849413 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68864 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397840384 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 1397909248 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 1300143 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 23142477 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3.056180 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.230269 # Request fanout histogram
1164,1167c1162,1163
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 21846885 94.17% 94.17% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 1352607 5.83% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 21842334 94.38% 94.38% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 1300143 5.62% 100.00% # Request fanout histogram
1169,1174c1165,1170
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 23199492 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 15761436995 # Layer occupancy (ticks)
< system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
< system.cpu.toL2Bus.respLayer0.occupancy 1798250 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 23142477 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 15756418748 # Layer occupancy (ticks)
> system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%)
> system.cpu.toL2Bus.respLayer0.occupancy 1812271 # Layer occupancy (ticks)
1176c1172
< system.cpu.toL2Bus.respLayer1.occupancy 26002804288 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 26100835834 # Layer occupancy (ticks)
1178,1186c1174,1182
< system.membus.trans_dist::ReadReq 3738412 # Transaction distribution
< system.membus.trans_dist::ReadResp 3738412 # Transaction distribution
< system.membus.trans_dist::Writeback 1638491 # Transaction distribution
< system.membus.trans_dist::ReadExReq 981933 # Transaction distribution
< system.membus.trans_dist::ReadExResp 981933 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11079181 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 11079181 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406965504 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 406965504 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadReq 3739202 # Transaction distribution
> system.membus.trans_dist::ReadResp 3739202 # Transaction distribution
> system.membus.trans_dist::Writeback 1639072 # Transaction distribution
> system.membus.trans_dist::ReadExReq 982028 # Transaction distribution
> system.membus.trans_dist::ReadExResp 982028 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11081532 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 11081532 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407059328 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 407059328 # Cumulative packet size per connected master and slave (bytes)
1188c1184
< system.membus.snoop_fanout::samples 6358836 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 6360302 # Request fanout histogram
1192c1188
< system.membus.snoop_fanout::0 6358836 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 6360302 100.00% 100.00% # Request fanout histogram
1197,1201c1193,1197
< system.membus.snoop_fanout::total 6358836 # Request fanout histogram
< system.membus.reqLayer0.occupancy 20942586092 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
< system.membus.respLayer1.occupancy 44003891862 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 5.8 # Layer utilization (%)
---
> system.membus.snoop_fanout::total 6360302 # Request fanout histogram
> system.membus.reqLayer0.occupancy 14493239223 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.9 # Layer utilization (%)
> system.membus.respLayer1.occupancy 25671846860 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 3.3 # Layer utilization (%)