3,5c3,5
< sim_seconds 0.533797 # Number of seconds simulated
< sim_ticks 533797009000 # Number of ticks simulated
< final_tick 533797009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.533762 # Number of seconds simulated
> sim_ticks 533761922000 # Number of ticks simulated
> final_tick 533761922000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 163502 # Simulator instruction rate (inst/s)
< host_op_rate 182399 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 56505895 # Simulator tick rate (ticks/s)
< host_mem_usage 249880 # Number of bytes of host memory used
< host_seconds 9446.75 # Real time elapsed on the host
---
> host_inst_rate 155948 # Simulator instruction rate (inst/s)
> host_op_rate 173972 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 53891847 # Simulator tick rate (ticks/s)
> host_mem_usage 269768 # Number of bytes of host memory used
> host_seconds 9904.32 # Real time elapsed on the host
16,48c16,48
< system.physmem.bytes_read::cpu.inst 47680 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 143743296 # Number of bytes read from this memory
< system.physmem.bytes_read::total 143790976 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 47680 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 47680 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 70431872 # Number of bytes written to this memory
< system.physmem.bytes_written::total 70431872 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 745 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 2245989 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 2246734 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1100498 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1100498 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 89322 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 269284566 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 269373889 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 89322 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 89322 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 131945048 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 131945048 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 131945048 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 89322 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 269284566 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 401318937 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 2246734 # Number of read requests accepted
< system.physmem.writeReqs 1100498 # Number of write requests accepted
< system.physmem.readBursts 2246734 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1100498 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 143754112 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 36864 # Total number of bytes read from write queue
< system.physmem.bytesWritten 70430784 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 143790976 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 70431872 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 576 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bytes_read::cpu.inst 47616 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 143740736 # Number of bytes read from this memory
> system.physmem.bytes_read::total 143788352 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 47616 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 47616 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 70437056 # Number of bytes written to this memory
> system.physmem.bytes_written::total 70437056 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 744 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 2245949 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 2246693 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1100579 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1100579 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 89208 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 269297472 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 269386680 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 89208 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 89208 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 131963434 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 131963434 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 131963434 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 89208 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 269297472 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 401350114 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 2246694 # Number of read requests accepted
> system.physmem.writeReqs 1100579 # Number of write requests accepted
> system.physmem.readBursts 2246694 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1100579 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 143750848 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 37568 # Total number of bytes read from write queue
> system.physmem.bytesWritten 70435904 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 143788416 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 70437056 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 587 # Number of DRAM read bursts serviced by the write queue
51,82c51,82
< system.physmem.perBankRdBursts::0 139750 # Per bank write bursts
< system.physmem.perBankRdBursts::1 136273 # Per bank write bursts
< system.physmem.perBankRdBursts::2 133708 # Per bank write bursts
< system.physmem.perBankRdBursts::3 136246 # Per bank write bursts
< system.physmem.perBankRdBursts::4 134906 # Per bank write bursts
< system.physmem.perBankRdBursts::5 135253 # Per bank write bursts
< system.physmem.perBankRdBursts::6 136175 # Per bank write bursts
< system.physmem.perBankRdBursts::7 136295 # Per bank write bursts
< system.physmem.perBankRdBursts::8 143732 # Per bank write bursts
< system.physmem.perBankRdBursts::9 146555 # Per bank write bursts
< system.physmem.perBankRdBursts::10 144302 # Per bank write bursts
< system.physmem.perBankRdBursts::11 146237 # Per bank write bursts
< system.physmem.perBankRdBursts::12 145788 # Per bank write bursts
< system.physmem.perBankRdBursts::13 146277 # Per bank write bursts
< system.physmem.perBankRdBursts::14 142119 # Per bank write bursts
< system.physmem.perBankRdBursts::15 142542 # Per bank write bursts
< system.physmem.perBankWrBursts::0 69128 # Per bank write bursts
< system.physmem.perBankWrBursts::1 67452 # Per bank write bursts
< system.physmem.perBankWrBursts::2 65650 # Per bank write bursts
< system.physmem.perBankWrBursts::3 66298 # Per bank write bursts
< system.physmem.perBankWrBursts::4 66182 # Per bank write bursts
< system.physmem.perBankWrBursts::5 66379 # Per bank write bursts
< system.physmem.perBankWrBursts::6 67939 # Per bank write bursts
< system.physmem.perBankWrBursts::7 68869 # Per bank write bursts
< system.physmem.perBankWrBursts::8 70353 # Per bank write bursts
< system.physmem.perBankWrBursts::9 70986 # Per bank write bursts
< system.physmem.perBankWrBursts::10 70505 # Per bank write bursts
< system.physmem.perBankWrBursts::11 70955 # Per bank write bursts
< system.physmem.perBankWrBursts::12 70250 # Per bank write bursts
< system.physmem.perBankWrBursts::13 70819 # Per bank write bursts
< system.physmem.perBankWrBursts::14 69624 # Per bank write bursts
< system.physmem.perBankWrBursts::15 69092 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 139629 # Per bank write bursts
> system.physmem.perBankRdBursts::1 136292 # Per bank write bursts
> system.physmem.perBankRdBursts::2 133828 # Per bank write bursts
> system.physmem.perBankRdBursts::3 136435 # Per bank write bursts
> system.physmem.perBankRdBursts::4 134766 # Per bank write bursts
> system.physmem.perBankRdBursts::5 135151 # Per bank write bursts
> system.physmem.perBankRdBursts::6 136244 # Per bank write bursts
> system.physmem.perBankRdBursts::7 136309 # Per bank write bursts
> system.physmem.perBankRdBursts::8 143829 # Per bank write bursts
> system.physmem.perBankRdBursts::9 146501 # Per bank write bursts
> system.physmem.perBankRdBursts::10 144298 # Per bank write bursts
> system.physmem.perBankRdBursts::11 146295 # Per bank write bursts
> system.physmem.perBankRdBursts::12 145712 # Per bank write bursts
> system.physmem.perBankRdBursts::13 146106 # Per bank write bursts
> system.physmem.perBankRdBursts::14 142241 # Per bank write bursts
> system.physmem.perBankRdBursts::15 142471 # Per bank write bursts
> system.physmem.perBankWrBursts::0 69077 # Per bank write bursts
> system.physmem.perBankWrBursts::1 67426 # Per bank write bursts
> system.physmem.perBankWrBursts::2 65726 # Per bank write bursts
> system.physmem.perBankWrBursts::3 66343 # Per bank write bursts
> system.physmem.perBankWrBursts::4 66130 # Per bank write bursts
> system.physmem.perBankWrBursts::5 66357 # Per bank write bursts
> system.physmem.perBankWrBursts::6 67984 # Per bank write bursts
> system.physmem.perBankWrBursts::7 68878 # Per bank write bursts
> system.physmem.perBankWrBursts::8 70373 # Per bank write bursts
> system.physmem.perBankWrBursts::9 70997 # Per bank write bursts
> system.physmem.perBankWrBursts::10 70493 # Per bank write bursts
> system.physmem.perBankWrBursts::11 70981 # Per bank write bursts
> system.physmem.perBankWrBursts::12 70269 # Per bank write bursts
> system.physmem.perBankWrBursts::13 70812 # Per bank write bursts
> system.physmem.perBankWrBursts::14 69646 # Per bank write bursts
> system.physmem.perBankWrBursts::15 69069 # Per bank write bursts
84,85c84,85
< system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
< system.physmem.totGap 533796944500 # Total gap between requests
---
> system.physmem.numWrRetry 2 # Number of times write queue was full causing retry
> system.physmem.totGap 533761847000 # Total gap between requests
92c92
< system.physmem.readPktSize::6 2246734 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 2246694 # Read request sizes (log2)
99,104c99,104
< system.physmem.writePktSize::6 1100498 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1621551 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 445207 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 135727 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::3 43660 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 12 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1100579 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1621644 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 445219 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 135704 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::3 43528 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see
132,239c132,239
< system.physmem.wrQLenPdf::0 48879 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::1 49064 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::2 49063 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::3 49078 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::4 49086 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::5 49106 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::6 49070 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::7 49088 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::8 49113 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::9 49112 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::10 49119 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::11 49167 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::12 49186 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::13 49268 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::14 49533 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::15 49888 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 50325 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 52053 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 51988 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 51535 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 52936 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 52147 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 2310 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 336 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 36 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 10 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
< system.physmem.bytesPerActivate::samples 2077673 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 103.074669 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 79.977753 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 184.400722 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::64-65 1659880 79.89% 79.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-129 227444 10.95% 90.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::192-193 69322 3.34% 94.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-257 37684 1.81% 95.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::320-321 24960 1.20% 97.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-385 12074 0.58% 97.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::448-449 8272 0.40% 98.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-513 8168 0.39% 98.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::576-577 4452 0.21% 98.78% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-641 3374 0.16% 98.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::704-705 2842 0.14% 99.08% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-769 2038 0.10% 99.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::832-833 1716 0.08% 99.26% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-897 1451 0.07% 99.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::960-961 1190 0.06% 99.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1025 1071 0.05% 99.44% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1088-1089 949 0.05% 99.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1152-1153 909 0.04% 99.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1216-1217 717 0.03% 99.56% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1280-1281 682 0.03% 99.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1344-1345 676 0.03% 99.62% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1408-1409 3081 0.15% 99.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1472-1473 420 0.02% 99.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1536-1537 289 0.01% 99.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1600-1601 203 0.01% 99.82% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1664-1665 186 0.01% 99.83% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1728-1729 219 0.01% 99.84% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1792-1793 499 0.02% 99.86% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1920-1921 143 0.01% 99.87% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1984-1985 125 0.01% 99.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2048-2049 127 0.01% 99.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2112-2113 94 0.00% 99.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2176-2177 128 0.01% 99.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2240-2241 92 0.00% 99.90% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2304-2305 97 0.00% 99.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2368-2369 82 0.00% 99.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2432-2433 82 0.00% 99.91% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2496-2497 62 0.00% 99.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2560-2561 59 0.00% 99.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2624-2625 52 0.00% 99.92% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2688-2689 72 0.00% 99.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2752-2753 47 0.00% 99.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2816-2817 62 0.00% 99.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2880-2881 51 0.00% 99.93% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::2944-2945 51 0.00% 99.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3008-3009 39 0.00% 99.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3072-3073 48 0.00% 99.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3136-3137 40 0.00% 99.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3200-3201 42 0.00% 99.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3264-3265 28 0.00% 99.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3328-3329 34 0.00% 99.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3392-3393 28 0.00% 99.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3456-3457 44 0.00% 99.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3520-3521 23 0.00% 99.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3584-3585 30 0.00% 99.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3648-3649 29 0.00% 99.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3712-3713 27 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3776-3777 28 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3840-3841 16 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3904-3905 17 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::3968-3969 28 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4032-4033 15 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4096-4097 19 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4160-4161 9 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4224-4225 25 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4288-4289 15 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4352-4353 12 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4416-4417 18 0.00% 99.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4480-4481 18 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4544-4545 19 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4608-4609 22 0.00% 99.97% # Bytes accessed per row activation
---
> system.physmem.wrQLenPdf::0 48877 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::1 49060 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::2 49089 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::3 49071 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::4 49076 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::5 49104 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::6 49085 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::7 49081 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::8 49079 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::9 49128 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::10 49123 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::11 49158 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::12 49172 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::13 49261 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::14 49504 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::15 49899 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 50373 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 52060 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 52016 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 51492 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 52976 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 52139 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 2343 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 326 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 39 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 16 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 5 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 4 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 6 # What write queue length does an incoming req see
> system.physmem.bytesPerActivate::samples 2078319 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 103.049035 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 79.954808 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 184.695982 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::64-65 1660986 79.92% 79.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-129 227336 10.94% 90.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::192-193 68882 3.31% 94.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-257 37662 1.81% 95.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::320-321 25035 1.20% 97.19% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-385 12093 0.58% 97.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::448-449 8438 0.41% 98.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-513 8141 0.39% 98.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::576-577 4391 0.21% 98.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-641 3442 0.17% 98.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::704-705 2829 0.14% 99.08% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-769 1974 0.09% 99.18% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::832-833 1676 0.08% 99.26% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-897 1442 0.07% 99.33% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::960-961 1174 0.06% 99.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1025 1106 0.05% 99.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1088-1089 969 0.05% 99.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1152-1153 858 0.04% 99.52% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1216-1217 735 0.04% 99.56% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1280-1281 673 0.03% 99.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1344-1345 651 0.03% 99.62% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1408-1409 3128 0.15% 99.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1472-1473 421 0.02% 99.79% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1536-1537 240 0.01% 99.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1600-1601 179 0.01% 99.81% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1664-1665 200 0.01% 99.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1728-1729 207 0.01% 99.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1792-1793 498 0.02% 99.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1856-1857 133 0.01% 99.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1920-1921 147 0.01% 99.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1984-1985 136 0.01% 99.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2048-2049 128 0.01% 99.88% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2112-2113 89 0.00% 99.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2176-2177 121 0.01% 99.89% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2240-2241 102 0.00% 99.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2304-2305 117 0.01% 99.90% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2368-2369 77 0.00% 99.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2432-2433 74 0.00% 99.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2496-2497 59 0.00% 99.91% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2560-2561 70 0.00% 99.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2624-2625 60 0.00% 99.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2688-2689 54 0.00% 99.92% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2752-2753 55 0.00% 99.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2816-2817 76 0.00% 99.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2880-2881 49 0.00% 99.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::2944-2945 45 0.00% 99.93% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3008-3009 33 0.00% 99.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3072-3073 66 0.00% 99.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3136-3137 39 0.00% 99.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3200-3201 33 0.00% 99.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3264-3265 36 0.00% 99.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3328-3329 47 0.00% 99.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3392-3393 27 0.00% 99.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3456-3457 23 0.00% 99.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3520-3521 22 0.00% 99.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3584-3585 27 0.00% 99.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3648-3649 21 0.00% 99.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3712-3713 25 0.00% 99.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3776-3777 26 0.00% 99.95% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3840-3841 40 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3904-3905 20 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::3968-3969 18 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4032-4033 16 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4096-4097 30 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4160-4161 10 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4224-4225 21 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4288-4289 16 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4352-4353 36 0.00% 99.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4416-4417 15 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4480-4481 15 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4544-4545 13 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4608-4609 17 0.00% 99.97% # Bytes accessed per row activation
241,251c241,251
< system.physmem.bytesPerActivate::4736-4737 34 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4800-4801 14 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4864-4865 17 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4928-4929 11 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::4992-4993 23 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5056-5057 14 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5120-5121 20 0.00% 99.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5184-5185 13 0.00% 99.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5248-5249 17 0.00% 99.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5312-5313 15 0.00% 99.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5376-5377 185 0.01% 99.99% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::4736-4737 17 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4800-4801 17 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4864-4865 32 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4928-4929 10 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::4992-4993 14 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5056-5057 15 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5120-5121 31 0.00% 99.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5184-5185 15 0.00% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5248-5249 10 0.00% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5312-5313 9 0.00% 99.98% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5376-5377 206 0.01% 99.99% # Bytes accessed per row activation
253,254c253,255
< system.physmem.bytesPerActivate::5504-5505 13 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5632-5633 6 0.00% 99.99% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::5504-5505 6 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5568-5569 4 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5632-5633 3 0.00% 99.99% # Bytes accessed per row activation
256,282c257,283
< system.physmem.bytesPerActivate::5760-5761 17 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5824-5825 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5888-5889 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::5952-5953 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6016-6017 14 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6080-6081 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6144-6145 8 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6208-6209 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6272-6273 12 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6336-6337 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6400-6401 7 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6464-6465 6 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6528-6529 16 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6656-6657 38 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6720-6721 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6784-6785 8 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6848-6849 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6912-6913 6 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::6976-6977 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7040-7041 3 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7104-7105 5 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7168-7169 4 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7232-7233 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7296-7297 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7424-7425 1 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7488-7489 2 0.00% 99.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7552-7553 13 0.00% 100.00% # Bytes accessed per row activation
---
> system.physmem.bytesPerActivate::5824-5825 2 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5888-5889 22 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::5952-5953 6 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6016-6017 4 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6080-6081 3 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6144-6145 5 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6208-6209 4 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6272-6273 3 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6336-6337 1 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6400-6401 20 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6464-6465 2 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6592-6593 3 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6656-6657 37 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6720-6721 2 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6784-6785 4 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6848-6849 1 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6912-6913 5 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::6976-6977 3 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7040-7041 2 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7104-7105 3 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7168-7169 13 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7232-7233 1 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7296-7297 1 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7360-7361 6 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7488-7489 1 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7552-7553 1 0.00% 99.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7616-7617 4 0.00% 100.00% # Bytes accessed per row activation
284,296c285,296
< system.physmem.bytesPerActivate::7744-7745 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7808-7809 3 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7872-7873 2 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::7936-7937 2 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8128-8129 1 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::8192-8193 82 0.00% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 2077673 # Bytes accessed per row activation
< system.physmem.totQLat 32821468000 # Total ticks spent queuing
< system.physmem.totMemAccLat 104059554250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 11230790000 # Total ticks spent in databus transfers
< system.physmem.totBankLat 60007296250 # Total ticks spent accessing banks
< system.physmem.avgQLat 14612.27 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 26715.53 # Average bank access latency per DRAM burst
---
> system.physmem.bytesPerActivate::7872-7873 1 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::7936-7937 6 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8000-8001 1 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8064-8065 4 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::8192-8193 88 0.00% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 2078319 # Bytes accessed per row activation
> system.physmem.totQLat 32815970750 # Total ticks spent queuing
> system.physmem.totMemAccLat 104054627000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 11230535000 # Total ticks spent in databus transfers
> system.physmem.totBankLat 60008121250 # Total ticks spent accessing banks
> system.physmem.avgQLat 14610.15 # Average queueing delay per DRAM burst
> system.physmem.avgBankLat 26716.50 # Average bank access latency per DRAM burst
298,302c298,302
< system.physmem.avgMemAccLat 46327.80 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 269.30 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 131.94 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 269.37 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 131.95 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 46326.66 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 269.32 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 131.96 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 269.39 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 131.96 # Average system write bandwidth in MiByte/s
308,326c308,326
< system.physmem.avgWrQLen 10.35 # Average write queue length when enqueuing
< system.physmem.readRowHits 932509 # Number of row buffer hits during reads
< system.physmem.writeRowHits 336457 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 41.52 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 30.57 # Row buffer hit rate for writes
< system.physmem.avgGap 159474.14 # Average gap between requests
< system.physmem.pageHitRate 37.92 # Row buffer hit rate, read and write combined
< system.physmem.prechargeAllPercent 5.98 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 401318817 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 1420235 # Transaction distribution
< system.membus.trans_dist::ReadResp 1420234 # Transaction distribution
< system.membus.trans_dist::Writeback 1100498 # Transaction distribution
< system.membus.trans_dist::ReadExReq 826499 # Transaction distribution
< system.membus.trans_dist::ReadExResp 826499 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593965 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5593965 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214222784 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 214222784 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 214222784 # Total data (bytes)
---
> system.physmem.avgWrQLen 10.33 # Average write queue length when enqueuing
> system.physmem.readRowHits 932061 # Number of row buffer hits during reads
> system.physmem.writeRowHits 336288 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 41.50 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 30.56 # Row buffer hit rate for writes
> system.physmem.avgGap 159461.70 # Average gap between requests
> system.physmem.pageHitRate 37.90 # Row buffer hit rate, read and write combined
> system.physmem.prechargeAllPercent 5.96 # Percentage of time for which DRAM has all the banks in precharge state
> system.membus.throughput 401350114 # Throughput (bytes/s)
> system.membus.trans_dist::ReadReq 1420099 # Transaction distribution
> system.membus.trans_dist::ReadResp 1420098 # Transaction distribution
> system.membus.trans_dist::Writeback 1100579 # Transaction distribution
> system.membus.trans_dist::ReadExReq 826595 # Transaction distribution
> system.membus.trans_dist::ReadExResp 826595 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5593966 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5593966 # Packet count per connected master and slave (bytes)
> system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214225408 # Cumulative packet size per connected master and slave (bytes)
> system.membus.tot_pkt_size::total 214225408 # Cumulative packet size per connected master and slave (bytes)
> system.membus.data_through_bus 214225408 # Total data (bytes)
328c328
< system.membus.reqLayer0.occupancy 12926153000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 12926034750 # Layer occupancy (ticks)
330c330
< system.membus.respLayer1.occupancy 21085487000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 21084340000 # Layer occupancy (ticks)
333,337c333,337
< system.cpu.branchPred.lookups 303451211 # Number of BP lookups
< system.cpu.branchPred.condPredicted 249690817 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 15200865 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 174297258 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 161770128 # Number of BTB hits
---
> system.cpu.branchPred.lookups 303426723 # Number of BP lookups
> system.cpu.branchPred.condPredicted 249665263 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 15197446 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 174885075 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 161766496 # Number of BTB hits
339,341c339,362
< system.cpu.branchPred.BTBHitPct 92.812779 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 17550277 # Number of times the RAS was used to get a target.
< system.cpu.branchPred.RASInCorrect 188 # Number of incorrect RAS predictions.
---
> system.cpu.branchPred.BTBHitPct 92.498743 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 17552924 # Number of times the RAS was used to get a target.
> system.cpu.branchPred.RASInCorrect 181 # Number of incorrect RAS predictions.
> system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
362a384,404
> system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
> system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
> system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
> system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
> system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
> system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
> system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
> system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
> system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
> system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
> system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
> system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
> system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
> system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
> system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
> system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
> system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
385c427
< system.cpu.numCycles 1067594019 # number of cpu cycles simulated
---
> system.cpu.numCycles 1067523845 # number of cpu cycles simulated
388,400c430,442
< system.cpu.fetch.icacheStallCycles 299164557 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 2189663567 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 303451211 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 179320405 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 435777521 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 88106670 # Number of cycles fetch has spent squashing
< system.cpu.fetch.BlockedCycles 164181608 # Number of cycles fetch has spent blocked
< system.cpu.fetch.PendingTrapStallCycles 55 # Number of stall cycles due to pending traps
< system.cpu.fetch.CacheLines 289571528 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 5986152 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 969098859 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 2.499353 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 3.206220 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.icacheStallCycles 299169160 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 2189552617 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 303426723 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 179319420 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 435766349 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 88088140 # Number of cycles fetch has spent squashing
> system.cpu.fetch.BlockedCycles 164108706 # Number of cycles fetch has spent blocked
> system.cpu.fetch.PendingTrapStallCycles 249 # Number of stall cycles due to pending traps
> system.cpu.fetch.CacheLines 289578845 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 5989031 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 969003000 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 2.499478 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 3.206212 # Number of instructions fetched each cycle (Total)
402,410c444,452
< system.cpu.fetch.rateDist::0 533321418 55.03% 55.03% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 25465587 2.63% 57.66% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 39057125 4.03% 61.69% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 48306210 4.98% 66.68% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 43759030 4.52% 71.19% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 46389880 4.79% 75.98% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 38408230 3.96% 79.94% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 18944401 1.95% 81.90% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 175446978 18.10% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 533236766 55.03% 55.03% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 25461427 2.63% 57.66% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 39064672 4.03% 61.69% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 48308848 4.99% 66.67% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 43759414 4.52% 71.19% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 46393042 4.79% 75.98% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 38404129 3.96% 79.94% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 18940871 1.95% 81.90% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 175433831 18.10% 100.00% # Number of instructions fetched each cycle (Total)
414,440c456,482
< system.cpu.fetch.rateDist::total 969098859 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.284238 # Number of branch fetches per cycle
< system.cpu.fetch.rate 2.051026 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 331405346 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 142029656 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 405372937 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 20316462 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 69974458 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 46022119 # Number of times decode resolved a branch
< system.cpu.decode.BranchMispred 690 # Number of times decode detected a branch misprediction
< system.cpu.decode.DecodedInsts 2369134638 # Number of instructions handled by decode
< system.cpu.decode.SquashedInsts 2461 # Number of squashed instructions handled by decode
< system.cpu.rename.SquashCycles 69974458 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 354905741 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 70599540 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 20110 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 400539970 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 73059040 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 2306329085 # Number of instructions processed by rename
< system.cpu.rename.ROBFullEvents 151792 # Number of times rename has blocked due to ROB full
< system.cpu.rename.IQFullEvents 5017639 # Number of times rename has blocked due to IQ full
< system.cpu.rename.LSQFullEvents 60125136 # Number of times rename has blocked due to LSQ full
< system.cpu.rename.FullRegisterEvents 1 # Number of times there has been no free registers
< system.cpu.rename.RenamedOperands 2282204226 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 10649650977 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 9763673843 # Number of integer rename lookups
< system.cpu.rename.fp_rename_lookups 354 # Number of floating rename lookups
---
> system.cpu.fetch.rateDist::total 969003000 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.284234 # Number of branch fetches per cycle
> system.cpu.fetch.rate 2.051057 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 331406137 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 141956827 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 405364012 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 20318148 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 69957876 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 46020737 # Number of times decode resolved a branch
> system.cpu.decode.BranchMispred 686 # Number of times decode detected a branch misprediction
> system.cpu.decode.DecodedInsts 2369052643 # Number of instructions handled by decode
> system.cpu.decode.SquashedInsts 2441 # Number of squashed instructions handled by decode
> system.cpu.rename.SquashCycles 69957876 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 354906744 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 70525275 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 17150 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 400533325 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 73062630 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 2306235389 # Number of instructions processed by rename
> system.cpu.rename.ROBFullEvents 151230 # Number of times rename has blocked due to ROB full
> system.cpu.rename.IQFullEvents 5013278 # Number of times rename has blocked due to IQ full
> system.cpu.rename.LSQFullEvents 60135849 # Number of times rename has blocked due to LSQ full
> system.cpu.rename.FullRegisterEvents 19 # Number of times there has been no free registers
> system.cpu.rename.RenamedOperands 2282078057 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 10649208068 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 9763247621 # Number of integer rename lookups
> system.cpu.rename.fp_rename_lookups 332 # Number of floating rename lookups
442,459c484,501
< system.cpu.rename.UndoneMaps 575884296 # Number of HB maps that are undone due to squashing
< system.cpu.rename.serializingInsts 843 # count of serializing insts renamed
< system.cpu.rename.tempSerializingInsts 840 # count of temporary serializing insts renamed
< system.cpu.rename.skidInsts 160951749 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 624757210 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 220789926 # Number of stores inserted to the mem dependence unit.
< system.cpu.memDep0.conflictingLoads 85935761 # Number of conflicting loads.
< system.cpu.memDep0.conflictingStores 70812981 # Number of conflicting stores.
< system.cpu.iq.iqInstsAdded 2202388527 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 863 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 2018815703 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 4014611 # Number of squashed instructions issued
< system.cpu.iq.iqSquashedInstsExamined 474721541 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 1127548434 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 693 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 969098859 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 2.083189 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.906427 # Number of insts issued each cycle
---
> system.cpu.rename.UndoneMaps 575758127 # Number of HB maps that are undone due to squashing
> system.cpu.rename.serializingInsts 542 # count of serializing insts renamed
> system.cpu.rename.tempSerializingInsts 539 # count of temporary serializing insts renamed
> system.cpu.rename.skidInsts 160926093 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 624728249 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 220785157 # Number of stores inserted to the mem dependence unit.
> system.cpu.memDep0.conflictingLoads 86065935 # Number of conflicting loads.
> system.cpu.memDep0.conflictingStores 71218939 # Number of conflicting stores.
> system.cpu.iq.iqInstsAdded 2202289570 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 584 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 2018746767 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 4010968 # Number of squashed instructions issued
> system.cpu.iq.iqSquashedInstsExamined 474628449 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 1127376318 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 414 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 969003000 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 2.083324 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.906240 # Number of insts issued each cycle
461,469c503,511
< system.cpu.iq.issued_per_cycle::0 286260209 29.54% 29.54% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 153575867 15.85% 45.39% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 160890539 16.60% 61.99% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 120276383 12.41% 74.40% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 123547545 12.75% 87.15% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 73803065 7.62% 94.76% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 38319485 3.95% 98.72% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 9898934 1.02% 99.74% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::8 2526832 0.26% 100.00% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 286111139 29.53% 29.53% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 153618591 15.85% 45.38% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 160911412 16.61% 61.99% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 120366979 12.42% 74.41% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 123454210 12.74% 87.15% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 73801369 7.62% 94.76% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 38320646 3.95% 98.72% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 9892378 1.02% 99.74% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::8 2526276 0.26% 100.00% # Number of insts issued each cycle
473c515
< system.cpu.iq.issued_per_cycle::total 969098859 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 969003000 # Number of insts issued each cycle
475,505c517,547
< system.cpu.iq.fu_full::IntAlu 899836 3.76% 3.76% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 5555 0.02% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.78% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 18259038 76.22% 80.00% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 4790984 20.00% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 901909 3.77% 3.77% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 5511 0.02% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 18267438 76.34% 80.13% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 4754077 19.87% 100.00% # attempts to use FU when none available
509,510c551,552
< system.cpu.iq.FU_type_0::IntAlu 1236944304 61.27% 61.27% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 924745 0.05% 61.32% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 1236913920 61.27% 61.27% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 925199 0.05% 61.32% # Type of FU issued
532c574
< system.cpu.iq.FU_type_0::SimdFloatCvt 39 0.00% 61.32% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatCvt 31 0.00% 61.32% # Type of FU issued
534,535c576,577
< system.cpu.iq.FU_type_0::SimdFloatMisc 21 0.00% 61.32% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 7 0.00% 61.32% # Type of FU issued
---
> system.cpu.iq.FU_type_0::SimdFloatMisc 20 0.00% 61.32% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 6 0.00% 61.32% # Type of FU issued
538,539c580,581
< system.cpu.iq.FU_type_0::MemRead 587884247 29.12% 90.44% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 193062337 9.56% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::MemRead 587869811 29.12% 90.44% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 193037777 9.56% 100.00% # Type of FU issued
542,554c584,596
< system.cpu.iq.FU_type_0::total 2018815703 # Type of FU issued
< system.cpu.iq.rate 1.890996 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 23955413 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.011866 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 5034700006 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 2677299944 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 1957368325 # Number of integer instruction queue wakeup accesses
< system.cpu.iq.fp_inst_queue_reads 283 # Number of floating instruction queue reads
< system.cpu.iq.fp_inst_queue_writes 522 # Number of floating instruction queue writes
< system.cpu.iq.fp_inst_queue_wakeup_accesses 110 # Number of floating instruction queue wakeup accesses
< system.cpu.iq.int_alu_accesses 2042770975 # Number of integer alu accesses
< system.cpu.iq.fp_alu_accesses 141 # Number of floating point alu accesses
< system.cpu.iew.lsq.thread0.forwLoads 64606441 # Number of loads that had data forwarded from stores
---
> system.cpu.iq.FU_type_0::total 2018746767 # Type of FU issued
> system.cpu.iq.rate 1.891055 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 23928935 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.011853 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 5034436167 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 2677107941 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 1957305969 # Number of integer instruction queue wakeup accesses
> system.cpu.iq.fp_inst_queue_reads 270 # Number of floating instruction queue reads
> system.cpu.iq.fp_inst_queue_writes 526 # Number of floating instruction queue writes
> system.cpu.iq.fp_inst_queue_wakeup_accesses 103 # Number of floating instruction queue wakeup accesses
> system.cpu.iq.int_alu_accesses 2042675566 # Number of integer alu accesses
> system.cpu.iq.fp_alu_accesses 136 # Number of floating point alu accesses
> system.cpu.iew.lsq.thread0.forwLoads 64599963 # Number of loads that had data forwarded from stores
556,559c598,601
< system.cpu.iew.lsq.thread0.squashedLoads 138830441 # Number of loads squashed
< system.cpu.iew.lsq.thread0.ignoredResponses 271664 # Number of memory responses ignored because the instruction is squashed
< system.cpu.iew.lsq.thread0.memOrderViolation 192064 # Number of memory ordering violations
< system.cpu.iew.lsq.thread0.squashedStores 45942881 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 138801480 # Number of loads squashed
> system.cpu.iew.lsq.thread0.ignoredResponses 270727 # Number of memory responses ignored because the instruction is squashed
> system.cpu.iew.lsq.thread0.memOrderViolation 192405 # Number of memory ordering violations
> system.cpu.iew.lsq.thread0.squashedStores 45938112 # Number of stores squashed
563c605
< system.cpu.iew.lsq.thread0.cacheBlocked 4771033 # Number of times an access to memory failed due to the cache being blocked
---
> system.cpu.iew.lsq.thread0.cacheBlocked 4771665 # Number of times an access to memory failed due to the cache being blocked
565,581c607,623
< system.cpu.iew.iewSquashCycles 69974458 # Number of cycles IEW is squashing
< system.cpu.iew.iewBlockCycles 33522833 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 1603829 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 2202389482 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 7882723 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 624757210 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 220789926 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 801 # Number of dispatched non-speculative instructions
< system.cpu.iew.iewIQFullEvents 479284 # Number of times the IQ has become full, causing a stall
< system.cpu.iew.iewLSQFullEvents 97151 # Number of times the LSQ has become full, causing a stall
< system.cpu.iew.memOrderViolationEvents 192064 # Number of memory order violations
< system.cpu.iew.predictedTakenIncorrect 8143428 # Number of branches that were predicted taken incorrectly
< system.cpu.iew.predictedNotTakenIncorrect 9602990 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 17746418 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 1988074209 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 574028107 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 30741494 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewSquashCycles 69957876 # Number of cycles IEW is squashing
> system.cpu.iew.iewBlockCycles 33460674 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 1602950 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 2202290297 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 7880065 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 624728249 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 220785157 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 522 # Number of dispatched non-speculative instructions
> system.cpu.iew.iewIQFullEvents 477902 # Number of times the IQ has become full, causing a stall
> system.cpu.iew.iewLSQFullEvents 97314 # Number of times the LSQ has become full, causing a stall
> system.cpu.iew.memOrderViolationEvents 192405 # Number of memory order violations
> system.cpu.iew.predictedTakenIncorrect 8143338 # Number of branches that were predicted taken incorrectly
> system.cpu.iew.predictedNotTakenIncorrect 9598007 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 17741345 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 1988017569 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 574014855 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 30729198 # Number of squashed instructions skipped in execute
583,591c625,633
< system.cpu.iew.exec_nop 92 # number of nop insts executed
< system.cpu.iew.exec_refs 764206037 # number of memory reference insts executed
< system.cpu.iew.exec_branches 238324356 # Number of branches executed
< system.cpu.iew.exec_stores 190177930 # Number of stores executed
< system.cpu.iew.exec_rate 1.862201 # Inst execution rate
< system.cpu.iew.wb_sent 1965784253 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 1957368435 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 1295422958 # num instructions producing a value
< system.cpu.iew.wb_consumers 2059236430 # num instructions consuming a value
---
> system.cpu.iew.exec_nop 143 # number of nop insts executed
> system.cpu.iew.exec_refs 764181270 # number of memory reference insts executed
> system.cpu.iew.exec_branches 238318975 # Number of branches executed
> system.cpu.iew.exec_stores 190166415 # Number of stores executed
> system.cpu.iew.exec_rate 1.862270 # Inst execution rate
> system.cpu.iew.wb_sent 1965726867 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 1957306072 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 1295394361 # num instructions producing a value
> system.cpu.iew.wb_consumers 2059160488 # num instructions consuming a value
593,594c635,636
< system.cpu.iew.wb_rate 1.833439 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.629079 # average fanout of values written-back
---
> system.cpu.iew.wb_rate 1.833501 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.629089 # average fanout of values written-back
596c638
< system.cpu.commit.commitSquashedInsts 479415060 # The number of squashed insts skipped by commit
---
> system.cpu.commit.commitSquashedInsts 479315418 # The number of squashed insts skipped by commit
598,601c640,643
< system.cpu.commit.branchMispredicts 15200205 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 899124401 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 1.916391 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 2.718302 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 15196786 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 899045124 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 1.916560 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 2.718243 # Number of insts commited each cycle
603,611c645,653
< system.cpu.commit.committed_per_cycle::0 410581675 45.66% 45.66% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 193287424 21.50% 67.16% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 72783200 8.09% 75.26% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 35268105 3.92% 79.18% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 18874620 2.10% 81.28% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 30803459 3.43% 84.70% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 19949403 2.22% 86.92% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 11408599 1.27% 88.19% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 106167916 11.81% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 410462230 45.66% 45.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 193303811 21.50% 67.16% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 72810970 8.10% 75.26% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 35275316 3.92% 79.18% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 18883906 2.10% 81.28% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 30780783 3.42% 84.70% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 19963318 2.22% 86.92% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 11415613 1.27% 88.19% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 106149177 11.81% 100.00% # Number of insts commited each cycle
615c657
< system.cpu.commit.committed_per_cycle::total 899124401 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 899045124 # Number of insts commited each cycle
626c668
< system.cpu.commit.bw_lim_events 106167916 # number cycles where commit BW limit reached
---
> system.cpu.commit.bw_lim_events 106149177 # number cycles where commit BW limit reached
628,631c670,673
< system.cpu.rob.rob_reads 2995444799 # The number of ROB reads
< system.cpu.rob.rob_writes 4475102834 # The number of ROB writes
< system.cpu.timesIdled 1153332 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 98495160 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 2995284619 # The number of ROB reads
> system.cpu.rob.rob_writes 4474886700 # The number of ROB writes
> system.cpu.timesIdled 1153694 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 98520845 # Total number of cycles that the CPU has spent unscheduled due to idling
635,643c677,685
< system.cpu.cpi 0.691195 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 0.691195 # CPI: Total CPI of All Threads
< system.cpu.ipc 1.446770 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 1.446770 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 9956366000 # number of integer regfile reads
< system.cpu.int_regfile_writes 1937254103 # number of integer regfile writes
< system.cpu.fp_regfile_reads 112 # number of floating regfile reads
< system.cpu.fp_regfile_writes 111 # number of floating regfile writes
< system.cpu.misc_regfile_reads 737634139 # number of misc regfile reads
---
> system.cpu.cpi 0.691149 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 0.691149 # CPI: Total CPI of All Threads
> system.cpu.ipc 1.446865 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 1.446865 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 9956057659 # number of integer regfile reads
> system.cpu.int_regfile_writes 1937206435 # number of integer regfile writes
> system.cpu.fp_regfile_reads 98 # number of floating regfile reads
> system.cpu.fp_regfile_writes 94 # number of floating regfile writes
> system.cpu.misc_regfile_reads 737611057 # number of misc regfile reads
645,657c687,699
< system.cpu.toL2Bus.throughput 1604602532 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 7709032 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 7709031 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 3780837 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 1893445 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 1893445 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1548 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22984242 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 22985790 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49536 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856482496 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 856532032 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 856532032 # Total data (bytes)
---
> system.cpu.toL2Bus.throughput 1604912326 # Throughput (bytes/s)
> system.cpu.toL2Bus.trans_dist::ReadReq 7709455 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 7709454 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 3782070 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 1893493 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 1893493 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1550 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22986415 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 22987965 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 49600 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 856591488 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.tot_pkt_size::total 856641088 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.data_through_bus 856641088 # Total data (bytes)
659c701
< system.cpu.toL2Bus.reqLayer0.occupancy 10472653342 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.reqLayer0.occupancy 10474747083 # Layer occupancy (ticks)
661c703
< system.cpu.toL2Bus.respLayer0.occupancy 1293249 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1295998 # Layer occupancy (ticks)
663c705
< system.cpu.toL2Bus.respLayer1.occupancy 14769367993 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 14769977492 # Layer occupancy (ticks)
665,669c707,711
< system.cpu.icache.tags.replacements 20 # number of replacements
< system.cpu.icache.tags.tagsinuse 628.438821 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 289570320 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 774 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 374121.860465 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 19 # number of replacements
> system.cpu.icache.tags.tagsinuse 628.273269 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 289577640 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 775 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 373648.567742 # Average number of references to valid blocks.
671,675c713,717
< system.cpu.icache.tags.occ_blocks::cpu.inst 628.438821 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.306855 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.306855 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 754 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::0 24 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 628.273269 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.306774 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.306774 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 756 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id
677,704c719,747
< system.cpu.icache.tags.age_task_id_blocks_1024::4 726 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.368164 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 579143830 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 579143830 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 289570320 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 289570320 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 289570320 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 289570320 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 289570320 # number of overall hits
< system.cpu.icache.overall_hits::total 289570320 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 1208 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 1208 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 1208 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 1208 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 1208 # number of overall misses
< system.cpu.icache.overall_misses::total 1208 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 83080499 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 83080499 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 83080499 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 83080499 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 83080499 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 83080499 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 289571528 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 289571528 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 289571528 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 289571528 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 289571528 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 289571528 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 727 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.369141 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 579158465 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 579158465 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 289577640 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 289577640 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 289577640 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 289577640 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 289577640 # number of overall hits
> system.cpu.icache.overall_hits::total 289577640 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 1205 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 1205 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 1205 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 1205 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 1205 # number of overall misses
> system.cpu.icache.overall_misses::total 1205 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 81284498 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 81284498 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 81284498 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 81284498 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 81284498 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 81284498 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 289578845 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 289578845 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 289578845 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 289578845 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 289578845 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 289578845 # number of overall (read+write) accesses
711,716c754,759
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68775.247517 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68775.247517 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68775.247517 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68775.247517 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68775.247517 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67456.014938 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 67456.014938 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 67456.014938 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 67456.014938 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 67456.014938 # average overall miss latency
725,742c768,785
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 434 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 434 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 434 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 434 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 434 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 434 # number of overall MSHR hits
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 774 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 774 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 774 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 774 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 774 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 774 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56793251 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 56793251 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56793251 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 56793251 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56793251 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 56793251 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 430 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 430 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 430 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 430 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 430 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 430 # number of overall MSHR hits
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 775 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 775 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 775 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 775 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 775 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 55854002 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 55854002 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 55854002 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 55854002 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 55854002 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 55854002 # number of overall MSHR miss cycles
749,754c792,797
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73376.293282 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73376.293282 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73376.293282 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 73376.293282 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72069.680000 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72069.680000 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72069.680000 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72069.680000 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72069.680000 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72069.680000 # average overall mshr miss latency
756,760c799,803
< system.cpu.l2cache.tags.replacements 2214050 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 31533.035321 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 9245310 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2243823 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.120338 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 2214011 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 31532.870200 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 9247003 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2243785 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.121163 # Average number of references to valid blocks.
762,765c805,808
< system.cpu.l2cache.tags.occ_blocks::writebacks 14302.277072 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.244042 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 17210.514207 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.436471 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 14303.376165 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.256077 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 17209.237958 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.436504 # Average percentage of cache occupancy
767,770c810,813
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.525223 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.962312 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 29773 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.525184 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.962307 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 29774 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
772,790c815,833
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1896 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23750 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3957 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908600 # Percentage of cache occupancy per task id
< system.cpu.l2cache.tags.tag_accesses 111203780 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 111203780 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 28 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 6288761 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 6288789 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 3780837 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 3780837 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1066946 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1066946 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 28 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 7355707 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 7355735 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 28 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 7355707 # number of overall hits
< system.cpu.l2cache.overall_hits::total 7355735 # number of overall hits
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1894 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23751 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3958 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908630 # Percentage of cache occupancy per task id
> system.cpu.l2cache.tags.tag_accesses 111217422 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 111217422 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 29 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 6289318 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 6289347 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 3782070 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 3782070 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1066898 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1066898 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 29 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 7356216 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 7356245 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 29 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 7356216 # number of overall hits
> system.cpu.l2cache.overall_hits::total 7356245 # number of overall hits
792,795c835,838
< system.cpu.l2cache.ReadReq_misses::cpu.data 1419497 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 1420243 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 826499 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 826499 # number of ReadExReq misses
---
> system.cpu.l2cache.ReadReq_misses::cpu.data 1419362 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 1420108 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 826595 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 826595 # number of ReadExReq misses
797,798c840,841
< system.cpu.l2cache.demand_misses::cpu.data 2245996 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 2246742 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 2245957 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 2246703 # number of demand (read+write) misses
800,847c843,890
< system.cpu.l2cache.overall_misses::cpu.data 2245996 # number of overall misses
< system.cpu.l2cache.overall_misses::total 2246742 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55733750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125730219750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 125785953500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76291008750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 76291008750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 55733750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 202021228500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 202076962250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 55733750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 202021228500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 202076962250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 774 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 7708258 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 7709032 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 3780837 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 3780837 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893445 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 1893445 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 774 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 9601703 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 9602477 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 774 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 9601703 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 9602477 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963824 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184153 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.184231 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436505 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.436505 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963824 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.233916 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.233975 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963824 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.233916 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.233975 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74710.120643 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88573.783354 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 88566.501296 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92306.232373 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92306.232373 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74710.120643 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89947.278846 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 89942.219556 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74710.120643 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89947.278846 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 89942.219556 # average overall miss latency
---
> system.cpu.l2cache.overall_misses::cpu.data 2245957 # number of overall misses
> system.cpu.l2cache.overall_misses::total 2246703 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 54783500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 125692113250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 125746896750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 76318094500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 76318094500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 54783500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 202010207750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 202064991250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 54783500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 202010207750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 202064991250 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 775 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 7708680 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 7709455 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 3782070 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 3782070 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 1893493 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 1893493 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 775 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 9602173 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 9602948 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 775 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 9602173 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 9602948 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.962581 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.184125 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.184203 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.436545 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.436545 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.962581 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.233901 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.233960 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.962581 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.233901 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.233960 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 73436.327078 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 88555.360260 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 88547.418048 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 92328.279871 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 92328.279871 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73436.327078 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89943.933811 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 89938.452590 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73436.327078 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89943.933811 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 89938.452590 # average overall miss latency
856,858c899,901
< system.cpu.l2cache.writebacks::writebacks 1100498 # number of writebacks
< system.cpu.l2cache.writebacks::total 1100498 # number of writebacks
< system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
---
> system.cpu.l2cache.writebacks::writebacks 1100579 # number of writebacks
> system.cpu.l2cache.writebacks::total 1100579 # number of writebacks
> system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits
860,861c903,904
< system.cpu.l2cache.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits
< system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
---
> system.cpu.l2cache.ReadReq_mshr_hits::total 9 # number of ReadReq MSHR hits
> system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits
863,864c906,907
< system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
< system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
---
> system.cpu.l2cache.demand_mshr_hits::total 9 # number of demand (read+write) MSHR hits
> system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits
866,910c909,953
< system.cpu.l2cache.overall_mshr_hits::total 8 # number of overall MSHR hits
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 745 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419490 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 1420235 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826499 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 826499 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 745 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 2245989 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 2246734 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 745 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 2245989 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 2246734 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 46285250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107925588000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107971873250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65906925250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65906925250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 46285250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173832513250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 173878798500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 46285250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173832513250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 173878798500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184152 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184230 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436505 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436505 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233916 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.233974 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.962532 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233916 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.233974 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62127.852349 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 76031.242207 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76023.949030 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79742.292792 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79742.292792 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62127.852349 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77396.867594 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77391.804504 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_mshr_hits::total 9 # number of overall MSHR hits
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 744 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1419355 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 1420099 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 826595 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 826595 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 744 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 2245950 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 2246694 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 744 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 2245950 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 2246694 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 45263000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 107889512500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 107934775500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 65933341000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 65933341000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45263000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 173822853500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 173868116500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45263000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 173822853500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 173868116500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.184124 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.184202 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.436545 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436545 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.233900 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.233959 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960000 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233900 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.233959 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60837.365591 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 76013.056987 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76005.106334 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79764.988900 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79764.988900 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60837.365591 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77393.910595 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77388.427841 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60837.365591 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77393.910595 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77388.427841 # average overall mshr miss latency
912,916c955,959
< system.cpu.dcache.tags.replacements 9597606 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4088.041920 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 656019476 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 9601702 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 68.323249 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.replacements 9598076 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4088.041397 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 656012597 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 9602172 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 68.319188 # Average number of references to valid blocks.
918c961
< system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041920 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4088.041397 # Average occupied blocks per requestor
922,924c965,967
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 642 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 2397 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 1056 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 635 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 2403 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 1057 # Occupied blocks per task id
927,934c970,977
< system.cpu.dcache.tags.tag_accesses 1355914350 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1355914350 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 489062653 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 489062653 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 166956698 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 166956698 # number of WriteReq hits
< system.cpu.dcache.LoadLockedReq_hits::cpu.data 64 # number of LoadLockedReq hits
< system.cpu.dcache.LoadLockedReq_hits::total 64 # number of LoadLockedReq hits
---
> system.cpu.dcache.tags.tag_accesses 1355899932 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1355899932 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 489056209 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 489056209 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 166956265 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 166956265 # number of WriteReq hits
> system.cpu.dcache.LoadLockedReq_hits::cpu.data 62 # number of LoadLockedReq hits
> system.cpu.dcache.LoadLockedReq_hits::total 62 # number of LoadLockedReq hits
937,944c980,987
< system.cpu.dcache.demand_hits::cpu.data 656019351 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 656019351 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 656019351 # number of overall hits
< system.cpu.dcache.overall_hits::total 656019351 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 11507496 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 11507496 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 5629349 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 5629349 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 656012474 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 656012474 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 656012474 # number of overall hits
> system.cpu.dcache.overall_hits::total 656012474 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 11506498 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 11506498 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 5629782 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 5629782 # number of WriteReq misses
947,962c990,1005
< system.cpu.dcache.demand_misses::cpu.data 17136845 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 17136845 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 17136845 # number of overall misses
< system.cpu.dcache.overall_misses::total 17136845 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 363702842488 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 363702842488 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 307744962906 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 307744962906 # number of WriteReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 224500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.LoadLockedReq_miss_latency::total 224500 # number of LoadLockedReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 671447805394 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 671447805394 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 671447805394 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 671447805394 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 500570149 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 500570149 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 17136280 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 17136280 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 17136280 # number of overall misses
> system.cpu.dcache.overall_misses::total 17136280 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 363307841237 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 363307841237 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 307618244019 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 307618244019 # number of WriteReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 233500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.LoadLockedReq_miss_latency::total 233500 # number of LoadLockedReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 670926085256 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 670926085256 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 670926085256 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 670926085256 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 500562707 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 500562707 # number of ReadReq accesses(hits+misses)
965,966c1008,1009
< system.cpu.dcache.LoadLockedReq_accesses::cpu.data 67 # number of LoadLockedReq accesses(hits+misses)
< system.cpu.dcache.LoadLockedReq_accesses::total 67 # number of LoadLockedReq accesses(hits+misses)
---
> system.cpu.dcache.LoadLockedReq_accesses::cpu.data 65 # number of LoadLockedReq accesses(hits+misses)
> system.cpu.dcache.LoadLockedReq_accesses::total 65 # number of LoadLockedReq accesses(hits+misses)
969,978c1012,1021
< system.cpu.dcache.demand_accesses::cpu.data 673156196 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 673156196 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 673156196 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 673156196 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022989 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.022989 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032618 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.032618 # miss rate for WriteReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.044776 # miss rate for LoadLockedReq accesses
< system.cpu.dcache.LoadLockedReq_miss_rate::total 0.044776 # miss rate for LoadLockedReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 673148754 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 673148754 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 673148754 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 673148754 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.022987 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.022987 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032620 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.032620 # miss rate for WriteReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046154 # miss rate for LoadLockedReq accesses
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046154 # miss rate for LoadLockedReq accesses
983,998c1026,1041
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31605.732688 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 31605.732688 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54667.948799 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 54667.948799 # average WriteReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 74833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 74833.333333 # average LoadLockedReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 39181.529937 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 39181.529937 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 39181.529937 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 24597243 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 3988018 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 1212289 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 65131 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.289917 # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets 61.230720 # average number of cycles each access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31574.145430 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 31574.145430 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54641.235490 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 54641.235490 # average WriteReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 77833.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 77833.333333 # average LoadLockedReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 39152.376435 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 39152.376435 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 39152.376435 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 24574937 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 3988182 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 1212192 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 65130 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.273139 # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets 61.234178 # average number of cycles each access was blocked
1001,1006c1044,1049
< system.cpu.dcache.writebacks::writebacks 3780837 # number of writebacks
< system.cpu.dcache.writebacks::total 3780837 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3799238 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 3799238 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3735904 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 3735904 # number of WriteReq MSHR hits
---
> system.cpu.dcache.writebacks::writebacks 3782070 # number of writebacks
> system.cpu.dcache.writebacks::total 3782070 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3797817 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 3797817 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3736290 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 3736290 # number of WriteReq MSHR hits
1009,1030c1052,1073
< system.cpu.dcache.demand_mshr_hits::cpu.data 7535142 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 7535142 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 7535142 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 7535142 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708258 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 7708258 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893445 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1893445 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 9601703 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 9601703 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 9601703 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9601703 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198213123757 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 198213123757 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89346986214 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 89346986214 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287560109971 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 287560109971 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287560109971 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 287560109971 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015399 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015399 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 7534107 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 7534107 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 7534107 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 7534107 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7708681 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 7708681 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1893492 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1893492 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 9602173 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 9602173 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9602173 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9602173 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 198180916008 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 198180916008 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 89373429339 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 89373429339 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 287554345347 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 287554345347 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 287554345347 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 287554345347 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015400 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015400 # mshr miss rate for ReadReq accesses
1033,1044c1076,1087
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.014264 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014264 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.014264 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25714.386280 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25714.386280 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47187.526553 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47187.526553 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29948.865318 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 29948.865318 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.014265 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014265 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.014265 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25708.797135 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25708.797135 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47200.320540 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47200.320540 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29946.799058 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 29946.799058 # average overall mshr miss latency