Cross Reference: /gem5/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt

stats.txt (10812:bacaefeb126a)	stats.txt (10827:7f5467f2f8b8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.771725 # Number of seconds simulated 4sim_ticks 771725169000 # Number of ticks simulated 5final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.771725 # Number of seconds simulated 4sim_ticks 771725169000 # Number of ticks simulated 5final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 109963 # Simulator instruction rate (inst/s) 8host_op_rate 118469 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 54942138 # Simulator tick rate (ticks/s) 10host_mem_usage 305172 # Number of bytes of host memory used 11host_seconds 14046.14 # Real time elapsed on the host	7host_inst_rate 137392 # Simulator instruction rate (inst/s) 8host_op_rate 148019 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 68646343 # Simulator tick rate (ticks/s) 10host_mem_usage 311812 # Number of bytes of host memory used 11host_seconds 11242.04 # Real time elapsed on the host
12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 238609216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 63286144 # Number of bytes read from this memory 19system.physmem.bytes_read::total 301961664 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 104822848 # Number of bytes written to this memory 23system.physmem.bytes_written::total 104822848 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 3728269 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 988846 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 4718151 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 1637857 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 1637857 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 85917 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 309189366 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 82006065 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 391281347 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 85917 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 85917 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 135829246 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 135829246 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 135829246 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 85917 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 309189366 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 82006065 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 527110594 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 4718151 # Number of read requests accepted 44system.physmem.writeReqs 1637857 # Number of write requests accepted 45system.physmem.readBursts 4718151 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 1637857 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 301519872 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 441792 # Total number of bytes read from write queue 49system.physmem.bytesWritten 104820544 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 301961664 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 104822848 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 6903 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 19 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 296668 # Per bank write bursts 56system.physmem.perBankRdBursts::1 294562 # Per bank write bursts 57system.physmem.perBankRdBursts::2 288307 # Per bank write bursts 58system.physmem.perBankRdBursts::3 292737 # Per bank write bursts 59system.physmem.perBankRdBursts::4 290232 # Per bank write bursts 60system.physmem.perBankRdBursts::5 289394 # Per bank write bursts 61system.physmem.perBankRdBursts::6 285167 # Per bank write bursts 62system.physmem.perBankRdBursts::7 280683 # Per bank write bursts 63system.physmem.perBankRdBursts::8 297292 # Per bank write bursts 64system.physmem.perBankRdBursts::9 302920 # Per bank write bursts 65system.physmem.perBankRdBursts::10 295430 # Per bank write bursts 66system.physmem.perBankRdBursts::11 301815 # Per bank write bursts 67system.physmem.perBankRdBursts::12 303322 # Per bank write bursts 68system.physmem.perBankRdBursts::13 302849 # Per bank write bursts 69system.physmem.perBankRdBursts::14 297025 # Per bank write bursts 70system.physmem.perBankRdBursts::15 292845 # Per bank write bursts 71system.physmem.perBankWrBursts::0 103942 # Per bank write bursts 72system.physmem.perBankWrBursts::1 102053 # Per bank write bursts 73system.physmem.perBankWrBursts::2 99317 # Per bank write bursts 74system.physmem.perBankWrBursts::3 99871 # Per bank write bursts 75system.physmem.perBankWrBursts::4 99169 # Per bank write bursts 76system.physmem.perBankWrBursts::5 98963 # Per bank write bursts 77system.physmem.perBankWrBursts::6 102735 # Per bank write bursts 78system.physmem.perBankWrBursts::7 104389 # Per bank write bursts 79system.physmem.perBankWrBursts::8 105226 # Per bank write bursts 80system.physmem.perBankWrBursts::9 104532 # Per bank write bursts 81system.physmem.perBankWrBursts::10 102159 # Per bank write bursts 82system.physmem.perBankWrBursts::11 102806 # Per bank write bursts 83system.physmem.perBankWrBursts::12 103028 # Per bank write bursts 84system.physmem.perBankWrBursts::13 102702 # Per bank write bursts 85system.physmem.perBankWrBursts::14 104263 # Per bank write bursts 86system.physmem.perBankWrBursts::15 102666 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 771725022000 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 4718151 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 1637857 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 2774626 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 1044189 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 331696 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 233512 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 153773 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 84990 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 39149 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 23715 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 18258 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 4255 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1688 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 411 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 22760 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 24545 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 59860 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 75448 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 85202 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 93103 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 99273 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 103279 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 105460 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 106422 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 106536 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 107239 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 108154 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 110632 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 113547 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 106733 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 103419 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 101598 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 2778 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 1044 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 449 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 193 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 4287400 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 94.775232 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 78.917076 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 101.448471 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 3413764 79.62% 79.62% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 675374 15.75% 95.38% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 96809 2.26% 97.63% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 35249 0.82% 98.46% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 22885 0.53% 98.99% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 12087 0.28% 99.27% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 7187 0.17% 99.44% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 5043 0.12% 99.56% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 19002 0.44% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 4287400 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 98767 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 47.700609 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 32.313411 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 98.282358 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-127 94950 96.14% 96.14% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::128-255 1367 1.38% 97.52% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::384-511 428 0.43% 98.73% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::512-639 356 0.36% 99.09% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::640-767 374 0.38% 99.47% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::768-895 247 0.25% 99.72% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::896-1023 145 0.15% 99.87% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::1024-1151 66 0.07% 99.94% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::1152-1279 31 0.03% 99.97% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::1280-1407 13 0.01% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::1408-1535 9 0.01% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1536-1663 1 0.00% 99.99% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::1920-2047 2 0.00% 99.99% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::2688-2815 1 0.00% 99.99% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::2944-3071 2 0.00% 100.00% # Reads before turning the bus around for writes 235system.physmem.rdPerTurnAround::3072-3199 2 0.00% 100.00% # Reads before turning the bus around for writes 236system.physmem.rdPerTurnAround::3200-3327 1 0.00% 100.00% # Reads before turning the bus around for writes 237system.physmem.rdPerTurnAround::3328-3455 1 0.00% 100.00% # Reads before turning the bus around for writes 238system.physmem.rdPerTurnAround::total 98767 # Reads before turning the bus around for writes 239system.physmem.wrPerTurnAround::samples 98767 # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::mean 16.582674 # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::gmean 16.549780 # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::stdev 1.086524 # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::16 73305 74.22% 74.22% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::17 1806 1.83% 76.05% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::18 18343 18.57% 94.62% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::19 3630 3.68% 98.30% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::20 937 0.95% 99.24% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::21 387 0.39% 99.64% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::22 162 0.16% 99.80% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::23 107 0.11% 99.91% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::24 60 0.06% 99.97% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::26 6 0.01% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::total 98767 # Writes before turning the bus around for reads 257system.physmem.totQLat 132285118194 # Total ticks spent queuing 258system.physmem.totMemAccLat 220621018194 # Total ticks spent from burst creation until serviced by the DRAM 259system.physmem.totBusLat 23556240000 # Total ticks spent in databus transfers 260system.physmem.avgQLat 28078.57 # Average queueing delay per DRAM burst 261system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 262system.physmem.avgMemAccLat 46828.57 # Average memory access latency per DRAM burst 263system.physmem.avgRdBW 390.71 # Average DRAM read bandwidth in MiByte/s 264system.physmem.avgWrBW 135.83 # Average achieved write bandwidth in MiByte/s 265system.physmem.avgRdBWSys 391.28 # Average system read bandwidth in MiByte/s 266system.physmem.avgWrBWSys 135.83 # Average system write bandwidth in MiByte/s 267system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 268system.physmem.busUtil 4.11 # Data bus utilization in percentage 269system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads 270system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes 271system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing 272system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing 273system.physmem.readRowHits 1709073 # Number of row buffer hits during reads 274system.physmem.writeRowHits 352585 # Number of row buffer hits during writes 275system.physmem.readRowHitRate 36.28 # Row buffer hit rate for reads 276system.physmem.writeRowHitRate 21.53 # Row buffer hit rate for writes 277system.physmem.avgGap 121416.62 # Average gap between requests 278system.physmem.pageHitRate 32.47 # Row buffer hit rate, read and write combined 279system.physmem_0.actEnergy 16073195040 # Energy for activate commands per rank (pJ) 280system.physmem_0.preEnergy 8770096500 # Energy for precharge commands per rank (pJ) 281system.physmem_0.readEnergy 18077007000 # Energy for read commands per rank (pJ) 282system.physmem_0.writeEnergy 5251294800 # Energy for write commands per rank (pJ) 283system.physmem_0.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ) 284system.physmem_0.actBackEnergy 410674128390 # Energy for active background per rank (pJ) 285system.physmem_0.preBackEnergy 102790850250 # Energy for precharge background per rank (pJ) 286system.physmem_0.totalEnergy 612041479260 # Total energy per rank (pJ) 287system.physmem_0.averagePower 793.088667 # Core power per rank (mW) 288system.physmem_0.memoryStateTime::IDLE 168453702129 # Time in different power states 289system.physmem_0.memoryStateTime::REF 25769380000 # Time in different power states 290system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 291system.physmem_0.memoryStateTime::ACT 577496605871 # Time in different power states 292system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 293system.physmem_1.actEnergy 16339027320 # Energy for activate commands per rank (pJ) 294system.physmem_1.preEnergy 8915143875 # Energy for precharge commands per rank (pJ) 295system.physmem_1.readEnergy 18669222000 # Energy for read commands per rank (pJ) 296system.physmem_1.writeEnergy 5361163200 # Energy for write commands per rank (pJ) 297system.physmem_1.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ) 298system.physmem_1.actBackEnergy 412008151545 # Energy for active background per rank (pJ) 299system.physmem_1.preBackEnergy 101620654500 # Energy for precharge background per rank (pJ) 300system.physmem_1.totalEnergy 613318269720 # Total energy per rank (pJ) 301system.physmem_1.averagePower 794.743144 # Core power per rank (mW) 302system.physmem_1.memoryStateTime::IDLE 166509885283 # Time in different power states 303system.physmem_1.memoryStateTime::REF 25769380000 # Time in different power states 304system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 305system.physmem_1.memoryStateTime::ACT 579440435717 # Time in different power states 306system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 307system.cpu.branchPred.lookups 286277860 # Number of BP lookups 308system.cpu.branchPred.condPredicted 223409255 # Number of conditional branches predicted 309system.cpu.branchPred.condIncorrect 14633591 # Number of conditional branches incorrect 310system.cpu.branchPred.BTBLookups 157407621 # Number of BTB lookups 311system.cpu.branchPred.BTBHits 150346120 # Number of BTB hits 312system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 313system.cpu.branchPred.BTBHitPct 95.513876 # BTB Hit Percentage 314system.cpu.branchPred.usedRAS 16641206 # Number of times the RAS was used to get a target. 315system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. 316system.cpu_clk_domain.clock 500 # Clock period in ticks 317system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 324system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 326system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 327system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 328system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 329system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 330system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 331system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 332system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 333system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 334system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 335system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 336system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 337system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 338system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 339system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 340system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 341system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 342system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 343system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 344system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 345system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 346system.cpu.dtb.walker.walks 0 # Table walker walks requested 347system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 353system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 354system.cpu.dtb.inst_hits 0 # ITB inst hits 355system.cpu.dtb.inst_misses 0 # ITB inst misses 356system.cpu.dtb.read_hits 0 # DTB read hits 357system.cpu.dtb.read_misses 0 # DTB read misses 358system.cpu.dtb.write_hits 0 # DTB write hits 359system.cpu.dtb.write_misses 0 # DTB write misses 360system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 361system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 362system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 363system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 364system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 365system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 366system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 367system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.dtb.read_accesses 0 # DTB read accesses 370system.cpu.dtb.write_accesses 0 # DTB write accesses 371system.cpu.dtb.inst_accesses 0 # ITB inst accesses 372system.cpu.dtb.hits 0 # DTB hits 373system.cpu.dtb.misses 0 # DTB misses 374system.cpu.dtb.accesses 0 # DTB accesses 375system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 382system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 383system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 384system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 385system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 386system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 387system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 388system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 389system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 390system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 391system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 392system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 393system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 394system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 395system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 396system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 397system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 398system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 399system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 400system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 401system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 402system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 403system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 404system.cpu.itb.walker.walks 0 # Table walker walks requested 405system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 409system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 410system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 411system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 412system.cpu.itb.inst_hits 0 # ITB inst hits 413system.cpu.itb.inst_misses 0 # ITB inst misses 414system.cpu.itb.read_hits 0 # DTB read hits 415system.cpu.itb.read_misses 0 # DTB read misses 416system.cpu.itb.write_hits 0 # DTB write hits 417system.cpu.itb.write_misses 0 # DTB write misses 418system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 419system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 420system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 421system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 422system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 423system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 424system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 425system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 426system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 427system.cpu.itb.read_accesses 0 # DTB read accesses 428system.cpu.itb.write_accesses 0 # DTB write accesses 429system.cpu.itb.inst_accesses 0 # ITB inst accesses 430system.cpu.itb.hits 0 # DTB hits 431system.cpu.itb.misses 0 # DTB misses 432system.cpu.itb.accesses 0 # DTB accesses 433system.cpu.workload.num_syscalls 46 # Number of system calls 434system.cpu.numCycles 1543450339 # number of cpu cycles simulated 435system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 436system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 437system.cpu.fetch.icacheStallCycles 13927699 # Number of cycles fetch is stalled on an Icache miss 438system.cpu.fetch.Insts 2067517377 # Number of instructions fetch has processed 439system.cpu.fetch.Branches 286277860 # Number of branches that fetch encountered 440system.cpu.fetch.predictedBranches 166987326 # Number of branches that fetch has predicted taken 441system.cpu.fetch.Cycles 1514795150 # Number of cycles fetch has run and was not squashing or blocked 442system.cpu.fetch.SquashCycles 29291799 # Number of cycles fetch has spent squashing 443system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 444system.cpu.fetch.IcacheWaitRetryStallCycles 907 # Number of stall cycles due to full MSHR 445system.cpu.fetch.CacheLines 656942032 # Number of cache lines fetched 446system.cpu.fetch.IcacheSquashes 957 # Number of outstanding Icache misses that were squashed 447system.cpu.fetch.rateDist::samples 1543369835 # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::mean 1.435149 # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::stdev 1.229340 # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::0 460957271 29.87% 29.87% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::1 465455811 30.16% 60.03% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::2 101360614 6.57% 66.59% # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::3 515596139 33.41% 100.00% # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 457system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 458system.cpu.fetch.rateDist::total 1543369835 # Number of instructions fetched each cycle (Total) 459system.cpu.fetch.branchRate 0.185479 # Number of branch fetches per cycle 460system.cpu.fetch.rate 1.339543 # Number of inst fetches per cycle 461system.cpu.decode.IdleCycles 74619350 # Number of cycles decode is idle 462system.cpu.decode.BlockedCycles 545977788 # Number of cycles decode is blocked 463system.cpu.decode.RunCycles 850086533 # Number of cycles decode is running 464system.cpu.decode.UnblockCycles 58040967 # Number of cycles decode is unblocking 465system.cpu.decode.SquashCycles 14645197 # Number of cycles decode is squashing 466system.cpu.decode.BranchResolved 42200501 # Number of times decode resolved a branch 467system.cpu.decode.BranchMispred 754 # Number of times decode detected a branch misprediction 468system.cpu.decode.DecodedInsts 2037190940 # Number of instructions handled by decode 469system.cpu.decode.SquashedInsts 52475133 # Number of squashed instructions handled by decode 470system.cpu.rename.SquashCycles 14645197 # Number of cycles rename is squashing 471system.cpu.rename.IdleCycles 139685845 # Number of cycles rename is idle 472system.cpu.rename.BlockCycles 464851768 # Number of cycles rename is blocking 473system.cpu.rename.serializeStallCycles 13523 # count of cycles rename stalled for serializing inst 474system.cpu.rename.RunCycles 837895691 # Number of cycles rename is running 475system.cpu.rename.UnblockCycles 86277811 # Number of cycles rename is unblocking 476system.cpu.rename.RenamedInsts 1976364426 # Number of instructions processed by rename 477system.cpu.rename.SquashedInsts 26735694 # Number of squashed instructions processed by rename 478system.cpu.rename.ROBFullEvents 45105241 # Number of times rename has blocked due to ROB full 479system.cpu.rename.IQFullEvents 125505 # Number of times rename has blocked due to IQ full 480system.cpu.rename.LQFullEvents 1481556 # Number of times rename has blocked due to LQ full 481system.cpu.rename.SQFullEvents 25500508 # Number of times rename has blocked due to SQ full 482system.cpu.rename.RenamedOperands 1985835865 # Number of destination operands rename has renamed 483system.cpu.rename.RenameLookups 9128071192 # Number of register rename lookups that rename has made 484system.cpu.rename.int_rename_lookups 2432849079 # Number of integer rename lookups 485system.cpu.rename.fp_rename_lookups 136 # Number of floating rename lookups 486system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed 487system.cpu.rename.UndoneMaps 310936920 # Number of HB maps that are undone due to squashing 488system.cpu.rename.serializingInsts 149 # count of serializing insts renamed 489system.cpu.rename.tempSerializingInsts 140 # count of temporary serializing insts renamed 490system.cpu.rename.skidInsts 111342876 # count of insts added to the skid buffer 491system.cpu.memDep0.insertedLoads 542549398 # Number of loads inserted to the mem dependence unit. 492system.cpu.memDep0.insertedStores 199301403 # Number of stores inserted to the mem dependence unit. 493system.cpu.memDep0.conflictingLoads 26926926 # Number of conflicting loads. 494system.cpu.memDep0.conflictingStores 29153523 # Number of conflicting stores. 495system.cpu.iq.iqInstsAdded 1947926711 # Number of instructions added to the IQ (excludes non-spec) 496system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ 497system.cpu.iq.iqInstsIssued 1857446823 # Number of instructions issued 498system.cpu.iq.iqSquashedInstsIssued 13498178 # Number of squashed instructions issued 499system.cpu.iq.iqSquashedInstsExamined 283894503 # Number of squashed instructions iterated over during squash; mainly for profiling 500system.cpu.iq.iqSquashedOperandsExamined 646939215 # Number of squashed operands that are examined and possibly removed from graph 501system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed 502system.cpu.iq.issued_per_cycle::samples 1543369835 # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::mean 1.203501 # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::stdev 1.151095 # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::0 590630846 38.27% 38.27% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::1 325771475 21.11% 59.38% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::2 378267234 24.51% 83.89% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::3 219666416 14.23% 98.12% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::4 29027688 1.88% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 517system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 518system.cpu.iq.issued_per_cycle::total 1543369835 # Number of insts issued each cycle 519system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 520system.cpu.iq.fu_full::IntAlu 166059149 40.99% 40.99% # attempts to use FU when none available 521system.cpu.iq.fu_full::IntMult 1996 0.00% 40.99% # attempts to use FU when none available 522system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available 524system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available 525system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available 526system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available 527system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available 528system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available 546system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available 547system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available 548system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 549system.cpu.iq.fu_full::MemRead 191393147 47.24% 88.23% # attempts to use FU when none available 550system.cpu.iq.fu_full::MemWrite 47682914 11.77% 100.00% # attempts to use FU when none available 551system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 552system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 553system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 554system.cpu.iq.FU_type_0::IntAlu 1138268714 61.28% 61.28% # Type of FU issued 555system.cpu.iq.FU_type_0::IntMult 801071 0.04% 61.32% # Type of FU issued 556system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 560system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 561system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 562system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 582system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued 583system.cpu.iq.FU_type_0::MemRead 532058987 28.64% 89.97% # Type of FU issued 584system.cpu.iq.FU_type_0::MemWrite 186318001 10.03% 100.00% # Type of FU issued 585system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 586system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 587system.cpu.iq.FU_type_0::total 1857446823 # Type of FU issued 588system.cpu.iq.rate 1.203438 # Inst issue rate 589system.cpu.iq.fu_busy_cnt 405137206 # FU busy when requested 590system.cpu.iq.fu_busy_rate 0.218115 # FU busy rate (busy events/executed inst) 591system.cpu.iq.int_inst_queue_reads 5676898637 # Number of integer instruction queue reads 592system.cpu.iq.int_inst_queue_writes 2231834122 # Number of integer instruction queue writes 593system.cpu.iq.int_inst_queue_wakeup_accesses 1805736851 # Number of integer instruction queue wakeup accesses 594system.cpu.iq.fp_inst_queue_reads 228 # Number of floating instruction queue reads 595system.cpu.iq.fp_inst_queue_writes 232 # Number of floating instruction queue writes 596system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses 597system.cpu.iq.int_alu_accesses 2262583902 # Number of integer alu accesses 598system.cpu.iq.fp_alu_accesses 127 # Number of floating point alu accesses 599system.cpu.iew.lsq.thread0.forwLoads 17817639 # Number of loads that had data forwarded from stores 600system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 601system.cpu.iew.lsq.thread0.squashedLoads 84243064 # Number of loads squashed 602system.cpu.iew.lsq.thread0.ignoredResponses 66651 # Number of memory responses ignored because the instruction is squashed 603system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations 604system.cpu.iew.lsq.thread0.squashedStores 24454358 # Number of stores squashed 605system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 606system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 607system.cpu.iew.lsq.thread0.rescheduledLoads 4525889 # Number of loads that were rescheduled 608system.cpu.iew.lsq.thread0.cacheBlocked 4805394 # Number of times an access to memory failed due to the cache being blocked 609system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 610system.cpu.iew.iewSquashCycles 14645197 # Number of cycles IEW is squashing 611system.cpu.iew.iewBlockCycles 25323327 # Number of cycles IEW is blocking 612system.cpu.iew.iewUnblockCycles 1332663 # Number of cycles IEW is unblocking 613system.cpu.iew.iewDispatchedInsts 1947926995 # Number of instructions dispatched to IQ 614system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 615system.cpu.iew.iewDispLoadInsts 542549398 # Number of dispatched load instructions 616system.cpu.iew.iewDispStoreInsts 199301403 # Number of dispatched store instructions 617system.cpu.iew.iewDispNonSpecInsts 146 # Number of dispatched non-speculative instructions 618system.cpu.iew.iewIQFullEvents 158839 # Number of times the IQ has become full, causing a stall 619system.cpu.iew.iewLSQFullEvents 1172731 # Number of times the LSQ has become full, causing a stall 620system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations 621system.cpu.iew.predictedTakenIncorrect 7701738 # Number of branches that were predicted taken incorrectly 622system.cpu.iew.predictedNotTakenIncorrect 8706499 # Number of branches that were predicted not taken incorrectly 623system.cpu.iew.branchMispredicts 16408237 # Number of branch mispredicts detected at execute 624system.cpu.iew.iewExecutedInsts 1827783249 # Number of executed instructions 625system.cpu.iew.iewExecLoadInsts 516881888 # Number of load instructions executed 626system.cpu.iew.iewExecSquashedInsts 29663574 # Number of squashed instructions skipped in execute 627system.cpu.iew.exec_swp 0 # number of swp insts executed 628system.cpu.iew.exec_nop 76 # number of nop insts executed 629system.cpu.iew.exec_refs 698636146 # number of memory reference insts executed 630system.cpu.iew.exec_branches 229555717 # Number of branches executed 631system.cpu.iew.exec_stores 181754258 # Number of stores executed 632system.cpu.iew.exec_rate 1.184219 # Inst execution rate 633system.cpu.iew.wb_sent 1808767141 # cumulative count of insts sent to commit 634system.cpu.iew.wb_count 1805736919 # cumulative count of insts written-back 635system.cpu.iew.wb_producers 1169322951 # num instructions producing a value 636system.cpu.iew.wb_consumers 1689713401 # num instructions consuming a value 637system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 638system.cpu.iew.wb_rate 1.169935 # insts written-back per cycle 639system.cpu.iew.wb_fanout 0.692024 # average fanout of values written-back 640system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 641system.cpu.commit.commitSquashedInsts 258002520 # The number of squashed insts skipped by commit 642system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards 643system.cpu.commit.branchMispredicts 14632889 # The number of times a branch was mispredicted 644system.cpu.commit.committed_per_cycle::samples 1503882923 # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::mean 1.106491 # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::stdev 2.024391 # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::0 923604765 61.41% 61.41% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::1 250635322 16.67% 78.08% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::2 110056363 7.32% 85.40% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::3 55280526 3.68% 89.07% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::4 29292132 1.95% 91.02% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::5 34092515 2.27% 93.29% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::6 24716046 1.64% 94.93% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::7 18126603 1.21% 96.14% # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::8 58078651 3.86% 100.00% # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 658system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 659system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 660system.cpu.commit.committed_per_cycle::total 1503882923 # Number of insts commited each cycle 661system.cpu.commit.committedInsts 1544563042 # Number of instructions committed 662system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed 663system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 664system.cpu.commit.refs 633153379 # Number of memory references committed 665system.cpu.commit.loads 458306334 # Number of loads committed 666system.cpu.commit.membars 62 # Number of memory barriers committed 667system.cpu.commit.branches 213462427 # Number of branches committed 668system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 669system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. 670system.cpu.commit.function_calls 13665177 # Number of function calls committed. 671system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 672system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction 673system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 674system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 676system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 677system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 678system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction 679system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction 680system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction 696system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction 697system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction 698system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 699system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 700system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 701system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 702system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction 703system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 704system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 705system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction 706system.cpu.commit.bw_lim_events 58078651 # number cycles where commit BW limit reached 707system.cpu.rob.rob_reads 3367838627 # The number of ROB reads 708system.cpu.rob.rob_writes 3883562090 # The number of ROB writes 709system.cpu.timesIdled 851 # Number of times that the entire CPU went into an idle state and unscheduled itself 710system.cpu.idleCycles 80504 # Total number of cycles that the CPU has spent unscheduled due to idling 711system.cpu.committedInsts 1544563024 # Number of Instructions Simulated 712system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated 713system.cpu.cpi 0.999280 # CPI: Cycles Per Instruction 714system.cpu.cpi_total 0.999280 # CPI: Total CPI of All Threads 715system.cpu.ipc 1.000721 # IPC: Instructions Per Cycle 716system.cpu.ipc_total 1.000721 # IPC: Total IPC of All Threads 717system.cpu.int_regfile_reads 2175739809 # number of integer regfile reads 718system.cpu.int_regfile_writes 1261583749 # number of integer regfile writes 719system.cpu.fp_regfile_reads 38 # number of floating regfile reads 720system.cpu.fp_regfile_writes 50 # number of floating regfile writes 721system.cpu.cc_regfile_reads 6965641029 # number of cc regfile reads 722system.cpu.cc_regfile_writes 551880821 # number of cc regfile writes 723system.cpu.misc_regfile_reads 675853491 # number of misc regfile reads 724system.cpu.misc_regfile_writes 124 # number of misc regfile writes 725system.cpu.dcache.tags.replacements 17005885 # number of replacements 726system.cpu.dcache.tags.tagsinuse 511.964949 # Cycle average of tags in use 727system.cpu.dcache.tags.total_refs 638186886 # Total number of references to valid blocks. 728system.cpu.dcache.tags.sampled_refs 17006397 # Sample count of references to valid blocks. 729system.cpu.dcache.tags.avg_refs 37.526284 # Average number of references to valid blocks. 730system.cpu.dcache.tags.warmup_cycle 78340000 # Cycle when the warmup percentage was hit. 731system.cpu.dcache.tags.occ_blocks::cpu.data 511.964949 # Average occupied blocks per requestor 732system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy 733system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy 734system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 735system.cpu.dcache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id 736system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 737system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 738system.cpu.dcache.tags.tag_accesses 1335687679 # Number of tag accesses 739system.cpu.dcache.tags.data_accesses 1335687679 # Number of data accesses 740system.cpu.dcache.ReadReq_hits::cpu.data 469400845 # number of ReadReq hits 741system.cpu.dcache.ReadReq_hits::total 469400845 # number of ReadReq hits 742system.cpu.dcache.WriteReq_hits::cpu.data 168785923 # number of WriteReq hits 743system.cpu.dcache.WriteReq_hits::total 168785923 # number of WriteReq hits 744system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 745system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 746system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 747system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 748system.cpu.dcache.demand_hits::cpu.data 638186768 # number of demand (read+write) hits 749system.cpu.dcache.demand_hits::total 638186768 # number of demand (read+write) hits 750system.cpu.dcache.overall_hits::cpu.data 638186768 # number of overall hits 751system.cpu.dcache.overall_hits::total 638186768 # number of overall hits 752system.cpu.dcache.ReadReq_misses::cpu.data 17353625 # number of ReadReq misses 753system.cpu.dcache.ReadReq_misses::total 17353625 # number of ReadReq misses 754system.cpu.dcache.WriteReq_misses::cpu.data 3800124 # number of WriteReq misses 755system.cpu.dcache.WriteReq_misses::total 3800124 # number of WriteReq misses 756system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 757system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 758system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 759system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses 760system.cpu.dcache.demand_misses::cpu.data 21153749 # number of demand (read+write) misses 761system.cpu.dcache.demand_misses::total 21153749 # number of demand (read+write) misses 762system.cpu.dcache.overall_misses::cpu.data 21153751 # number of overall misses 763system.cpu.dcache.overall_misses::total 21153751 # number of overall misses 764system.cpu.dcache.ReadReq_miss_latency::cpu.data 417050356298 # number of ReadReq miss cycles 765system.cpu.dcache.ReadReq_miss_latency::total 417050356298 # number of ReadReq miss cycles 766system.cpu.dcache.WriteReq_miss_latency::cpu.data 149886013526 # number of WriteReq miss cycles 767system.cpu.dcache.WriteReq_miss_latency::total 149886013526 # number of WriteReq miss cycles 768system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204500 # number of LoadLockedReq miss cycles 769system.cpu.dcache.LoadLockedReq_miss_latency::total 204500 # number of LoadLockedReq miss cycles 770system.cpu.dcache.demand_miss_latency::cpu.data 566936369824 # number of demand (read+write) miss cycles 771system.cpu.dcache.demand_miss_latency::total 566936369824 # number of demand (read+write) miss cycles 772system.cpu.dcache.overall_miss_latency::cpu.data 566936369824 # number of overall miss cycles 773system.cpu.dcache.overall_miss_latency::total 566936369824 # number of overall miss cycles 774system.cpu.dcache.ReadReq_accesses::cpu.data 486754470 # number of ReadReq accesses(hits+misses) 775system.cpu.dcache.ReadReq_accesses::total 486754470 # number of ReadReq accesses(hits+misses) 776system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 777system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 778system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) 779system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) 780system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 781system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 782system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 783system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 784system.cpu.dcache.demand_accesses::cpu.data 659340517 # number of demand (read+write) accesses 785system.cpu.dcache.demand_accesses::total 659340517 # number of demand (read+write) accesses 786system.cpu.dcache.overall_accesses::cpu.data 659340519 # number of overall (read+write) accesses 787system.cpu.dcache.overall_accesses::total 659340519 # number of overall (read+write) accesses 788system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035652 # miss rate for ReadReq accesses 789system.cpu.dcache.ReadReq_miss_rate::total 0.035652 # miss rate for ReadReq accesses 790system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022019 # miss rate for WriteReq accesses 791system.cpu.dcache.WriteReq_miss_rate::total 0.022019 # miss rate for WriteReq accesses 792system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 793system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 794system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses 795system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses 796system.cpu.dcache.demand_miss_rate::cpu.data 0.032083 # miss rate for demand accesses 797system.cpu.dcache.demand_miss_rate::total 0.032083 # miss rate for demand accesses 798system.cpu.dcache.overall_miss_rate::cpu.data 0.032083 # miss rate for overall accesses 799system.cpu.dcache.overall_miss_rate::total 0.032083 # miss rate for overall accesses 800system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24032.463321 # average ReadReq miss latency 801system.cpu.dcache.ReadReq_avg_miss_latency::total 24032.463321 # average ReadReq miss latency 802system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39442.400702 # average WriteReq miss latency 803system.cpu.dcache.WriteReq_avg_miss_latency::total 39442.400702 # average WriteReq miss latency 804system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51125 # average LoadLockedReq miss latency 805system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51125 # average LoadLockedReq miss latency 806system.cpu.dcache.demand_avg_miss_latency::cpu.data 26800.751480 # average overall miss latency 807system.cpu.dcache.demand_avg_miss_latency::total 26800.751480 # average overall miss latency 808system.cpu.dcache.overall_avg_miss_latency::cpu.data 26800.748946 # average overall miss latency 809system.cpu.dcache.overall_avg_miss_latency::total 26800.748946 # average overall miss latency 810system.cpu.dcache.blocked_cycles::no_mshrs 20736521 # number of cycles access was blocked 811system.cpu.dcache.blocked_cycles::no_targets 3309459 # number of cycles access was blocked 812system.cpu.dcache.blocked::no_mshrs 945396 # number of cycles access was blocked 813system.cpu.dcache.blocked::no_targets 67047 # number of cycles access was blocked 814system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.934217 # average number of cycles each access was blocked 815system.cpu.dcache.avg_blocked_cycles::no_targets 49.360285 # average number of cycles each access was blocked 816system.cpu.dcache.fast_writes 0 # number of fast writes performed 817system.cpu.dcache.cache_copies 0 # number of cache copies performed 818system.cpu.dcache.writebacks::writebacks 4830628 # number of writebacks 819system.cpu.dcache.writebacks::total 4830628 # number of writebacks 820system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3084713 # number of ReadReq MSHR hits 821system.cpu.dcache.ReadReq_mshr_hits::total 3084713 # number of ReadReq MSHR hits 822system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1062640 # number of WriteReq MSHR hits 823system.cpu.dcache.WriteReq_mshr_hits::total 1062640 # number of WriteReq MSHR hits 824system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 825system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits 826system.cpu.dcache.demand_mshr_hits::cpu.data 4147353 # number of demand (read+write) MSHR hits 827system.cpu.dcache.demand_mshr_hits::total 4147353 # number of demand (read+write) MSHR hits 828system.cpu.dcache.overall_mshr_hits::cpu.data 4147353 # number of overall MSHR hits 829system.cpu.dcache.overall_mshr_hits::total 4147353 # number of overall MSHR hits 830system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268912 # number of ReadReq MSHR misses 831system.cpu.dcache.ReadReq_mshr_misses::total 14268912 # number of ReadReq MSHR misses 832system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737484 # number of WriteReq MSHR misses 833system.cpu.dcache.WriteReq_mshr_misses::total 2737484 # number of WriteReq MSHR misses 834system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 835system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 836system.cpu.dcache.demand_mshr_misses::cpu.data 17006396 # number of demand (read+write) MSHR misses 837system.cpu.dcache.demand_mshr_misses::total 17006396 # number of demand (read+write) MSHR misses 838system.cpu.dcache.overall_mshr_misses::cpu.data 17006397 # number of overall MSHR misses 839system.cpu.dcache.overall_mshr_misses::total 17006397 # number of overall MSHR misses 840system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 328919129806 # number of ReadReq MSHR miss cycles 841system.cpu.dcache.ReadReq_mshr_miss_latency::total 328919129806 # number of ReadReq MSHR miss cycles 842system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115124697729 # number of WriteReq MSHR miss cycles 843system.cpu.dcache.WriteReq_mshr_miss_latency::total 115124697729 # number of WriteReq MSHR miss cycles 844system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles 845system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles 846system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444043827535 # number of demand (read+write) MSHR miss cycles 847system.cpu.dcache.demand_mshr_miss_latency::total 444043827535 # number of demand (read+write) MSHR miss cycles 848system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444043895285 # number of overall MSHR miss cycles 849system.cpu.dcache.overall_mshr_miss_latency::total 444043895285 # number of overall MSHR miss cycles 850system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses 851system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses 852system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses 853system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses 854system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses 855system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses 856system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses 857system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses 858system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses 859system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses 860system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23051.451281 # average ReadReq mshr miss latency 861system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23051.451281 # average ReadReq mshr miss latency 862system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42054.929902 # average WriteReq mshr miss latency 863system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42054.929902 # average WriteReq mshr miss latency 864system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency 865system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.401495 # average overall mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.401495 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.403943 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.403943 # average overall mshr miss latency 870system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 871system.cpu.icache.tags.replacements 589 # number of replacements 872system.cpu.icache.tags.tagsinuse 446.078018 # Cycle average of tags in use 873system.cpu.icache.tags.total_refs 656940406 # Total number of references to valid blocks. 874system.cpu.icache.tags.sampled_refs 1077 # Sample count of references to valid blocks. 875system.cpu.icache.tags.avg_refs 609972.521820 # Average number of references to valid blocks. 876system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 877system.cpu.icache.tags.occ_blocks::cpu.inst 446.078018 # Average occupied blocks per requestor 878system.cpu.icache.tags.occ_percent::cpu.inst 0.871246 # Average percentage of cache occupancy 879system.cpu.icache.tags.occ_percent::total 0.871246 # Average percentage of cache occupancy 880system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id 881system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 882system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id 883system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id 884system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id 885system.cpu.icache.tags.tag_accesses 1313885139 # Number of tag accesses 886system.cpu.icache.tags.data_accesses 1313885139 # Number of data accesses 887system.cpu.icache.ReadReq_hits::cpu.inst 656940406 # number of ReadReq hits 888system.cpu.icache.ReadReq_hits::total 656940406 # number of ReadReq hits 889system.cpu.icache.demand_hits::cpu.inst 656940406 # number of demand (read+write) hits 890system.cpu.icache.demand_hits::total 656940406 # number of demand (read+write) hits 891system.cpu.icache.overall_hits::cpu.inst 656940406 # number of overall hits 892system.cpu.icache.overall_hits::total 656940406 # number of overall hits 893system.cpu.icache.ReadReq_misses::cpu.inst 1625 # number of ReadReq misses 894system.cpu.icache.ReadReq_misses::total 1625 # number of ReadReq misses 895system.cpu.icache.demand_misses::cpu.inst 1625 # number of demand (read+write) misses 896system.cpu.icache.demand_misses::total 1625 # number of demand (read+write) misses 897system.cpu.icache.overall_misses::cpu.inst 1625 # number of overall misses 898system.cpu.icache.overall_misses::total 1625 # number of overall misses 899system.cpu.icache.ReadReq_miss_latency::cpu.inst 105016775 # number of ReadReq miss cycles 900system.cpu.icache.ReadReq_miss_latency::total 105016775 # number of ReadReq miss cycles 901system.cpu.icache.demand_miss_latency::cpu.inst 105016775 # number of demand (read+write) miss cycles 902system.cpu.icache.demand_miss_latency::total 105016775 # number of demand (read+write) miss cycles 903system.cpu.icache.overall_miss_latency::cpu.inst 105016775 # number of overall miss cycles 904system.cpu.icache.overall_miss_latency::total 105016775 # number of overall miss cycles 905system.cpu.icache.ReadReq_accesses::cpu.inst 656942031 # number of ReadReq accesses(hits+misses) 906system.cpu.icache.ReadReq_accesses::total 656942031 # number of ReadReq accesses(hits+misses) 907system.cpu.icache.demand_accesses::cpu.inst 656942031 # number of demand (read+write) accesses 908system.cpu.icache.demand_accesses::total 656942031 # number of demand (read+write) accesses 909system.cpu.icache.overall_accesses::cpu.inst 656942031 # number of overall (read+write) accesses 910system.cpu.icache.overall_accesses::total 656942031 # number of overall (read+write) accesses 911system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 912system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 913system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 914system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 915system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 916system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 917system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64625.707692 # average ReadReq miss latency 918system.cpu.icache.ReadReq_avg_miss_latency::total 64625.707692 # average ReadReq miss latency 919system.cpu.icache.demand_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency 920system.cpu.icache.demand_avg_miss_latency::total 64625.707692 # average overall miss latency 921system.cpu.icache.overall_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency 922system.cpu.icache.overall_avg_miss_latency::total 64625.707692 # average overall miss latency 923system.cpu.icache.blocked_cycles::no_mshrs 17596 # number of cycles access was blocked 924system.cpu.icache.blocked_cycles::no_targets 547 # number of cycles access was blocked 925system.cpu.icache.blocked::no_mshrs 191 # number of cycles access was blocked 926system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked 927system.cpu.icache.avg_blocked_cycles::no_mshrs 92.125654 # average number of cycles each access was blocked 928system.cpu.icache.avg_blocked_cycles::no_targets 60.777778 # average number of cycles each access was blocked 929system.cpu.icache.fast_writes 0 # number of fast writes performed 930system.cpu.icache.cache_copies 0 # number of cache copies performed 931system.cpu.icache.ReadReq_mshr_hits::cpu.inst 548 # number of ReadReq MSHR hits 932system.cpu.icache.ReadReq_mshr_hits::total 548 # number of ReadReq MSHR hits 933system.cpu.icache.demand_mshr_hits::cpu.inst 548 # number of demand (read+write) MSHR hits 934system.cpu.icache.demand_mshr_hits::total 548 # number of demand (read+write) MSHR hits 935system.cpu.icache.overall_mshr_hits::cpu.inst 548 # number of overall MSHR hits 936system.cpu.icache.overall_mshr_hits::total 548 # number of overall MSHR hits 937system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses 938system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses 939system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses 940system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses 941system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses 942system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses 943system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76192959 # number of ReadReq MSHR miss cycles 944system.cpu.icache.ReadReq_mshr_miss_latency::total 76192959 # number of ReadReq MSHR miss cycles 945system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76192959 # number of demand (read+write) MSHR miss cycles 946system.cpu.icache.demand_mshr_miss_latency::total 76192959 # number of demand (read+write) MSHR miss cycles 947system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76192959 # number of overall MSHR miss cycles 948system.cpu.icache.overall_mshr_miss_latency::total 76192959 # number of overall MSHR miss cycles 949system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 950system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 951system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 952system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 953system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 954system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 955system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70745.551532 # average ReadReq mshr miss latency 956system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70745.551532 # average ReadReq mshr miss latency 957system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70745.551532 # average overall mshr miss latency 958system.cpu.icache.demand_avg_mshr_miss_latency::total 70745.551532 # average overall mshr miss latency 959system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70745.551532 # average overall mshr miss latency 960system.cpu.icache.overall_avg_mshr_miss_latency::total 70745.551532 # average overall mshr miss latency 961system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 962system.cpu.l2cache.prefetcher.num_hwpf_issued 10938258 # number of hwpf issued 963system.cpu.l2cache.prefetcher.pfIdentified 11626730 # number of prefetch candidates identified 964system.cpu.l2cache.prefetcher.pfBufferHit 430783 # number of redundant prefetches already in prefetch queue 965system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 966system.cpu.l2cache.prefetcher.pfRemovedFull 3 # number of prefetches dropped due to prefetch queue size 967system.cpu.l2cache.prefetcher.pfSpanPage 4654278 # number of prefetches not generated due to page crossing 968system.cpu.l2cache.tags.replacements 4710195 # number of replacements 969system.cpu.l2cache.tags.tagsinuse 16130.419578 # Cycle average of tags in use 970system.cpu.l2cache.tags.total_refs 15323813 # Total number of references to valid blocks. 971system.cpu.l2cache.tags.sampled_refs 4726123 # Sample count of references to valid blocks. 972system.cpu.l2cache.tags.avg_refs 3.242364 # Average number of references to valid blocks. 973system.cpu.l2cache.tags.warmup_cycle 29466216500 # Cycle when the warmup percentage was hit. 974system.cpu.l2cache.tags.occ_blocks::writebacks 5234.041152 # Average occupied blocks per requestor 975system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.862974 # Average occupied blocks per requestor 976system.cpu.l2cache.tags.occ_blocks::cpu.data 7585.301260 # Average occupied blocks per requestor 977system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3292.214193 # Average occupied blocks per requestor 978system.cpu.l2cache.tags.occ_percent::writebacks 0.319461 # Average percentage of cache occupancy 979system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001151 # Average percentage of cache occupancy 980system.cpu.l2cache.tags.occ_percent::cpu.data 0.462970 # Average percentage of cache occupancy 981system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.200941 # Average percentage of cache occupancy 982system.cpu.l2cache.tags.occ_percent::total 0.984523 # Average percentage of cache occupancy 983system.cpu.l2cache.tags.occ_task_id_blocks::1022 739 # Occupied blocks per task id 984system.cpu.l2cache.tags.occ_task_id_blocks::1024 15189 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id 986system.cpu.l2cache.tags.age_task_id_blocks_1022::1 553 # Occupied blocks per task id 987system.cpu.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id 988system.cpu.l2cache.tags.age_task_id_blocks_1024::0 505 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2391 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1230 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9214 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1849 # Occupied blocks per task id 993system.cpu.l2cache.tags.occ_task_id_percent::1022 0.045105 # Percentage of cache occupancy per task id 994system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927063 # Percentage of cache occupancy per task id 995system.cpu.l2cache.tags.tag_accesses 356873283 # Number of tag accesses 996system.cpu.l2cache.tags.data_accesses 356873283 # Number of data accesses 997system.cpu.l2cache.ReadReq_hits::cpu.inst 41 # number of ReadReq hits 998system.cpu.l2cache.ReadReq_hits::cpu.data 11486555 # number of ReadReq hits 999system.cpu.l2cache.ReadReq_hits::total 11486596 # number of ReadReq hits 1000system.cpu.l2cache.Writeback_hits::writebacks 4830628 # number of Writeback hits 1001system.cpu.l2cache.Writeback_hits::total 4830628 # number of Writeback hits 1002system.cpu.l2cache.ReadExReq_hits::cpu.data 1752756 # number of ReadExReq hits 1003system.cpu.l2cache.ReadExReq_hits::total 1752756 # number of ReadExReq hits 1004system.cpu.l2cache.demand_hits::cpu.inst 41 # number of demand (read+write) hits 1005system.cpu.l2cache.demand_hits::cpu.data 13239311 # number of demand (read+write) hits 1006system.cpu.l2cache.demand_hits::total 13239352 # number of demand (read+write) hits 1007system.cpu.l2cache.overall_hits::cpu.inst 41 # number of overall hits 1008system.cpu.l2cache.overall_hits::cpu.data 13239311 # number of overall hits 1009system.cpu.l2cache.overall_hits::total 13239352 # number of overall hits 1010system.cpu.l2cache.ReadReq_misses::cpu.inst 1036 # number of ReadReq misses 1011system.cpu.l2cache.ReadReq_misses::cpu.data 2782314 # number of ReadReq misses 1012system.cpu.l2cache.ReadReq_misses::total 2783350 # number of ReadReq misses 1013system.cpu.l2cache.ReadExReq_misses::cpu.data 984772 # number of ReadExReq misses 1014system.cpu.l2cache.ReadExReq_misses::total 984772 # number of ReadExReq misses 1015system.cpu.l2cache.demand_misses::cpu.inst 1036 # number of demand (read+write) misses 1016system.cpu.l2cache.demand_misses::cpu.data 3767086 # number of demand (read+write) misses 1017system.cpu.l2cache.demand_misses::total 3768122 # number of demand (read+write) misses 1018system.cpu.l2cache.overall_misses::cpu.inst 1036 # number of overall misses 1019system.cpu.l2cache.overall_misses::cpu.data 3767086 # number of overall misses 1020system.cpu.l2cache.overall_misses::total 3768122 # number of overall misses 1021system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 75378470 # number of ReadReq miss cycles 1022system.cpu.l2cache.ReadReq_miss_latency::cpu.data 238879414609 # number of ReadReq miss cycles 1023system.cpu.l2cache.ReadReq_miss_latency::total 238954793079 # number of ReadReq miss cycles 1024system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100155661373 # number of ReadExReq miss cycles 1025system.cpu.l2cache.ReadExReq_miss_latency::total 100155661373 # number of ReadExReq miss cycles 1026system.cpu.l2cache.demand_miss_latency::cpu.inst 75378470 # number of demand (read+write) miss cycles 1027system.cpu.l2cache.demand_miss_latency::cpu.data 339035075982 # number of demand (read+write) miss cycles 1028system.cpu.l2cache.demand_miss_latency::total 339110454452 # number of demand (read+write) miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.inst 75378470 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::cpu.data 339035075982 # number of overall miss cycles 1031system.cpu.l2cache.overall_miss_latency::total 339110454452 # number of overall miss cycles 1032system.cpu.l2cache.ReadReq_accesses::cpu.inst 1077 # number of ReadReq accesses(hits+misses) 1033system.cpu.l2cache.ReadReq_accesses::cpu.data 14268869 # number of ReadReq accesses(hits+misses) 1034system.cpu.l2cache.ReadReq_accesses::total 14269946 # number of ReadReq accesses(hits+misses) 1035system.cpu.l2cache.Writeback_accesses::writebacks 4830628 # number of Writeback accesses(hits+misses) 1036system.cpu.l2cache.Writeback_accesses::total 4830628 # number of Writeback accesses(hits+misses) 1037system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737528 # number of ReadExReq accesses(hits+misses) 1038system.cpu.l2cache.ReadExReq_accesses::total 2737528 # number of ReadExReq accesses(hits+misses) 1039system.cpu.l2cache.demand_accesses::cpu.inst 1077 # number of demand (read+write) accesses 1040system.cpu.l2cache.demand_accesses::cpu.data 17006397 # number of demand (read+write) accesses 1041system.cpu.l2cache.demand_accesses::total 17007474 # number of demand (read+write) accesses 1042system.cpu.l2cache.overall_accesses::cpu.inst 1077 # number of overall (read+write) accesses 1043system.cpu.l2cache.overall_accesses::cpu.data 17006397 # number of overall (read+write) accesses 1044system.cpu.l2cache.overall_accesses::total 17007474 # number of overall (read+write) accesses 1045system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961931 # miss rate for ReadReq accesses 1046system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.194992 # miss rate for ReadReq accesses 1047system.cpu.l2cache.ReadReq_miss_rate::total 0.195050 # miss rate for ReadReq accesses 1048system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359730 # miss rate for ReadExReq accesses 1049system.cpu.l2cache.ReadExReq_miss_rate::total 0.359730 # miss rate for ReadExReq accesses 1050system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961931 # miss rate for demand accesses 1051system.cpu.l2cache.demand_miss_rate::cpu.data 0.221510 # miss rate for demand accesses 1052system.cpu.l2cache.demand_miss_rate::total 0.221557 # miss rate for demand accesses 1053system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961931 # miss rate for overall accesses 1054system.cpu.l2cache.overall_miss_rate::cpu.data 0.221510 # miss rate for overall accesses 1055system.cpu.l2cache.overall_miss_rate::total 0.221557 # miss rate for overall accesses 1056system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72759.140927 # average ReadReq miss latency 1057system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.382353 # average ReadReq miss latency 1058system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.507385 # average ReadReq miss latency 1059system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101704.416223 # average ReadExReq miss latency 1060system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101704.416223 # average ReadExReq miss latency 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72759.140927 # average overall miss latency 1062system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89999.292817 # average overall miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::total 89994.552844 # average overall miss latency 1064system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72759.140927 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89999.292817 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::total 89994.552844 # average overall miss latency 1067system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked 1068system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1069system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked 1070system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1071system.cpu.l2cache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked 1072system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1073system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1074system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1075system.cpu.l2cache.writebacks::writebacks 1637857 # number of writebacks 1076system.cpu.l2cache.writebacks::total 1637857 # number of writebacks 1077system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 35708 # number of ReadReq MSHR hits 1078system.cpu.l2cache.ReadReq_mshr_hits::total 35708 # number of ReadReq MSHR hits 1079system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3730 # number of ReadExReq MSHR hits 1080system.cpu.l2cache.ReadExReq_mshr_hits::total 3730 # number of ReadExReq MSHR hits 1081system.cpu.l2cache.demand_mshr_hits::cpu.data 39438 # number of demand (read+write) MSHR hits 1082system.cpu.l2cache.demand_mshr_hits::total 39438 # number of demand (read+write) MSHR hits 1083system.cpu.l2cache.overall_mshr_hits::cpu.data 39438 # number of overall MSHR hits 1084system.cpu.l2cache.overall_mshr_hits::total 39438 # number of overall MSHR hits 1085system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1036 # number of ReadReq MSHR misses 1086system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2746606 # number of ReadReq MSHR misses 1087system.cpu.l2cache.ReadReq_mshr_misses::total 2747642 # number of ReadReq MSHR misses 1088system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 992835 # number of HardPFReq MSHR misses 1089system.cpu.l2cache.HardPFReq_mshr_misses::total 992835 # number of HardPFReq MSHR misses 1090system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981042 # number of ReadExReq MSHR misses 1091system.cpu.l2cache.ReadExReq_mshr_misses::total 981042 # number of ReadExReq MSHR misses 1092system.cpu.l2cache.demand_mshr_misses::cpu.inst 1036 # number of demand (read+write) MSHR misses 1093system.cpu.l2cache.demand_mshr_misses::cpu.data 3727648 # number of demand (read+write) MSHR misses 1094system.cpu.l2cache.demand_mshr_misses::total 3728684 # number of demand (read+write) MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 1036 # number of overall MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::cpu.data 3727648 # number of overall MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 992835 # number of overall MSHR misses 1098system.cpu.l2cache.overall_mshr_misses::total 4721519 # number of overall MSHR misses 1099system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66562530 # number of ReadReq MSHR miss cycles 1100system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212706720467 # number of ReadReq MSHR miss cycles 1101system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212773282997 # number of ReadReq MSHR miss cycles 1102system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70893901794 # number of HardPFReq MSHR miss cycles 1103system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70893901794 # number of HardPFReq MSHR miss cycles 1104system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91380975745 # number of ReadExReq MSHR miss cycles 1105system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91380975745 # number of ReadExReq MSHR miss cycles 1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66562530 # number of demand (read+write) MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304087696212 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.demand_mshr_miss_latency::total 304154258742 # number of demand (read+write) MSHR miss cycles 1109system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66562530 # number of overall MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304087696212 # number of overall MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70893901794 # number of overall MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::total 375048160536 # number of overall MSHR miss cycles 1113system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for ReadReq accesses 1114system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192489 # mshr miss rate for ReadReq accesses 1115system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192547 # mshr miss rate for ReadReq accesses 1116system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1117system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1118system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358368 # mshr miss rate for ReadExReq accesses 1119system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358368 # mshr miss rate for ReadExReq accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for demand accesses 1121system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for demand accesses 1122system.cpu.l2cache.demand_mshr_miss_rate::total 0.219238 # mshr miss rate for demand accesses 1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for overall accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for overall accesses 1125system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1126system.cpu.l2cache.overall_mshr_miss_rate::total 0.277614 # mshr miss rate for overall accesses 1127system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64249.546332 # average ReadReq mshr miss latency 1128system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77443.477684 # average ReadReq mshr miss latency 1129system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77438.502904 # average ReadReq mshr miss latency 1130system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average HardPFReq mshr miss latency 1131system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71405.522362 # average HardPFReq mshr miss latency 1132system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93146.853799 # average ReadExReq mshr miss latency 1133system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93146.853799 # average ReadExReq mshr miss latency 1134system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency 1135system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency 1136system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81571.476355 # average overall mshr miss latency 1137system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency 1138system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79433.792501 # average overall mshr miss latency 1141system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1142system.cpu.toL2Bus.trans_dist::ReadReq 14269946 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::ReadResp 14269946 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::Writeback 4830628 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::HardPFReq 1298291 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::ReadExReq 2737528 # Transaction distribution 1147system.cpu.toL2Bus.trans_dist::ReadExResp 2737528 # Transaction distribution 1148system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2154 # Packet count per connected master and slave (bytes) 1149system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38843422 # Packet count per connected master and slave (bytes) 1150system.cpu.toL2Bus.pkt_count::total 38845576 # Packet count per connected master and slave (bytes) 1151system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68928 # Cumulative packet size per connected master and slave (bytes) 1152system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397569600 # Cumulative packet size per connected master and slave (bytes) 1153system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes) 1154system.cpu.toL2Bus.snoops 1298291 # Total snoops (count) 1155system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram	12sim_insts 1544563024 # Number of instructions simulated 13sim_ops 1664032416 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 238609216 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 63286144 # Number of bytes read from this memory 19system.physmem.bytes_read::total 301961664 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 104822848 # Number of bytes written to this memory 23system.physmem.bytes_written::total 104822848 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 3728269 # Number of read requests responded to by this memory 26system.physmem.num_reads::cpu.l2cache.prefetcher 988846 # Number of read requests responded to by this memory 27system.physmem.num_reads::total 4718151 # Number of read requests responded to by this memory 28system.physmem.num_writes::writebacks 1637857 # Number of write requests responded to by this memory 29system.physmem.num_writes::total 1637857 # Number of write requests responded to by this memory 30system.physmem.bw_read::cpu.inst 85917 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::cpu.data 309189366 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_read::cpu.l2cache.prefetcher 82006065 # Total read bandwidth from this memory (bytes/s) 33system.physmem.bw_read::total 391281347 # Total read bandwidth from this memory (bytes/s) 34system.physmem.bw_inst_read::cpu.inst 85917 # Instruction read bandwidth from this memory (bytes/s) 35system.physmem.bw_inst_read::total 85917 # Instruction read bandwidth from this memory (bytes/s) 36system.physmem.bw_write::writebacks 135829246 # Write bandwidth from this memory (bytes/s) 37system.physmem.bw_write::total 135829246 # Write bandwidth from this memory (bytes/s) 38system.physmem.bw_total::writebacks 135829246 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::cpu.inst 85917 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.bw_total::cpu.data 309189366 # Total bandwidth to/from this memory (bytes/s) 41system.physmem.bw_total::cpu.l2cache.prefetcher 82006065 # Total bandwidth to/from this memory (bytes/s) 42system.physmem.bw_total::total 527110594 # Total bandwidth to/from this memory (bytes/s) 43system.physmem.readReqs 4718151 # Number of read requests accepted 44system.physmem.writeReqs 1637857 # Number of write requests accepted 45system.physmem.readBursts 4718151 # Number of DRAM read bursts, including those serviced by the write queue 46system.physmem.writeBursts 1637857 # Number of DRAM write bursts, including those merged in the write queue 47system.physmem.bytesReadDRAM 301519872 # Total number of bytes read from DRAM 48system.physmem.bytesReadWrQ 441792 # Total number of bytes read from write queue 49system.physmem.bytesWritten 104820544 # Total number of bytes written to DRAM 50system.physmem.bytesReadSys 301961664 # Total read bytes from the system interface side 51system.physmem.bytesWrittenSys 104822848 # Total written bytes from the system interface side 52system.physmem.servicedByWrQ 6903 # Number of DRAM read bursts serviced by the write queue 53system.physmem.mergedWrBursts 19 # Number of DRAM write bursts merged with an existing one 54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 55system.physmem.perBankRdBursts::0 296668 # Per bank write bursts 56system.physmem.perBankRdBursts::1 294562 # Per bank write bursts 57system.physmem.perBankRdBursts::2 288307 # Per bank write bursts 58system.physmem.perBankRdBursts::3 292737 # Per bank write bursts 59system.physmem.perBankRdBursts::4 290232 # Per bank write bursts 60system.physmem.perBankRdBursts::5 289394 # Per bank write bursts 61system.physmem.perBankRdBursts::6 285167 # Per bank write bursts 62system.physmem.perBankRdBursts::7 280683 # Per bank write bursts 63system.physmem.perBankRdBursts::8 297292 # Per bank write bursts 64system.physmem.perBankRdBursts::9 302920 # Per bank write bursts 65system.physmem.perBankRdBursts::10 295430 # Per bank write bursts 66system.physmem.perBankRdBursts::11 301815 # Per bank write bursts 67system.physmem.perBankRdBursts::12 303322 # Per bank write bursts 68system.physmem.perBankRdBursts::13 302849 # Per bank write bursts 69system.physmem.perBankRdBursts::14 297025 # Per bank write bursts 70system.physmem.perBankRdBursts::15 292845 # Per bank write bursts 71system.physmem.perBankWrBursts::0 103942 # Per bank write bursts 72system.physmem.perBankWrBursts::1 102053 # Per bank write bursts 73system.physmem.perBankWrBursts::2 99317 # Per bank write bursts 74system.physmem.perBankWrBursts::3 99871 # Per bank write bursts 75system.physmem.perBankWrBursts::4 99169 # Per bank write bursts 76system.physmem.perBankWrBursts::5 98963 # Per bank write bursts 77system.physmem.perBankWrBursts::6 102735 # Per bank write bursts 78system.physmem.perBankWrBursts::7 104389 # Per bank write bursts 79system.physmem.perBankWrBursts::8 105226 # Per bank write bursts 80system.physmem.perBankWrBursts::9 104532 # Per bank write bursts 81system.physmem.perBankWrBursts::10 102159 # Per bank write bursts 82system.physmem.perBankWrBursts::11 102806 # Per bank write bursts 83system.physmem.perBankWrBursts::12 103028 # Per bank write bursts 84system.physmem.perBankWrBursts::13 102702 # Per bank write bursts 85system.physmem.perBankWrBursts::14 104263 # Per bank write bursts 86system.physmem.perBankWrBursts::15 102666 # Per bank write bursts 87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 89system.physmem.totGap 771725022000 # Total gap between requests 90system.physmem.readPktSize::0 0 # Read request sizes (log2) 91system.physmem.readPktSize::1 0 # Read request sizes (log2) 92system.physmem.readPktSize::2 0 # Read request sizes (log2) 93system.physmem.readPktSize::3 0 # Read request sizes (log2) 94system.physmem.readPktSize::4 0 # Read request sizes (log2) 95system.physmem.readPktSize::5 0 # Read request sizes (log2) 96system.physmem.readPktSize::6 4718151 # Read request sizes (log2) 97system.physmem.writePktSize::0 0 # Write request sizes (log2) 98system.physmem.writePktSize::1 0 # Write request sizes (log2) 99system.physmem.writePktSize::2 0 # Write request sizes (log2) 100system.physmem.writePktSize::3 0 # Write request sizes (log2) 101system.physmem.writePktSize::4 0 # Write request sizes (log2) 102system.physmem.writePktSize::5 0 # Write request sizes (log2) 103system.physmem.writePktSize::6 1637857 # Write request sizes (log2) 104system.physmem.rdQLenPdf::0 2774626 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::1 1044189 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::2 331696 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::3 233512 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::4 153773 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::5 84990 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::6 39149 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::7 23715 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::8 18258 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::9 4255 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::10 1688 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::12 411 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::15 22760 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::16 24545 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::17 59860 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::18 75448 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::19 85202 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::20 93103 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::21 99273 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::22 103279 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::23 105460 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::24 106422 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::25 106536 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::26 107239 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::27 108154 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::28 110632 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::29 113547 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::30 106733 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::31 103419 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::32 101598 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::33 2778 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::34 1044 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::35 449 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::36 193 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 200system.physmem.bytesPerActivate::samples 4287400 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::mean 94.775232 # Bytes accessed per row activation 202system.physmem.bytesPerActivate::gmean 78.917076 # Bytes accessed per row activation 203system.physmem.bytesPerActivate::stdev 101.448471 # Bytes accessed per row activation 204system.physmem.bytesPerActivate::0-127 3413764 79.62% 79.62% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::128-255 675374 15.75% 95.38% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::256-383 96809 2.26% 97.63% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::384-511 35249 0.82% 98.46% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::512-639 22885 0.53% 98.99% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::640-767 12087 0.28% 99.27% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::768-895 7187 0.17% 99.44% # Bytes accessed per row activation 211system.physmem.bytesPerActivate::896-1023 5043 0.12% 99.56% # Bytes accessed per row activation 212system.physmem.bytesPerActivate::1024-1151 19002 0.44% 100.00% # Bytes accessed per row activation 213system.physmem.bytesPerActivate::total 4287400 # Bytes accessed per row activation 214system.physmem.rdPerTurnAround::samples 98767 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::mean 47.700609 # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::gmean 32.313411 # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::stdev 98.282358 # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::0-127 94950 96.14% 96.14% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::128-255 1367 1.38% 97.52% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::384-511 428 0.43% 98.73% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::512-639 356 0.36% 99.09% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::640-767 374 0.38% 99.47% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::768-895 247 0.25% 99.72% # Reads before turning the bus around for writes 225system.physmem.rdPerTurnAround::896-1023 145 0.15% 99.87% # Reads before turning the bus around for writes 226system.physmem.rdPerTurnAround::1024-1151 66 0.07% 99.94% # Reads before turning the bus around for writes 227system.physmem.rdPerTurnAround::1152-1279 31 0.03% 99.97% # Reads before turning the bus around for writes 228system.physmem.rdPerTurnAround::1280-1407 13 0.01% 99.98% # Reads before turning the bus around for writes 229system.physmem.rdPerTurnAround::1408-1535 9 0.01% 99.99% # Reads before turning the bus around for writes 230system.physmem.rdPerTurnAround::1536-1663 1 0.00% 99.99% # Reads before turning the bus around for writes 231system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes 232system.physmem.rdPerTurnAround::1920-2047 2 0.00% 99.99% # Reads before turning the bus around for writes 233system.physmem.rdPerTurnAround::2688-2815 1 0.00% 99.99% # Reads before turning the bus around for writes 234system.physmem.rdPerTurnAround::2944-3071 2 0.00% 100.00% # Reads before turning the bus around for writes 235system.physmem.rdPerTurnAround::3072-3199 2 0.00% 100.00% # Reads before turning the bus around for writes 236system.physmem.rdPerTurnAround::3200-3327 1 0.00% 100.00% # Reads before turning the bus around for writes 237system.physmem.rdPerTurnAround::3328-3455 1 0.00% 100.00% # Reads before turning the bus around for writes 238system.physmem.rdPerTurnAround::total 98767 # Reads before turning the bus around for writes 239system.physmem.wrPerTurnAround::samples 98767 # Writes before turning the bus around for reads 240system.physmem.wrPerTurnAround::mean 16.582674 # Writes before turning the bus around for reads 241system.physmem.wrPerTurnAround::gmean 16.549780 # Writes before turning the bus around for reads 242system.physmem.wrPerTurnAround::stdev 1.086524 # Writes before turning the bus around for reads 243system.physmem.wrPerTurnAround::16 73305 74.22% 74.22% # Writes before turning the bus around for reads 244system.physmem.wrPerTurnAround::17 1806 1.83% 76.05% # Writes before turning the bus around for reads 245system.physmem.wrPerTurnAround::18 18343 18.57% 94.62% # Writes before turning the bus around for reads 246system.physmem.wrPerTurnAround::19 3630 3.68% 98.30% # Writes before turning the bus around for reads 247system.physmem.wrPerTurnAround::20 937 0.95% 99.24% # Writes before turning the bus around for reads 248system.physmem.wrPerTurnAround::21 387 0.39% 99.64% # Writes before turning the bus around for reads 249system.physmem.wrPerTurnAround::22 162 0.16% 99.80% # Writes before turning the bus around for reads 250system.physmem.wrPerTurnAround::23 107 0.11% 99.91% # Writes before turning the bus around for reads 251system.physmem.wrPerTurnAround::24 60 0.06% 99.97% # Writes before turning the bus around for reads 252system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads 253system.physmem.wrPerTurnAround::26 6 0.01% 100.00% # Writes before turning the bus around for reads 254system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads 255system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads 256system.physmem.wrPerTurnAround::total 98767 # Writes before turning the bus around for reads 257system.physmem.totQLat 132285118194 # Total ticks spent queuing 258system.physmem.totMemAccLat 220621018194 # Total ticks spent from burst creation until serviced by the DRAM 259system.physmem.totBusLat 23556240000 # Total ticks spent in databus transfers 260system.physmem.avgQLat 28078.57 # Average queueing delay per DRAM burst 261system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 262system.physmem.avgMemAccLat 46828.57 # Average memory access latency per DRAM burst 263system.physmem.avgRdBW 390.71 # Average DRAM read bandwidth in MiByte/s 264system.physmem.avgWrBW 135.83 # Average achieved write bandwidth in MiByte/s 265system.physmem.avgRdBWSys 391.28 # Average system read bandwidth in MiByte/s 266system.physmem.avgWrBWSys 135.83 # Average system write bandwidth in MiByte/s 267system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 268system.physmem.busUtil 4.11 # Data bus utilization in percentage 269system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads 270system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes 271system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing 272system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing 273system.physmem.readRowHits 1709073 # Number of row buffer hits during reads 274system.physmem.writeRowHits 352585 # Number of row buffer hits during writes 275system.physmem.readRowHitRate 36.28 # Row buffer hit rate for reads 276system.physmem.writeRowHitRate 21.53 # Row buffer hit rate for writes 277system.physmem.avgGap 121416.62 # Average gap between requests 278system.physmem.pageHitRate 32.47 # Row buffer hit rate, read and write combined 279system.physmem_0.actEnergy 16073195040 # Energy for activate commands per rank (pJ) 280system.physmem_0.preEnergy 8770096500 # Energy for precharge commands per rank (pJ) 281system.physmem_0.readEnergy 18077007000 # Energy for read commands per rank (pJ) 282system.physmem_0.writeEnergy 5251294800 # Energy for write commands per rank (pJ) 283system.physmem_0.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ) 284system.physmem_0.actBackEnergy 410674128390 # Energy for active background per rank (pJ) 285system.physmem_0.preBackEnergy 102790850250 # Energy for precharge background per rank (pJ) 286system.physmem_0.totalEnergy 612041479260 # Total energy per rank (pJ) 287system.physmem_0.averagePower 793.088667 # Core power per rank (mW) 288system.physmem_0.memoryStateTime::IDLE 168453702129 # Time in different power states 289system.physmem_0.memoryStateTime::REF 25769380000 # Time in different power states 290system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 291system.physmem_0.memoryStateTime::ACT 577496605871 # Time in different power states 292system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 293system.physmem_1.actEnergy 16339027320 # Energy for activate commands per rank (pJ) 294system.physmem_1.preEnergy 8915143875 # Energy for precharge commands per rank (pJ) 295system.physmem_1.readEnergy 18669222000 # Energy for read commands per rank (pJ) 296system.physmem_1.writeEnergy 5361163200 # Energy for write commands per rank (pJ) 297system.physmem_1.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ) 298system.physmem_1.actBackEnergy 412008151545 # Energy for active background per rank (pJ) 299system.physmem_1.preBackEnergy 101620654500 # Energy for precharge background per rank (pJ) 300system.physmem_1.totalEnergy 613318269720 # Total energy per rank (pJ) 301system.physmem_1.averagePower 794.743144 # Core power per rank (mW) 302system.physmem_1.memoryStateTime::IDLE 166509885283 # Time in different power states 303system.physmem_1.memoryStateTime::REF 25769380000 # Time in different power states 304system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 305system.physmem_1.memoryStateTime::ACT 579440435717 # Time in different power states 306system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 307system.cpu.branchPred.lookups 286277860 # Number of BP lookups 308system.cpu.branchPred.condPredicted 223409255 # Number of conditional branches predicted 309system.cpu.branchPred.condIncorrect 14633591 # Number of conditional branches incorrect 310system.cpu.branchPred.BTBLookups 157407621 # Number of BTB lookups 311system.cpu.branchPred.BTBHits 150346120 # Number of BTB hits 312system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 313system.cpu.branchPred.BTBHitPct 95.513876 # BTB Hit Percentage 314system.cpu.branchPred.usedRAS 16641206 # Number of times the RAS was used to get a target. 315system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions. 316system.cpu_clk_domain.clock 500 # Clock period in ticks 317system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 324system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 326system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 327system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 328system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 329system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 330system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 331system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 332system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 333system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 334system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 335system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 336system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 337system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 338system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 339system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 340system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 341system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 342system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 343system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 344system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 345system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 346system.cpu.dtb.walker.walks 0 # Table walker walks requested 347system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 351system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 352system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 353system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 354system.cpu.dtb.inst_hits 0 # ITB inst hits 355system.cpu.dtb.inst_misses 0 # ITB inst misses 356system.cpu.dtb.read_hits 0 # DTB read hits 357system.cpu.dtb.read_misses 0 # DTB read misses 358system.cpu.dtb.write_hits 0 # DTB write hits 359system.cpu.dtb.write_misses 0 # DTB write misses 360system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 361system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 362system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 363system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 364system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 365system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 366system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 367system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 368system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 369system.cpu.dtb.read_accesses 0 # DTB read accesses 370system.cpu.dtb.write_accesses 0 # DTB write accesses 371system.cpu.dtb.inst_accesses 0 # ITB inst accesses 372system.cpu.dtb.hits 0 # DTB hits 373system.cpu.dtb.misses 0 # DTB misses 374system.cpu.dtb.accesses 0 # DTB accesses 375system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 381system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 382system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 383system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 384system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 385system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 386system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 387system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 388system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 389system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 390system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 391system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 392system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 393system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 394system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 395system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 396system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 397system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 398system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 399system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 400system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 401system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 402system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 403system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 404system.cpu.itb.walker.walks 0 # Table walker walks requested 405system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 409system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 410system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 411system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 412system.cpu.itb.inst_hits 0 # ITB inst hits 413system.cpu.itb.inst_misses 0 # ITB inst misses 414system.cpu.itb.read_hits 0 # DTB read hits 415system.cpu.itb.read_misses 0 # DTB read misses 416system.cpu.itb.write_hits 0 # DTB write hits 417system.cpu.itb.write_misses 0 # DTB write misses 418system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 419system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 420system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 421system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 422system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 423system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 424system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 425system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 426system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 427system.cpu.itb.read_accesses 0 # DTB read accesses 428system.cpu.itb.write_accesses 0 # DTB write accesses 429system.cpu.itb.inst_accesses 0 # ITB inst accesses 430system.cpu.itb.hits 0 # DTB hits 431system.cpu.itb.misses 0 # DTB misses 432system.cpu.itb.accesses 0 # DTB accesses 433system.cpu.workload.num_syscalls 46 # Number of system calls 434system.cpu.numCycles 1543450339 # number of cpu cycles simulated 435system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 436system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 437system.cpu.fetch.icacheStallCycles 13927699 # Number of cycles fetch is stalled on an Icache miss 438system.cpu.fetch.Insts 2067517377 # Number of instructions fetch has processed 439system.cpu.fetch.Branches 286277860 # Number of branches that fetch encountered 440system.cpu.fetch.predictedBranches 166987326 # Number of branches that fetch has predicted taken 441system.cpu.fetch.Cycles 1514795150 # Number of cycles fetch has run and was not squashing or blocked 442system.cpu.fetch.SquashCycles 29291799 # Number of cycles fetch has spent squashing 443system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 444system.cpu.fetch.IcacheWaitRetryStallCycles 907 # Number of stall cycles due to full MSHR 445system.cpu.fetch.CacheLines 656942032 # Number of cache lines fetched 446system.cpu.fetch.IcacheSquashes 957 # Number of outstanding Icache misses that were squashed 447system.cpu.fetch.rateDist::samples 1543369835 # Number of instructions fetched each cycle (Total) 448system.cpu.fetch.rateDist::mean 1.435149 # Number of instructions fetched each cycle (Total) 449system.cpu.fetch.rateDist::stdev 1.229340 # Number of instructions fetched each cycle (Total) 450system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 451system.cpu.fetch.rateDist::0 460957271 29.87% 29.87% # Number of instructions fetched each cycle (Total) 452system.cpu.fetch.rateDist::1 465455811 30.16% 60.03% # Number of instructions fetched each cycle (Total) 453system.cpu.fetch.rateDist::2 101360614 6.57% 66.59% # Number of instructions fetched each cycle (Total) 454system.cpu.fetch.rateDist::3 515596139 33.41% 100.00% # Number of instructions fetched each cycle (Total) 455system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 456system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 457system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 458system.cpu.fetch.rateDist::total 1543369835 # Number of instructions fetched each cycle (Total) 459system.cpu.fetch.branchRate 0.185479 # Number of branch fetches per cycle 460system.cpu.fetch.rate 1.339543 # Number of inst fetches per cycle 461system.cpu.decode.IdleCycles 74619350 # Number of cycles decode is idle 462system.cpu.decode.BlockedCycles 545977788 # Number of cycles decode is blocked 463system.cpu.decode.RunCycles 850086533 # Number of cycles decode is running 464system.cpu.decode.UnblockCycles 58040967 # Number of cycles decode is unblocking 465system.cpu.decode.SquashCycles 14645197 # Number of cycles decode is squashing 466system.cpu.decode.BranchResolved 42200501 # Number of times decode resolved a branch 467system.cpu.decode.BranchMispred 754 # Number of times decode detected a branch misprediction 468system.cpu.decode.DecodedInsts 2037190940 # Number of instructions handled by decode 469system.cpu.decode.SquashedInsts 52475133 # Number of squashed instructions handled by decode 470system.cpu.rename.SquashCycles 14645197 # Number of cycles rename is squashing 471system.cpu.rename.IdleCycles 139685845 # Number of cycles rename is idle 472system.cpu.rename.BlockCycles 464851768 # Number of cycles rename is blocking 473system.cpu.rename.serializeStallCycles 13523 # count of cycles rename stalled for serializing inst 474system.cpu.rename.RunCycles 837895691 # Number of cycles rename is running 475system.cpu.rename.UnblockCycles 86277811 # Number of cycles rename is unblocking 476system.cpu.rename.RenamedInsts 1976364426 # Number of instructions processed by rename 477system.cpu.rename.SquashedInsts 26735694 # Number of squashed instructions processed by rename 478system.cpu.rename.ROBFullEvents 45105241 # Number of times rename has blocked due to ROB full 479system.cpu.rename.IQFullEvents 125505 # Number of times rename has blocked due to IQ full 480system.cpu.rename.LQFullEvents 1481556 # Number of times rename has blocked due to LQ full 481system.cpu.rename.SQFullEvents 25500508 # Number of times rename has blocked due to SQ full 482system.cpu.rename.RenamedOperands 1985835865 # Number of destination operands rename has renamed 483system.cpu.rename.RenameLookups 9128071192 # Number of register rename lookups that rename has made 484system.cpu.rename.int_rename_lookups 2432849079 # Number of integer rename lookups 485system.cpu.rename.fp_rename_lookups 136 # Number of floating rename lookups 486system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed 487system.cpu.rename.UndoneMaps 310936920 # Number of HB maps that are undone due to squashing 488system.cpu.rename.serializingInsts 149 # count of serializing insts renamed 489system.cpu.rename.tempSerializingInsts 140 # count of temporary serializing insts renamed 490system.cpu.rename.skidInsts 111342876 # count of insts added to the skid buffer 491system.cpu.memDep0.insertedLoads 542549398 # Number of loads inserted to the mem dependence unit. 492system.cpu.memDep0.insertedStores 199301403 # Number of stores inserted to the mem dependence unit. 493system.cpu.memDep0.conflictingLoads 26926926 # Number of conflicting loads. 494system.cpu.memDep0.conflictingStores 29153523 # Number of conflicting stores. 495system.cpu.iq.iqInstsAdded 1947926711 # Number of instructions added to the IQ (excludes non-spec) 496system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ 497system.cpu.iq.iqInstsIssued 1857446823 # Number of instructions issued 498system.cpu.iq.iqSquashedInstsIssued 13498178 # Number of squashed instructions issued 499system.cpu.iq.iqSquashedInstsExamined 283894503 # Number of squashed instructions iterated over during squash; mainly for profiling 500system.cpu.iq.iqSquashedOperandsExamined 646939215 # Number of squashed operands that are examined and possibly removed from graph 501system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed 502system.cpu.iq.issued_per_cycle::samples 1543369835 # Number of insts issued each cycle 503system.cpu.iq.issued_per_cycle::mean 1.203501 # Number of insts issued each cycle 504system.cpu.iq.issued_per_cycle::stdev 1.151095 # Number of insts issued each cycle 505system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 506system.cpu.iq.issued_per_cycle::0 590630846 38.27% 38.27% # Number of insts issued each cycle 507system.cpu.iq.issued_per_cycle::1 325771475 21.11% 59.38% # Number of insts issued each cycle 508system.cpu.iq.issued_per_cycle::2 378267234 24.51% 83.89% # Number of insts issued each cycle 509system.cpu.iq.issued_per_cycle::3 219666416 14.23% 98.12% # Number of insts issued each cycle 510system.cpu.iq.issued_per_cycle::4 29027688 1.88% 100.00% # Number of insts issued each cycle 511system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle 512system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 513system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 514system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 515system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 516system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 517system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle 518system.cpu.iq.issued_per_cycle::total 1543369835 # Number of insts issued each cycle 519system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 520system.cpu.iq.fu_full::IntAlu 166059149 40.99% 40.99% # attempts to use FU when none available 521system.cpu.iq.fu_full::IntMult 1996 0.00% 40.99% # attempts to use FU when none available 522system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available 523system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available 524system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available 525system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available 526system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available 527system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available 528system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 529system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available 530system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available 531system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available 532system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available 533system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available 534system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available 535system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available 536system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available 537system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available 538system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available 539system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available 540system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available 541system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available 542system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available 543system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available 544system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available 545system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available 546system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available 547system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available 548system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available 549system.cpu.iq.fu_full::MemRead 191393147 47.24% 88.23% # attempts to use FU when none available 550system.cpu.iq.fu_full::MemWrite 47682914 11.77% 100.00% # attempts to use FU when none available 551system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 552system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 553system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 554system.cpu.iq.FU_type_0::IntAlu 1138268714 61.28% 61.28% # Type of FU issued 555system.cpu.iq.FU_type_0::IntMult 801071 0.04% 61.32% # Type of FU issued 556system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued 557system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued 558system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued 559system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued 560system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued 561system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued 562system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued 563system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued 564system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued 565system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued 566system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued 567system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued 568system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued 569system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued 570system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued 571system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued 572system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued 573system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued 574system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued 575system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued 576system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued 577system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued 578system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued 579system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued 580system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued 581system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued 582system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued 583system.cpu.iq.FU_type_0::MemRead 532058987 28.64% 89.97% # Type of FU issued 584system.cpu.iq.FU_type_0::MemWrite 186318001 10.03% 100.00% # Type of FU issued 585system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 586system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 587system.cpu.iq.FU_type_0::total 1857446823 # Type of FU issued 588system.cpu.iq.rate 1.203438 # Inst issue rate 589system.cpu.iq.fu_busy_cnt 405137206 # FU busy when requested 590system.cpu.iq.fu_busy_rate 0.218115 # FU busy rate (busy events/executed inst) 591system.cpu.iq.int_inst_queue_reads 5676898637 # Number of integer instruction queue reads 592system.cpu.iq.int_inst_queue_writes 2231834122 # Number of integer instruction queue writes 593system.cpu.iq.int_inst_queue_wakeup_accesses 1805736851 # Number of integer instruction queue wakeup accesses 594system.cpu.iq.fp_inst_queue_reads 228 # Number of floating instruction queue reads 595system.cpu.iq.fp_inst_queue_writes 232 # Number of floating instruction queue writes 596system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses 597system.cpu.iq.int_alu_accesses 2262583902 # Number of integer alu accesses 598system.cpu.iq.fp_alu_accesses 127 # Number of floating point alu accesses 599system.cpu.iew.lsq.thread0.forwLoads 17817639 # Number of loads that had data forwarded from stores 600system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 601system.cpu.iew.lsq.thread0.squashedLoads 84243064 # Number of loads squashed 602system.cpu.iew.lsq.thread0.ignoredResponses 66651 # Number of memory responses ignored because the instruction is squashed 603system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations 604system.cpu.iew.lsq.thread0.squashedStores 24454358 # Number of stores squashed 605system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 606system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 607system.cpu.iew.lsq.thread0.rescheduledLoads 4525889 # Number of loads that were rescheduled 608system.cpu.iew.lsq.thread0.cacheBlocked 4805394 # Number of times an access to memory failed due to the cache being blocked 609system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 610system.cpu.iew.iewSquashCycles 14645197 # Number of cycles IEW is squashing 611system.cpu.iew.iewBlockCycles 25323327 # Number of cycles IEW is blocking 612system.cpu.iew.iewUnblockCycles 1332663 # Number of cycles IEW is unblocking 613system.cpu.iew.iewDispatchedInsts 1947926995 # Number of instructions dispatched to IQ 614system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 615system.cpu.iew.iewDispLoadInsts 542549398 # Number of dispatched load instructions 616system.cpu.iew.iewDispStoreInsts 199301403 # Number of dispatched store instructions 617system.cpu.iew.iewDispNonSpecInsts 146 # Number of dispatched non-speculative instructions 618system.cpu.iew.iewIQFullEvents 158839 # Number of times the IQ has become full, causing a stall 619system.cpu.iew.iewLSQFullEvents 1172731 # Number of times the LSQ has become full, causing a stall 620system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations 621system.cpu.iew.predictedTakenIncorrect 7701738 # Number of branches that were predicted taken incorrectly 622system.cpu.iew.predictedNotTakenIncorrect 8706499 # Number of branches that were predicted not taken incorrectly 623system.cpu.iew.branchMispredicts 16408237 # Number of branch mispredicts detected at execute 624system.cpu.iew.iewExecutedInsts 1827783249 # Number of executed instructions 625system.cpu.iew.iewExecLoadInsts 516881888 # Number of load instructions executed 626system.cpu.iew.iewExecSquashedInsts 29663574 # Number of squashed instructions skipped in execute 627system.cpu.iew.exec_swp 0 # number of swp insts executed 628system.cpu.iew.exec_nop 76 # number of nop insts executed 629system.cpu.iew.exec_refs 698636146 # number of memory reference insts executed 630system.cpu.iew.exec_branches 229555717 # Number of branches executed 631system.cpu.iew.exec_stores 181754258 # Number of stores executed 632system.cpu.iew.exec_rate 1.184219 # Inst execution rate 633system.cpu.iew.wb_sent 1808767141 # cumulative count of insts sent to commit 634system.cpu.iew.wb_count 1805736919 # cumulative count of insts written-back 635system.cpu.iew.wb_producers 1169322951 # num instructions producing a value 636system.cpu.iew.wb_consumers 1689713401 # num instructions consuming a value 637system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 638system.cpu.iew.wb_rate 1.169935 # insts written-back per cycle 639system.cpu.iew.wb_fanout 0.692024 # average fanout of values written-back 640system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 641system.cpu.commit.commitSquashedInsts 258002520 # The number of squashed insts skipped by commit 642system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards 643system.cpu.commit.branchMispredicts 14632889 # The number of times a branch was mispredicted 644system.cpu.commit.committed_per_cycle::samples 1503882923 # Number of insts commited each cycle 645system.cpu.commit.committed_per_cycle::mean 1.106491 # Number of insts commited each cycle 646system.cpu.commit.committed_per_cycle::stdev 2.024391 # Number of insts commited each cycle 647system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 648system.cpu.commit.committed_per_cycle::0 923604765 61.41% 61.41% # Number of insts commited each cycle 649system.cpu.commit.committed_per_cycle::1 250635322 16.67% 78.08% # Number of insts commited each cycle 650system.cpu.commit.committed_per_cycle::2 110056363 7.32% 85.40% # Number of insts commited each cycle 651system.cpu.commit.committed_per_cycle::3 55280526 3.68% 89.07% # Number of insts commited each cycle 652system.cpu.commit.committed_per_cycle::4 29292132 1.95% 91.02% # Number of insts commited each cycle 653system.cpu.commit.committed_per_cycle::5 34092515 2.27% 93.29% # Number of insts commited each cycle 654system.cpu.commit.committed_per_cycle::6 24716046 1.64% 94.93% # Number of insts commited each cycle 655system.cpu.commit.committed_per_cycle::7 18126603 1.21% 96.14% # Number of insts commited each cycle 656system.cpu.commit.committed_per_cycle::8 58078651 3.86% 100.00% # Number of insts commited each cycle 657system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 658system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 659system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 660system.cpu.commit.committed_per_cycle::total 1503882923 # Number of insts commited each cycle 661system.cpu.commit.committedInsts 1544563042 # Number of instructions committed 662system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed 663system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 664system.cpu.commit.refs 633153379 # Number of memory references committed 665system.cpu.commit.loads 458306334 # Number of loads committed 666system.cpu.commit.membars 62 # Number of memory barriers committed 667system.cpu.commit.branches 213462427 # Number of branches committed 668system.cpu.commit.fp_insts 36 # Number of committed floating point instructions. 669system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions. 670system.cpu.commit.function_calls 13665177 # Number of function calls committed. 671system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 672system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction 673system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 674system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 675system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 676system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 677system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 678system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction 679system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction 680system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction 681system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction 682system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction 683system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction 684system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction 685system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction 686system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction 687system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction 688system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction 689system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction 690system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction 691system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction 692system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction 693system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction 694system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction 695system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction 696system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction 697system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction 698system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 699system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 700system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 701system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 702system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction 703system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 704system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 705system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction 706system.cpu.commit.bw_lim_events 58078651 # number cycles where commit BW limit reached 707system.cpu.rob.rob_reads 3367838627 # The number of ROB reads 708system.cpu.rob.rob_writes 3883562090 # The number of ROB writes 709system.cpu.timesIdled 851 # Number of times that the entire CPU went into an idle state and unscheduled itself 710system.cpu.idleCycles 80504 # Total number of cycles that the CPU has spent unscheduled due to idling 711system.cpu.committedInsts 1544563024 # Number of Instructions Simulated 712system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated 713system.cpu.cpi 0.999280 # CPI: Cycles Per Instruction 714system.cpu.cpi_total 0.999280 # CPI: Total CPI of All Threads 715system.cpu.ipc 1.000721 # IPC: Instructions Per Cycle 716system.cpu.ipc_total 1.000721 # IPC: Total IPC of All Threads 717system.cpu.int_regfile_reads 2175739809 # number of integer regfile reads 718system.cpu.int_regfile_writes 1261583749 # number of integer regfile writes 719system.cpu.fp_regfile_reads 38 # number of floating regfile reads 720system.cpu.fp_regfile_writes 50 # number of floating regfile writes 721system.cpu.cc_regfile_reads 6965641029 # number of cc regfile reads 722system.cpu.cc_regfile_writes 551880821 # number of cc regfile writes 723system.cpu.misc_regfile_reads 675853491 # number of misc regfile reads 724system.cpu.misc_regfile_writes 124 # number of misc regfile writes 725system.cpu.dcache.tags.replacements 17005885 # number of replacements 726system.cpu.dcache.tags.tagsinuse 511.964949 # Cycle average of tags in use 727system.cpu.dcache.tags.total_refs 638186886 # Total number of references to valid blocks. 728system.cpu.dcache.tags.sampled_refs 17006397 # Sample count of references to valid blocks. 729system.cpu.dcache.tags.avg_refs 37.526284 # Average number of references to valid blocks. 730system.cpu.dcache.tags.warmup_cycle 78340000 # Cycle when the warmup percentage was hit. 731system.cpu.dcache.tags.occ_blocks::cpu.data 511.964949 # Average occupied blocks per requestor 732system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy 733system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy 734system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id 735system.cpu.dcache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id 736system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id 737system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 738system.cpu.dcache.tags.tag_accesses 1335687679 # Number of tag accesses 739system.cpu.dcache.tags.data_accesses 1335687679 # Number of data accesses 740system.cpu.dcache.ReadReq_hits::cpu.data 469400845 # number of ReadReq hits 741system.cpu.dcache.ReadReq_hits::total 469400845 # number of ReadReq hits 742system.cpu.dcache.WriteReq_hits::cpu.data 168785923 # number of WriteReq hits 743system.cpu.dcache.WriteReq_hits::total 168785923 # number of WriteReq hits 744system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits 745system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits 746system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 747system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 748system.cpu.dcache.demand_hits::cpu.data 638186768 # number of demand (read+write) hits 749system.cpu.dcache.demand_hits::total 638186768 # number of demand (read+write) hits 750system.cpu.dcache.overall_hits::cpu.data 638186768 # number of overall hits 751system.cpu.dcache.overall_hits::total 638186768 # number of overall hits 752system.cpu.dcache.ReadReq_misses::cpu.data 17353625 # number of ReadReq misses 753system.cpu.dcache.ReadReq_misses::total 17353625 # number of ReadReq misses 754system.cpu.dcache.WriteReq_misses::cpu.data 3800124 # number of WriteReq misses 755system.cpu.dcache.WriteReq_misses::total 3800124 # number of WriteReq misses 756system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 757system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses 758system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses 759system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses 760system.cpu.dcache.demand_misses::cpu.data 21153749 # number of demand (read+write) misses 761system.cpu.dcache.demand_misses::total 21153749 # number of demand (read+write) misses 762system.cpu.dcache.overall_misses::cpu.data 21153751 # number of overall misses 763system.cpu.dcache.overall_misses::total 21153751 # number of overall misses 764system.cpu.dcache.ReadReq_miss_latency::cpu.data 417050356298 # number of ReadReq miss cycles 765system.cpu.dcache.ReadReq_miss_latency::total 417050356298 # number of ReadReq miss cycles 766system.cpu.dcache.WriteReq_miss_latency::cpu.data 149886013526 # number of WriteReq miss cycles 767system.cpu.dcache.WriteReq_miss_latency::total 149886013526 # number of WriteReq miss cycles 768system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204500 # number of LoadLockedReq miss cycles 769system.cpu.dcache.LoadLockedReq_miss_latency::total 204500 # number of LoadLockedReq miss cycles 770system.cpu.dcache.demand_miss_latency::cpu.data 566936369824 # number of demand (read+write) miss cycles 771system.cpu.dcache.demand_miss_latency::total 566936369824 # number of demand (read+write) miss cycles 772system.cpu.dcache.overall_miss_latency::cpu.data 566936369824 # number of overall miss cycles 773system.cpu.dcache.overall_miss_latency::total 566936369824 # number of overall miss cycles 774system.cpu.dcache.ReadReq_accesses::cpu.data 486754470 # number of ReadReq accesses(hits+misses) 775system.cpu.dcache.ReadReq_accesses::total 486754470 # number of ReadReq accesses(hits+misses) 776system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 777system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 778system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses) 779system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses) 780system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 781system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 782system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 783system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 784system.cpu.dcache.demand_accesses::cpu.data 659340517 # number of demand (read+write) accesses 785system.cpu.dcache.demand_accesses::total 659340517 # number of demand (read+write) accesses 786system.cpu.dcache.overall_accesses::cpu.data 659340519 # number of overall (read+write) accesses 787system.cpu.dcache.overall_accesses::total 659340519 # number of overall (read+write) accesses 788system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035652 # miss rate for ReadReq accesses 789system.cpu.dcache.ReadReq_miss_rate::total 0.035652 # miss rate for ReadReq accesses 790system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022019 # miss rate for WriteReq accesses 791system.cpu.dcache.WriteReq_miss_rate::total 0.022019 # miss rate for WriteReq accesses 792system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses 793system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses 794system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses 795system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses 796system.cpu.dcache.demand_miss_rate::cpu.data 0.032083 # miss rate for demand accesses 797system.cpu.dcache.demand_miss_rate::total 0.032083 # miss rate for demand accesses 798system.cpu.dcache.overall_miss_rate::cpu.data 0.032083 # miss rate for overall accesses 799system.cpu.dcache.overall_miss_rate::total 0.032083 # miss rate for overall accesses 800system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24032.463321 # average ReadReq miss latency 801system.cpu.dcache.ReadReq_avg_miss_latency::total 24032.463321 # average ReadReq miss latency 802system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39442.400702 # average WriteReq miss latency 803system.cpu.dcache.WriteReq_avg_miss_latency::total 39442.400702 # average WriteReq miss latency 804system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51125 # average LoadLockedReq miss latency 805system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51125 # average LoadLockedReq miss latency 806system.cpu.dcache.demand_avg_miss_latency::cpu.data 26800.751480 # average overall miss latency 807system.cpu.dcache.demand_avg_miss_latency::total 26800.751480 # average overall miss latency 808system.cpu.dcache.overall_avg_miss_latency::cpu.data 26800.748946 # average overall miss latency 809system.cpu.dcache.overall_avg_miss_latency::total 26800.748946 # average overall miss latency 810system.cpu.dcache.blocked_cycles::no_mshrs 20736521 # number of cycles access was blocked 811system.cpu.dcache.blocked_cycles::no_targets 3309459 # number of cycles access was blocked 812system.cpu.dcache.blocked::no_mshrs 945396 # number of cycles access was blocked 813system.cpu.dcache.blocked::no_targets 67047 # number of cycles access was blocked 814system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.934217 # average number of cycles each access was blocked 815system.cpu.dcache.avg_blocked_cycles::no_targets 49.360285 # average number of cycles each access was blocked 816system.cpu.dcache.fast_writes 0 # number of fast writes performed 817system.cpu.dcache.cache_copies 0 # number of cache copies performed 818system.cpu.dcache.writebacks::writebacks 4830628 # number of writebacks 819system.cpu.dcache.writebacks::total 4830628 # number of writebacks 820system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3084713 # number of ReadReq MSHR hits 821system.cpu.dcache.ReadReq_mshr_hits::total 3084713 # number of ReadReq MSHR hits 822system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1062640 # number of WriteReq MSHR hits 823system.cpu.dcache.WriteReq_mshr_hits::total 1062640 # number of WriteReq MSHR hits 824system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits 825system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits 826system.cpu.dcache.demand_mshr_hits::cpu.data 4147353 # number of demand (read+write) MSHR hits 827system.cpu.dcache.demand_mshr_hits::total 4147353 # number of demand (read+write) MSHR hits 828system.cpu.dcache.overall_mshr_hits::cpu.data 4147353 # number of overall MSHR hits 829system.cpu.dcache.overall_mshr_hits::total 4147353 # number of overall MSHR hits 830system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268912 # number of ReadReq MSHR misses 831system.cpu.dcache.ReadReq_mshr_misses::total 14268912 # number of ReadReq MSHR misses 832system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737484 # number of WriteReq MSHR misses 833system.cpu.dcache.WriteReq_mshr_misses::total 2737484 # number of WriteReq MSHR misses 834system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 835system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 836system.cpu.dcache.demand_mshr_misses::cpu.data 17006396 # number of demand (read+write) MSHR misses 837system.cpu.dcache.demand_mshr_misses::total 17006396 # number of demand (read+write) MSHR misses 838system.cpu.dcache.overall_mshr_misses::cpu.data 17006397 # number of overall MSHR misses 839system.cpu.dcache.overall_mshr_misses::total 17006397 # number of overall MSHR misses 840system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 328919129806 # number of ReadReq MSHR miss cycles 841system.cpu.dcache.ReadReq_mshr_miss_latency::total 328919129806 # number of ReadReq MSHR miss cycles 842system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115124697729 # number of WriteReq MSHR miss cycles 843system.cpu.dcache.WriteReq_mshr_miss_latency::total 115124697729 # number of WriteReq MSHR miss cycles 844system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles 845system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles 846system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444043827535 # number of demand (read+write) MSHR miss cycles 847system.cpu.dcache.demand_mshr_miss_latency::total 444043827535 # number of demand (read+write) MSHR miss cycles 848system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444043895285 # number of overall MSHR miss cycles 849system.cpu.dcache.overall_mshr_miss_latency::total 444043895285 # number of overall MSHR miss cycles 850system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses 851system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses 852system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses 853system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses 854system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses 855system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses 856system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses 857system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses 858system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses 859system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses 860system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23051.451281 # average ReadReq mshr miss latency 861system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23051.451281 # average ReadReq mshr miss latency 862system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42054.929902 # average WriteReq mshr miss latency 863system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42054.929902 # average WriteReq mshr miss latency 864system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency 865system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency 866system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.401495 # average overall mshr miss latency 867system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.401495 # average overall mshr miss latency 868system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.403943 # average overall mshr miss latency 869system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.403943 # average overall mshr miss latency 870system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 871system.cpu.icache.tags.replacements 589 # number of replacements 872system.cpu.icache.tags.tagsinuse 446.078018 # Cycle average of tags in use 873system.cpu.icache.tags.total_refs 656940406 # Total number of references to valid blocks. 874system.cpu.icache.tags.sampled_refs 1077 # Sample count of references to valid blocks. 875system.cpu.icache.tags.avg_refs 609972.521820 # Average number of references to valid blocks. 876system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 877system.cpu.icache.tags.occ_blocks::cpu.inst 446.078018 # Average occupied blocks per requestor 878system.cpu.icache.tags.occ_percent::cpu.inst 0.871246 # Average percentage of cache occupancy 879system.cpu.icache.tags.occ_percent::total 0.871246 # Average percentage of cache occupancy 880system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id 881system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 882system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id 883system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id 884system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id 885system.cpu.icache.tags.tag_accesses 1313885139 # Number of tag accesses 886system.cpu.icache.tags.data_accesses 1313885139 # Number of data accesses 887system.cpu.icache.ReadReq_hits::cpu.inst 656940406 # number of ReadReq hits 888system.cpu.icache.ReadReq_hits::total 656940406 # number of ReadReq hits 889system.cpu.icache.demand_hits::cpu.inst 656940406 # number of demand (read+write) hits 890system.cpu.icache.demand_hits::total 656940406 # number of demand (read+write) hits 891system.cpu.icache.overall_hits::cpu.inst 656940406 # number of overall hits 892system.cpu.icache.overall_hits::total 656940406 # number of overall hits 893system.cpu.icache.ReadReq_misses::cpu.inst 1625 # number of ReadReq misses 894system.cpu.icache.ReadReq_misses::total 1625 # number of ReadReq misses 895system.cpu.icache.demand_misses::cpu.inst 1625 # number of demand (read+write) misses 896system.cpu.icache.demand_misses::total 1625 # number of demand (read+write) misses 897system.cpu.icache.overall_misses::cpu.inst 1625 # number of overall misses 898system.cpu.icache.overall_misses::total 1625 # number of overall misses 899system.cpu.icache.ReadReq_miss_latency::cpu.inst 105016775 # number of ReadReq miss cycles 900system.cpu.icache.ReadReq_miss_latency::total 105016775 # number of ReadReq miss cycles 901system.cpu.icache.demand_miss_latency::cpu.inst 105016775 # number of demand (read+write) miss cycles 902system.cpu.icache.demand_miss_latency::total 105016775 # number of demand (read+write) miss cycles 903system.cpu.icache.overall_miss_latency::cpu.inst 105016775 # number of overall miss cycles 904system.cpu.icache.overall_miss_latency::total 105016775 # number of overall miss cycles 905system.cpu.icache.ReadReq_accesses::cpu.inst 656942031 # number of ReadReq accesses(hits+misses) 906system.cpu.icache.ReadReq_accesses::total 656942031 # number of ReadReq accesses(hits+misses) 907system.cpu.icache.demand_accesses::cpu.inst 656942031 # number of demand (read+write) accesses 908system.cpu.icache.demand_accesses::total 656942031 # number of demand (read+write) accesses 909system.cpu.icache.overall_accesses::cpu.inst 656942031 # number of overall (read+write) accesses 910system.cpu.icache.overall_accesses::total 656942031 # number of overall (read+write) accesses 911system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 912system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 913system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 914system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 915system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 916system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 917system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64625.707692 # average ReadReq miss latency 918system.cpu.icache.ReadReq_avg_miss_latency::total 64625.707692 # average ReadReq miss latency 919system.cpu.icache.demand_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency 920system.cpu.icache.demand_avg_miss_latency::total 64625.707692 # average overall miss latency 921system.cpu.icache.overall_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency 922system.cpu.icache.overall_avg_miss_latency::total 64625.707692 # average overall miss latency 923system.cpu.icache.blocked_cycles::no_mshrs 17596 # number of cycles access was blocked 924system.cpu.icache.blocked_cycles::no_targets 547 # number of cycles access was blocked 925system.cpu.icache.blocked::no_mshrs 191 # number of cycles access was blocked 926system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked 927system.cpu.icache.avg_blocked_cycles::no_mshrs 92.125654 # average number of cycles each access was blocked 928system.cpu.icache.avg_blocked_cycles::no_targets 60.777778 # average number of cycles each access was blocked 929system.cpu.icache.fast_writes 0 # number of fast writes performed 930system.cpu.icache.cache_copies 0 # number of cache copies performed 931system.cpu.icache.ReadReq_mshr_hits::cpu.inst 548 # number of ReadReq MSHR hits 932system.cpu.icache.ReadReq_mshr_hits::total 548 # number of ReadReq MSHR hits 933system.cpu.icache.demand_mshr_hits::cpu.inst 548 # number of demand (read+write) MSHR hits 934system.cpu.icache.demand_mshr_hits::total 548 # number of demand (read+write) MSHR hits 935system.cpu.icache.overall_mshr_hits::cpu.inst 548 # number of overall MSHR hits 936system.cpu.icache.overall_mshr_hits::total 548 # number of overall MSHR hits 937system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses 938system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses 939system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses 940system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses 941system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses 942system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses 943system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76192959 # number of ReadReq MSHR miss cycles 944system.cpu.icache.ReadReq_mshr_miss_latency::total 76192959 # number of ReadReq MSHR miss cycles 945system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76192959 # number of demand (read+write) MSHR miss cycles 946system.cpu.icache.demand_mshr_miss_latency::total 76192959 # number of demand (read+write) MSHR miss cycles 947system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76192959 # number of overall MSHR miss cycles 948system.cpu.icache.overall_mshr_miss_latency::total 76192959 # number of overall MSHR miss cycles 949system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 950system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 951system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 952system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 953system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 954system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 955system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70745.551532 # average ReadReq mshr miss latency 956system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70745.551532 # average ReadReq mshr miss latency 957system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70745.551532 # average overall mshr miss latency 958system.cpu.icache.demand_avg_mshr_miss_latency::total 70745.551532 # average overall mshr miss latency 959system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70745.551532 # average overall mshr miss latency 960system.cpu.icache.overall_avg_mshr_miss_latency::total 70745.551532 # average overall mshr miss latency 961system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 962system.cpu.l2cache.prefetcher.num_hwpf_issued 10938258 # number of hwpf issued 963system.cpu.l2cache.prefetcher.pfIdentified 11626730 # number of prefetch candidates identified 964system.cpu.l2cache.prefetcher.pfBufferHit 430783 # number of redundant prefetches already in prefetch queue 965system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 966system.cpu.l2cache.prefetcher.pfRemovedFull 3 # number of prefetches dropped due to prefetch queue size 967system.cpu.l2cache.prefetcher.pfSpanPage 4654278 # number of prefetches not generated due to page crossing 968system.cpu.l2cache.tags.replacements 4710195 # number of replacements 969system.cpu.l2cache.tags.tagsinuse 16130.419578 # Cycle average of tags in use 970system.cpu.l2cache.tags.total_refs 15323813 # Total number of references to valid blocks. 971system.cpu.l2cache.tags.sampled_refs 4726123 # Sample count of references to valid blocks. 972system.cpu.l2cache.tags.avg_refs 3.242364 # Average number of references to valid blocks. 973system.cpu.l2cache.tags.warmup_cycle 29466216500 # Cycle when the warmup percentage was hit. 974system.cpu.l2cache.tags.occ_blocks::writebacks 5234.041152 # Average occupied blocks per requestor 975system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.862974 # Average occupied blocks per requestor 976system.cpu.l2cache.tags.occ_blocks::cpu.data 7585.301260 # Average occupied blocks per requestor 977system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3292.214193 # Average occupied blocks per requestor 978system.cpu.l2cache.tags.occ_percent::writebacks 0.319461 # Average percentage of cache occupancy 979system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001151 # Average percentage of cache occupancy 980system.cpu.l2cache.tags.occ_percent::cpu.data 0.462970 # Average percentage of cache occupancy 981system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.200941 # Average percentage of cache occupancy 982system.cpu.l2cache.tags.occ_percent::total 0.984523 # Average percentage of cache occupancy 983system.cpu.l2cache.tags.occ_task_id_blocks::1022 739 # Occupied blocks per task id 984system.cpu.l2cache.tags.occ_task_id_blocks::1024 15189 # Occupied blocks per task id 985system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id 986system.cpu.l2cache.tags.age_task_id_blocks_1022::1 553 # Occupied blocks per task id 987system.cpu.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id 988system.cpu.l2cache.tags.age_task_id_blocks_1024::0 505 # Occupied blocks per task id 989system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2391 # Occupied blocks per task id 990system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1230 # Occupied blocks per task id 991system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9214 # Occupied blocks per task id 992system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1849 # Occupied blocks per task id 993system.cpu.l2cache.tags.occ_task_id_percent::1022 0.045105 # Percentage of cache occupancy per task id 994system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927063 # Percentage of cache occupancy per task id 995system.cpu.l2cache.tags.tag_accesses 356873283 # Number of tag accesses 996system.cpu.l2cache.tags.data_accesses 356873283 # Number of data accesses 997system.cpu.l2cache.ReadReq_hits::cpu.inst 41 # number of ReadReq hits 998system.cpu.l2cache.ReadReq_hits::cpu.data 11486555 # number of ReadReq hits 999system.cpu.l2cache.ReadReq_hits::total 11486596 # number of ReadReq hits 1000system.cpu.l2cache.Writeback_hits::writebacks 4830628 # number of Writeback hits 1001system.cpu.l2cache.Writeback_hits::total 4830628 # number of Writeback hits 1002system.cpu.l2cache.ReadExReq_hits::cpu.data 1752756 # number of ReadExReq hits 1003system.cpu.l2cache.ReadExReq_hits::total 1752756 # number of ReadExReq hits 1004system.cpu.l2cache.demand_hits::cpu.inst 41 # number of demand (read+write) hits 1005system.cpu.l2cache.demand_hits::cpu.data 13239311 # number of demand (read+write) hits 1006system.cpu.l2cache.demand_hits::total 13239352 # number of demand (read+write) hits 1007system.cpu.l2cache.overall_hits::cpu.inst 41 # number of overall hits 1008system.cpu.l2cache.overall_hits::cpu.data 13239311 # number of overall hits 1009system.cpu.l2cache.overall_hits::total 13239352 # number of overall hits 1010system.cpu.l2cache.ReadReq_misses::cpu.inst 1036 # number of ReadReq misses 1011system.cpu.l2cache.ReadReq_misses::cpu.data 2782314 # number of ReadReq misses 1012system.cpu.l2cache.ReadReq_misses::total 2783350 # number of ReadReq misses 1013system.cpu.l2cache.ReadExReq_misses::cpu.data 984772 # number of ReadExReq misses 1014system.cpu.l2cache.ReadExReq_misses::total 984772 # number of ReadExReq misses 1015system.cpu.l2cache.demand_misses::cpu.inst 1036 # number of demand (read+write) misses 1016system.cpu.l2cache.demand_misses::cpu.data 3767086 # number of demand (read+write) misses 1017system.cpu.l2cache.demand_misses::total 3768122 # number of demand (read+write) misses 1018system.cpu.l2cache.overall_misses::cpu.inst 1036 # number of overall misses 1019system.cpu.l2cache.overall_misses::cpu.data 3767086 # number of overall misses 1020system.cpu.l2cache.overall_misses::total 3768122 # number of overall misses 1021system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 75378470 # number of ReadReq miss cycles 1022system.cpu.l2cache.ReadReq_miss_latency::cpu.data 238879414609 # number of ReadReq miss cycles 1023system.cpu.l2cache.ReadReq_miss_latency::total 238954793079 # number of ReadReq miss cycles 1024system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100155661373 # number of ReadExReq miss cycles 1025system.cpu.l2cache.ReadExReq_miss_latency::total 100155661373 # number of ReadExReq miss cycles 1026system.cpu.l2cache.demand_miss_latency::cpu.inst 75378470 # number of demand (read+write) miss cycles 1027system.cpu.l2cache.demand_miss_latency::cpu.data 339035075982 # number of demand (read+write) miss cycles 1028system.cpu.l2cache.demand_miss_latency::total 339110454452 # number of demand (read+write) miss cycles 1029system.cpu.l2cache.overall_miss_latency::cpu.inst 75378470 # number of overall miss cycles 1030system.cpu.l2cache.overall_miss_latency::cpu.data 339035075982 # number of overall miss cycles 1031system.cpu.l2cache.overall_miss_latency::total 339110454452 # number of overall miss cycles 1032system.cpu.l2cache.ReadReq_accesses::cpu.inst 1077 # number of ReadReq accesses(hits+misses) 1033system.cpu.l2cache.ReadReq_accesses::cpu.data 14268869 # number of ReadReq accesses(hits+misses) 1034system.cpu.l2cache.ReadReq_accesses::total 14269946 # number of ReadReq accesses(hits+misses) 1035system.cpu.l2cache.Writeback_accesses::writebacks 4830628 # number of Writeback accesses(hits+misses) 1036system.cpu.l2cache.Writeback_accesses::total 4830628 # number of Writeback accesses(hits+misses) 1037system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737528 # number of ReadExReq accesses(hits+misses) 1038system.cpu.l2cache.ReadExReq_accesses::total 2737528 # number of ReadExReq accesses(hits+misses) 1039system.cpu.l2cache.demand_accesses::cpu.inst 1077 # number of demand (read+write) accesses 1040system.cpu.l2cache.demand_accesses::cpu.data 17006397 # number of demand (read+write) accesses 1041system.cpu.l2cache.demand_accesses::total 17007474 # number of demand (read+write) accesses 1042system.cpu.l2cache.overall_accesses::cpu.inst 1077 # number of overall (read+write) accesses 1043system.cpu.l2cache.overall_accesses::cpu.data 17006397 # number of overall (read+write) accesses 1044system.cpu.l2cache.overall_accesses::total 17007474 # number of overall (read+write) accesses 1045system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961931 # miss rate for ReadReq accesses 1046system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.194992 # miss rate for ReadReq accesses 1047system.cpu.l2cache.ReadReq_miss_rate::total 0.195050 # miss rate for ReadReq accesses 1048system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359730 # miss rate for ReadExReq accesses 1049system.cpu.l2cache.ReadExReq_miss_rate::total 0.359730 # miss rate for ReadExReq accesses 1050system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961931 # miss rate for demand accesses 1051system.cpu.l2cache.demand_miss_rate::cpu.data 0.221510 # miss rate for demand accesses 1052system.cpu.l2cache.demand_miss_rate::total 0.221557 # miss rate for demand accesses 1053system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961931 # miss rate for overall accesses 1054system.cpu.l2cache.overall_miss_rate::cpu.data 0.221510 # miss rate for overall accesses 1055system.cpu.l2cache.overall_miss_rate::total 0.221557 # miss rate for overall accesses 1056system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72759.140927 # average ReadReq miss latency 1057system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.382353 # average ReadReq miss latency 1058system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.507385 # average ReadReq miss latency 1059system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101704.416223 # average ReadExReq miss latency 1060system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101704.416223 # average ReadExReq miss latency 1061system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72759.140927 # average overall miss latency 1062system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89999.292817 # average overall miss latency 1063system.cpu.l2cache.demand_avg_miss_latency::total 89994.552844 # average overall miss latency 1064system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72759.140927 # average overall miss latency 1065system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89999.292817 # average overall miss latency 1066system.cpu.l2cache.overall_avg_miss_latency::total 89994.552844 # average overall miss latency 1067system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked 1068system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1069system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked 1070system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1071system.cpu.l2cache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked 1072system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1073system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1074system.cpu.l2cache.cache_copies 0 # number of cache copies performed 1075system.cpu.l2cache.writebacks::writebacks 1637857 # number of writebacks 1076system.cpu.l2cache.writebacks::total 1637857 # number of writebacks 1077system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 35708 # number of ReadReq MSHR hits 1078system.cpu.l2cache.ReadReq_mshr_hits::total 35708 # number of ReadReq MSHR hits 1079system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3730 # number of ReadExReq MSHR hits 1080system.cpu.l2cache.ReadExReq_mshr_hits::total 3730 # number of ReadExReq MSHR hits 1081system.cpu.l2cache.demand_mshr_hits::cpu.data 39438 # number of demand (read+write) MSHR hits 1082system.cpu.l2cache.demand_mshr_hits::total 39438 # number of demand (read+write) MSHR hits 1083system.cpu.l2cache.overall_mshr_hits::cpu.data 39438 # number of overall MSHR hits 1084system.cpu.l2cache.overall_mshr_hits::total 39438 # number of overall MSHR hits 1085system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1036 # number of ReadReq MSHR misses 1086system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2746606 # number of ReadReq MSHR misses 1087system.cpu.l2cache.ReadReq_mshr_misses::total 2747642 # number of ReadReq MSHR misses 1088system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 992835 # number of HardPFReq MSHR misses 1089system.cpu.l2cache.HardPFReq_mshr_misses::total 992835 # number of HardPFReq MSHR misses 1090system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981042 # number of ReadExReq MSHR misses 1091system.cpu.l2cache.ReadExReq_mshr_misses::total 981042 # number of ReadExReq MSHR misses 1092system.cpu.l2cache.demand_mshr_misses::cpu.inst 1036 # number of demand (read+write) MSHR misses 1093system.cpu.l2cache.demand_mshr_misses::cpu.data 3727648 # number of demand (read+write) MSHR misses 1094system.cpu.l2cache.demand_mshr_misses::total 3728684 # number of demand (read+write) MSHR misses 1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 1036 # number of overall MSHR misses 1096system.cpu.l2cache.overall_mshr_misses::cpu.data 3727648 # number of overall MSHR misses 1097system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 992835 # number of overall MSHR misses 1098system.cpu.l2cache.overall_mshr_misses::total 4721519 # number of overall MSHR misses 1099system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66562530 # number of ReadReq MSHR miss cycles 1100system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212706720467 # number of ReadReq MSHR miss cycles 1101system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212773282997 # number of ReadReq MSHR miss cycles 1102system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70893901794 # number of HardPFReq MSHR miss cycles 1103system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70893901794 # number of HardPFReq MSHR miss cycles 1104system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91380975745 # number of ReadExReq MSHR miss cycles 1105system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91380975745 # number of ReadExReq MSHR miss cycles 1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66562530 # number of demand (read+write) MSHR miss cycles 1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304087696212 # number of demand (read+write) MSHR miss cycles 1108system.cpu.l2cache.demand_mshr_miss_latency::total 304154258742 # number of demand (read+write) MSHR miss cycles 1109system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66562530 # number of overall MSHR miss cycles 1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304087696212 # number of overall MSHR miss cycles 1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70893901794 # number of overall MSHR miss cycles 1112system.cpu.l2cache.overall_mshr_miss_latency::total 375048160536 # number of overall MSHR miss cycles 1113system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for ReadReq accesses 1114system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192489 # mshr miss rate for ReadReq accesses 1115system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192547 # mshr miss rate for ReadReq accesses 1116system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1117system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1118system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358368 # mshr miss rate for ReadExReq accesses 1119system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358368 # mshr miss rate for ReadExReq accesses 1120system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for demand accesses 1121system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for demand accesses 1122system.cpu.l2cache.demand_mshr_miss_rate::total 0.219238 # mshr miss rate for demand accesses 1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for overall accesses 1124system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for overall accesses 1125system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1126system.cpu.l2cache.overall_mshr_miss_rate::total 0.277614 # mshr miss rate for overall accesses 1127system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64249.546332 # average ReadReq mshr miss latency 1128system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77443.477684 # average ReadReq mshr miss latency 1129system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77438.502904 # average ReadReq mshr miss latency 1130system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average HardPFReq mshr miss latency 1131system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71405.522362 # average HardPFReq mshr miss latency 1132system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93146.853799 # average ReadExReq mshr miss latency 1133system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93146.853799 # average ReadExReq mshr miss latency 1134system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency 1135system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency 1136system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81571.476355 # average overall mshr miss latency 1137system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency 1138system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency 1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average overall mshr miss latency 1140system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79433.792501 # average overall mshr miss latency 1141system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1142system.cpu.toL2Bus.trans_dist::ReadReq 14269946 # Transaction distribution 1143system.cpu.toL2Bus.trans_dist::ReadResp 14269946 # Transaction distribution 1144system.cpu.toL2Bus.trans_dist::Writeback 4830628 # Transaction distribution 1145system.cpu.toL2Bus.trans_dist::HardPFReq 1298291 # Transaction distribution 1146system.cpu.toL2Bus.trans_dist::ReadExReq 2737528 # Transaction distribution 1147system.cpu.toL2Bus.trans_dist::ReadExResp 2737528 # Transaction distribution 1148system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2154 # Packet count per connected master and slave (bytes) 1149system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38843422 # Packet count per connected master and slave (bytes) 1150system.cpu.toL2Bus.pkt_count::total 38845576 # Packet count per connected master and slave (bytes) 1151system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68928 # Cumulative packet size per connected master and slave (bytes) 1152system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397569600 # Cumulative packet size per connected master and slave (bytes) 1153system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes) 1154system.cpu.toL2Bus.snoops 1298291 # Total snoops (count) 1155system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram
1156system.cpu.toL2Bus.snoop_fanout::mean 3.056115 # Request fanout histogram	1156system.cpu.toL2Bus.snoop_fanout::mean 1.056115 # Request fanout histogram
1157system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1159system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram	1157system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram 1158system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1159system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1160system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1162system.cpu.toL2Bus.snoop_fanout::3 21838103 94.39% 94.39% # Request fanout histogram 1163system.cpu.toL2Bus.snoop_fanout::4 1298291 5.61% 100.00% # Request fanout histogram	1160system.cpu.toL2Bus.snoop_fanout::1 21838103 94.39% 94.39% # Request fanout histogram 1161system.cpu.toL2Bus.snoop_fanout::2 1298291 5.61% 100.00% # Request fanout histogram
1164system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram	1162system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1165system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1166system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram	1163system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 1164system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1167system.cpu.toL2Bus.snoop_fanout::total 23136394 # Request fanout histogram 1168system.cpu.toL2Bus.reqLayer0.occupancy 15749679999 # Layer occupancy (ticks) 1169system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) 1170system.cpu.toL2Bus.respLayer0.occupancy 1817030 # Layer occupancy (ticks) 1171system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1172system.cpu.toL2Bus.respLayer1.occupancy 26101043977 # Layer occupancy (ticks) 1173system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) 1174system.membus.trans_dist::ReadReq 3736842 # Transaction distribution 1175system.membus.trans_dist::ReadResp 3736842 # Transaction distribution 1176system.membus.trans_dist::Writeback 1637857 # Transaction distribution 1177system.membus.trans_dist::ReadExReq 981309 # Transaction distribution 1178system.membus.trans_dist::ReadExResp 981309 # Transaction distribution 1179system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11074159 # Packet count per connected master and slave (bytes) 1180system.membus.pkt_count::total 11074159 # Packet count per connected master and slave (bytes) 1181system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406784512 # Cumulative packet size per connected master and slave (bytes) 1182system.membus.pkt_size::total 406784512 # Cumulative packet size per connected master and slave (bytes) 1183system.membus.snoops 0 # Total snoops (count) 1184system.membus.snoop_fanout::samples 6356008 # Request fanout histogram 1185system.membus.snoop_fanout::mean 0 # Request fanout histogram 1186system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1187system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1188system.membus.snoop_fanout::0 6356008 100.00% 100.00% # Request fanout histogram 1189system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1190system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1191system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1192system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1193system.membus.snoop_fanout::total 6356008 # Request fanout histogram 1194system.membus.reqLayer0.occupancy 14483850639 # Layer occupancy (ticks) 1195system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) 1196system.membus.respLayer1.occupancy 25655332661 # Layer occupancy (ticks) 1197system.membus.respLayer1.utilization 3.3 # Layer utilization (%) 1198 1199---------- End Simulation Statistics ----------	1165system.cpu.toL2Bus.snoop_fanout::total 23136394 # Request fanout histogram 1166system.cpu.toL2Bus.reqLayer0.occupancy 15749679999 # Layer occupancy (ticks) 1167system.cpu.toL2Bus.reqLayer0.utilization 2.0 # Layer utilization (%) 1168system.cpu.toL2Bus.respLayer0.occupancy 1817030 # Layer occupancy (ticks) 1169system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 1170system.cpu.toL2Bus.respLayer1.occupancy 26101043977 # Layer occupancy (ticks) 1171system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%) 1172system.membus.trans_dist::ReadReq 3736842 # Transaction distribution 1173system.membus.trans_dist::ReadResp 3736842 # Transaction distribution 1174system.membus.trans_dist::Writeback 1637857 # Transaction distribution 1175system.membus.trans_dist::ReadExReq 981309 # Transaction distribution 1176system.membus.trans_dist::ReadExResp 981309 # Transaction distribution 1177system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11074159 # Packet count per connected master and slave (bytes) 1178system.membus.pkt_count::total 11074159 # Packet count per connected master and slave (bytes) 1179system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406784512 # Cumulative packet size per connected master and slave (bytes) 1180system.membus.pkt_size::total 406784512 # Cumulative packet size per connected master and slave (bytes) 1181system.membus.snoops 0 # Total snoops (count) 1182system.membus.snoop_fanout::samples 6356008 # Request fanout histogram 1183system.membus.snoop_fanout::mean 0 # Request fanout histogram 1184system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1185system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1186system.membus.snoop_fanout::0 6356008 100.00% 100.00% # Request fanout histogram 1187system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1188system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1189system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1190system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1191system.membus.snoop_fanout::total 6356008 # Request fanout histogram 1192system.membus.reqLayer0.occupancy 14483850639 # Layer occupancy (ticks) 1193system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) 1194system.membus.respLayer1.occupancy 25655332661 # Layer occupancy (ticks) 1195system.membus.respLayer1.utilization 3.3 # Layer utilization (%) 1196 1197---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.771725 # Number of seconds simulated
4sim_ticks 771725169000 # Number of ticks simulated
5final_tick 771725169000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 109963 # Simulator instruction rate (inst/s)
8host_op_rate 118469 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 54942138 # Simulator tick rate (ticks/s)
10host_mem_usage 305172 # Number of bytes of host memory used
11host_seconds 14046.14 # Real time elapsed on the host

7host_inst_rate 137392 # Simulator instruction rate (inst/s)
8host_op_rate 148019 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 68646343 # Simulator tick rate (ticks/s)
10host_mem_usage 311812 # Number of bytes of host memory used
11host_seconds 11242.04 # Real time elapsed on the host

12sim_insts 1544563024 # Number of instructions simulated
13sim_ops 1664032416 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 238609216 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 63286144 # Number of bytes read from this memory
19system.physmem.bytes_read::total 301961664 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 104822848 # Number of bytes written to this memory
23system.physmem.bytes_written::total 104822848 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 3728269 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.l2cache.prefetcher 988846 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 4718151 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 1637857 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 1637857 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 85917 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 309189366 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.l2cache.prefetcher 82006065 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 391281347 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 85917 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 85917 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 135829246 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 135829246 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 135829246 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 85917 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 309189366 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.l2cache.prefetcher 82006065 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 527110594 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 4718151 # Number of read requests accepted
44system.physmem.writeReqs 1637857 # Number of write requests accepted
45system.physmem.readBursts 4718151 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 1637857 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 301519872 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 441792 # Total number of bytes read from write queue
49system.physmem.bytesWritten 104820544 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 301961664 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 104822848 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 6903 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 19 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 296668 # Per bank write bursts
56system.physmem.perBankRdBursts::1 294562 # Per bank write bursts
57system.physmem.perBankRdBursts::2 288307 # Per bank write bursts
58system.physmem.perBankRdBursts::3 292737 # Per bank write bursts
59system.physmem.perBankRdBursts::4 290232 # Per bank write bursts
60system.physmem.perBankRdBursts::5 289394 # Per bank write bursts
61system.physmem.perBankRdBursts::6 285167 # Per bank write bursts
62system.physmem.perBankRdBursts::7 280683 # Per bank write bursts
63system.physmem.perBankRdBursts::8 297292 # Per bank write bursts
64system.physmem.perBankRdBursts::9 302920 # Per bank write bursts
65system.physmem.perBankRdBursts::10 295430 # Per bank write bursts
66system.physmem.perBankRdBursts::11 301815 # Per bank write bursts
67system.physmem.perBankRdBursts::12 303322 # Per bank write bursts
68system.physmem.perBankRdBursts::13 302849 # Per bank write bursts
69system.physmem.perBankRdBursts::14 297025 # Per bank write bursts
70system.physmem.perBankRdBursts::15 292845 # Per bank write bursts
71system.physmem.perBankWrBursts::0 103942 # Per bank write bursts
72system.physmem.perBankWrBursts::1 102053 # Per bank write bursts
73system.physmem.perBankWrBursts::2 99317 # Per bank write bursts
74system.physmem.perBankWrBursts::3 99871 # Per bank write bursts
75system.physmem.perBankWrBursts::4 99169 # Per bank write bursts
76system.physmem.perBankWrBursts::5 98963 # Per bank write bursts
77system.physmem.perBankWrBursts::6 102735 # Per bank write bursts
78system.physmem.perBankWrBursts::7 104389 # Per bank write bursts
79system.physmem.perBankWrBursts::8 105226 # Per bank write bursts
80system.physmem.perBankWrBursts::9 104532 # Per bank write bursts
81system.physmem.perBankWrBursts::10 102159 # Per bank write bursts
82system.physmem.perBankWrBursts::11 102806 # Per bank write bursts
83system.physmem.perBankWrBursts::12 103028 # Per bank write bursts
84system.physmem.perBankWrBursts::13 102702 # Per bank write bursts
85system.physmem.perBankWrBursts::14 104263 # Per bank write bursts
86system.physmem.perBankWrBursts::15 102666 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89system.physmem.totGap 771725022000 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 4718151 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 1637857 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 2774626 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 1044189 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 331696 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 233512 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 153773 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 84990 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 39149 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 23715 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 18258 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 4255 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 1688 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 754 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 411 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 226 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
132system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
133system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
134system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
135system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
136system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 22760 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 24545 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 59860 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 75448 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 85202 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 93103 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 99273 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 103279 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 105460 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 106422 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 106536 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 107239 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 108154 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 110632 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 113547 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 106733 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 103419 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 101598 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 2778 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 1044 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 449 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 193 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 83 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 37 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 13 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 5 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 4287400 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 94.775232 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 78.917076 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 101.448471 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 3413764 79.62% 79.62% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 675374 15.75% 95.38% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 96809 2.26% 97.63% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 35249 0.82% 98.46% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 22885 0.53% 98.99% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 12087 0.28% 99.27% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 7187 0.17% 99.44% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 5043 0.12% 99.56% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 19002 0.44% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 4287400 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 98767 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 47.700609 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::gmean 32.313411 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::stdev 98.282358 # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::0-127 94950 96.14% 96.14% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::128-255 1367 1.38% 97.52% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::256-383 770 0.78% 98.30% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::384-511 428 0.43% 98.73% # Reads before turning the bus around for writes
222system.physmem.rdPerTurnAround::512-639 356 0.36% 99.09% # Reads before turning the bus around for writes
223system.physmem.rdPerTurnAround::640-767 374 0.38% 99.47% # Reads before turning the bus around for writes
224system.physmem.rdPerTurnAround::768-895 247 0.25% 99.72% # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::896-1023 145 0.15% 99.87% # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::1024-1151 66 0.07% 99.94% # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::1152-1279 31 0.03% 99.97% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::1280-1407 13 0.01% 99.98% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::1408-1535 9 0.01% 99.99% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::1536-1663 1 0.00% 99.99% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::1792-1919 1 0.00% 99.99% # Reads before turning the bus around for writes
232system.physmem.rdPerTurnAround::1920-2047 2 0.00% 99.99% # Reads before turning the bus around for writes
233system.physmem.rdPerTurnAround::2688-2815 1 0.00% 99.99% # Reads before turning the bus around for writes
234system.physmem.rdPerTurnAround::2944-3071 2 0.00% 100.00% # Reads before turning the bus around for writes
235system.physmem.rdPerTurnAround::3072-3199 2 0.00% 100.00% # Reads before turning the bus around for writes
236system.physmem.rdPerTurnAround::3200-3327 1 0.00% 100.00% # Reads before turning the bus around for writes
237system.physmem.rdPerTurnAround::3328-3455 1 0.00% 100.00% # Reads before turning the bus around for writes
238system.physmem.rdPerTurnAround::total 98767 # Reads before turning the bus around for writes
239system.physmem.wrPerTurnAround::samples 98767 # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::mean 16.582674 # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::gmean 16.549780 # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::stdev 1.086524 # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::16 73305 74.22% 74.22% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::17 1806 1.83% 76.05% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::18 18343 18.57% 94.62% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::19 3630 3.68% 98.30% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::20 937 0.95% 99.24% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::21 387 0.39% 99.64% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::22 162 0.16% 99.80% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::23 107 0.11% 99.91% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::24 60 0.06% 99.97% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::25 22 0.02% 99.99% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::26 6 0.01% 100.00% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::30 1 0.00% 100.00% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::total 98767 # Writes before turning the bus around for reads
257system.physmem.totQLat 132285118194 # Total ticks spent queuing
258system.physmem.totMemAccLat 220621018194 # Total ticks spent from burst creation until serviced by the DRAM
259system.physmem.totBusLat 23556240000 # Total ticks spent in databus transfers
260system.physmem.avgQLat 28078.57 # Average queueing delay per DRAM burst
261system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
262system.physmem.avgMemAccLat 46828.57 # Average memory access latency per DRAM burst
263system.physmem.avgRdBW 390.71 # Average DRAM read bandwidth in MiByte/s
264system.physmem.avgWrBW 135.83 # Average achieved write bandwidth in MiByte/s
265system.physmem.avgRdBWSys 391.28 # Average system read bandwidth in MiByte/s
266system.physmem.avgWrBWSys 135.83 # Average system write bandwidth in MiByte/s
267system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
268system.physmem.busUtil 4.11 # Data bus utilization in percentage
269system.physmem.busUtilRead 3.05 # Data bus utilization in percentage for reads
270system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes
271system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
272system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing
273system.physmem.readRowHits 1709073 # Number of row buffer hits during reads
274system.physmem.writeRowHits 352585 # Number of row buffer hits during writes
275system.physmem.readRowHitRate 36.28 # Row buffer hit rate for reads
276system.physmem.writeRowHitRate 21.53 # Row buffer hit rate for writes
277system.physmem.avgGap 121416.62 # Average gap between requests
278system.physmem.pageHitRate 32.47 # Row buffer hit rate, read and write combined
279system.physmem_0.actEnergy 16073195040 # Energy for activate commands per rank (pJ)
280system.physmem_0.preEnergy 8770096500 # Energy for precharge commands per rank (pJ)
281system.physmem_0.readEnergy 18077007000 # Energy for read commands per rank (pJ)
282system.physmem_0.writeEnergy 5251294800 # Energy for write commands per rank (pJ)
283system.physmem_0.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ)
284system.physmem_0.actBackEnergy 410674128390 # Energy for active background per rank (pJ)
285system.physmem_0.preBackEnergy 102790850250 # Energy for precharge background per rank (pJ)
286system.physmem_0.totalEnergy 612041479260 # Total energy per rank (pJ)
287system.physmem_0.averagePower 793.088667 # Core power per rank (mW)
288system.physmem_0.memoryStateTime::IDLE 168453702129 # Time in different power states
289system.physmem_0.memoryStateTime::REF 25769380000 # Time in different power states
290system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
291system.physmem_0.memoryStateTime::ACT 577496605871 # Time in different power states
292system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
293system.physmem_1.actEnergy 16339027320 # Energy for activate commands per rank (pJ)
294system.physmem_1.preEnergy 8915143875 # Energy for precharge commands per rank (pJ)
295system.physmem_1.readEnergy 18669222000 # Energy for read commands per rank (pJ)
296system.physmem_1.writeEnergy 5361163200 # Energy for write commands per rank (pJ)
297system.physmem_1.refreshEnergy 50404907280 # Energy for refresh commands per rank (pJ)
298system.physmem_1.actBackEnergy 412008151545 # Energy for active background per rank (pJ)
299system.physmem_1.preBackEnergy 101620654500 # Energy for precharge background per rank (pJ)
300system.physmem_1.totalEnergy 613318269720 # Total energy per rank (pJ)
301system.physmem_1.averagePower 794.743144 # Core power per rank (mW)
302system.physmem_1.memoryStateTime::IDLE 166509885283 # Time in different power states
303system.physmem_1.memoryStateTime::REF 25769380000 # Time in different power states
304system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
305system.physmem_1.memoryStateTime::ACT 579440435717 # Time in different power states
306system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
307system.cpu.branchPred.lookups 286277860 # Number of BP lookups
308system.cpu.branchPred.condPredicted 223409255 # Number of conditional branches predicted
309system.cpu.branchPred.condIncorrect 14633591 # Number of conditional branches incorrect
310system.cpu.branchPred.BTBLookups 157407621 # Number of BTB lookups
311system.cpu.branchPred.BTBHits 150346120 # Number of BTB hits
312system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
313system.cpu.branchPred.BTBHitPct 95.513876 # BTB Hit Percentage
314system.cpu.branchPred.usedRAS 16641206 # Number of times the RAS was used to get a target.
315system.cpu.branchPred.RASInCorrect 65 # Number of incorrect RAS predictions.
316system.cpu_clk_domain.clock 500 # Clock period in ticks
317system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
324system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
325system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
326system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
327system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
328system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
329system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
330system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
331system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
332system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
333system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
334system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
335system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
336system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
337system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
338system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
339system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
340system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
341system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
342system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
343system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
344system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
345system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
346system.cpu.dtb.walker.walks 0 # Table walker walks requested
347system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
348system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
349system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
350system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
351system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
352system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
353system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
354system.cpu.dtb.inst_hits 0 # ITB inst hits
355system.cpu.dtb.inst_misses 0 # ITB inst misses
356system.cpu.dtb.read_hits 0 # DTB read hits
357system.cpu.dtb.read_misses 0 # DTB read misses
358system.cpu.dtb.write_hits 0 # DTB write hits
359system.cpu.dtb.write_misses 0 # DTB write misses
360system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
361system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
362system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
363system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
364system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
365system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
366system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
367system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
368system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
369system.cpu.dtb.read_accesses 0 # DTB read accesses
370system.cpu.dtb.write_accesses 0 # DTB write accesses
371system.cpu.dtb.inst_accesses 0 # ITB inst accesses
372system.cpu.dtb.hits 0 # DTB hits
373system.cpu.dtb.misses 0 # DTB misses
374system.cpu.dtb.accesses 0 # DTB accesses
375system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
381system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
382system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
383system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
384system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
385system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
386system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
387system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
388system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
389system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
390system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
391system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
392system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
393system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
394system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
395system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
396system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
397system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
398system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
399system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
400system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
401system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
402system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
403system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
404system.cpu.itb.walker.walks 0 # Table walker walks requested
405system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
406system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
407system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
408system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
409system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
410system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
411system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
412system.cpu.itb.inst_hits 0 # ITB inst hits
413system.cpu.itb.inst_misses 0 # ITB inst misses
414system.cpu.itb.read_hits 0 # DTB read hits
415system.cpu.itb.read_misses 0 # DTB read misses
416system.cpu.itb.write_hits 0 # DTB write hits
417system.cpu.itb.write_misses 0 # DTB write misses
418system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
419system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
420system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
421system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
422system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
423system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
424system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
425system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
426system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
427system.cpu.itb.read_accesses 0 # DTB read accesses
428system.cpu.itb.write_accesses 0 # DTB write accesses
429system.cpu.itb.inst_accesses 0 # ITB inst accesses
430system.cpu.itb.hits 0 # DTB hits
431system.cpu.itb.misses 0 # DTB misses
432system.cpu.itb.accesses 0 # DTB accesses
433system.cpu.workload.num_syscalls 46 # Number of system calls
434system.cpu.numCycles 1543450339 # number of cpu cycles simulated
435system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
436system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
437system.cpu.fetch.icacheStallCycles 13927699 # Number of cycles fetch is stalled on an Icache miss
438system.cpu.fetch.Insts 2067517377 # Number of instructions fetch has processed
439system.cpu.fetch.Branches 286277860 # Number of branches that fetch encountered
440system.cpu.fetch.predictedBranches 166987326 # Number of branches that fetch has predicted taken
441system.cpu.fetch.Cycles 1514795150 # Number of cycles fetch has run and was not squashing or blocked
442system.cpu.fetch.SquashCycles 29291799 # Number of cycles fetch has spent squashing
443system.cpu.fetch.MiscStallCycles 180 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
444system.cpu.fetch.IcacheWaitRetryStallCycles 907 # Number of stall cycles due to full MSHR
445system.cpu.fetch.CacheLines 656942032 # Number of cache lines fetched
446system.cpu.fetch.IcacheSquashes 957 # Number of outstanding Icache misses that were squashed
447system.cpu.fetch.rateDist::samples 1543369835 # Number of instructions fetched each cycle (Total)
448system.cpu.fetch.rateDist::mean 1.435149 # Number of instructions fetched each cycle (Total)
449system.cpu.fetch.rateDist::stdev 1.229340 # Number of instructions fetched each cycle (Total)
450system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
451system.cpu.fetch.rateDist::0 460957271 29.87% 29.87% # Number of instructions fetched each cycle (Total)
452system.cpu.fetch.rateDist::1 465455811 30.16% 60.03% # Number of instructions fetched each cycle (Total)
453system.cpu.fetch.rateDist::2 101360614 6.57% 66.59% # Number of instructions fetched each cycle (Total)
454system.cpu.fetch.rateDist::3 515596139 33.41% 100.00% # Number of instructions fetched each cycle (Total)
455system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
456system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
457system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
458system.cpu.fetch.rateDist::total 1543369835 # Number of instructions fetched each cycle (Total)
459system.cpu.fetch.branchRate 0.185479 # Number of branch fetches per cycle
460system.cpu.fetch.rate 1.339543 # Number of inst fetches per cycle
461system.cpu.decode.IdleCycles 74619350 # Number of cycles decode is idle
462system.cpu.decode.BlockedCycles 545977788 # Number of cycles decode is blocked
463system.cpu.decode.RunCycles 850086533 # Number of cycles decode is running
464system.cpu.decode.UnblockCycles 58040967 # Number of cycles decode is unblocking
465system.cpu.decode.SquashCycles 14645197 # Number of cycles decode is squashing
466system.cpu.decode.BranchResolved 42200501 # Number of times decode resolved a branch
467system.cpu.decode.BranchMispred 754 # Number of times decode detected a branch misprediction
468system.cpu.decode.DecodedInsts 2037190940 # Number of instructions handled by decode
469system.cpu.decode.SquashedInsts 52475133 # Number of squashed instructions handled by decode
470system.cpu.rename.SquashCycles 14645197 # Number of cycles rename is squashing
471system.cpu.rename.IdleCycles 139685845 # Number of cycles rename is idle
472system.cpu.rename.BlockCycles 464851768 # Number of cycles rename is blocking
473system.cpu.rename.serializeStallCycles 13523 # count of cycles rename stalled for serializing inst
474system.cpu.rename.RunCycles 837895691 # Number of cycles rename is running
475system.cpu.rename.UnblockCycles 86277811 # Number of cycles rename is unblocking
476system.cpu.rename.RenamedInsts 1976364426 # Number of instructions processed by rename
477system.cpu.rename.SquashedInsts 26735694 # Number of squashed instructions processed by rename
478system.cpu.rename.ROBFullEvents 45105241 # Number of times rename has blocked due to ROB full
479system.cpu.rename.IQFullEvents 125505 # Number of times rename has blocked due to IQ full
480system.cpu.rename.LQFullEvents 1481556 # Number of times rename has blocked due to LQ full
481system.cpu.rename.SQFullEvents 25500508 # Number of times rename has blocked due to SQ full
482system.cpu.rename.RenamedOperands 1985835865 # Number of destination operands rename has renamed
483system.cpu.rename.RenameLookups 9128071192 # Number of register rename lookups that rename has made
484system.cpu.rename.int_rename_lookups 2432849079 # Number of integer rename lookups
485system.cpu.rename.fp_rename_lookups 136 # Number of floating rename lookups
486system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
487system.cpu.rename.UndoneMaps 310936920 # Number of HB maps that are undone due to squashing
488system.cpu.rename.serializingInsts 149 # count of serializing insts renamed
489system.cpu.rename.tempSerializingInsts 140 # count of temporary serializing insts renamed
490system.cpu.rename.skidInsts 111342876 # count of insts added to the skid buffer
491system.cpu.memDep0.insertedLoads 542549398 # Number of loads inserted to the mem dependence unit.
492system.cpu.memDep0.insertedStores 199301403 # Number of stores inserted to the mem dependence unit.
493system.cpu.memDep0.conflictingLoads 26926926 # Number of conflicting loads.
494system.cpu.memDep0.conflictingStores 29153523 # Number of conflicting stores.
495system.cpu.iq.iqInstsAdded 1947926711 # Number of instructions added to the IQ (excludes non-spec)
496system.cpu.iq.iqNonSpecInstsAdded 208 # Number of non-speculative instructions added to the IQ
497system.cpu.iq.iqInstsIssued 1857446823 # Number of instructions issued
498system.cpu.iq.iqSquashedInstsIssued 13498178 # Number of squashed instructions issued
499system.cpu.iq.iqSquashedInstsExamined 283894503 # Number of squashed instructions iterated over during squash; mainly for profiling
500system.cpu.iq.iqSquashedOperandsExamined 646939215 # Number of squashed operands that are examined and possibly removed from graph
501system.cpu.iq.iqSquashedNonSpecRemoved 38 # Number of squashed non-spec instructions that were removed
502system.cpu.iq.issued_per_cycle::samples 1543369835 # Number of insts issued each cycle
503system.cpu.iq.issued_per_cycle::mean 1.203501 # Number of insts issued each cycle
504system.cpu.iq.issued_per_cycle::stdev 1.151095 # Number of insts issued each cycle
505system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
506system.cpu.iq.issued_per_cycle::0 590630846 38.27% 38.27% # Number of insts issued each cycle
507system.cpu.iq.issued_per_cycle::1 325771475 21.11% 59.38% # Number of insts issued each cycle
508system.cpu.iq.issued_per_cycle::2 378267234 24.51% 83.89% # Number of insts issued each cycle
509system.cpu.iq.issued_per_cycle::3 219666416 14.23% 98.12% # Number of insts issued each cycle
510system.cpu.iq.issued_per_cycle::4 29027688 1.88% 100.00% # Number of insts issued each cycle
511system.cpu.iq.issued_per_cycle::5 6176 0.00% 100.00% # Number of insts issued each cycle
512system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
513system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
514system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
515system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
516system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
517system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
518system.cpu.iq.issued_per_cycle::total 1543369835 # Number of insts issued each cycle
519system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
520system.cpu.iq.fu_full::IntAlu 166059149 40.99% 40.99% # attempts to use FU when none available
521system.cpu.iq.fu_full::IntMult 1996 0.00% 40.99% # attempts to use FU when none available
522system.cpu.iq.fu_full::IntDiv 0 0.00% 40.99% # attempts to use FU when none available
523system.cpu.iq.fu_full::FloatAdd 0 0.00% 40.99% # attempts to use FU when none available
524system.cpu.iq.fu_full::FloatCmp 0 0.00% 40.99% # attempts to use FU when none available
525system.cpu.iq.fu_full::FloatCvt 0 0.00% 40.99% # attempts to use FU when none available
526system.cpu.iq.fu_full::FloatMult 0 0.00% 40.99% # attempts to use FU when none available
527system.cpu.iq.fu_full::FloatDiv 0 0.00% 40.99% # attempts to use FU when none available
528system.cpu.iq.fu_full::FloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
529system.cpu.iq.fu_full::SimdAdd 0 0.00% 40.99% # attempts to use FU when none available
530system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 40.99% # attempts to use FU when none available
531system.cpu.iq.fu_full::SimdAlu 0 0.00% 40.99% # attempts to use FU when none available
532system.cpu.iq.fu_full::SimdCmp 0 0.00% 40.99% # attempts to use FU when none available
533system.cpu.iq.fu_full::SimdCvt 0 0.00% 40.99% # attempts to use FU when none available
534system.cpu.iq.fu_full::SimdMisc 0 0.00% 40.99% # attempts to use FU when none available
535system.cpu.iq.fu_full::SimdMult 0 0.00% 40.99% # attempts to use FU when none available
536system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 40.99% # attempts to use FU when none available
537system.cpu.iq.fu_full::SimdShift 0 0.00% 40.99% # attempts to use FU when none available
538system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 40.99% # attempts to use FU when none available
539system.cpu.iq.fu_full::SimdSqrt 0 0.00% 40.99% # attempts to use FU when none available
540system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 40.99% # attempts to use FU when none available
541system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 40.99% # attempts to use FU when none available
542system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 40.99% # attempts to use FU when none available
543system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 40.99% # attempts to use FU when none available
544system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 40.99% # attempts to use FU when none available
545system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 40.99% # attempts to use FU when none available
546system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 40.99% # attempts to use FU when none available
547system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.99% # attempts to use FU when none available
548system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 40.99% # attempts to use FU when none available
549system.cpu.iq.fu_full::MemRead 191393147 47.24% 88.23% # attempts to use FU when none available
550system.cpu.iq.fu_full::MemWrite 47682914 11.77% 100.00% # attempts to use FU when none available
551system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
552system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
553system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
554system.cpu.iq.FU_type_0::IntAlu 1138268714 61.28% 61.28% # Type of FU issued
555system.cpu.iq.FU_type_0::IntMult 801071 0.04% 61.32% # Type of FU issued
556system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
557system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
558system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
559system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
560system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
561system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
562system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
563system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued
564system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.32% # Type of FU issued
565system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.32% # Type of FU issued
566system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.32% # Type of FU issued
567system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.32% # Type of FU issued
568system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.32% # Type of FU issued
569system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
570system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
571system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
572system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
573system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
574system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
575system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
576system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
577system.cpu.iq.FU_type_0::SimdFloatCvt 28 0.00% 61.32% # Type of FU issued
578system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
579system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
580system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
581system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
582system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
583system.cpu.iq.FU_type_0::MemRead 532058987 28.64% 89.97% # Type of FU issued
584system.cpu.iq.FU_type_0::MemWrite 186318001 10.03% 100.00% # Type of FU issued
585system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
586system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
587system.cpu.iq.FU_type_0::total 1857446823 # Type of FU issued
588system.cpu.iq.rate 1.203438 # Inst issue rate
589system.cpu.iq.fu_busy_cnt 405137206 # FU busy when requested
590system.cpu.iq.fu_busy_rate 0.218115 # FU busy rate (busy events/executed inst)
591system.cpu.iq.int_inst_queue_reads 5676898637 # Number of integer instruction queue reads
592system.cpu.iq.int_inst_queue_writes 2231834122 # Number of integer instruction queue writes
593system.cpu.iq.int_inst_queue_wakeup_accesses 1805736851 # Number of integer instruction queue wakeup accesses
594system.cpu.iq.fp_inst_queue_reads 228 # Number of floating instruction queue reads
595system.cpu.iq.fp_inst_queue_writes 232 # Number of floating instruction queue writes
596system.cpu.iq.fp_inst_queue_wakeup_accesses 68 # Number of floating instruction queue wakeup accesses
597system.cpu.iq.int_alu_accesses 2262583902 # Number of integer alu accesses
598system.cpu.iq.fp_alu_accesses 127 # Number of floating point alu accesses
599system.cpu.iew.lsq.thread0.forwLoads 17817639 # Number of loads that had data forwarded from stores
600system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
601system.cpu.iew.lsq.thread0.squashedLoads 84243064 # Number of loads squashed
602system.cpu.iew.lsq.thread0.ignoredResponses 66651 # Number of memory responses ignored because the instruction is squashed
603system.cpu.iew.lsq.thread0.memOrderViolation 13168 # Number of memory ordering violations
604system.cpu.iew.lsq.thread0.squashedStores 24454358 # Number of stores squashed
605system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
606system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
607system.cpu.iew.lsq.thread0.rescheduledLoads 4525889 # Number of loads that were rescheduled
608system.cpu.iew.lsq.thread0.cacheBlocked 4805394 # Number of times an access to memory failed due to the cache being blocked
609system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
610system.cpu.iew.iewSquashCycles 14645197 # Number of cycles IEW is squashing
611system.cpu.iew.iewBlockCycles 25323327 # Number of cycles IEW is blocking
612system.cpu.iew.iewUnblockCycles 1332663 # Number of cycles IEW is unblocking
613system.cpu.iew.iewDispatchedInsts 1947926995 # Number of instructions dispatched to IQ
614system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
615system.cpu.iew.iewDispLoadInsts 542549398 # Number of dispatched load instructions
616system.cpu.iew.iewDispStoreInsts 199301403 # Number of dispatched store instructions
617system.cpu.iew.iewDispNonSpecInsts 146 # Number of dispatched non-speculative instructions
618system.cpu.iew.iewIQFullEvents 158839 # Number of times the IQ has become full, causing a stall
619system.cpu.iew.iewLSQFullEvents 1172731 # Number of times the LSQ has become full, causing a stall
620system.cpu.iew.memOrderViolationEvents 13168 # Number of memory order violations
621system.cpu.iew.predictedTakenIncorrect 7701738 # Number of branches that were predicted taken incorrectly
622system.cpu.iew.predictedNotTakenIncorrect 8706499 # Number of branches that were predicted not taken incorrectly
623system.cpu.iew.branchMispredicts 16408237 # Number of branch mispredicts detected at execute
624system.cpu.iew.iewExecutedInsts 1827783249 # Number of executed instructions
625system.cpu.iew.iewExecLoadInsts 516881888 # Number of load instructions executed
626system.cpu.iew.iewExecSquashedInsts 29663574 # Number of squashed instructions skipped in execute
627system.cpu.iew.exec_swp 0 # number of swp insts executed
628system.cpu.iew.exec_nop 76 # number of nop insts executed
629system.cpu.iew.exec_refs 698636146 # number of memory reference insts executed
630system.cpu.iew.exec_branches 229555717 # Number of branches executed
631system.cpu.iew.exec_stores 181754258 # Number of stores executed
632system.cpu.iew.exec_rate 1.184219 # Inst execution rate
633system.cpu.iew.wb_sent 1808767141 # cumulative count of insts sent to commit
634system.cpu.iew.wb_count 1805736919 # cumulative count of insts written-back
635system.cpu.iew.wb_producers 1169322951 # num instructions producing a value
636system.cpu.iew.wb_consumers 1689713401 # num instructions consuming a value
637system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
638system.cpu.iew.wb_rate 1.169935 # insts written-back per cycle
639system.cpu.iew.wb_fanout 0.692024 # average fanout of values written-back
640system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
641system.cpu.commit.commitSquashedInsts 258002520 # The number of squashed insts skipped by commit
642system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
643system.cpu.commit.branchMispredicts 14632889 # The number of times a branch was mispredicted
644system.cpu.commit.committed_per_cycle::samples 1503882923 # Number of insts commited each cycle
645system.cpu.commit.committed_per_cycle::mean 1.106491 # Number of insts commited each cycle
646system.cpu.commit.committed_per_cycle::stdev 2.024391 # Number of insts commited each cycle
647system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
648system.cpu.commit.committed_per_cycle::0 923604765 61.41% 61.41% # Number of insts commited each cycle
649system.cpu.commit.committed_per_cycle::1 250635322 16.67% 78.08% # Number of insts commited each cycle
650system.cpu.commit.committed_per_cycle::2 110056363 7.32% 85.40% # Number of insts commited each cycle
651system.cpu.commit.committed_per_cycle::3 55280526 3.68% 89.07% # Number of insts commited each cycle
652system.cpu.commit.committed_per_cycle::4 29292132 1.95% 91.02% # Number of insts commited each cycle
653system.cpu.commit.committed_per_cycle::5 34092515 2.27% 93.29% # Number of insts commited each cycle
654system.cpu.commit.committed_per_cycle::6 24716046 1.64% 94.93% # Number of insts commited each cycle
655system.cpu.commit.committed_per_cycle::7 18126603 1.21% 96.14% # Number of insts commited each cycle
656system.cpu.commit.committed_per_cycle::8 58078651 3.86% 100.00% # Number of insts commited each cycle
657system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
658system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
659system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
660system.cpu.commit.committed_per_cycle::total 1503882923 # Number of insts commited each cycle
661system.cpu.commit.committedInsts 1544563042 # Number of instructions committed
662system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed
663system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
664system.cpu.commit.refs 633153379 # Number of memory references committed
665system.cpu.commit.loads 458306334 # Number of loads committed
666system.cpu.commit.membars 62 # Number of memory barriers committed
667system.cpu.commit.branches 213462427 # Number of branches committed
668system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.
669system.cpu.commit.int_insts 1477900421 # Number of committed integer instructions.
670system.cpu.commit.function_calls 13665177 # Number of function calls committed.
671system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
672system.cpu.commit.op_class_0::IntAlu 1030178730 61.91% 61.91% # Class of committed instruction
673system.cpu.commit.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction
674system.cpu.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction
675system.cpu.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction
676system.cpu.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction
677system.cpu.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction
678system.cpu.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction
679system.cpu.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction
680system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction
681system.cpu.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction
682system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction
683system.cpu.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction
684system.cpu.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction
685system.cpu.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction
686system.cpu.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction
687system.cpu.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction
688system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction
689system.cpu.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction
690system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction
691system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction
692system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction
693system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction
694system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction
695system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction
696system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction
697system.cpu.commit.op_class_0::SimdFloatMisc 3 0.00% 61.95% # Class of committed instruction
698system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
699system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
700system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
701system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
702system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
703system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
704system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
705system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction
706system.cpu.commit.bw_lim_events 58078651 # number cycles where commit BW limit reached
707system.cpu.rob.rob_reads 3367838627 # The number of ROB reads
708system.cpu.rob.rob_writes 3883562090 # The number of ROB writes
709system.cpu.timesIdled 851 # Number of times that the entire CPU went into an idle state and unscheduled itself
710system.cpu.idleCycles 80504 # Total number of cycles that the CPU has spent unscheduled due to idling
711system.cpu.committedInsts 1544563024 # Number of Instructions Simulated
712system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated
713system.cpu.cpi 0.999280 # CPI: Cycles Per Instruction
714system.cpu.cpi_total 0.999280 # CPI: Total CPI of All Threads
715system.cpu.ipc 1.000721 # IPC: Instructions Per Cycle
716system.cpu.ipc_total 1.000721 # IPC: Total IPC of All Threads
717system.cpu.int_regfile_reads 2175739809 # number of integer regfile reads
718system.cpu.int_regfile_writes 1261583749 # number of integer regfile writes
719system.cpu.fp_regfile_reads 38 # number of floating regfile reads
720system.cpu.fp_regfile_writes 50 # number of floating regfile writes
721system.cpu.cc_regfile_reads 6965641029 # number of cc regfile reads
722system.cpu.cc_regfile_writes 551880821 # number of cc regfile writes
723system.cpu.misc_regfile_reads 675853491 # number of misc regfile reads
724system.cpu.misc_regfile_writes 124 # number of misc regfile writes
725system.cpu.dcache.tags.replacements 17005885 # number of replacements
726system.cpu.dcache.tags.tagsinuse 511.964949 # Cycle average of tags in use
727system.cpu.dcache.tags.total_refs 638186886 # Total number of references to valid blocks.
728system.cpu.dcache.tags.sampled_refs 17006397 # Sample count of references to valid blocks.
729system.cpu.dcache.tags.avg_refs 37.526284 # Average number of references to valid blocks.
730system.cpu.dcache.tags.warmup_cycle 78340000 # Cycle when the warmup percentage was hit.
731system.cpu.dcache.tags.occ_blocks::cpu.data 511.964949 # Average occupied blocks per requestor
732system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy
733system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy
734system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
735system.cpu.dcache.tags.age_task_id_blocks_1024::0 423 # Occupied blocks per task id
736system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id
737system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
738system.cpu.dcache.tags.tag_accesses 1335687679 # Number of tag accesses
739system.cpu.dcache.tags.data_accesses 1335687679 # Number of data accesses
740system.cpu.dcache.ReadReq_hits::cpu.data 469400845 # number of ReadReq hits
741system.cpu.dcache.ReadReq_hits::total 469400845 # number of ReadReq hits
742system.cpu.dcache.WriteReq_hits::cpu.data 168785923 # number of WriteReq hits
743system.cpu.dcache.WriteReq_hits::total 168785923 # number of WriteReq hits
744system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
745system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
746system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
747system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
748system.cpu.dcache.demand_hits::cpu.data 638186768 # number of demand (read+write) hits
749system.cpu.dcache.demand_hits::total 638186768 # number of demand (read+write) hits
750system.cpu.dcache.overall_hits::cpu.data 638186768 # number of overall hits
751system.cpu.dcache.overall_hits::total 638186768 # number of overall hits
752system.cpu.dcache.ReadReq_misses::cpu.data 17353625 # number of ReadReq misses
753system.cpu.dcache.ReadReq_misses::total 17353625 # number of ReadReq misses
754system.cpu.dcache.WriteReq_misses::cpu.data 3800124 # number of WriteReq misses
755system.cpu.dcache.WriteReq_misses::total 3800124 # number of WriteReq misses
756system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
757system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
758system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
759system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
760system.cpu.dcache.demand_misses::cpu.data 21153749 # number of demand (read+write) misses
761system.cpu.dcache.demand_misses::total 21153749 # number of demand (read+write) misses
762system.cpu.dcache.overall_misses::cpu.data 21153751 # number of overall misses
763system.cpu.dcache.overall_misses::total 21153751 # number of overall misses
764system.cpu.dcache.ReadReq_miss_latency::cpu.data 417050356298 # number of ReadReq miss cycles
765system.cpu.dcache.ReadReq_miss_latency::total 417050356298 # number of ReadReq miss cycles
766system.cpu.dcache.WriteReq_miss_latency::cpu.data 149886013526 # number of WriteReq miss cycles
767system.cpu.dcache.WriteReq_miss_latency::total 149886013526 # number of WriteReq miss cycles
768system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 204500 # number of LoadLockedReq miss cycles
769system.cpu.dcache.LoadLockedReq_miss_latency::total 204500 # number of LoadLockedReq miss cycles
770system.cpu.dcache.demand_miss_latency::cpu.data 566936369824 # number of demand (read+write) miss cycles
771system.cpu.dcache.demand_miss_latency::total 566936369824 # number of demand (read+write) miss cycles
772system.cpu.dcache.overall_miss_latency::cpu.data 566936369824 # number of overall miss cycles
773system.cpu.dcache.overall_miss_latency::total 566936369824 # number of overall miss cycles
774system.cpu.dcache.ReadReq_accesses::cpu.data 486754470 # number of ReadReq accesses(hits+misses)
775system.cpu.dcache.ReadReq_accesses::total 486754470 # number of ReadReq accesses(hits+misses)
776system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
777system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
778system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
779system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
780system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
781system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
782system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
783system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
784system.cpu.dcache.demand_accesses::cpu.data 659340517 # number of demand (read+write) accesses
785system.cpu.dcache.demand_accesses::total 659340517 # number of demand (read+write) accesses
786system.cpu.dcache.overall_accesses::cpu.data 659340519 # number of overall (read+write) accesses
787system.cpu.dcache.overall_accesses::total 659340519 # number of overall (read+write) accesses
788system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035652 # miss rate for ReadReq accesses
789system.cpu.dcache.ReadReq_miss_rate::total 0.035652 # miss rate for ReadReq accesses
790system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022019 # miss rate for WriteReq accesses
791system.cpu.dcache.WriteReq_miss_rate::total 0.022019 # miss rate for WriteReq accesses
792system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
793system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
794system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
795system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
796system.cpu.dcache.demand_miss_rate::cpu.data 0.032083 # miss rate for demand accesses
797system.cpu.dcache.demand_miss_rate::total 0.032083 # miss rate for demand accesses
798system.cpu.dcache.overall_miss_rate::cpu.data 0.032083 # miss rate for overall accesses
799system.cpu.dcache.overall_miss_rate::total 0.032083 # miss rate for overall accesses
800system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24032.463321 # average ReadReq miss latency
801system.cpu.dcache.ReadReq_avg_miss_latency::total 24032.463321 # average ReadReq miss latency
802system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39442.400702 # average WriteReq miss latency
803system.cpu.dcache.WriteReq_avg_miss_latency::total 39442.400702 # average WriteReq miss latency
804system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51125 # average LoadLockedReq miss latency
805system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51125 # average LoadLockedReq miss latency
806system.cpu.dcache.demand_avg_miss_latency::cpu.data 26800.751480 # average overall miss latency
807system.cpu.dcache.demand_avg_miss_latency::total 26800.751480 # average overall miss latency
808system.cpu.dcache.overall_avg_miss_latency::cpu.data 26800.748946 # average overall miss latency
809system.cpu.dcache.overall_avg_miss_latency::total 26800.748946 # average overall miss latency
810system.cpu.dcache.blocked_cycles::no_mshrs 20736521 # number of cycles access was blocked
811system.cpu.dcache.blocked_cycles::no_targets 3309459 # number of cycles access was blocked
812system.cpu.dcache.blocked::no_mshrs 945396 # number of cycles access was blocked
813system.cpu.dcache.blocked::no_targets 67047 # number of cycles access was blocked
814system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.934217 # average number of cycles each access was blocked
815system.cpu.dcache.avg_blocked_cycles::no_targets 49.360285 # average number of cycles each access was blocked
816system.cpu.dcache.fast_writes 0 # number of fast writes performed
817system.cpu.dcache.cache_copies 0 # number of cache copies performed
818system.cpu.dcache.writebacks::writebacks 4830628 # number of writebacks
819system.cpu.dcache.writebacks::total 4830628 # number of writebacks
820system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3084713 # number of ReadReq MSHR hits
821system.cpu.dcache.ReadReq_mshr_hits::total 3084713 # number of ReadReq MSHR hits
822system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1062640 # number of WriteReq MSHR hits
823system.cpu.dcache.WriteReq_mshr_hits::total 1062640 # number of WriteReq MSHR hits
824system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
825system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
826system.cpu.dcache.demand_mshr_hits::cpu.data 4147353 # number of demand (read+write) MSHR hits
827system.cpu.dcache.demand_mshr_hits::total 4147353 # number of demand (read+write) MSHR hits
828system.cpu.dcache.overall_mshr_hits::cpu.data 4147353 # number of overall MSHR hits
829system.cpu.dcache.overall_mshr_hits::total 4147353 # number of overall MSHR hits
830system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14268912 # number of ReadReq MSHR misses
831system.cpu.dcache.ReadReq_mshr_misses::total 14268912 # number of ReadReq MSHR misses
832system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737484 # number of WriteReq MSHR misses
833system.cpu.dcache.WriteReq_mshr_misses::total 2737484 # number of WriteReq MSHR misses
834system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
835system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
836system.cpu.dcache.demand_mshr_misses::cpu.data 17006396 # number of demand (read+write) MSHR misses
837system.cpu.dcache.demand_mshr_misses::total 17006396 # number of demand (read+write) MSHR misses
838system.cpu.dcache.overall_mshr_misses::cpu.data 17006397 # number of overall MSHR misses
839system.cpu.dcache.overall_mshr_misses::total 17006397 # number of overall MSHR misses
840system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 328919129806 # number of ReadReq MSHR miss cycles
841system.cpu.dcache.ReadReq_mshr_miss_latency::total 328919129806 # number of ReadReq MSHR miss cycles
842system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 115124697729 # number of WriteReq MSHR miss cycles
843system.cpu.dcache.WriteReq_mshr_miss_latency::total 115124697729 # number of WriteReq MSHR miss cycles
844system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 67750 # number of SoftPFReq MSHR miss cycles
845system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 67750 # number of SoftPFReq MSHR miss cycles
846system.cpu.dcache.demand_mshr_miss_latency::cpu.data 444043827535 # number of demand (read+write) MSHR miss cycles
847system.cpu.dcache.demand_mshr_miss_latency::total 444043827535 # number of demand (read+write) MSHR miss cycles
848system.cpu.dcache.overall_mshr_miss_latency::cpu.data 444043895285 # number of overall MSHR miss cycles
849system.cpu.dcache.overall_mshr_miss_latency::total 444043895285 # number of overall MSHR miss cycles
850system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029314 # mshr miss rate for ReadReq accesses
851system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029314 # mshr miss rate for ReadReq accesses
852system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
853system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
854system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
855system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
856system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for demand accesses
857system.cpu.dcache.demand_mshr_miss_rate::total 0.025793 # mshr miss rate for demand accesses
858system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025793 # mshr miss rate for overall accesses
859system.cpu.dcache.overall_mshr_miss_rate::total 0.025793 # mshr miss rate for overall accesses
860system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23051.451281 # average ReadReq mshr miss latency
861system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23051.451281 # average ReadReq mshr miss latency
862system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42054.929902 # average WriteReq mshr miss latency
863system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42054.929902 # average WriteReq mshr miss latency
864system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 67750 # average SoftPFReq mshr miss latency
865system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 67750 # average SoftPFReq mshr miss latency
866system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.401495 # average overall mshr miss latency
867system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.401495 # average overall mshr miss latency
868system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.403943 # average overall mshr miss latency
869system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.403943 # average overall mshr miss latency
870system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
871system.cpu.icache.tags.replacements 589 # number of replacements
872system.cpu.icache.tags.tagsinuse 446.078018 # Cycle average of tags in use
873system.cpu.icache.tags.total_refs 656940406 # Total number of references to valid blocks.
874system.cpu.icache.tags.sampled_refs 1077 # Sample count of references to valid blocks.
875system.cpu.icache.tags.avg_refs 609972.521820 # Average number of references to valid blocks.
876system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
877system.cpu.icache.tags.occ_blocks::cpu.inst 446.078018 # Average occupied blocks per requestor
878system.cpu.icache.tags.occ_percent::cpu.inst 0.871246 # Average percentage of cache occupancy
879system.cpu.icache.tags.occ_percent::total 0.871246 # Average percentage of cache occupancy
880system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id
881system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
882system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
883system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id
884system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id
885system.cpu.icache.tags.tag_accesses 1313885139 # Number of tag accesses
886system.cpu.icache.tags.data_accesses 1313885139 # Number of data accesses
887system.cpu.icache.ReadReq_hits::cpu.inst 656940406 # number of ReadReq hits
888system.cpu.icache.ReadReq_hits::total 656940406 # number of ReadReq hits
889system.cpu.icache.demand_hits::cpu.inst 656940406 # number of demand (read+write) hits
890system.cpu.icache.demand_hits::total 656940406 # number of demand (read+write) hits
891system.cpu.icache.overall_hits::cpu.inst 656940406 # number of overall hits
892system.cpu.icache.overall_hits::total 656940406 # number of overall hits
893system.cpu.icache.ReadReq_misses::cpu.inst 1625 # number of ReadReq misses
894system.cpu.icache.ReadReq_misses::total 1625 # number of ReadReq misses
895system.cpu.icache.demand_misses::cpu.inst 1625 # number of demand (read+write) misses
896system.cpu.icache.demand_misses::total 1625 # number of demand (read+write) misses
897system.cpu.icache.overall_misses::cpu.inst 1625 # number of overall misses
898system.cpu.icache.overall_misses::total 1625 # number of overall misses
899system.cpu.icache.ReadReq_miss_latency::cpu.inst 105016775 # number of ReadReq miss cycles
900system.cpu.icache.ReadReq_miss_latency::total 105016775 # number of ReadReq miss cycles
901system.cpu.icache.demand_miss_latency::cpu.inst 105016775 # number of demand (read+write) miss cycles
902system.cpu.icache.demand_miss_latency::total 105016775 # number of demand (read+write) miss cycles
903system.cpu.icache.overall_miss_latency::cpu.inst 105016775 # number of overall miss cycles
904system.cpu.icache.overall_miss_latency::total 105016775 # number of overall miss cycles
905system.cpu.icache.ReadReq_accesses::cpu.inst 656942031 # number of ReadReq accesses(hits+misses)
906system.cpu.icache.ReadReq_accesses::total 656942031 # number of ReadReq accesses(hits+misses)
907system.cpu.icache.demand_accesses::cpu.inst 656942031 # number of demand (read+write) accesses
908system.cpu.icache.demand_accesses::total 656942031 # number of demand (read+write) accesses
909system.cpu.icache.overall_accesses::cpu.inst 656942031 # number of overall (read+write) accesses
910system.cpu.icache.overall_accesses::total 656942031 # number of overall (read+write) accesses
911system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
912system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
913system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
914system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
915system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
916system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
917system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64625.707692 # average ReadReq miss latency
918system.cpu.icache.ReadReq_avg_miss_latency::total 64625.707692 # average ReadReq miss latency
919system.cpu.icache.demand_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency
920system.cpu.icache.demand_avg_miss_latency::total 64625.707692 # average overall miss latency
921system.cpu.icache.overall_avg_miss_latency::cpu.inst 64625.707692 # average overall miss latency
922system.cpu.icache.overall_avg_miss_latency::total 64625.707692 # average overall miss latency
923system.cpu.icache.blocked_cycles::no_mshrs 17596 # number of cycles access was blocked
924system.cpu.icache.blocked_cycles::no_targets 547 # number of cycles access was blocked
925system.cpu.icache.blocked::no_mshrs 191 # number of cycles access was blocked
926system.cpu.icache.blocked::no_targets 9 # number of cycles access was blocked
927system.cpu.icache.avg_blocked_cycles::no_mshrs 92.125654 # average number of cycles each access was blocked
928system.cpu.icache.avg_blocked_cycles::no_targets 60.777778 # average number of cycles each access was blocked
929system.cpu.icache.fast_writes 0 # number of fast writes performed
930system.cpu.icache.cache_copies 0 # number of cache copies performed
931system.cpu.icache.ReadReq_mshr_hits::cpu.inst 548 # number of ReadReq MSHR hits
932system.cpu.icache.ReadReq_mshr_hits::total 548 # number of ReadReq MSHR hits
933system.cpu.icache.demand_mshr_hits::cpu.inst 548 # number of demand (read+write) MSHR hits
934system.cpu.icache.demand_mshr_hits::total 548 # number of demand (read+write) MSHR hits
935system.cpu.icache.overall_mshr_hits::cpu.inst 548 # number of overall MSHR hits
936system.cpu.icache.overall_mshr_hits::total 548 # number of overall MSHR hits
937system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1077 # number of ReadReq MSHR misses
938system.cpu.icache.ReadReq_mshr_misses::total 1077 # number of ReadReq MSHR misses
939system.cpu.icache.demand_mshr_misses::cpu.inst 1077 # number of demand (read+write) MSHR misses
940system.cpu.icache.demand_mshr_misses::total 1077 # number of demand (read+write) MSHR misses
941system.cpu.icache.overall_mshr_misses::cpu.inst 1077 # number of overall MSHR misses
942system.cpu.icache.overall_mshr_misses::total 1077 # number of overall MSHR misses
943system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76192959 # number of ReadReq MSHR miss cycles
944system.cpu.icache.ReadReq_mshr_miss_latency::total 76192959 # number of ReadReq MSHR miss cycles
945system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76192959 # number of demand (read+write) MSHR miss cycles
946system.cpu.icache.demand_mshr_miss_latency::total 76192959 # number of demand (read+write) MSHR miss cycles
947system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76192959 # number of overall MSHR miss cycles
948system.cpu.icache.overall_mshr_miss_latency::total 76192959 # number of overall MSHR miss cycles
949system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
950system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
951system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
952system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
953system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
954system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
955system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70745.551532 # average ReadReq mshr miss latency
956system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70745.551532 # average ReadReq mshr miss latency
957system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70745.551532 # average overall mshr miss latency
958system.cpu.icache.demand_avg_mshr_miss_latency::total 70745.551532 # average overall mshr miss latency
959system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70745.551532 # average overall mshr miss latency
960system.cpu.icache.overall_avg_mshr_miss_latency::total 70745.551532 # average overall mshr miss latency
961system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
962system.cpu.l2cache.prefetcher.num_hwpf_issued 10938258 # number of hwpf issued
963system.cpu.l2cache.prefetcher.pfIdentified 11626730 # number of prefetch candidates identified
964system.cpu.l2cache.prefetcher.pfBufferHit 430783 # number of redundant prefetches already in prefetch queue
965system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
966system.cpu.l2cache.prefetcher.pfRemovedFull 3 # number of prefetches dropped due to prefetch queue size
967system.cpu.l2cache.prefetcher.pfSpanPage 4654278 # number of prefetches not generated due to page crossing
968system.cpu.l2cache.tags.replacements 4710195 # number of replacements
969system.cpu.l2cache.tags.tagsinuse 16130.419578 # Cycle average of tags in use
970system.cpu.l2cache.tags.total_refs 15323813 # Total number of references to valid blocks.
971system.cpu.l2cache.tags.sampled_refs 4726123 # Sample count of references to valid blocks.
972system.cpu.l2cache.tags.avg_refs 3.242364 # Average number of references to valid blocks.
973system.cpu.l2cache.tags.warmup_cycle 29466216500 # Cycle when the warmup percentage was hit.
974system.cpu.l2cache.tags.occ_blocks::writebacks 5234.041152 # Average occupied blocks per requestor
975system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.862974 # Average occupied blocks per requestor
976system.cpu.l2cache.tags.occ_blocks::cpu.data 7585.301260 # Average occupied blocks per requestor
977system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3292.214193 # Average occupied blocks per requestor
978system.cpu.l2cache.tags.occ_percent::writebacks 0.319461 # Average percentage of cache occupancy
979system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001151 # Average percentage of cache occupancy
980system.cpu.l2cache.tags.occ_percent::cpu.data 0.462970 # Average percentage of cache occupancy
981system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.200941 # Average percentage of cache occupancy
982system.cpu.l2cache.tags.occ_percent::total 0.984523 # Average percentage of cache occupancy
983system.cpu.l2cache.tags.occ_task_id_blocks::1022 739 # Occupied blocks per task id
984system.cpu.l2cache.tags.occ_task_id_blocks::1024 15189 # Occupied blocks per task id
985system.cpu.l2cache.tags.age_task_id_blocks_1022::0 5 # Occupied blocks per task id
986system.cpu.l2cache.tags.age_task_id_blocks_1022::1 553 # Occupied blocks per task id
987system.cpu.l2cache.tags.age_task_id_blocks_1022::3 181 # Occupied blocks per task id
988system.cpu.l2cache.tags.age_task_id_blocks_1024::0 505 # Occupied blocks per task id
989system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2391 # Occupied blocks per task id
990system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1230 # Occupied blocks per task id
991system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9214 # Occupied blocks per task id
992system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1849 # Occupied blocks per task id
993system.cpu.l2cache.tags.occ_task_id_percent::1022 0.045105 # Percentage of cache occupancy per task id
994system.cpu.l2cache.tags.occ_task_id_percent::1024 0.927063 # Percentage of cache occupancy per task id
995system.cpu.l2cache.tags.tag_accesses 356873283 # Number of tag accesses
996system.cpu.l2cache.tags.data_accesses 356873283 # Number of data accesses
997system.cpu.l2cache.ReadReq_hits::cpu.inst 41 # number of ReadReq hits
998system.cpu.l2cache.ReadReq_hits::cpu.data 11486555 # number of ReadReq hits
999system.cpu.l2cache.ReadReq_hits::total 11486596 # number of ReadReq hits
1000system.cpu.l2cache.Writeback_hits::writebacks 4830628 # number of Writeback hits
1001system.cpu.l2cache.Writeback_hits::total 4830628 # number of Writeback hits
1002system.cpu.l2cache.ReadExReq_hits::cpu.data 1752756 # number of ReadExReq hits
1003system.cpu.l2cache.ReadExReq_hits::total 1752756 # number of ReadExReq hits
1004system.cpu.l2cache.demand_hits::cpu.inst 41 # number of demand (read+write) hits
1005system.cpu.l2cache.demand_hits::cpu.data 13239311 # number of demand (read+write) hits
1006system.cpu.l2cache.demand_hits::total 13239352 # number of demand (read+write) hits
1007system.cpu.l2cache.overall_hits::cpu.inst 41 # number of overall hits
1008system.cpu.l2cache.overall_hits::cpu.data 13239311 # number of overall hits
1009system.cpu.l2cache.overall_hits::total 13239352 # number of overall hits
1010system.cpu.l2cache.ReadReq_misses::cpu.inst 1036 # number of ReadReq misses
1011system.cpu.l2cache.ReadReq_misses::cpu.data 2782314 # number of ReadReq misses
1012system.cpu.l2cache.ReadReq_misses::total 2783350 # number of ReadReq misses
1013system.cpu.l2cache.ReadExReq_misses::cpu.data 984772 # number of ReadExReq misses
1014system.cpu.l2cache.ReadExReq_misses::total 984772 # number of ReadExReq misses
1015system.cpu.l2cache.demand_misses::cpu.inst 1036 # number of demand (read+write) misses
1016system.cpu.l2cache.demand_misses::cpu.data 3767086 # number of demand (read+write) misses
1017system.cpu.l2cache.demand_misses::total 3768122 # number of demand (read+write) misses
1018system.cpu.l2cache.overall_misses::cpu.inst 1036 # number of overall misses
1019system.cpu.l2cache.overall_misses::cpu.data 3767086 # number of overall misses
1020system.cpu.l2cache.overall_misses::total 3768122 # number of overall misses
1021system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 75378470 # number of ReadReq miss cycles
1022system.cpu.l2cache.ReadReq_miss_latency::cpu.data 238879414609 # number of ReadReq miss cycles
1023system.cpu.l2cache.ReadReq_miss_latency::total 238954793079 # number of ReadReq miss cycles
1024system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 100155661373 # number of ReadExReq miss cycles
1025system.cpu.l2cache.ReadExReq_miss_latency::total 100155661373 # number of ReadExReq miss cycles
1026system.cpu.l2cache.demand_miss_latency::cpu.inst 75378470 # number of demand (read+write) miss cycles
1027system.cpu.l2cache.demand_miss_latency::cpu.data 339035075982 # number of demand (read+write) miss cycles
1028system.cpu.l2cache.demand_miss_latency::total 339110454452 # number of demand (read+write) miss cycles
1029system.cpu.l2cache.overall_miss_latency::cpu.inst 75378470 # number of overall miss cycles
1030system.cpu.l2cache.overall_miss_latency::cpu.data 339035075982 # number of overall miss cycles
1031system.cpu.l2cache.overall_miss_latency::total 339110454452 # number of overall miss cycles
1032system.cpu.l2cache.ReadReq_accesses::cpu.inst 1077 # number of ReadReq accesses(hits+misses)
1033system.cpu.l2cache.ReadReq_accesses::cpu.data 14268869 # number of ReadReq accesses(hits+misses)
1034system.cpu.l2cache.ReadReq_accesses::total 14269946 # number of ReadReq accesses(hits+misses)
1035system.cpu.l2cache.Writeback_accesses::writebacks 4830628 # number of Writeback accesses(hits+misses)
1036system.cpu.l2cache.Writeback_accesses::total 4830628 # number of Writeback accesses(hits+misses)
1037system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737528 # number of ReadExReq accesses(hits+misses)
1038system.cpu.l2cache.ReadExReq_accesses::total 2737528 # number of ReadExReq accesses(hits+misses)
1039system.cpu.l2cache.demand_accesses::cpu.inst 1077 # number of demand (read+write) accesses
1040system.cpu.l2cache.demand_accesses::cpu.data 17006397 # number of demand (read+write) accesses
1041system.cpu.l2cache.demand_accesses::total 17007474 # number of demand (read+write) accesses
1042system.cpu.l2cache.overall_accesses::cpu.inst 1077 # number of overall (read+write) accesses
1043system.cpu.l2cache.overall_accesses::cpu.data 17006397 # number of overall (read+write) accesses
1044system.cpu.l2cache.overall_accesses::total 17007474 # number of overall (read+write) accesses
1045system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961931 # miss rate for ReadReq accesses
1046system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.194992 # miss rate for ReadReq accesses
1047system.cpu.l2cache.ReadReq_miss_rate::total 0.195050 # miss rate for ReadReq accesses
1048system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359730 # miss rate for ReadExReq accesses
1049system.cpu.l2cache.ReadExReq_miss_rate::total 0.359730 # miss rate for ReadExReq accesses
1050system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961931 # miss rate for demand accesses
1051system.cpu.l2cache.demand_miss_rate::cpu.data 0.221510 # miss rate for demand accesses
1052system.cpu.l2cache.demand_miss_rate::total 0.221557 # miss rate for demand accesses
1053system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961931 # miss rate for overall accesses
1054system.cpu.l2cache.overall_miss_rate::cpu.data 0.221510 # miss rate for overall accesses
1055system.cpu.l2cache.overall_miss_rate::total 0.221557 # miss rate for overall accesses
1056system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72759.140927 # average ReadReq miss latency
1057system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85856.382353 # average ReadReq miss latency
1058system.cpu.l2cache.ReadReq_avg_miss_latency::total 85851.507385 # average ReadReq miss latency
1059system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101704.416223 # average ReadExReq miss latency
1060system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101704.416223 # average ReadExReq miss latency
1061system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72759.140927 # average overall miss latency
1062system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89999.292817 # average overall miss latency
1063system.cpu.l2cache.demand_avg_miss_latency::total 89994.552844 # average overall miss latency
1064system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72759.140927 # average overall miss latency
1065system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89999.292817 # average overall miss latency
1066system.cpu.l2cache.overall_avg_miss_latency::total 89994.552844 # average overall miss latency
1067system.cpu.l2cache.blocked_cycles::no_mshrs 53 # number of cycles access was blocked
1068system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1069system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
1070system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1071system.cpu.l2cache.avg_blocked_cycles::no_mshrs 26.500000 # average number of cycles each access was blocked
1072system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1073system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1074system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1075system.cpu.l2cache.writebacks::writebacks 1637857 # number of writebacks
1076system.cpu.l2cache.writebacks::total 1637857 # number of writebacks
1077system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 35708 # number of ReadReq MSHR hits
1078system.cpu.l2cache.ReadReq_mshr_hits::total 35708 # number of ReadReq MSHR hits
1079system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3730 # number of ReadExReq MSHR hits
1080system.cpu.l2cache.ReadExReq_mshr_hits::total 3730 # number of ReadExReq MSHR hits
1081system.cpu.l2cache.demand_mshr_hits::cpu.data 39438 # number of demand (read+write) MSHR hits
1082system.cpu.l2cache.demand_mshr_hits::total 39438 # number of demand (read+write) MSHR hits
1083system.cpu.l2cache.overall_mshr_hits::cpu.data 39438 # number of overall MSHR hits
1084system.cpu.l2cache.overall_mshr_hits::total 39438 # number of overall MSHR hits
1085system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1036 # number of ReadReq MSHR misses
1086system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2746606 # number of ReadReq MSHR misses
1087system.cpu.l2cache.ReadReq_mshr_misses::total 2747642 # number of ReadReq MSHR misses
1088system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 992835 # number of HardPFReq MSHR misses
1089system.cpu.l2cache.HardPFReq_mshr_misses::total 992835 # number of HardPFReq MSHR misses
1090system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981042 # number of ReadExReq MSHR misses
1091system.cpu.l2cache.ReadExReq_mshr_misses::total 981042 # number of ReadExReq MSHR misses
1092system.cpu.l2cache.demand_mshr_misses::cpu.inst 1036 # number of demand (read+write) MSHR misses
1093system.cpu.l2cache.demand_mshr_misses::cpu.data 3727648 # number of demand (read+write) MSHR misses
1094system.cpu.l2cache.demand_mshr_misses::total 3728684 # number of demand (read+write) MSHR misses
1095system.cpu.l2cache.overall_mshr_misses::cpu.inst 1036 # number of overall MSHR misses
1096system.cpu.l2cache.overall_mshr_misses::cpu.data 3727648 # number of overall MSHR misses
1097system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 992835 # number of overall MSHR misses
1098system.cpu.l2cache.overall_mshr_misses::total 4721519 # number of overall MSHR misses
1099system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 66562530 # number of ReadReq MSHR miss cycles
1100system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 212706720467 # number of ReadReq MSHR miss cycles
1101system.cpu.l2cache.ReadReq_mshr_miss_latency::total 212773282997 # number of ReadReq MSHR miss cycles
1102system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 70893901794 # number of HardPFReq MSHR miss cycles
1103system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 70893901794 # number of HardPFReq MSHR miss cycles
1104system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 91380975745 # number of ReadExReq MSHR miss cycles
1105system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 91380975745 # number of ReadExReq MSHR miss cycles
1106system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 66562530 # number of demand (read+write) MSHR miss cycles
1107system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 304087696212 # number of demand (read+write) MSHR miss cycles
1108system.cpu.l2cache.demand_mshr_miss_latency::total 304154258742 # number of demand (read+write) MSHR miss cycles
1109system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 66562530 # number of overall MSHR miss cycles
1110system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 304087696212 # number of overall MSHR miss cycles
1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 70893901794 # number of overall MSHR miss cycles
1112system.cpu.l2cache.overall_mshr_miss_latency::total 375048160536 # number of overall MSHR miss cycles
1113system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for ReadReq accesses
1114system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192489 # mshr miss rate for ReadReq accesses
1115system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192547 # mshr miss rate for ReadReq accesses
1116system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1117system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1118system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358368 # mshr miss rate for ReadExReq accesses
1119system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358368 # mshr miss rate for ReadExReq accesses
1120system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for demand accesses
1121system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for demand accesses
1122system.cpu.l2cache.demand_mshr_miss_rate::total 0.219238 # mshr miss rate for demand accesses
1123system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961931 # mshr miss rate for overall accesses
1124system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219191 # mshr miss rate for overall accesses
1125system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1126system.cpu.l2cache.overall_mshr_miss_rate::total 0.277614 # mshr miss rate for overall accesses
1127system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64249.546332 # average ReadReq mshr miss latency
1128system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 77443.477684 # average ReadReq mshr miss latency
1129system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 77438.502904 # average ReadReq mshr miss latency
1130system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average HardPFReq mshr miss latency
1131system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 71405.522362 # average HardPFReq mshr miss latency
1132system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 93146.853799 # average ReadExReq mshr miss latency
1133system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 93146.853799 # average ReadExReq mshr miss latency
1134system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency
1135system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency
1136system.cpu.l2cache.demand_avg_mshr_miss_latency::total 81571.476355 # average overall mshr miss latency
1137system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64249.546332 # average overall mshr miss latency
1138system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81576.290522 # average overall mshr miss latency
1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 71405.522362 # average overall mshr miss latency
1140system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79433.792501 # average overall mshr miss latency
1141system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1142system.cpu.toL2Bus.trans_dist::ReadReq 14269946 # Transaction distribution
1143system.cpu.toL2Bus.trans_dist::ReadResp 14269946 # Transaction distribution
1144system.cpu.toL2Bus.trans_dist::Writeback 4830628 # Transaction distribution
1145system.cpu.toL2Bus.trans_dist::HardPFReq 1298291 # Transaction distribution
1146system.cpu.toL2Bus.trans_dist::ReadExReq 2737528 # Transaction distribution
1147system.cpu.toL2Bus.trans_dist::ReadExResp 2737528 # Transaction distribution
1148system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2154 # Packet count per connected master and slave (bytes)
1149system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38843422 # Packet count per connected master and slave (bytes)
1150system.cpu.toL2Bus.pkt_count::total 38845576 # Packet count per connected master and slave (bytes)
1151system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68928 # Cumulative packet size per connected master and slave (bytes)
1152system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1397569600 # Cumulative packet size per connected master and slave (bytes)
1153system.cpu.toL2Bus.pkt_size::total 1397638528 # Cumulative packet size per connected master and slave (bytes)
1154system.cpu.toL2Bus.snoops 1298291 # Total snoops (count)
1155system.cpu.toL2Bus.snoop_fanout::samples 23136394 # Request fanout histogram

1156system.cpu.toL2Bus.snoop_fanout::mean 3.056115 # Request fanout histogram

1156system.cpu.toL2Bus.snoop_fanout::mean 1.056115 # Request fanout histogram

1157system.cpu.toL2Bus.snoop_fanout::stdev 0.230143 # Request fanout histogram
1158system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1159system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

1160system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1161system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1162system.cpu.toL2Bus.snoop_fanout::3 21838103 94.39% 94.39% # Request fanout histogram
1163system.cpu.toL2Bus.snoop_fanout::4 1298291 5.61% 100.00% # Request fanout histogram

1160system.cpu.toL2Bus.snoop_fanout::1 21838103 94.39% 94.39% # Request fanout histogram
1161system.cpu.toL2Bus.snoop_fanout::2 1298291 5.61% 100.00% # Request fanout histogram

1164system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1162system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

1165system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
1166system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram

1163system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1164system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram