1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.770277 # Number of seconds simulated
4sim_ticks 770277033000 # Number of ticks simulated
5final_tick 770277033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 139677 # Simulator instruction rate (inst/s)
8host_op_rate 150481 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 69657391 # Simulator tick rate (ticks/s)
10host_mem_usage 313196 # Number of bytes of host memory used
11host_seconds 11058.08 # Real time elapsed on the host
12sim_insts 1544563024 # Number of instructions simulated
13sim_ops 1664032416 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 66048 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 238802560 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 63353600 # Number of bytes read from this memory
19system.physmem.bytes_read::total 302222208 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 66048 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 66048 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 104930816 # Number of bytes written to this memory
23system.physmem.bytes_written::total 104930816 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 1032 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 3731290 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.l2cache.prefetcher 989900 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 4722222 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 1639544 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 1639544 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 85746 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 310021654 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.l2cache.prefetcher 82247811 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 392355211 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 85746 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 85746 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 136224776 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 136224776 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 136224776 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 85746 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 310021654 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.l2cache.prefetcher 82247811 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 528579987 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 4722222 # Number of read requests accepted
44system.physmem.writeReqs 1639544 # Number of write requests accepted
45system.physmem.readBursts 4722222 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 1639544 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 301770432 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 451776 # Total number of bytes read from write queue
49system.physmem.bytesWritten 104928448 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 302222208 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 104930816 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 7059 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 16 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 297173 # Per bank write bursts
56system.physmem.perBankRdBursts::1 295012 # Per bank write bursts
57system.physmem.perBankRdBursts::2 289245 # Per bank write bursts
58system.physmem.perBankRdBursts::3 293018 # Per bank write bursts
59system.physmem.perBankRdBursts::4 289731 # Per bank write bursts
60system.physmem.perBankRdBursts::5 289594 # Per bank write bursts
61system.physmem.perBankRdBursts::6 284433 # Per bank write bursts
62system.physmem.perBankRdBursts::7 281274 # Per bank write bursts
63system.physmem.perBankRdBursts::8 297880 # Per bank write bursts
64system.physmem.perBankRdBursts::9 304149 # Per bank write bursts
65system.physmem.perBankRdBursts::10 295533 # Per bank write bursts
66system.physmem.perBankRdBursts::11 302217 # Per bank write bursts
67system.physmem.perBankRdBursts::12 302962 # Per bank write bursts
68system.physmem.perBankRdBursts::13 302377 # Per bank write bursts
69system.physmem.perBankRdBursts::14 297334 # Per bank write bursts
70system.physmem.perBankRdBursts::15 293231 # Per bank write bursts
71system.physmem.perBankWrBursts::0 104274 # Per bank write bursts
72system.physmem.perBankWrBursts::1 102166 # Per bank write bursts
73system.physmem.perBankWrBursts::2 99582 # Per bank write bursts
74system.physmem.perBankWrBursts::3 100201 # Per bank write bursts
75system.physmem.perBankWrBursts::4 99226 # Per bank write bursts
76system.physmem.perBankWrBursts::5 98958 # Per bank write bursts
77system.physmem.perBankWrBursts::6 102876 # Per bank write bursts
78system.physmem.perBankWrBursts::7 104542 # Per bank write bursts
79system.physmem.perBankWrBursts::8 105498 # Per bank write bursts
80system.physmem.perBankWrBursts::9 104632 # Per bank write bursts
81system.physmem.perBankWrBursts::10 102325 # Per bank write bursts
82system.physmem.perBankWrBursts::11 102766 # Per bank write bursts
83system.physmem.perBankWrBursts::12 102939 # Per bank write bursts
84system.physmem.perBankWrBursts::13 102535 # Per bank write bursts
85system.physmem.perBankWrBursts::14 104418 # Per bank write bursts
86system.physmem.perBankWrBursts::15 102569 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89system.physmem.totGap 770276886500 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 4722222 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 1639544 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 2779707 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 1048806 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 331545 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 232118 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 150885 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 83926 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 38903 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 23907 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 18114 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 4239 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 1660 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 740 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 412 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 195 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 6 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see

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143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 23226 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 24914 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 60170 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 75550 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 85536 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 93678 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 100036 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 103937 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 105744 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 106378 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 106329 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 106819 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 108389 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 111286 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 114103 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 105493 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 102233 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 101372 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 2580 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 1027 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 427 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 176 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 65 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 27 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 12 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 5 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 4293402 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 94.726038 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 78.887603 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 101.441683 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 3419558 79.65% 79.65% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 676188 15.75% 95.40% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 96097 2.24% 97.63% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 35320 0.82% 98.46% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 22691 0.53% 98.99% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 12222 0.28% 99.27% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 7184 0.17% 99.44% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 5103 0.12% 99.56% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 19039 0.44% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 4293402 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 98787 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 47.730481 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::gmean 32.341812 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::stdev 98.609970 # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::0-127 94999 96.17% 96.17% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::128-255 1343 1.36% 97.52% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::256-383 771 0.78% 98.31% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::384-511 397 0.40% 98.71% # Reads before turning the bus around for writes
222system.physmem.rdPerTurnAround::512-639 383 0.39% 99.10% # Reads before turning the bus around for writes
223system.physmem.rdPerTurnAround::640-767 367 0.37% 99.47% # Reads before turning the bus around for writes
224system.physmem.rdPerTurnAround::768-895 255 0.26% 99.72% # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::896-1023 139 0.14% 99.87% # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::1024-1151 71 0.07% 99.94% # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::1152-1279 36 0.04% 99.97% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::1280-1407 14 0.01% 99.99% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::1408-1535 4 0.00% 99.99% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::1536-1663 1 0.00% 99.99% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes
232system.physmem.rdPerTurnAround::2176-2303 1 0.00% 99.99% # Reads before turning the bus around for writes
233system.physmem.rdPerTurnAround::3328-3455 1 0.00% 100.00% # Reads before turning the bus around for writes
234system.physmem.rdPerTurnAround::3456-3583 1 0.00% 100.00% # Reads before turning the bus around for writes
235system.physmem.rdPerTurnAround::3840-3967 1 0.00% 100.00% # Reads before turning the bus around for writes
236system.physmem.rdPerTurnAround::3968-4095 2 0.00% 100.00% # Reads before turning the bus around for writes
237system.physmem.rdPerTurnAround::total 98787 # Reads before turning the bus around for writes
238system.physmem.wrPerTurnAround::samples 98787 # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::mean 16.596384 # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::gmean 16.562558 # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::stdev 1.102794 # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::16 72931 73.83% 73.83% # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::17 1712 1.73% 75.56% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::18 18497 18.72% 94.28% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::19 3886 3.93% 98.22% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::20 1013 1.03% 99.24% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::21 377 0.38% 99.62% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::22 169 0.17% 99.80% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::23 93 0.09% 99.89% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::24 49 0.05% 99.94% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::25 46 0.05% 99.99% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::26 12 0.01% 100.00% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::total 98787 # Writes before turning the bus around for reads
256system.physmem.totQLat 131372718643 # Total ticks spent queuing
257system.physmem.totMemAccLat 219782024893 # Total ticks spent from burst creation until serviced by the DRAM
258system.physmem.totBusLat 23575815000 # Total ticks spent in databus transfers
259system.physmem.avgQLat 27861.76 # Average queueing delay per DRAM burst
260system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
261system.physmem.avgMemAccLat 46611.76 # Average memory access latency per DRAM burst
262system.physmem.avgRdBW 391.77 # Average DRAM read bandwidth in MiByte/s
263system.physmem.avgWrBW 136.22 # Average achieved write bandwidth in MiByte/s
264system.physmem.avgRdBWSys 392.36 # Average system read bandwidth in MiByte/s
265system.physmem.avgWrBWSys 136.22 # Average system write bandwidth in MiByte/s
266system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
267system.physmem.busUtil 4.12 # Data bus utilization in percentage
268system.physmem.busUtilRead 3.06 # Data bus utilization in percentage for reads
269system.physmem.busUtilWrite 1.06 # Data bus utilization in percentage for writes
270system.physmem.avgRdQLen 1.44 # Average read queue length when enqueuing
271system.physmem.avgWrQLen 24.97 # Average write queue length when enqueuing
272system.physmem.readRowHits 1708262 # Number of row buffer hits during reads
273system.physmem.writeRowHits 352995 # Number of row buffer hits during writes
274system.physmem.readRowHitRate 36.23 # Row buffer hit rate for reads
275system.physmem.writeRowHitRate 21.53 # Row buffer hit rate for writes
276system.physmem.avgGap 121079.10 # Average gap between requests
277system.physmem.pageHitRate 32.44 # Row buffer hit rate, read and write combined
278system.physmem_0.actEnergy 16098316920 # Energy for activate commands per rank (pJ)
279system.physmem_0.preEnergy 8783803875 # Energy for precharge commands per rank (pJ)
280system.physmem_0.readEnergy 18090555600 # Energy for read commands per rank (pJ)
281system.physmem_0.writeEnergy 5260230720 # Energy for write commands per rank (pJ)
282system.physmem_0.refreshEnergy 50310315120 # Energy for refresh commands per rank (pJ)
283system.physmem_0.actBackEnergy 409970854125 # Energy for active background per rank (pJ)
284system.physmem_0.preBackEnergy 102538812000 # Energy for precharge background per rank (pJ)
285system.physmem_0.totalEnergy 611052888360 # Total energy per rank (pJ)
286system.physmem_0.averagePower 793.296379 # Core power per rank (mW)
287system.physmem_0.memoryStateTime::IDLE 168045428834 # Time in different power states
288system.physmem_0.memoryStateTime::REF 25721020000 # Time in different power states
289system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
290system.physmem_0.memoryStateTime::ACT 576504578166 # Time in different power states
291system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
292system.physmem_1.actEnergy 16359303240 # Energy for activate commands per rank (pJ)
293system.physmem_1.preEnergy 8926207125 # Energy for precharge commands per rank (pJ)
294system.physmem_1.readEnergy 18686249400 # Energy for read commands per rank (pJ)
295system.physmem_1.writeEnergy 5363152560 # Energy for write commands per rank (pJ)
296system.physmem_1.refreshEnergy 50310315120 # Energy for refresh commands per rank (pJ)
297system.physmem_1.actBackEnergy 411485095035 # Energy for active background per rank (pJ)
298system.physmem_1.preBackEnergy 101210530500 # Energy for precharge background per rank (pJ)
299system.physmem_1.totalEnergy 612340852980 # Total energy per rank (pJ)
300system.physmem_1.averagePower 794.968472 # Core power per rank (mW)
301system.physmem_1.memoryStateTime::IDLE 165832482361 # Time in different power states
302system.physmem_1.memoryStateTime::REF 25721020000 # Time in different power states
303system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
304system.physmem_1.memoryStateTime::ACT 578718185889 # Time in different power states
305system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
306system.cpu.branchPred.lookups 286281176 # Number of BP lookups
307system.cpu.branchPred.condPredicted 223407845 # Number of conditional branches predicted
308system.cpu.branchPred.condIncorrect 14631280 # Number of conditional branches incorrect
309system.cpu.branchPred.BTBLookups 158010784 # Number of BTB lookups
310system.cpu.branchPred.BTBHits 150352507 # Number of BTB hits
311system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
312system.cpu.branchPred.BTBHitPct 95.153320 # BTB Hit Percentage
313system.cpu.branchPred.usedRAS 16641956 # Number of times the RAS was used to get a target.
314system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions.
315system.cpu_clk_domain.clock 500 # Clock period in ticks
316system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

425system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
426system.cpu.itb.read_accesses 0 # DTB read accesses
427system.cpu.itb.write_accesses 0 # DTB write accesses
428system.cpu.itb.inst_accesses 0 # ITB inst accesses
429system.cpu.itb.hits 0 # DTB hits
430system.cpu.itb.misses 0 # DTB misses
431system.cpu.itb.accesses 0 # DTB accesses
432system.cpu.workload.num_syscalls 46 # Number of system calls
433system.cpu.numCycles 1540554067 # number of cpu cycles simulated
434system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
435system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
436system.cpu.fetch.icacheStallCycles 13926810 # Number of cycles fetch is stalled on an Icache miss
437system.cpu.fetch.Insts 2067510841 # Number of instructions fetch has processed
438system.cpu.fetch.Branches 286281176 # Number of branches that fetch encountered
439system.cpu.fetch.predictedBranches 166994463 # Number of branches that fetch has predicted taken
440system.cpu.fetch.Cycles 1511903145 # Number of cycles fetch has run and was not squashing or blocked
441system.cpu.fetch.SquashCycles 29287205 # Number of cycles fetch has spent squashing
442system.cpu.fetch.MiscStallCycles 183 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
443system.cpu.fetch.IcacheWaitRetryStallCycles 944 # Number of stall cycles due to full MSHR
444system.cpu.fetch.CacheLines 656946227 # Number of cache lines fetched
445system.cpu.fetch.IcacheSquashes 957 # Number of outstanding Icache misses that were squashed
446system.cpu.fetch.rateDist::samples 1540474684 # Number of instructions fetched each cycle (Total)
447system.cpu.fetch.rateDist::mean 1.437849 # Number of instructions fetched each cycle (Total)
448system.cpu.fetch.rateDist::stdev 1.228901 # Number of instructions fetched each cycle (Total)
449system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
450system.cpu.fetch.rateDist::0 458056876 29.73% 29.73% # Number of instructions fetched each cycle (Total)
451system.cpu.fetch.rateDist::1 465435106 30.21% 59.95% # Number of instructions fetched each cycle (Total)
452system.cpu.fetch.rateDist::2 101413024 6.58% 66.53% # Number of instructions fetched each cycle (Total)
453system.cpu.fetch.rateDist::3 515569678 33.47% 100.00% # Number of instructions fetched each cycle (Total)
454system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
455system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
456system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
457system.cpu.fetch.rateDist::total 1540474684 # Number of instructions fetched each cycle (Total)
458system.cpu.fetch.branchRate 0.185830 # Number of branch fetches per cycle
459system.cpu.fetch.rate 1.342057 # Number of inst fetches per cycle
460system.cpu.decode.IdleCycles 74648924 # Number of cycles decode is idle
461system.cpu.decode.BlockedCycles 543079640 # Number of cycles decode is blocked
462system.cpu.decode.RunCycles 849978540 # Number of cycles decode is running
463system.cpu.decode.UnblockCycles 58124682 # Number of cycles decode is unblocking
464system.cpu.decode.SquashCycles 14642898 # Number of cycles decode is squashing
465system.cpu.decode.BranchResolved 42203677 # Number of times decode resolved a branch
466system.cpu.decode.BranchMispred 755 # Number of times decode detected a branch misprediction
467system.cpu.decode.DecodedInsts 2037193143 # Number of instructions handled by decode
468system.cpu.decode.SquashedInsts 52473156 # Number of squashed instructions handled by decode
469system.cpu.rename.SquashCycles 14642898 # Number of cycles rename is squashing
470system.cpu.rename.IdleCycles 139724503 # Number of cycles rename is idle
471system.cpu.rename.BlockCycles 462464867 # Number of cycles rename is blocking
472system.cpu.rename.serializeStallCycles 13004 # count of cycles rename stalled for serializing inst
473system.cpu.rename.RunCycles 837848817 # Number of cycles rename is running
474system.cpu.rename.UnblockCycles 85780595 # Number of cycles rename is unblocking
475system.cpu.rename.RenamedInsts 1976362381 # Number of instructions processed by rename
476system.cpu.rename.SquashedInsts 26752450 # Number of squashed instructions processed by rename
477system.cpu.rename.ROBFullEvents 45148759 # Number of times rename has blocked due to ROB full
478system.cpu.rename.IQFullEvents 125663 # Number of times rename has blocked due to IQ full
479system.cpu.rename.LQFullEvents 1475660 # Number of times rename has blocked due to LQ full
480system.cpu.rename.SQFullEvents 24911172 # Number of times rename has blocked due to SQ full
481system.cpu.rename.RenamedOperands 1985832580 # Number of destination operands rename has renamed
482system.cpu.rename.RenameLookups 9128057886 # Number of register rename lookups that rename has made
483system.cpu.rename.int_rename_lookups 2432844380 # Number of integer rename lookups
484system.cpu.rename.fp_rename_lookups 133 # Number of floating rename lookups
485system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
486system.cpu.rename.UndoneMaps 310933635 # Number of HB maps that are undone due to squashing
487system.cpu.rename.serializingInsts 157 # count of serializing insts renamed
488system.cpu.rename.tempSerializingInsts 149 # count of temporary serializing insts renamed
489system.cpu.rename.skidInsts 111445716 # count of insts added to the skid buffer
490system.cpu.memDep0.insertedLoads 542550479 # Number of loads inserted to the mem dependence unit.
491system.cpu.memDep0.insertedStores 199301883 # Number of stores inserted to the mem dependence unit.
492system.cpu.memDep0.conflictingLoads 26937332 # Number of conflicting loads.
493system.cpu.memDep0.conflictingStores 29252722 # Number of conflicting stores.
494system.cpu.iq.iqInstsAdded 1947933921 # Number of instructions added to the IQ (excludes non-spec)
495system.cpu.iq.iqNonSpecInstsAdded 216 # Number of non-speculative instructions added to the IQ
496system.cpu.iq.iqInstsIssued 1857470724 # Number of instructions issued
497system.cpu.iq.iqSquashedInstsIssued 13498979 # Number of squashed instructions issued
498system.cpu.iq.iqSquashedInstsExamined 283901721 # Number of squashed instructions iterated over during squash; mainly for profiling
499system.cpu.iq.iqSquashedOperandsExamined 647143115 # Number of squashed operands that are examined and possibly removed from graph
500system.cpu.iq.iqSquashedNonSpecRemoved 46 # Number of squashed non-spec instructions that were removed
501system.cpu.iq.issued_per_cycle::samples 1540474684 # Number of insts issued each cycle
502system.cpu.iq.issued_per_cycle::mean 1.205778 # Number of insts issued each cycle
503system.cpu.iq.issued_per_cycle::stdev 1.150877 # Number of insts issued each cycle
504system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
505system.cpu.iq.issued_per_cycle::0 587582159 38.14% 38.14% # Number of insts issued each cycle
506system.cpu.iq.issued_per_cycle::1 326005186 21.16% 59.31% # Number of insts issued each cycle
507system.cpu.iq.issued_per_cycle::2 378227465 24.55% 83.86% # Number of insts issued each cycle
508system.cpu.iq.issued_per_cycle::3 219635075 14.26% 98.12% # Number of insts issued each cycle
509system.cpu.iq.issued_per_cycle::4 29018612 1.88% 100.00% # Number of insts issued each cycle
510system.cpu.iq.issued_per_cycle::5 6187 0.00% 100.00% # Number of insts issued each cycle
511system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
512system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
513system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
514system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
515system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
516system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
517system.cpu.iq.issued_per_cycle::total 1540474684 # Number of insts issued each cycle
518system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
519system.cpu.iq.fu_full::IntAlu 166090735 41.00% 41.00% # attempts to use FU when none available
520system.cpu.iq.fu_full::IntMult 2011 0.00% 41.00% # attempts to use FU when none available
521system.cpu.iq.fu_full::IntDiv 0 0.00% 41.00% # attempts to use FU when none available
522system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.00% # attempts to use FU when none available
523system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.00% # attempts to use FU when none available
524system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.00% # attempts to use FU when none available
525system.cpu.iq.fu_full::FloatMult 0 0.00% 41.00% # attempts to use FU when none available
526system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.00% # attempts to use FU when none available
527system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.00% # attempts to use FU when none available
528system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.00% # attempts to use FU when none available
529system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.00% # attempts to use FU when none available
530system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.00% # attempts to use FU when none available
531system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.00% # attempts to use FU when none available
532system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.00% # attempts to use FU when none available
533system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.00% # attempts to use FU when none available
534system.cpu.iq.fu_full::SimdMult 0 0.00% 41.00% # attempts to use FU when none available
535system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.00% # attempts to use FU when none available
536system.cpu.iq.fu_full::SimdShift 0 0.00% 41.00% # attempts to use FU when none available
537system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.00% # attempts to use FU when none available
538system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.00% # attempts to use FU when none available
539system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.00% # attempts to use FU when none available
540system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.00% # attempts to use FU when none available
541system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.00% # attempts to use FU when none available
542system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.00% # attempts to use FU when none available
543system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.00% # attempts to use FU when none available
544system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.00% # attempts to use FU when none available
545system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.00% # attempts to use FU when none available
546system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.00% # attempts to use FU when none available
547system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.00% # attempts to use FU when none available
548system.cpu.iq.fu_full::MemRead 191466761 47.26% 88.26% # attempts to use FU when none available
549system.cpu.iq.fu_full::MemWrite 47541933 11.74% 100.00% # attempts to use FU when none available
550system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
551system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
552system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
553system.cpu.iq.FU_type_0::IntAlu 1138243565 61.28% 61.28% # Type of FU issued
554system.cpu.iq.FU_type_0::IntMult 801032 0.04% 61.32% # Type of FU issued
555system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.32% # Type of FU issued
556system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.32% # Type of FU issued
557system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.32% # Type of FU issued
558system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.32% # Type of FU issued
559system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.32% # Type of FU issued
560system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.32% # Type of FU issued
561system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.32% # Type of FU issued
562system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.32% # Type of FU issued

--- 5 unchanged lines hidden (view full) ---

568system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.32% # Type of FU issued
569system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.32% # Type of FU issued
570system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.32% # Type of FU issued
571system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.32% # Type of FU issued
572system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.32% # Type of FU issued
573system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.32% # Type of FU issued
574system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.32% # Type of FU issued
575system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.32% # Type of FU issued
576system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.32% # Type of FU issued
577system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.32% # Type of FU issued
578system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.32% # Type of FU issued
579system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.32% # Type of FU issued
580system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.32% # Type of FU issued
581system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.32% # Type of FU issued
582system.cpu.iq.FU_type_0::MemRead 532113978 28.65% 89.97% # Type of FU issued
583system.cpu.iq.FU_type_0::MemWrite 186312098 10.03% 100.00% # Type of FU issued
584system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
585system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
586system.cpu.iq.FU_type_0::total 1857470724 # Type of FU issued
587system.cpu.iq.rate 1.205716 # Inst issue rate
588system.cpu.iq.fu_busy_cnt 405101440 # FU busy when requested
589system.cpu.iq.fu_busy_rate 0.218093 # FU busy rate (busy events/executed inst)
590system.cpu.iq.int_inst_queue_reads 5674016313 # Number of integer instruction queue reads
591system.cpu.iq.int_inst_queue_writes 2231848584 # Number of integer instruction queue writes
592system.cpu.iq.int_inst_queue_wakeup_accesses 1805694743 # Number of integer instruction queue wakeup accesses
593system.cpu.iq.fp_inst_queue_reads 238 # Number of floating instruction queue reads
594system.cpu.iq.fp_inst_queue_writes 230 # Number of floating instruction queue writes
595system.cpu.iq.fp_inst_queue_wakeup_accesses 70 # Number of floating instruction queue wakeup accesses
596system.cpu.iq.int_alu_accesses 2262572030 # Number of integer alu accesses
597system.cpu.iq.fp_alu_accesses 134 # Number of floating point alu accesses
598system.cpu.iew.lsq.thread0.forwLoads 17810782 # Number of loads that had data forwarded from stores
599system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
600system.cpu.iew.lsq.thread0.squashedLoads 84244145 # Number of loads squashed
601system.cpu.iew.lsq.thread0.ignoredResponses 66602 # Number of memory responses ignored because the instruction is squashed
602system.cpu.iew.lsq.thread0.memOrderViolation 13196 # Number of memory ordering violations
603system.cpu.iew.lsq.thread0.squashedStores 24454838 # Number of stores squashed
604system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
605system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
606system.cpu.iew.lsq.thread0.rescheduledLoads 4507141 # Number of loads that were rescheduled
607system.cpu.iew.lsq.thread0.cacheBlocked 4884537 # Number of times an access to memory failed due to the cache being blocked
608system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
609system.cpu.iew.iewSquashCycles 14642898 # Number of cycles IEW is squashing
610system.cpu.iew.iewBlockCycles 25317454 # Number of cycles IEW is blocking
611system.cpu.iew.iewUnblockCycles 1284847 # Number of cycles IEW is unblocking
612system.cpu.iew.iewDispatchedInsts 1947934221 # Number of instructions dispatched to IQ
613system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
614system.cpu.iew.iewDispLoadInsts 542550479 # Number of dispatched load instructions
615system.cpu.iew.iewDispStoreInsts 199301883 # Number of dispatched store instructions
616system.cpu.iew.iewDispNonSpecInsts 154 # Number of dispatched non-speculative instructions
617system.cpu.iew.iewIQFullEvents 159143 # Number of times the IQ has become full, causing a stall
618system.cpu.iew.iewLSQFullEvents 1124751 # Number of times the LSQ has become full, causing a stall
619system.cpu.iew.memOrderViolationEvents 13196 # Number of memory order violations
620system.cpu.iew.predictedTakenIncorrect 7700546 # Number of branches that were predicted taken incorrectly
621system.cpu.iew.predictedNotTakenIncorrect 8704736 # Number of branches that were predicted not taken incorrectly
622system.cpu.iew.branchMispredicts 16405282 # Number of branch mispredicts detected at execute
623system.cpu.iew.iewExecutedInsts 1827804607 # Number of executed instructions
624system.cpu.iew.iewExecLoadInsts 516933891 # Number of load instructions executed
625system.cpu.iew.iewExecSquashedInsts 29666117 # Number of squashed instructions skipped in execute
626system.cpu.iew.exec_swp 0 # number of swp insts executed
627system.cpu.iew.exec_nop 84 # number of nop insts executed
628system.cpu.iew.exec_refs 698685293 # number of memory reference insts executed
629system.cpu.iew.exec_branches 229544445 # Number of branches executed
630system.cpu.iew.exec_stores 181751402 # Number of stores executed
631system.cpu.iew.exec_rate 1.186459 # Inst execution rate
632system.cpu.iew.wb_sent 1808724876 # cumulative count of insts sent to commit
633system.cpu.iew.wb_count 1805694813 # cumulative count of insts written-back
634system.cpu.iew.wb_producers 1169261823 # num instructions producing a value
635system.cpu.iew.wb_consumers 1689660637 # num instructions consuming a value
636system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
637system.cpu.iew.wb_rate 1.172107 # insts written-back per cycle
638system.cpu.iew.wb_fanout 0.692010 # average fanout of values written-back
639system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
640system.cpu.commit.commitSquashedInsts 258006259 # The number of squashed insts skipped by commit
641system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
642system.cpu.commit.branchMispredicts 14630576 # The number of times a branch was mispredicted
643system.cpu.commit.committed_per_cycle::samples 1500991330 # Number of insts commited each cycle
644system.cpu.commit.committed_per_cycle::mean 1.108622 # Number of insts commited each cycle
645system.cpu.commit.committed_per_cycle::stdev 2.025694 # Number of insts commited each cycle
646system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
647system.cpu.commit.committed_per_cycle::0 920697347 61.34% 61.34% # Number of insts commited each cycle
648system.cpu.commit.committed_per_cycle::1 250635150 16.70% 78.04% # Number of insts commited each cycle
649system.cpu.commit.committed_per_cycle::2 110066020 7.33% 85.37% # Number of insts commited each cycle
650system.cpu.commit.committed_per_cycle::3 55280178 3.68% 89.05% # Number of insts commited each cycle
651system.cpu.commit.committed_per_cycle::4 29318113 1.95% 91.01% # Number of insts commited each cycle
652system.cpu.commit.committed_per_cycle::5 34079049 2.27% 93.28% # Number of insts commited each cycle
653system.cpu.commit.committed_per_cycle::6 24716376 1.65% 94.92% # Number of insts commited each cycle
654system.cpu.commit.committed_per_cycle::7 18134019 1.21% 96.13% # Number of insts commited each cycle
655system.cpu.commit.committed_per_cycle::8 58065078 3.87% 100.00% # Number of insts commited each cycle
656system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
657system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
658system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
659system.cpu.commit.committed_per_cycle::total 1500991330 # Number of insts commited each cycle
660system.cpu.commit.committedInsts 1544563042 # Number of instructions committed
661system.cpu.commit.committedOps 1664032434 # Number of ops (including micro ops) committed
662system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
663system.cpu.commit.refs 633153379 # Number of memory references committed
664system.cpu.commit.loads 458306334 # Number of loads committed
665system.cpu.commit.membars 62 # Number of memory barriers committed
666system.cpu.commit.branches 213462427 # Number of branches committed
667system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.

--- 29 unchanged lines hidden (view full) ---

697system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
698system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
699system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
700system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
701system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
702system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
703system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
704system.cpu.commit.op_class_0::total 1664032434 # Class of committed instruction
705system.cpu.commit.bw_lim_events 58065078 # number cycles where commit BW limit reached
706system.cpu.rob.rob_reads 3364964346 # The number of ROB reads
707system.cpu.rob.rob_writes 3883565961 # The number of ROB writes
708system.cpu.timesIdled 839 # Number of times that the entire CPU went into an idle state and unscheduled itself
709system.cpu.idleCycles 79383 # Total number of cycles that the CPU has spent unscheduled due to idling
710system.cpu.committedInsts 1544563024 # Number of Instructions Simulated
711system.cpu.committedOps 1664032416 # Number of Ops (including micro ops) Simulated
712system.cpu.cpi 0.997404 # CPI: Cycles Per Instruction
713system.cpu.cpi_total 0.997404 # CPI: Total CPI of All Threads
714system.cpu.ipc 1.002602 # IPC: Instructions Per Cycle
715system.cpu.ipc_total 1.002602 # IPC: Total IPC of All Threads
716system.cpu.int_regfile_reads 2175788919 # number of integer regfile reads
717system.cpu.int_regfile_writes 1261560913 # number of integer regfile writes
718system.cpu.fp_regfile_reads 42 # number of floating regfile reads
719system.cpu.fp_regfile_writes 52 # number of floating regfile writes
720system.cpu.cc_regfile_reads 6965670330 # number of cc regfile reads
721system.cpu.cc_regfile_writes 551865131 # number of cc regfile writes
722system.cpu.misc_regfile_reads 675839076 # number of misc regfile reads
723system.cpu.misc_regfile_writes 124 # number of misc regfile writes
724system.cpu.dcache.tags.replacements 17004565 # number of replacements
725system.cpu.dcache.tags.tagsinuse 511.965160 # Cycle average of tags in use
726system.cpu.dcache.tags.total_refs 638055083 # Total number of references to valid blocks.
727system.cpu.dcache.tags.sampled_refs 17005077 # Sample count of references to valid blocks.
728system.cpu.dcache.tags.avg_refs 37.521446 # Average number of references to valid blocks.
729system.cpu.dcache.tags.warmup_cycle 77552500 # Cycle when the warmup percentage was hit.
730system.cpu.dcache.tags.occ_blocks::cpu.data 511.965160 # Average occupied blocks per requestor
731system.cpu.dcache.tags.occ_percent::cpu.data 0.999932 # Average percentage of cache occupancy
732system.cpu.dcache.tags.occ_percent::total 0.999932 # Average percentage of cache occupancy
733system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
734system.cpu.dcache.tags.age_task_id_blocks_1024::0 415 # Occupied blocks per task id
735system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id
736system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
737system.cpu.dcache.tags.tag_accesses 1335687503 # Number of tag accesses
738system.cpu.dcache.tags.data_accesses 1335687503 # Number of data accesses
739system.cpu.dcache.ReadReq_hits::cpu.data 469335942 # number of ReadReq hits
740system.cpu.dcache.ReadReq_hits::total 469335942 # number of ReadReq hits
741system.cpu.dcache.WriteReq_hits::cpu.data 168719023 # number of WriteReq hits
742system.cpu.dcache.WriteReq_hits::total 168719023 # number of WriteReq hits
743system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
744system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
745system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
746system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
747system.cpu.dcache.demand_hits::cpu.data 638054965 # number of demand (read+write) hits
748system.cpu.dcache.demand_hits::total 638054965 # number of demand (read+write) hits
749system.cpu.dcache.overall_hits::cpu.data 638054965 # number of overall hits
750system.cpu.dcache.overall_hits::total 638054965 # number of overall hits
751system.cpu.dcache.ReadReq_misses::cpu.data 17419100 # number of ReadReq misses
752system.cpu.dcache.ReadReq_misses::total 17419100 # number of ReadReq misses
753system.cpu.dcache.WriteReq_misses::cpu.data 3867024 # number of WriteReq misses
754system.cpu.dcache.WriteReq_misses::total 3867024 # number of WriteReq misses
755system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
756system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
757system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
758system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
759system.cpu.dcache.demand_misses::cpu.data 21286124 # number of demand (read+write) misses
760system.cpu.dcache.demand_misses::total 21286124 # number of demand (read+write) misses
761system.cpu.dcache.overall_misses::cpu.data 21286126 # number of overall misses
762system.cpu.dcache.overall_misses::total 21286126 # number of overall misses
763system.cpu.dcache.ReadReq_miss_latency::cpu.data 415512136500 # number of ReadReq miss cycles
764system.cpu.dcache.ReadReq_miss_latency::total 415512136500 # number of ReadReq miss cycles
765system.cpu.dcache.WriteReq_miss_latency::cpu.data 149273741664 # number of WriteReq miss cycles
766system.cpu.dcache.WriteReq_miss_latency::total 149273741664 # number of WriteReq miss cycles
767system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 290000 # number of LoadLockedReq miss cycles
768system.cpu.dcache.LoadLockedReq_miss_latency::total 290000 # number of LoadLockedReq miss cycles
769system.cpu.dcache.demand_miss_latency::cpu.data 564785878164 # number of demand (read+write) miss cycles
770system.cpu.dcache.demand_miss_latency::total 564785878164 # number of demand (read+write) miss cycles
771system.cpu.dcache.overall_miss_latency::cpu.data 564785878164 # number of overall miss cycles
772system.cpu.dcache.overall_miss_latency::total 564785878164 # number of overall miss cycles
773system.cpu.dcache.ReadReq_accesses::cpu.data 486755042 # number of ReadReq accesses(hits+misses)
774system.cpu.dcache.ReadReq_accesses::total 486755042 # number of ReadReq accesses(hits+misses)
775system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
776system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
777system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
778system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
779system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
780system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
781system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
782system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
783system.cpu.dcache.demand_accesses::cpu.data 659341089 # number of demand (read+write) accesses
784system.cpu.dcache.demand_accesses::total 659341089 # number of demand (read+write) accesses
785system.cpu.dcache.overall_accesses::cpu.data 659341091 # number of overall (read+write) accesses
786system.cpu.dcache.overall_accesses::total 659341091 # number of overall (read+write) accesses
787system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035786 # miss rate for ReadReq accesses
788system.cpu.dcache.ReadReq_miss_rate::total 0.035786 # miss rate for ReadReq accesses
789system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.022406 # miss rate for WriteReq accesses
790system.cpu.dcache.WriteReq_miss_rate::total 0.022406 # miss rate for WriteReq accesses
791system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
792system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
793system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
794system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
795system.cpu.dcache.demand_miss_rate::cpu.data 0.032284 # miss rate for demand accesses
796system.cpu.dcache.demand_miss_rate::total 0.032284 # miss rate for demand accesses
797system.cpu.dcache.overall_miss_rate::cpu.data 0.032284 # miss rate for overall accesses
798system.cpu.dcache.overall_miss_rate::total 0.032284 # miss rate for overall accesses
799system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 23853.823475 # average ReadReq miss latency
800system.cpu.dcache.ReadReq_avg_miss_latency::total 23853.823475 # average ReadReq miss latency
801system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38601.710686 # average WriteReq miss latency
802system.cpu.dcache.WriteReq_avg_miss_latency::total 38601.710686 # average WriteReq miss latency
803system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72500 # average LoadLockedReq miss latency
804system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72500 # average LoadLockedReq miss latency
805system.cpu.dcache.demand_avg_miss_latency::cpu.data 26533.054029 # average overall miss latency
806system.cpu.dcache.demand_avg_miss_latency::total 26533.054029 # average overall miss latency
807system.cpu.dcache.overall_avg_miss_latency::cpu.data 26533.051536 # average overall miss latency
808system.cpu.dcache.overall_avg_miss_latency::total 26533.051536 # average overall miss latency
809system.cpu.dcache.blocked_cycles::no_mshrs 20783046 # number of cycles access was blocked
810system.cpu.dcache.blocked_cycles::no_targets 3318451 # number of cycles access was blocked
811system.cpu.dcache.blocked::no_mshrs 945637 # number of cycles access was blocked
812system.cpu.dcache.blocked::no_targets 67068 # number of cycles access was blocked
813system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.977827 # average number of cycles each access was blocked
814system.cpu.dcache.avg_blocked_cycles::no_targets 49.478902 # average number of cycles each access was blocked
815system.cpu.dcache.fast_writes 0 # number of fast writes performed
816system.cpu.dcache.cache_copies 0 # number of cache copies performed
817system.cpu.dcache.writebacks::writebacks 4838877 # number of writebacks
818system.cpu.dcache.writebacks::total 4838877 # number of writebacks
819system.cpu.dcache.ReadReq_mshr_hits::cpu.data 3151642 # number of ReadReq MSHR hits
820system.cpu.dcache.ReadReq_mshr_hits::total 3151642 # number of ReadReq MSHR hits
821system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1129406 # number of WriteReq MSHR hits
822system.cpu.dcache.WriteReq_mshr_hits::total 1129406 # number of WriteReq MSHR hits
823system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
824system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
825system.cpu.dcache.demand_mshr_hits::cpu.data 4281048 # number of demand (read+write) MSHR hits
826system.cpu.dcache.demand_mshr_hits::total 4281048 # number of demand (read+write) MSHR hits
827system.cpu.dcache.overall_mshr_hits::cpu.data 4281048 # number of overall MSHR hits
828system.cpu.dcache.overall_mshr_hits::total 4281048 # number of overall MSHR hits
829system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14267458 # number of ReadReq MSHR misses
830system.cpu.dcache.ReadReq_mshr_misses::total 14267458 # number of ReadReq MSHR misses
831system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737618 # number of WriteReq MSHR misses
832system.cpu.dcache.WriteReq_mshr_misses::total 2737618 # number of WriteReq MSHR misses
833system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
834system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
835system.cpu.dcache.demand_mshr_misses::cpu.data 17005076 # number of demand (read+write) MSHR misses
836system.cpu.dcache.demand_mshr_misses::total 17005076 # number of demand (read+write) MSHR misses
837system.cpu.dcache.overall_mshr_misses::cpu.data 17005077 # number of overall MSHR misses
838system.cpu.dcache.overall_mshr_misses::total 17005077 # number of overall MSHR misses
839system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 335579712500 # number of ReadReq MSHR miss cycles
840system.cpu.dcache.ReadReq_mshr_miss_latency::total 335579712500 # number of ReadReq MSHR miss cycles
841system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 116324734517 # number of WriteReq MSHR miss cycles
842system.cpu.dcache.WriteReq_mshr_miss_latency::total 116324734517 # number of WriteReq MSHR miss cycles
843system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 68000 # number of SoftPFReq MSHR miss cycles
844system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 68000 # number of SoftPFReq MSHR miss cycles
845system.cpu.dcache.demand_mshr_miss_latency::cpu.data 451904447017 # number of demand (read+write) MSHR miss cycles
846system.cpu.dcache.demand_mshr_miss_latency::total 451904447017 # number of demand (read+write) MSHR miss cycles
847system.cpu.dcache.overall_mshr_miss_latency::cpu.data 451904515017 # number of overall MSHR miss cycles
848system.cpu.dcache.overall_mshr_miss_latency::total 451904515017 # number of overall MSHR miss cycles
849system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029311 # mshr miss rate for ReadReq accesses
850system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029311 # mshr miss rate for ReadReq accesses
851system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015862 # mshr miss rate for WriteReq accesses
852system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015862 # mshr miss rate for WriteReq accesses
853system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
854system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
855system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for demand accesses
856system.cpu.dcache.demand_mshr_miss_rate::total 0.025791 # mshr miss rate for demand accesses
857system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025791 # mshr miss rate for overall accesses
858system.cpu.dcache.overall_mshr_miss_rate::total 0.025791 # mshr miss rate for overall accesses
859system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 23520.637839 # average ReadReq mshr miss latency
860system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 23520.637839 # average ReadReq mshr miss latency
861system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 42491.222120 # average WriteReq mshr miss latency
862system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 42491.222120 # average WriteReq mshr miss latency
863system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 68000 # average SoftPFReq mshr miss latency
864system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 68000 # average SoftPFReq mshr miss latency
865system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26574.679644 # average overall mshr miss latency
866system.cpu.dcache.demand_avg_mshr_miss_latency::total 26574.679644 # average overall mshr miss latency
867system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26574.682080 # average overall mshr miss latency
868system.cpu.dcache.overall_avg_mshr_miss_latency::total 26574.682080 # average overall mshr miss latency
869system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
870system.cpu.icache.tags.replacements 585 # number of replacements
871system.cpu.icache.tags.tagsinuse 445.973645 # Cycle average of tags in use
872system.cpu.icache.tags.total_refs 656944607 # Total number of references to valid blocks.
873system.cpu.icache.tags.sampled_refs 1073 # Sample count of references to valid blocks.
874system.cpu.icache.tags.avg_refs 612250.332712 # Average number of references to valid blocks.
875system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
876system.cpu.icache.tags.occ_blocks::cpu.inst 445.973645 # Average occupied blocks per requestor
877system.cpu.icache.tags.occ_percent::cpu.inst 0.871042 # Average percentage of cache occupancy
878system.cpu.icache.tags.occ_percent::total 0.871042 # Average percentage of cache occupancy
879system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id
880system.cpu.icache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
881system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
882system.cpu.icache.tags.age_task_id_blocks_1024::4 442 # Occupied blocks per task id
883system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id
884system.cpu.icache.tags.tag_accesses 1313893525 # Number of tag accesses
885system.cpu.icache.tags.data_accesses 1313893525 # Number of data accesses
886system.cpu.icache.ReadReq_hits::cpu.inst 656944607 # number of ReadReq hits
887system.cpu.icache.ReadReq_hits::total 656944607 # number of ReadReq hits
888system.cpu.icache.demand_hits::cpu.inst 656944607 # number of demand (read+write) hits
889system.cpu.icache.demand_hits::total 656944607 # number of demand (read+write) hits
890system.cpu.icache.overall_hits::cpu.inst 656944607 # number of overall hits
891system.cpu.icache.overall_hits::total 656944607 # number of overall hits
892system.cpu.icache.ReadReq_misses::cpu.inst 1619 # number of ReadReq misses
893system.cpu.icache.ReadReq_misses::total 1619 # number of ReadReq misses
894system.cpu.icache.demand_misses::cpu.inst 1619 # number of demand (read+write) misses
895system.cpu.icache.demand_misses::total 1619 # number of demand (read+write) misses
896system.cpu.icache.overall_misses::cpu.inst 1619 # number of overall misses
897system.cpu.icache.overall_misses::total 1619 # number of overall misses
898system.cpu.icache.ReadReq_miss_latency::cpu.inst 105131986 # number of ReadReq miss cycles
899system.cpu.icache.ReadReq_miss_latency::total 105131986 # number of ReadReq miss cycles
900system.cpu.icache.demand_miss_latency::cpu.inst 105131986 # number of demand (read+write) miss cycles
901system.cpu.icache.demand_miss_latency::total 105131986 # number of demand (read+write) miss cycles
902system.cpu.icache.overall_miss_latency::cpu.inst 105131986 # number of overall miss cycles
903system.cpu.icache.overall_miss_latency::total 105131986 # number of overall miss cycles
904system.cpu.icache.ReadReq_accesses::cpu.inst 656946226 # number of ReadReq accesses(hits+misses)
905system.cpu.icache.ReadReq_accesses::total 656946226 # number of ReadReq accesses(hits+misses)
906system.cpu.icache.demand_accesses::cpu.inst 656946226 # number of demand (read+write) accesses
907system.cpu.icache.demand_accesses::total 656946226 # number of demand (read+write) accesses
908system.cpu.icache.overall_accesses::cpu.inst 656946226 # number of overall (read+write) accesses
909system.cpu.icache.overall_accesses::total 656946226 # number of overall (read+write) accesses
910system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
911system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
912system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
913system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
914system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
915system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
916system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 64936.371834 # average ReadReq miss latency
917system.cpu.icache.ReadReq_avg_miss_latency::total 64936.371834 # average ReadReq miss latency
918system.cpu.icache.demand_avg_miss_latency::cpu.inst 64936.371834 # average overall miss latency
919system.cpu.icache.demand_avg_miss_latency::total 64936.371834 # average overall miss latency
920system.cpu.icache.overall_avg_miss_latency::cpu.inst 64936.371834 # average overall miss latency
921system.cpu.icache.overall_avg_miss_latency::total 64936.371834 # average overall miss latency
922system.cpu.icache.blocked_cycles::no_mshrs 17916 # number of cycles access was blocked
923system.cpu.icache.blocked_cycles::no_targets 510 # number of cycles access was blocked
924system.cpu.icache.blocked::no_mshrs 192 # number of cycles access was blocked
925system.cpu.icache.blocked::no_targets 8 # number of cycles access was blocked
926system.cpu.icache.avg_blocked_cycles::no_mshrs 93.312500 # average number of cycles each access was blocked
927system.cpu.icache.avg_blocked_cycles::no_targets 63.750000 # average number of cycles each access was blocked
928system.cpu.icache.fast_writes 0 # number of fast writes performed
929system.cpu.icache.cache_copies 0 # number of cache copies performed
930system.cpu.icache.ReadReq_mshr_hits::cpu.inst 546 # number of ReadReq MSHR hits
931system.cpu.icache.ReadReq_mshr_hits::total 546 # number of ReadReq MSHR hits
932system.cpu.icache.demand_mshr_hits::cpu.inst 546 # number of demand (read+write) MSHR hits
933system.cpu.icache.demand_mshr_hits::total 546 # number of demand (read+write) MSHR hits
934system.cpu.icache.overall_mshr_hits::cpu.inst 546 # number of overall MSHR hits
935system.cpu.icache.overall_mshr_hits::total 546 # number of overall MSHR hits
936system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1073 # number of ReadReq MSHR misses
937system.cpu.icache.ReadReq_mshr_misses::total 1073 # number of ReadReq MSHR misses
938system.cpu.icache.demand_mshr_misses::cpu.inst 1073 # number of demand (read+write) MSHR misses
939system.cpu.icache.demand_mshr_misses::total 1073 # number of demand (read+write) MSHR misses
940system.cpu.icache.overall_mshr_misses::cpu.inst 1073 # number of overall MSHR misses
941system.cpu.icache.overall_mshr_misses::total 1073 # number of overall MSHR misses
942system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 76698989 # number of ReadReq MSHR miss cycles
943system.cpu.icache.ReadReq_mshr_miss_latency::total 76698989 # number of ReadReq MSHR miss cycles
944system.cpu.icache.demand_mshr_miss_latency::cpu.inst 76698989 # number of demand (read+write) MSHR miss cycles
945system.cpu.icache.demand_mshr_miss_latency::total 76698989 # number of demand (read+write) MSHR miss cycles
946system.cpu.icache.overall_mshr_miss_latency::cpu.inst 76698989 # number of overall MSHR miss cycles
947system.cpu.icache.overall_mshr_miss_latency::total 76698989 # number of overall MSHR miss cycles
948system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
949system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
950system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
951system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
952system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
953system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
954system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71480.884436 # average ReadReq mshr miss latency
955system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71480.884436 # average ReadReq mshr miss latency
956system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71480.884436 # average overall mshr miss latency
957system.cpu.icache.demand_avg_mshr_miss_latency::total 71480.884436 # average overall mshr miss latency
958system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71480.884436 # average overall mshr miss latency
959system.cpu.icache.overall_avg_mshr_miss_latency::total 71480.884436 # average overall mshr miss latency
960system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
961system.cpu.l2cache.prefetcher.num_hwpf_issued 10956462 # number of hwpf issued
962system.cpu.l2cache.prefetcher.pfIdentified 11638997 # number of prefetch candidates identified
963system.cpu.l2cache.prefetcher.pfBufferHit 427337 # number of redundant prefetches already in prefetch queue
964system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
965system.cpu.l2cache.prefetcher.pfRemovedFull 2 # number of prefetches dropped due to prefetch queue size
966system.cpu.l2cache.prefetcher.pfSpanPage 4654603 # number of prefetches not generated due to page crossing
967system.cpu.l2cache.tags.replacements 4714185 # number of replacements
968system.cpu.l2cache.tags.tagsinuse 16129.978160 # Cycle average of tags in use
969system.cpu.l2cache.tags.total_refs 27368962 # Total number of references to valid blocks.
970system.cpu.l2cache.tags.sampled_refs 4730113 # Sample count of references to valid blocks.
971system.cpu.l2cache.tags.avg_refs 5.786112 # Average number of references to valid blocks.
972system.cpu.l2cache.tags.warmup_cycle 29467370500 # Cycle when the warmup percentage was hit.
973system.cpu.l2cache.tags.occ_blocks::writebacks 5231.697931 # Average occupied blocks per requestor
974system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.454317 # Average occupied blocks per requestor
975system.cpu.l2cache.tags.occ_blocks::cpu.data 7577.410769 # Average occupied blocks per requestor
976system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3302.415144 # Average occupied blocks per requestor
977system.cpu.l2cache.tags.occ_percent::writebacks 0.319318 # Average percentage of cache occupancy
978system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001126 # Average percentage of cache occupancy
979system.cpu.l2cache.tags.occ_percent::cpu.data 0.462488 # Average percentage of cache occupancy
980system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.201563 # Average percentage of cache occupancy
981system.cpu.l2cache.tags.occ_percent::total 0.984496 # Average percentage of cache occupancy
982system.cpu.l2cache.tags.occ_task_id_blocks::1022 757 # Occupied blocks per task id
983system.cpu.l2cache.tags.occ_task_id_blocks::1024 15171 # Occupied blocks per task id
984system.cpu.l2cache.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id
985system.cpu.l2cache.tags.age_task_id_blocks_1022::1 554 # Occupied blocks per task id
986system.cpu.l2cache.tags.age_task_id_blocks_1022::3 202 # Occupied blocks per task id
987system.cpu.l2cache.tags.age_task_id_blocks_1024::0 498 # Occupied blocks per task id
988system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2399 # Occupied blocks per task id
989system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1267 # Occupied blocks per task id
990system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9187 # Occupied blocks per task id
991system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1820 # Occupied blocks per task id
992system.cpu.l2cache.tags.occ_task_id_percent::1022 0.046204 # Percentage of cache occupancy per task id
993system.cpu.l2cache.tags.occ_task_id_percent::1024 0.925964 # Percentage of cache occupancy per task id
994system.cpu.l2cache.tags.tag_accesses 551303538 # Number of tag accesses
995system.cpu.l2cache.tags.data_accesses 551303538 # Number of data accesses
996system.cpu.l2cache.Writeback_hits::writebacks 4838877 # number of Writeback hits
997system.cpu.l2cache.Writeback_hits::total 4838877 # number of Writeback hits
998system.cpu.l2cache.ReadExReq_hits::cpu.data 1752165 # number of ReadExReq hits
999system.cpu.l2cache.ReadExReq_hits::total 1752165 # number of ReadExReq hits
1000system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41 # number of ReadCleanReq hits
1001system.cpu.l2cache.ReadCleanReq_hits::total 41 # number of ReadCleanReq hits
1002system.cpu.l2cache.ReadSharedReq_hits::cpu.data 11480053 # number of ReadSharedReq hits
1003system.cpu.l2cache.ReadSharedReq_hits::total 11480053 # number of ReadSharedReq hits
1004system.cpu.l2cache.demand_hits::cpu.inst 41 # number of demand (read+write) hits
1005system.cpu.l2cache.demand_hits::cpu.data 13232218 # number of demand (read+write) hits
1006system.cpu.l2cache.demand_hits::total 13232259 # number of demand (read+write) hits
1007system.cpu.l2cache.overall_hits::cpu.inst 41 # number of overall hits
1008system.cpu.l2cache.overall_hits::cpu.data 13232218 # number of overall hits
1009system.cpu.l2cache.overall_hits::total 13232259 # number of overall hits
1010system.cpu.l2cache.ReadExReq_misses::cpu.data 985500 # number of ReadExReq misses
1011system.cpu.l2cache.ReadExReq_misses::total 985500 # number of ReadExReq misses
1012system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 1032 # number of ReadCleanReq misses
1013system.cpu.l2cache.ReadCleanReq_misses::total 1032 # number of ReadCleanReq misses
1014system.cpu.l2cache.ReadSharedReq_misses::cpu.data 2787359 # number of ReadSharedReq misses
1015system.cpu.l2cache.ReadSharedReq_misses::total 2787359 # number of ReadSharedReq misses
1016system.cpu.l2cache.demand_misses::cpu.inst 1032 # number of demand (read+write) misses
1017system.cpu.l2cache.demand_misses::cpu.data 3772859 # number of demand (read+write) misses
1018system.cpu.l2cache.demand_misses::total 3773891 # number of demand (read+write) misses
1019system.cpu.l2cache.overall_misses::cpu.inst 1032 # number of overall misses
1020system.cpu.l2cache.overall_misses::cpu.data 3772859 # number of overall misses
1021system.cpu.l2cache.overall_misses::total 3773891 # number of overall misses
1022system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 99776080498 # number of ReadExReq miss cycles
1023system.cpu.l2cache.ReadExReq_miss_latency::total 99776080498 # number of ReadExReq miss cycles
1024system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 75349500 # number of ReadCleanReq miss cycles
1025system.cpu.l2cache.ReadCleanReq_miss_latency::total 75349500 # number of ReadCleanReq miss cycles
1026system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 238464802000 # number of ReadSharedReq miss cycles
1027system.cpu.l2cache.ReadSharedReq_miss_latency::total 238464802000 # number of ReadSharedReq miss cycles
1028system.cpu.l2cache.demand_miss_latency::cpu.inst 75349500 # number of demand (read+write) miss cycles
1029system.cpu.l2cache.demand_miss_latency::cpu.data 338240882498 # number of demand (read+write) miss cycles
1030system.cpu.l2cache.demand_miss_latency::total 338316231998 # number of demand (read+write) miss cycles
1031system.cpu.l2cache.overall_miss_latency::cpu.inst 75349500 # number of overall miss cycles
1032system.cpu.l2cache.overall_miss_latency::cpu.data 338240882498 # number of overall miss cycles
1033system.cpu.l2cache.overall_miss_latency::total 338316231998 # number of overall miss cycles
1034system.cpu.l2cache.Writeback_accesses::writebacks 4838877 # number of Writeback accesses(hits+misses)
1035system.cpu.l2cache.Writeback_accesses::total 4838877 # number of Writeback accesses(hits+misses)
1036system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737665 # number of ReadExReq accesses(hits+misses)
1037system.cpu.l2cache.ReadExReq_accesses::total 2737665 # number of ReadExReq accesses(hits+misses)
1038system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1073 # number of ReadCleanReq accesses(hits+misses)
1039system.cpu.l2cache.ReadCleanReq_accesses::total 1073 # number of ReadCleanReq accesses(hits+misses)
1040system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 14267412 # number of ReadSharedReq accesses(hits+misses)
1041system.cpu.l2cache.ReadSharedReq_accesses::total 14267412 # number of ReadSharedReq accesses(hits+misses)
1042system.cpu.l2cache.demand_accesses::cpu.inst 1073 # number of demand (read+write) accesses
1043system.cpu.l2cache.demand_accesses::cpu.data 17005077 # number of demand (read+write) accesses
1044system.cpu.l2cache.demand_accesses::total 17006150 # number of demand (read+write) accesses
1045system.cpu.l2cache.overall_accesses::cpu.inst 1073 # number of overall (read+write) accesses
1046system.cpu.l2cache.overall_accesses::cpu.data 17005077 # number of overall (read+write) accesses
1047system.cpu.l2cache.overall_accesses::total 17006150 # number of overall (read+write) accesses
1048system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359978 # miss rate for ReadExReq accesses
1049system.cpu.l2cache.ReadExReq_miss_rate::total 0.359978 # miss rate for ReadExReq accesses
1050system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.961789 # miss rate for ReadCleanReq accesses
1051system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.961789 # miss rate for ReadCleanReq accesses
1052system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.195365 # miss rate for ReadSharedReq accesses
1053system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.195365 # miss rate for ReadSharedReq accesses
1054system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961789 # miss rate for demand accesses
1055system.cpu.l2cache.demand_miss_rate::cpu.data 0.221867 # miss rate for demand accesses
1056system.cpu.l2cache.demand_miss_rate::total 0.221913 # miss rate for demand accesses
1057system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961789 # miss rate for overall accesses
1058system.cpu.l2cache.overall_miss_rate::cpu.data 0.221867 # miss rate for overall accesses
1059system.cpu.l2cache.overall_miss_rate::total 0.221913 # miss rate for overall accesses
1060system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 101244.120242 # average ReadExReq miss latency
1061system.cpu.l2cache.ReadExReq_avg_miss_latency::total 101244.120242 # average ReadExReq miss latency
1062system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 73013.081395 # average ReadCleanReq miss latency
1063system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 73013.081395 # average ReadCleanReq miss latency
1064system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85552.238517 # average ReadSharedReq miss latency
1065system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85552.238517 # average ReadSharedReq miss latency
1066system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 73013.081395 # average overall miss latency
1067system.cpu.l2cache.demand_avg_miss_latency::cpu.data 89651.079592 # average overall miss latency
1068system.cpu.l2cache.demand_avg_miss_latency::total 89646.529801 # average overall miss latency
1069system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 73013.081395 # average overall miss latency
1070system.cpu.l2cache.overall_avg_miss_latency::cpu.data 89651.079592 # average overall miss latency
1071system.cpu.l2cache.overall_avg_miss_latency::total 89646.529801 # average overall miss latency
1072system.cpu.l2cache.blocked_cycles::no_mshrs 42 # number of cycles access was blocked
1073system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1074system.cpu.l2cache.blocked::no_mshrs 2 # number of cycles access was blocked
1075system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1076system.cpu.l2cache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked
1077system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1078system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1079system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1080system.cpu.l2cache.writebacks::writebacks 1639544 # number of writebacks
1081system.cpu.l2cache.writebacks::total 1639544 # number of writebacks
1082system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3899 # number of ReadExReq MSHR hits
1083system.cpu.l2cache.ReadExReq_mshr_hits::total 3899 # number of ReadExReq MSHR hits
1084system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 38390 # number of ReadSharedReq MSHR hits
1085system.cpu.l2cache.ReadSharedReq_mshr_hits::total 38390 # number of ReadSharedReq MSHR hits
1086system.cpu.l2cache.demand_mshr_hits::cpu.data 42289 # number of demand (read+write) MSHR hits
1087system.cpu.l2cache.demand_mshr_hits::total 42289 # number of demand (read+write) MSHR hits
1088system.cpu.l2cache.overall_mshr_hits::cpu.data 42289 # number of overall MSHR hits
1089system.cpu.l2cache.overall_mshr_hits::total 42289 # number of overall MSHR hits
1090system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 100257 # number of CleanEvict MSHR misses
1091system.cpu.l2cache.CleanEvict_mshr_misses::total 100257 # number of CleanEvict MSHR misses
1092system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993873 # number of HardPFReq MSHR misses
1093system.cpu.l2cache.HardPFReq_mshr_misses::total 993873 # number of HardPFReq MSHR misses
1094system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981601 # number of ReadExReq MSHR misses
1095system.cpu.l2cache.ReadExReq_mshr_misses::total 981601 # number of ReadExReq MSHR misses
1096system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 1032 # number of ReadCleanReq MSHR misses
1097system.cpu.l2cache.ReadCleanReq_mshr_misses::total 1032 # number of ReadCleanReq MSHR misses
1098system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 2748969 # number of ReadSharedReq MSHR misses
1099system.cpu.l2cache.ReadSharedReq_mshr_misses::total 2748969 # number of ReadSharedReq MSHR misses
1100system.cpu.l2cache.demand_mshr_misses::cpu.inst 1032 # number of demand (read+write) MSHR misses
1101system.cpu.l2cache.demand_mshr_misses::cpu.data 3730570 # number of demand (read+write) MSHR misses
1102system.cpu.l2cache.demand_mshr_misses::total 3731602 # number of demand (read+write) MSHR misses
1103system.cpu.l2cache.overall_mshr_misses::cpu.inst 1032 # number of overall MSHR misses
1104system.cpu.l2cache.overall_mshr_misses::cpu.data 3730570 # number of overall MSHR misses
1105system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993873 # number of overall MSHR misses
1106system.cpu.l2cache.overall_mshr_misses::total 4725475 # number of overall MSHR misses
1107system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 72684245482 # number of HardPFReq MSHR miss cycles
1108system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 72684245482 # number of HardPFReq MSHR miss cycles
1109system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 93518423498 # number of ReadExReq MSHR miss cycles
1110system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 93518423498 # number of ReadExReq MSHR miss cycles
1111system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 69157500 # number of ReadCleanReq MSHR miss cycles
1112system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 69157500 # number of ReadCleanReq MSHR miss cycles
1113system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 219665951000 # number of ReadSharedReq MSHR miss cycles
1114system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 219665951000 # number of ReadSharedReq MSHR miss cycles
1115system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69157500 # number of demand (read+write) MSHR miss cycles
1116system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 313184374498 # number of demand (read+write) MSHR miss cycles
1117system.cpu.l2cache.demand_mshr_miss_latency::total 313253531998 # number of demand (read+write) MSHR miss cycles
1118system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69157500 # number of overall MSHR miss cycles
1119system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 313184374498 # number of overall MSHR miss cycles
1120system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 72684245482 # number of overall MSHR miss cycles
1121system.cpu.l2cache.overall_mshr_miss_latency::total 385937777480 # number of overall MSHR miss cycles
1122system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
1123system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
1124system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1125system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1126system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358554 # mshr miss rate for ReadExReq accesses
1127system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358554 # mshr miss rate for ReadExReq accesses
1128system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.961789 # mshr miss rate for ReadCleanReq accesses
1129system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.961789 # mshr miss rate for ReadCleanReq accesses
1130system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.192675 # mshr miss rate for ReadSharedReq accesses
1131system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.192675 # mshr miss rate for ReadSharedReq accesses
1132system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.961789 # mshr miss rate for demand accesses
1133system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219380 # mshr miss rate for demand accesses
1134system.cpu.l2cache.demand_mshr_miss_rate::total 0.219427 # mshr miss rate for demand accesses
1135system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.961789 # mshr miss rate for overall accesses
1136system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219380 # mshr miss rate for overall accesses
1137system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1138system.cpu.l2cache.overall_mshr_miss_rate::total 0.277869 # mshr miss rate for overall accesses
1139system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 73132.327251 # average HardPFReq mshr miss latency
1140system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 73132.327251 # average HardPFReq mshr miss latency
1141system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 95271.320524 # average ReadExReq mshr miss latency
1142system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 95271.320524 # average ReadExReq mshr miss latency
1143system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67013.081395 # average ReadCleanReq mshr miss latency
1144system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67013.081395 # average ReadCleanReq mshr miss latency
1145system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79908.486054 # average ReadSharedReq mshr miss latency
1146system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79908.486054 # average ReadSharedReq mshr miss latency
1147system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67013.081395 # average overall mshr miss latency
1148system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83950.810331 # average overall mshr miss latency
1149system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83946.126087 # average overall mshr miss latency
1150system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67013.081395 # average overall mshr miss latency
1151system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83950.810331 # average overall mshr miss latency
1152system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 73132.327251 # average overall mshr miss latency
1153system.cpu.l2cache.overall_avg_mshr_miss_latency::total 81671.742519 # average overall mshr miss latency
1154system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1155system.cpu.toL2Bus.trans_dist::ReadResp 14268485 # Transaction distribution
1156system.cpu.toL2Bus.trans_dist::Writeback 6478421 # Transaction distribution
1157system.cpu.toL2Bus.trans_dist::CleanEvict 15219349 # Transaction distribution
1158system.cpu.toL2Bus.trans_dist::HardPFReq 1327311 # Transaction distribution
1159system.cpu.toL2Bus.trans_dist::ReadExReq 2737665 # Transaction distribution
1160system.cpu.toL2Bus.trans_dist::ReadExResp 2737665 # Transaction distribution
1161system.cpu.toL2Bus.trans_dist::ReadCleanReq 1073 # Transaction distribution
1162system.cpu.toL2Bus.trans_dist::ReadSharedReq 14267412 # Transaction distribution
1163system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2727 # Packet count per connected master and slave (bytes)
1164system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 50993158 # Packet count per connected master and slave (bytes)
1165system.cpu.toL2Bus.pkt_count::total 50995885 # Packet count per connected master and slave (bytes)
1166system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 68672 # Cumulative packet size per connected master and slave (bytes)
1167system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398013056 # Cumulative packet size per connected master and slave (bytes)
1168system.cpu.toL2Bus.pkt_size::total 1398081728 # Cumulative packet size per connected master and slave (bytes)
1169system.cpu.toL2Bus.snoops 6041496 # Total snoops (count)
1170system.cpu.toL2Bus.snoop_fanout::samples 40052798 # Request fanout histogram
1171system.cpu.toL2Bus.snoop_fanout::mean 1.150838 # Request fanout histogram
1172system.cpu.toL2Bus.snoop_fanout::stdev 0.357891 # Request fanout histogram
1173system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1174system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1175system.cpu.toL2Bus.snoop_fanout::1 34011302 84.92% 84.92% # Request fanout histogram
1176system.cpu.toL2Bus.snoop_fanout::2 6041496 15.08% 100.00% # Request fanout histogram
1177system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1178system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
1179system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
1180system.cpu.toL2Bus.snoop_fanout::total 40052798 # Request fanout histogram
1181system.cpu.toL2Bus.reqLayer0.occupancy 21844528998 # Layer occupancy (ticks)
1182system.cpu.toL2Bus.reqLayer0.utilization 2.8 # Layer utilization (%)
1183system.cpu.toL2Bus.respLayer0.occupancy 1609500 # Layer occupancy (ticks)
1184system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1185system.cpu.toL2Bus.respLayer1.occupancy 25507619991 # Layer occupancy (ticks)
1186system.cpu.toL2Bus.respLayer1.utilization 3.3 # Layer utilization (%)
1187system.membus.trans_dist::ReadResp 3740347 # Transaction distribution
1188system.membus.trans_dist::Writeback 1639544 # Transaction distribution
1189system.membus.trans_dist::CleanEvict 3065371 # Transaction distribution
1190system.membus.trans_dist::ReadExReq 981875 # Transaction distribution
1191system.membus.trans_dist::ReadExResp 981875 # Transaction distribution
1192system.membus.trans_dist::ReadSharedReq 3740347 # Transaction distribution
1193system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14149359 # Packet count per connected master and slave (bytes)
1194system.membus.pkt_count::total 14149359 # Packet count per connected master and slave (bytes)
1195system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 407153024 # Cumulative packet size per connected master and slave (bytes)
1196system.membus.pkt_size::total 407153024 # Cumulative packet size per connected master and slave (bytes)
1197system.membus.snoops 0 # Total snoops (count)
1198system.membus.snoop_fanout::samples 9427137 # Request fanout histogram
1199system.membus.snoop_fanout::mean 0 # Request fanout histogram
1200system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1201system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1202system.membus.snoop_fanout::0 9427137 100.00% 100.00% # Request fanout histogram
1203system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1204system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1205system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1206system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1207system.membus.snoop_fanout::total 9427137 # Request fanout histogram
1208system.membus.reqLayer0.occupancy 17268043532 # Layer occupancy (ticks)
1209system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
1210system.membus.respLayer1.occupancy 25679820043 # Layer occupancy (ticks)
1211system.membus.respLayer1.utilization 3.3 # Layer utilization (%)
1212
1213---------- End Simulation Statistics ----------