1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.756343 # Number of seconds simulated
4sim_ticks 756342731500 # Number of ticks simulated
5final_tick 756342731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 137786 # Simulator instruction rate (inst/s)
8host_op_rate 148444 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 67471289 # Simulator tick rate (ticks/s)
10host_mem_usage 311496 # Number of bytes of host memory used
11host_seconds 11209.85 # Real time elapsed on the host
12sim_insts 1544563023 # Number of instructions simulated
13sim_ops 1664032415 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 66304 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 238887296 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.l2cache.prefetcher 63148480 # Number of bytes read from this memory
19system.physmem.bytes_read::total 302102080 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 66304 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 66304 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 104863424 # Number of bytes written to this memory
23system.physmem.bytes_written::total 104863424 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 1036 # Number of read requests responded to by this memory
25system.physmem.num_reads::cpu.data 3732614 # Number of read requests responded to by this memory
26system.physmem.num_reads::cpu.l2cache.prefetcher 986695 # Number of read requests responded to by this memory
27system.physmem.num_reads::total 4720345 # Number of read requests responded to by this memory
28system.physmem.num_writes::writebacks 1638491 # Number of write requests responded to by this memory
29system.physmem.num_writes::total 1638491 # Number of write requests responded to by this memory
30system.physmem.bw_read::cpu.inst 87664 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_read::cpu.data 315845299 # Total read bandwidth from this memory (bytes/s)
32system.physmem.bw_read::cpu.l2cache.prefetcher 83491885 # Total read bandwidth from this memory (bytes/s)
33system.physmem.bw_read::total 399424847 # Total read bandwidth from this memory (bytes/s)
34system.physmem.bw_inst_read::cpu.inst 87664 # Instruction read bandwidth from this memory (bytes/s)
35system.physmem.bw_inst_read::total 87664 # Instruction read bandwidth from this memory (bytes/s)
36system.physmem.bw_write::writebacks 138645378 # Write bandwidth from this memory (bytes/s)
37system.physmem.bw_write::total 138645378 # Write bandwidth from this memory (bytes/s)
38system.physmem.bw_total::writebacks 138645378 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.bw_total::cpu.inst 87664 # Total bandwidth to/from this memory (bytes/s)
40system.physmem.bw_total::cpu.data 315845299 # Total bandwidth to/from this memory (bytes/s)
41system.physmem.bw_total::cpu.l2cache.prefetcher 83491885 # Total bandwidth to/from this memory (bytes/s)
42system.physmem.bw_total::total 538070225 # Total bandwidth to/from this memory (bytes/s)
43system.physmem.readReqs 4720345 # Number of read requests accepted
44system.physmem.writeReqs 1638491 # Number of write requests accepted
45system.physmem.readBursts 4720345 # Number of DRAM read bursts, including those serviced by the write queue
46system.physmem.writeBursts 1638491 # Number of DRAM write bursts, including those merged in the write queue
47system.physmem.bytesReadDRAM 301644480 # Total number of bytes read from DRAM
48system.physmem.bytesReadWrQ 457600 # Total number of bytes read from write queue
49system.physmem.bytesWritten 104860480 # Total number of bytes written to DRAM
50system.physmem.bytesReadSys 302102080 # Total read bytes from the system interface side
51system.physmem.bytesWrittenSys 104863424 # Total written bytes from the system interface side
52system.physmem.servicedByWrQ 7150 # Number of DRAM read bursts serviced by the write queue
53system.physmem.mergedWrBursts 20 # Number of DRAM write bursts merged with an existing one
54system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
55system.physmem.perBankRdBursts::0 296862 # Per bank write bursts
56system.physmem.perBankRdBursts::1 294626 # Per bank write bursts
57system.physmem.perBankRdBursts::2 288270 # Per bank write bursts
58system.physmem.perBankRdBursts::3 292812 # Per bank write bursts
59system.physmem.perBankRdBursts::4 290199 # Per bank write bursts
60system.physmem.perBankRdBursts::5 289793 # Per bank write bursts
61system.physmem.perBankRdBursts::6 284872 # Per bank write bursts
62system.physmem.perBankRdBursts::7 281493 # Per bank write bursts
63system.physmem.perBankRdBursts::8 297311 # Per bank write bursts
64system.physmem.perBankRdBursts::9 303290 # Per bank write bursts
65system.physmem.perBankRdBursts::10 295469 # Per bank write bursts
66system.physmem.perBankRdBursts::11 301855 # Per bank write bursts
67system.physmem.perBankRdBursts::12 303298 # Per bank write bursts
68system.physmem.perBankRdBursts::13 302373 # Per bank write bursts
69system.physmem.perBankRdBursts::14 297652 # Per bank write bursts
70system.physmem.perBankRdBursts::15 293020 # Per bank write bursts
71system.physmem.perBankWrBursts::0 104131 # Per bank write bursts
72system.physmem.perBankWrBursts::1 101826 # Per bank write bursts
73system.physmem.perBankWrBursts::2 99098 # Per bank write bursts
74system.physmem.perBankWrBursts::3 99979 # Per bank write bursts
75system.physmem.perBankWrBursts::4 99438 # Per bank write bursts
76system.physmem.perBankWrBursts::5 99115 # Per bank write bursts
77system.physmem.perBankWrBursts::6 102674 # Per bank write bursts
78system.physmem.perBankWrBursts::7 104427 # Per bank write bursts
79system.physmem.perBankWrBursts::8 105209 # Per bank write bursts
80system.physmem.perBankWrBursts::9 104570 # Per bank write bursts
81system.physmem.perBankWrBursts::10 102342 # Per bank write bursts
82system.physmem.perBankWrBursts::11 102683 # Per bank write bursts
83system.physmem.perBankWrBursts::12 102787 # Per bank write bursts
84system.physmem.perBankWrBursts::13 102808 # Per bank write bursts
85system.physmem.perBankWrBursts::14 104630 # Per bank write bursts
86system.physmem.perBankWrBursts::15 102728 # Per bank write bursts
87system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
88system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
89system.physmem.totGap 756342591500 # Total gap between requests
90system.physmem.readPktSize::0 0 # Read request sizes (log2)
91system.physmem.readPktSize::1 0 # Read request sizes (log2)
92system.physmem.readPktSize::2 0 # Read request sizes (log2)
93system.physmem.readPktSize::3 0 # Read request sizes (log2)
94system.physmem.readPktSize::4 0 # Read request sizes (log2)
95system.physmem.readPktSize::5 0 # Read request sizes (log2)
96system.physmem.readPktSize::6 4720345 # Read request sizes (log2)
97system.physmem.writePktSize::0 0 # Write request sizes (log2)
98system.physmem.writePktSize::1 0 # Write request sizes (log2)
99system.physmem.writePktSize::2 0 # Write request sizes (log2)
100system.physmem.writePktSize::3 0 # Write request sizes (log2)
101system.physmem.writePktSize::4 0 # Write request sizes (log2)
102system.physmem.writePktSize::5 0 # Write request sizes (log2)
103system.physmem.writePktSize::6 1638491 # Write request sizes (log2)
104system.physmem.rdQLenPdf::0 2764600 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::1 1036830 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::2 329452 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::3 239558 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::4 162691 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::5 91104 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::6 40419 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::7 23320 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::8 17706 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::9 4471 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::10 1653 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::11 733 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::12 418 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::13 229 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::14 10 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see

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143system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::15 22698 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::16 24488 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::17 59650 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::18 74848 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::19 84172 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::20 91913 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::21 98459 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::22 103044 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::23 106253 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::24 107840 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::25 108834 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::26 109988 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::27 110978 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::28 113431 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::29 107071 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::30 104798 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::31 103128 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::32 101631 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::33 3003 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::34 1224 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::35 572 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::36 248 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::37 103 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::38 42 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::39 18 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::40 8 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::41 4 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::43 2 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::44 1 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::45 1 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::46 3 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
196system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
197system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
198system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
199system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
200system.physmem.bytesPerActivate::samples 4285614 # Bytes accessed per row activation
201system.physmem.bytesPerActivate::mean 94.853108 # Bytes accessed per row activation
202system.physmem.bytesPerActivate::gmean 78.948636 # Bytes accessed per row activation
203system.physmem.bytesPerActivate::stdev 101.693693 # Bytes accessed per row activation
204system.physmem.bytesPerActivate::0-127 3410667 79.58% 79.58% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::128-255 676414 15.78% 95.37% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::256-383 97051 2.26% 97.63% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::384-511 35005 0.82% 98.45% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::512-639 22710 0.53% 98.98% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::640-767 12276 0.29% 99.27% # Bytes accessed per row activation
210system.physmem.bytesPerActivate::768-895 7200 0.17% 99.43% # Bytes accessed per row activation
211system.physmem.bytesPerActivate::896-1023 5155 0.12% 99.55% # Bytes accessed per row activation
212system.physmem.bytesPerActivate::1024-1151 19136 0.45% 100.00% # Bytes accessed per row activation
213system.physmem.bytesPerActivate::total 4285614 # Bytes accessed per row activation
214system.physmem.rdPerTurnAround::samples 98802 # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::mean 47.703225 # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::gmean 32.303831 # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::stdev 97.301104 # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::0-127 94981 96.13% 96.13% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::128-255 1362 1.38% 97.51% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::256-383 759 0.77% 98.28% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::384-511 434 0.44% 98.72% # Reads before turning the bus around for writes
222system.physmem.rdPerTurnAround::512-639 380 0.38% 99.10% # Reads before turning the bus around for writes
223system.physmem.rdPerTurnAround::640-767 348 0.35% 99.46% # Reads before turning the bus around for writes
224system.physmem.rdPerTurnAround::768-895 273 0.28% 99.73% # Reads before turning the bus around for writes
225system.physmem.rdPerTurnAround::896-1023 148 0.15% 99.88% # Reads before turning the bus around for writes
226system.physmem.rdPerTurnAround::1024-1151 67 0.07% 99.95% # Reads before turning the bus around for writes
227system.physmem.rdPerTurnAround::1152-1279 20 0.02% 99.97% # Reads before turning the bus around for writes
228system.physmem.rdPerTurnAround::1280-1407 9 0.01% 99.98% # Reads before turning the bus around for writes
229system.physmem.rdPerTurnAround::1408-1535 8 0.01% 99.99% # Reads before turning the bus around for writes
230system.physmem.rdPerTurnAround::1536-1663 4 0.00% 99.99% # Reads before turning the bus around for writes
231system.physmem.rdPerTurnAround::1920-2047 1 0.00% 99.99% # Reads before turning the bus around for writes
232system.physmem.rdPerTurnAround::2048-2175 1 0.00% 99.99% # Reads before turning the bus around for writes
233system.physmem.rdPerTurnAround::2176-2303 2 0.00% 99.99% # Reads before turning the bus around for writes
234system.physmem.rdPerTurnAround::2432-2559 1 0.00% 100.00% # Reads before turning the bus around for writes
235system.physmem.rdPerTurnAround::2560-2687 1 0.00% 100.00% # Reads before turning the bus around for writes
236system.physmem.rdPerTurnAround::2688-2815 1 0.00% 100.00% # Reads before turning the bus around for writes
237system.physmem.rdPerTurnAround::2816-2943 2 0.00% 100.00% # Reads before turning the bus around for writes
238system.physmem.rdPerTurnAround::total 98802 # Reads before turning the bus around for writes
239system.physmem.wrPerTurnAround::samples 98802 # Writes before turning the bus around for reads
240system.physmem.wrPerTurnAround::mean 16.583116 # Writes before turning the bus around for reads
241system.physmem.wrPerTurnAround::gmean 16.550078 # Writes before turning the bus around for reads
242system.physmem.wrPerTurnAround::stdev 1.089696 # Writes before turning the bus around for reads
243system.physmem.wrPerTurnAround::16 73349 74.24% 74.24% # Writes before turning the bus around for reads
244system.physmem.wrPerTurnAround::17 1793 1.81% 76.05% # Writes before turning the bus around for reads
245system.physmem.wrPerTurnAround::18 18295 18.52% 94.57% # Writes before turning the bus around for reads
246system.physmem.wrPerTurnAround::19 3696 3.74% 98.31% # Writes before turning the bus around for reads
247system.physmem.wrPerTurnAround::20 920 0.93% 99.24% # Writes before turning the bus around for reads
248system.physmem.wrPerTurnAround::21 398 0.40% 99.64% # Writes before turning the bus around for reads
249system.physmem.wrPerTurnAround::22 161 0.16% 99.81% # Writes before turning the bus around for reads
250system.physmem.wrPerTurnAround::23 94 0.10% 99.90% # Writes before turning the bus around for reads
251system.physmem.wrPerTurnAround::24 50 0.05% 99.95% # Writes before turning the bus around for reads
252system.physmem.wrPerTurnAround::25 24 0.02% 99.98% # Writes before turning the bus around for reads
253system.physmem.wrPerTurnAround::26 14 0.01% 99.99% # Writes before turning the bus around for reads
254system.physmem.wrPerTurnAround::27 5 0.01% 100.00% # Writes before turning the bus around for reads
255system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads
256system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads
257system.physmem.wrPerTurnAround::total 98802 # Writes before turning the bus around for reads
258system.physmem.totQLat 132475907765 # Total ticks spent queuing
259system.physmem.totMemAccLat 220848314015 # Total ticks spent from burst creation until serviced by the DRAM
260system.physmem.totBusLat 23565975000 # Total ticks spent in databus transfers
261system.physmem.avgQLat 28107.45 # Average queueing delay per DRAM burst
262system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
263system.physmem.avgMemAccLat 46857.45 # Average memory access latency per DRAM burst
264system.physmem.avgRdBW 398.82 # Average DRAM read bandwidth in MiByte/s
265system.physmem.avgWrBW 138.64 # Average achieved write bandwidth in MiByte/s
266system.physmem.avgRdBWSys 399.42 # Average system read bandwidth in MiByte/s
267system.physmem.avgWrBWSys 138.65 # Average system write bandwidth in MiByte/s
268system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
269system.physmem.busUtil 4.20 # Data bus utilization in percentage
270system.physmem.busUtilRead 3.12 # Data bus utilization in percentage for reads
271system.physmem.busUtilWrite 1.08 # Data bus utilization in percentage for writes
272system.physmem.avgRdQLen 1.43 # Average read queue length when enqueuing
273system.physmem.avgWrQLen 24.87 # Average write queue length when enqueuing
274system.physmem.readRowHits 1712938 # Number of row buffer hits during reads
275system.physmem.writeRowHits 353078 # Number of row buffer hits during writes
276system.physmem.readRowHitRate 36.34 # Row buffer hit rate for reads
277system.physmem.writeRowHitRate 21.55 # Row buffer hit rate for writes
278system.physmem.avgGap 118943.56 # Average gap between requests
279system.physmem.pageHitRate 32.53 # Row buffer hit rate, read and write combined
280system.physmem_0.actEnergy 16066436400 # Energy for activate commands per rank (pJ)
281system.physmem_0.preEnergy 8766408750 # Energy for precharge commands per rank (pJ)
282system.physmem_0.readEnergy 18087404400 # Energy for read commands per rank (pJ)
283system.physmem_0.writeEnergy 5253193440 # Energy for write commands per rank (pJ)
284system.physmem_0.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ)
285system.physmem_0.actBackEnergy 400853320515 # Energy for active background per rank (pJ)
286system.physmem_0.preBackEnergy 102178887750 # Energy for precharge background per rank (pJ)
287system.physmem_0.totalEnergy 600606152535 # Total energy per rank (pJ)
288system.physmem_0.averagePower 794.094387 # Core power per rank (mW)
289system.physmem_0.memoryStateTime::IDLE 167492103071 # Time in different power states
290system.physmem_0.memoryStateTime::REF 25255880000 # Time in different power states
291system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
292system.physmem_0.memoryStateTime::ACT 563593117929 # Time in different power states
293system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
294system.physmem_1.actEnergy 16332729840 # Energy for activate commands per rank (pJ)
295system.physmem_1.preEnergy 8911707750 # Energy for precharge commands per rank (pJ)
296system.physmem_1.readEnergy 18675259200 # Energy for read commands per rank (pJ)
297system.physmem_1.writeEnergy 5363826480 # Energy for write commands per rank (pJ)
298system.physmem_1.refreshEnergy 49400501280 # Energy for refresh commands per rank (pJ)
299system.physmem_1.actBackEnergy 402415744095 # Energy for active background per rank (pJ)
300system.physmem_1.preBackEnergy 100808340750 # Energy for precharge background per rank (pJ)
301system.physmem_1.totalEnergy 601908109395 # Total energy per rank (pJ)
302system.physmem_1.averagePower 795.815775 # Core power per rank (mW)
303system.physmem_1.memoryStateTime::IDLE 165215512876 # Time in different power states
304system.physmem_1.memoryStateTime::REF 25255880000 # Time in different power states
305system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
306system.physmem_1.memoryStateTime::ACT 565869633374 # Time in different power states
307system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
308system.cpu.branchPred.lookups 286251205 # Number of BP lookups
309system.cpu.branchPred.condPredicted 223383370 # Number of conditional branches predicted
310system.cpu.branchPred.condIncorrect 14630986 # Number of conditional branches incorrect
311system.cpu.branchPred.BTBLookups 158738952 # Number of BTB lookups
312system.cpu.branchPred.BTBHits 150334108 # Number of BTB hits
313system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
314system.cpu.branchPred.BTBHitPct 94.705242 # BTB Hit Percentage
315system.cpu.branchPred.usedRAS 16640646 # Number of times the RAS was used to get a target.
316system.cpu.branchPred.RASInCorrect 64 # Number of incorrect RAS predictions.
317system.cpu_clk_domain.clock 500 # Clock period in ticks
318system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
321system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
322system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
323system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
324system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst

--- 102 unchanged lines hidden (view full) ---

427system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
428system.cpu.itb.read_accesses 0 # DTB read accesses
429system.cpu.itb.write_accesses 0 # DTB write accesses
430system.cpu.itb.inst_accesses 0 # ITB inst accesses
431system.cpu.itb.hits 0 # DTB hits
432system.cpu.itb.misses 0 # DTB misses
433system.cpu.itb.accesses 0 # DTB accesses
434system.cpu.workload.num_syscalls 46 # Number of system calls
435system.cpu.numCycles 1512685464 # number of cpu cycles simulated
436system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
437system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
438system.cpu.fetch.icacheStallCycles 13925295 # Number of cycles fetch is stalled on an Icache miss
439system.cpu.fetch.Insts 2067334861 # Number of instructions fetch has processed
440system.cpu.fetch.Branches 286251205 # Number of branches that fetch encountered
441system.cpu.fetch.predictedBranches 166974754 # Number of branches that fetch has predicted taken
442system.cpu.fetch.Cycles 1484044715 # Number of cycles fetch has run and was not squashing or blocked
443system.cpu.fetch.SquashCycles 29286501 # Number of cycles fetch has spent squashing
444system.cpu.fetch.MiscStallCycles 170 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
445system.cpu.fetch.IcacheWaitRetryStallCycles 1090 # Number of stall cycles due to full MSHR
446system.cpu.fetch.CacheLines 656878260 # Number of cache lines fetched
447system.cpu.fetch.IcacheSquashes 961 # Number of outstanding Icache misses that were squashed
448system.cpu.fetch.rateDist::samples 1512614520 # Number of instructions fetched each cycle (Total)
449system.cpu.fetch.rateDist::mean 1.464203 # Number of instructions fetched each cycle (Total)
450system.cpu.fetch.rateDist::stdev 1.224459 # Number of instructions fetched each cycle (Total)
451system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
452system.cpu.fetch.rateDist::0 430302331 28.45% 28.45% # Number of instructions fetched each cycle (Total)
453system.cpu.fetch.rateDist::1 465370544 30.77% 59.21% # Number of instructions fetched each cycle (Total)
454system.cpu.fetch.rateDist::2 101420857 6.71% 65.92% # Number of instructions fetched each cycle (Total)
455system.cpu.fetch.rateDist::3 515520788 34.08% 100.00% # Number of instructions fetched each cycle (Total)
456system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
457system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
458system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total)
459system.cpu.fetch.rateDist::total 1512614520 # Number of instructions fetched each cycle (Total)
460system.cpu.fetch.branchRate 0.189234 # Number of branch fetches per cycle
461system.cpu.fetch.rate 1.366665 # Number of inst fetches per cycle
462system.cpu.decode.IdleCycles 74740374 # Number of cycles decode is idle
463system.cpu.decode.BlockedCycles 515177494 # Number of cycles decode is blocked
464system.cpu.decode.RunCycles 849893259 # Number of cycles decode is running
465system.cpu.decode.UnblockCycles 58160845 # Number of cycles decode is unblocking
466system.cpu.decode.SquashCycles 14642548 # Number of cycles decode is squashing
467system.cpu.decode.BranchResolved 42195150 # Number of times decode resolved a branch
468system.cpu.decode.BranchMispred 750 # Number of times decode detected a branch misprediction
469system.cpu.decode.DecodedInsts 2036986769 # Number of instructions handled by decode
470system.cpu.decode.SquashedInsts 52385989 # Number of squashed instructions handled by decode
471system.cpu.rename.SquashCycles 14642548 # Number of cycles rename is squashing
472system.cpu.rename.IdleCycles 139815435 # Number of cycles rename is idle
473system.cpu.rename.BlockCycles 436624028 # Number of cycles rename is blocking
474system.cpu.rename.serializeStallCycles 12701 # count of cycles rename stalled for serializing inst
475system.cpu.rename.RunCycles 837804287 # Number of cycles rename is running
476system.cpu.rename.UnblockCycles 83715521 # Number of cycles rename is unblocking
477system.cpu.rename.RenamedInsts 1976173031 # Number of instructions processed by rename
478system.cpu.rename.SquashedInsts 26689335 # Number of squashed instructions processed by rename
479system.cpu.rename.ROBFullEvents 45146280 # Number of times rename has blocked due to ROB full
480system.cpu.rename.IQFullEvents 125414 # Number of times rename has blocked due to IQ full
481system.cpu.rename.LQFullEvents 1394915 # Number of times rename has blocked due to LQ full
482system.cpu.rename.SQFullEvents 22818803 # Number of times rename has blocked due to SQ full
483system.cpu.rename.RenamedOperands 1985649062 # Number of destination operands rename has renamed
484system.cpu.rename.RenameLookups 9127137269 # Number of register rename lookups that rename has made
485system.cpu.rename.int_rename_lookups 2432583454 # Number of integer rename lookups
486system.cpu.rename.fp_rename_lookups 143 # Number of floating rename lookups
487system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
488system.cpu.rename.UndoneMaps 310750117 # Number of HB maps that are undone due to squashing
489system.cpu.rename.serializingInsts 155 # count of serializing insts renamed
490system.cpu.rename.tempSerializingInsts 146 # count of temporary serializing insts renamed
491system.cpu.rename.skidInsts 111721700 # count of insts added to the skid buffer
492system.cpu.memDep0.insertedLoads 542489680 # Number of loads inserted to the mem dependence unit.
493system.cpu.memDep0.insertedStores 199288909 # Number of stores inserted to the mem dependence unit.
494system.cpu.memDep0.conflictingLoads 26826914 # Number of conflicting loads.
495system.cpu.memDep0.conflictingStores 28715919 # Number of conflicting stores.
496system.cpu.iq.iqInstsAdded 1947778041 # Number of instructions added to the IQ (excludes non-spec)
497system.cpu.iq.iqNonSpecInstsAdded 214 # Number of non-speculative instructions added to the IQ
498system.cpu.iq.iqInstsIssued 1857580897 # Number of instructions issued
499system.cpu.iq.iqSquashedInstsIssued 13541153 # Number of squashed instructions issued
500system.cpu.iq.iqSquashedInstsExamined 279193675 # Number of squashed instructions iterated over during squash; mainly for profiling
501system.cpu.iq.iqSquashedOperandsExamined 645796508 # Number of squashed operands that are examined and possibly removed from graph
502system.cpu.iq.iqSquashedNonSpecRemoved 44 # Number of squashed non-spec instructions that were removed
503system.cpu.iq.issued_per_cycle::samples 1512614520 # Number of insts issued each cycle
504system.cpu.iq.issued_per_cycle::mean 1.228060 # Number of insts issued each cycle
505system.cpu.iq.issued_per_cycle::stdev 1.150014 # Number of insts issued each cycle
506system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
507system.cpu.iq.issued_per_cycle::0 560160519 37.03% 37.03% # Number of insts issued each cycle
508system.cpu.iq.issued_per_cycle::1 325201183 21.50% 58.53% # Number of insts issued each cycle
509system.cpu.iq.issued_per_cycle::2 378431439 25.02% 83.55% # Number of insts issued each cycle
510system.cpu.iq.issued_per_cycle::3 219774852 14.53% 98.08% # Number of insts issued each cycle
511system.cpu.iq.issued_per_cycle::4 29040355 1.92% 100.00% # Number of insts issued each cycle
512system.cpu.iq.issued_per_cycle::5 6172 0.00% 100.00% # Number of insts issued each cycle
513system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle
514system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle
515system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle
516system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
517system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
518system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle
519system.cpu.iq.issued_per_cycle::total 1512614520 # Number of insts issued each cycle
520system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
521system.cpu.iq.fu_full::IntAlu 166509117 41.02% 41.02% # attempts to use FU when none available
522system.cpu.iq.fu_full::IntMult 1974 0.00% 41.02% # attempts to use FU when none available
523system.cpu.iq.fu_full::IntDiv 0 0.00% 41.02% # attempts to use FU when none available
524system.cpu.iq.fu_full::FloatAdd 0 0.00% 41.02% # attempts to use FU when none available
525system.cpu.iq.fu_full::FloatCmp 0 0.00% 41.02% # attempts to use FU when none available
526system.cpu.iq.fu_full::FloatCvt 0 0.00% 41.02% # attempts to use FU when none available
527system.cpu.iq.fu_full::FloatMult 0 0.00% 41.02% # attempts to use FU when none available
528system.cpu.iq.fu_full::FloatDiv 0 0.00% 41.02% # attempts to use FU when none available
529system.cpu.iq.fu_full::FloatSqrt 0 0.00% 41.02% # attempts to use FU when none available
530system.cpu.iq.fu_full::SimdAdd 0 0.00% 41.02% # attempts to use FU when none available
531system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 41.02% # attempts to use FU when none available
532system.cpu.iq.fu_full::SimdAlu 0 0.00% 41.02% # attempts to use FU when none available
533system.cpu.iq.fu_full::SimdCmp 0 0.00% 41.02% # attempts to use FU when none available
534system.cpu.iq.fu_full::SimdCvt 0 0.00% 41.02% # attempts to use FU when none available
535system.cpu.iq.fu_full::SimdMisc 0 0.00% 41.02% # attempts to use FU when none available
536system.cpu.iq.fu_full::SimdMult 0 0.00% 41.02% # attempts to use FU when none available
537system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 41.02% # attempts to use FU when none available
538system.cpu.iq.fu_full::SimdShift 0 0.00% 41.02% # attempts to use FU when none available
539system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 41.02% # attempts to use FU when none available
540system.cpu.iq.fu_full::SimdSqrt 0 0.00% 41.02% # attempts to use FU when none available
541system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 41.02% # attempts to use FU when none available
542system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 41.02% # attempts to use FU when none available
543system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 41.02% # attempts to use FU when none available
544system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 41.02% # attempts to use FU when none available
545system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 41.02% # attempts to use FU when none available
546system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 41.02% # attempts to use FU when none available
547system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 41.02% # attempts to use FU when none available
548system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.02% # attempts to use FU when none available
549system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 41.02% # attempts to use FU when none available
550system.cpu.iq.fu_full::MemRead 191277328 47.12% 88.14% # attempts to use FU when none available
551system.cpu.iq.fu_full::MemWrite 48123931 11.86% 100.00% # attempts to use FU when none available
552system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
553system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
554system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
555system.cpu.iq.FU_type_0::IntAlu 1138363415 61.28% 61.28% # Type of FU issued
556system.cpu.iq.FU_type_0::IntMult 801029 0.04% 61.33% # Type of FU issued
557system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.33% # Type of FU issued
558system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 61.33% # Type of FU issued
559system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.33% # Type of FU issued
560system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.33% # Type of FU issued
561system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.33% # Type of FU issued
562system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.33% # Type of FU issued
563system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.33% # Type of FU issued
564system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.33% # Type of FU issued
565system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.33% # Type of FU issued
566system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.33% # Type of FU issued
567system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.33% # Type of FU issued
568system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.33% # Type of FU issued
569system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.33% # Type of FU issued
570system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.33% # Type of FU issued
571system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.33% # Type of FU issued
572system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.33% # Type of FU issued
573system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.33% # Type of FU issued
574system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.33% # Type of FU issued
575system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.33% # Type of FU issued
576system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.33% # Type of FU issued
577system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.33% # Type of FU issued
578system.cpu.iq.FU_type_0::SimdFloatCvt 29 0.00% 61.33% # Type of FU issued
579system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.33% # Type of FU issued
580system.cpu.iq.FU_type_0::SimdFloatMisc 22 0.00% 61.33% # Type of FU issued
581system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.33% # Type of FU issued
582system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.33% # Type of FU issued
583system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.33% # Type of FU issued
584system.cpu.iq.FU_type_0::MemRead 532094788 28.64% 89.97% # Type of FU issued
585system.cpu.iq.FU_type_0::MemWrite 186321614 10.03% 100.00% # Type of FU issued
586system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
587system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
588system.cpu.iq.FU_type_0::total 1857580897 # Type of FU issued
589system.cpu.iq.rate 1.228002 # Inst issue rate
590system.cpu.iq.fu_busy_cnt 405912350 # FU busy when requested
591system.cpu.iq.fu_busy_rate 0.218517 # FU busy rate (busy events/executed inst)
592system.cpu.iq.int_inst_queue_reads 5647229580 # Number of integer instruction queue reads
593system.cpu.iq.int_inst_queue_writes 2226984572 # Number of integer instruction queue writes
594system.cpu.iq.int_inst_queue_wakeup_accesses 1805831958 # Number of integer instruction queue wakeup accesses
595system.cpu.iq.fp_inst_queue_reads 237 # Number of floating instruction queue reads
596system.cpu.iq.fp_inst_queue_writes 246 # Number of floating instruction queue writes
597system.cpu.iq.fp_inst_queue_wakeup_accesses 69 # Number of floating instruction queue wakeup accesses
598system.cpu.iq.int_alu_accesses 2263493115 # Number of integer alu accesses
599system.cpu.iq.fp_alu_accesses 132 # Number of floating point alu accesses
600system.cpu.iew.lsq.thread0.forwLoads 17832338 # Number of loads that had data forwarded from stores
601system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
602system.cpu.iew.lsq.thread0.squashedLoads 84183346 # Number of loads squashed
603system.cpu.iew.lsq.thread0.ignoredResponses 66238 # Number of memory responses ignored because the instruction is squashed
604system.cpu.iew.lsq.thread0.memOrderViolation 13114 # Number of memory ordering violations
605system.cpu.iew.lsq.thread0.squashedStores 24441864 # Number of stores squashed
606system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
607system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
608system.cpu.iew.lsq.thread0.rescheduledLoads 4579390 # Number of loads that were rescheduled
609system.cpu.iew.lsq.thread0.cacheBlocked 4849629 # Number of times an access to memory failed due to the cache being blocked
610system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
611system.cpu.iew.iewSquashCycles 14642548 # Number of cycles IEW is squashing
612system.cpu.iew.iewBlockCycles 25281228 # Number of cycles IEW is blocking
613system.cpu.iew.iewUnblockCycles 1183865 # Number of cycles IEW is unblocking
614system.cpu.iew.iewDispatchedInsts 1947778336 # Number of instructions dispatched to IQ
615system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch
616system.cpu.iew.iewDispLoadInsts 542489680 # Number of dispatched load instructions
617system.cpu.iew.iewDispStoreInsts 199288909 # Number of dispatched store instructions
618system.cpu.iew.iewDispNonSpecInsts 152 # Number of dispatched non-speculative instructions
619system.cpu.iew.iewIQFullEvents 158613 # Number of times the IQ has become full, causing a stall
620system.cpu.iew.iewLSQFullEvents 1024253 # Number of times the LSQ has become full, causing a stall
621system.cpu.iew.memOrderViolationEvents 13114 # Number of memory order violations
622system.cpu.iew.predictedTakenIncorrect 7709445 # Number of branches that were predicted taken incorrectly
623system.cpu.iew.predictedNotTakenIncorrect 8723908 # Number of branches that were predicted not taken incorrectly
624system.cpu.iew.branchMispredicts 16433353 # Number of branch mispredicts detected at execute
625system.cpu.iew.iewExecutedInsts 1827918594 # Number of executed instructions
626system.cpu.iew.iewExecLoadInsts 516926976 # Number of load instructions executed
627system.cpu.iew.iewExecSquashedInsts 29662303 # Number of squashed instructions skipped in execute
628system.cpu.iew.exec_swp 0 # number of swp insts executed
629system.cpu.iew.exec_nop 81 # number of nop insts executed
630system.cpu.iew.exec_refs 698686621 # number of memory reference insts executed
631system.cpu.iew.exec_branches 229598858 # Number of branches executed
632system.cpu.iew.exec_stores 181759645 # Number of stores executed
633system.cpu.iew.exec_rate 1.208393 # Inst execution rate
634system.cpu.iew.wb_sent 1808851456 # cumulative count of insts sent to commit
635system.cpu.iew.wb_count 1805832027 # cumulative count of insts written-back
636system.cpu.iew.wb_producers 1169265268 # num instructions producing a value
637system.cpu.iew.wb_consumers 1689455879 # num instructions consuming a value
638system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
639system.cpu.iew.wb_rate 1.193792 # insts written-back per cycle
640system.cpu.iew.wb_fanout 0.692096 # average fanout of values written-back
641system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
642system.cpu.commit.commitSquashedInsts 257820227 # The number of squashed insts skipped by commit
643system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
644system.cpu.commit.branchMispredicts 14630284 # The number of times a branch was mispredicted
645system.cpu.commit.committed_per_cycle::samples 1473146552 # Number of insts commited each cycle
646system.cpu.commit.committed_per_cycle::mean 1.129577 # Number of insts commited each cycle
647system.cpu.commit.committed_per_cycle::stdev 2.040655 # Number of insts commited each cycle
648system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
649system.cpu.commit.committed_per_cycle::0 893288218 60.64% 60.64% # Number of insts commited each cycle
650system.cpu.commit.committed_per_cycle::1 250810214 17.03% 77.66% # Number of insts commited each cycle
651system.cpu.commit.committed_per_cycle::2 109558722 7.44% 85.10% # Number of insts commited each cycle
652system.cpu.commit.committed_per_cycle::3 55058301 3.74% 88.84% # Number of insts commited each cycle
653system.cpu.commit.committed_per_cycle::4 29206870 1.98% 90.82% # Number of insts commited each cycle
654system.cpu.commit.committed_per_cycle::5 33934631 2.30% 93.12% # Number of insts commited each cycle
655system.cpu.commit.committed_per_cycle::6 24884814 1.69% 94.81% # Number of insts commited each cycle
656system.cpu.commit.committed_per_cycle::7 18117903 1.23% 96.04% # Number of insts commited each cycle
657system.cpu.commit.committed_per_cycle::8 58286879 3.96% 100.00% # Number of insts commited each cycle
658system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
659system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
660system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
661system.cpu.commit.committed_per_cycle::total 1473146552 # Number of insts commited each cycle
662system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
663system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed
664system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
665system.cpu.commit.refs 633153379 # Number of memory references committed
666system.cpu.commit.loads 458306334 # Number of loads committed
667system.cpu.commit.membars 62 # Number of memory barriers committed
668system.cpu.commit.branches 213462426 # Number of branches committed
669system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.

--- 29 unchanged lines hidden (view full) ---

699system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
700system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
701system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
702system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
703system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
704system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
705system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
706system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction
707system.cpu.commit.bw_lim_events 58286879 # number cycles where commit BW limit reached
708system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
709system.cpu.rob.rob_reads 3336711734 # The number of ROB reads
710system.cpu.rob.rob_writes 3883178493 # The number of ROB writes
711system.cpu.timesIdled 871 # Number of times that the entire CPU went into an idle state and unscheduled itself
712system.cpu.idleCycles 70944 # Total number of cycles that the CPU has spent unscheduled due to idling
713system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
714system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated
715system.cpu.cpi 0.979361 # CPI: Cycles Per Instruction
716system.cpu.cpi_total 0.979361 # CPI: Total CPI of All Threads
717system.cpu.ipc 1.021073 # IPC: Instructions Per Cycle
718system.cpu.ipc_total 1.021073 # IPC: Total IPC of All Threads
719system.cpu.int_regfile_reads 2175874054 # number of integer regfile reads
720system.cpu.int_regfile_writes 1261590215 # number of integer regfile writes
721system.cpu.fp_regfile_reads 38 # number of floating regfile reads
722system.cpu.fp_regfile_writes 51 # number of floating regfile writes
723system.cpu.cc_regfile_reads 6966029517 # number of cc regfile reads
724system.cpu.cc_regfile_writes 551971474 # number of cc regfile writes
725system.cpu.misc_regfile_reads 675853074 # number of misc regfile reads
726system.cpu.misc_regfile_writes 124 # number of misc regfile writes
727system.cpu.dcache.tags.replacements 17007297 # number of replacements
728system.cpu.dcache.tags.tagsinuse 511.963762 # Cycle average of tags in use
729system.cpu.dcache.tags.total_refs 638259274 # Total number of references to valid blocks.
730system.cpu.dcache.tags.sampled_refs 17007809 # Sample count of references to valid blocks.
731system.cpu.dcache.tags.avg_refs 37.527425 # Average number of references to valid blocks.
732system.cpu.dcache.tags.warmup_cycle 79888000 # Cycle when the warmup percentage was hit.
733system.cpu.dcache.tags.occ_blocks::cpu.data 511.963762 # Average occupied blocks per requestor
734system.cpu.dcache.tags.occ_percent::cpu.data 0.999929 # Average percentage of cache occupancy
735system.cpu.dcache.tags.occ_percent::total 0.999929 # Average percentage of cache occupancy
736system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
737system.cpu.dcache.tags.age_task_id_blocks_1024::0 405 # Occupied blocks per task id
738system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id
739system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
740system.cpu.dcache.tags.tag_accesses 1335624835 # Number of tag accesses
741system.cpu.dcache.tags.data_accesses 1335624835 # Number of data accesses
742system.cpu.dcache.ReadReq_hits::cpu.data 469463783 # number of ReadReq hits
743system.cpu.dcache.ReadReq_hits::total 469463783 # number of ReadReq hits
744system.cpu.dcache.WriteReq_hits::cpu.data 168795373 # number of WriteReq hits
745system.cpu.dcache.WriteReq_hits::total 168795373 # number of WriteReq hits
746system.cpu.dcache.LoadLockedReq_hits::cpu.data 57 # number of LoadLockedReq hits
747system.cpu.dcache.LoadLockedReq_hits::total 57 # number of LoadLockedReq hits
748system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
749system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
750system.cpu.dcache.demand_hits::cpu.data 638259156 # number of demand (read+write) hits
751system.cpu.dcache.demand_hits::total 638259156 # number of demand (read+write) hits
752system.cpu.dcache.overall_hits::cpu.data 638259156 # number of overall hits
753system.cpu.dcache.overall_hits::total 638259156 # number of overall hits
754system.cpu.dcache.ReadReq_misses::cpu.data 17258559 # number of ReadReq misses
755system.cpu.dcache.ReadReq_misses::total 17258559 # number of ReadReq misses
756system.cpu.dcache.WriteReq_misses::cpu.data 3790674 # number of WriteReq misses
757system.cpu.dcache.WriteReq_misses::total 3790674 # number of WriteReq misses
758system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
759system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
760system.cpu.dcache.LoadLockedReq_misses::cpu.data 4 # number of LoadLockedReq misses
761system.cpu.dcache.LoadLockedReq_misses::total 4 # number of LoadLockedReq misses
762system.cpu.dcache.demand_misses::cpu.data 21049233 # number of demand (read+write) misses
763system.cpu.dcache.demand_misses::total 21049233 # number of demand (read+write) misses
764system.cpu.dcache.overall_misses::cpu.data 21049235 # number of overall misses
765system.cpu.dcache.overall_misses::total 21049235 # number of overall misses
766system.cpu.dcache.ReadReq_miss_latency::cpu.data 392276819281 # number of ReadReq miss cycles
767system.cpu.dcache.ReadReq_miss_latency::total 392276819281 # number of ReadReq miss cycles
768system.cpu.dcache.WriteReq_miss_latency::cpu.data 143202458834 # number of WriteReq miss cycles
769system.cpu.dcache.WriteReq_miss_latency::total 143202458834 # number of WriteReq miss cycles
770system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 194000 # number of LoadLockedReq miss cycles
771system.cpu.dcache.LoadLockedReq_miss_latency::total 194000 # number of LoadLockedReq miss cycles
772system.cpu.dcache.demand_miss_latency::cpu.data 535479278115 # number of demand (read+write) miss cycles
773system.cpu.dcache.demand_miss_latency::total 535479278115 # number of demand (read+write) miss cycles
774system.cpu.dcache.overall_miss_latency::cpu.data 535479278115 # number of overall miss cycles
775system.cpu.dcache.overall_miss_latency::total 535479278115 # number of overall miss cycles
776system.cpu.dcache.ReadReq_accesses::cpu.data 486722342 # number of ReadReq accesses(hits+misses)
777system.cpu.dcache.ReadReq_accesses::total 486722342 # number of ReadReq accesses(hits+misses)
778system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
779system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
780system.cpu.dcache.SoftPFReq_accesses::cpu.data 2 # number of SoftPFReq accesses(hits+misses)
781system.cpu.dcache.SoftPFReq_accesses::total 2 # number of SoftPFReq accesses(hits+misses)
782system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses)
783system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
784system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
785system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
786system.cpu.dcache.demand_accesses::cpu.data 659308389 # number of demand (read+write) accesses
787system.cpu.dcache.demand_accesses::total 659308389 # number of demand (read+write) accesses
788system.cpu.dcache.overall_accesses::cpu.data 659308391 # number of overall (read+write) accesses
789system.cpu.dcache.overall_accesses::total 659308391 # number of overall (read+write) accesses
790system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.035459 # miss rate for ReadReq accesses
791system.cpu.dcache.ReadReq_miss_rate::total 0.035459 # miss rate for ReadReq accesses
792system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.021964 # miss rate for WriteReq accesses
793system.cpu.dcache.WriteReq_miss_rate::total 0.021964 # miss rate for WriteReq accesses
794system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 1 # miss rate for SoftPFReq accesses
795system.cpu.dcache.SoftPFReq_miss_rate::total 1 # miss rate for SoftPFReq accesses
796system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.065574 # miss rate for LoadLockedReq accesses
797system.cpu.dcache.LoadLockedReq_miss_rate::total 0.065574 # miss rate for LoadLockedReq accesses
798system.cpu.dcache.demand_miss_rate::cpu.data 0.031926 # miss rate for demand accesses
799system.cpu.dcache.demand_miss_rate::total 0.031926 # miss rate for demand accesses
800system.cpu.dcache.overall_miss_rate::cpu.data 0.031926 # miss rate for overall accesses
801system.cpu.dcache.overall_miss_rate::total 0.031926 # miss rate for overall accesses
802system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22729.407437 # average ReadReq miss latency
803system.cpu.dcache.ReadReq_avg_miss_latency::total 22729.407437 # average ReadReq miss latency
804system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37777.571702 # average WriteReq miss latency
805system.cpu.dcache.WriteReq_avg_miss_latency::total 37777.571702 # average WriteReq miss latency
806system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 48500 # average LoadLockedReq miss latency
807system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 48500 # average LoadLockedReq miss latency
808system.cpu.dcache.demand_avg_miss_latency::cpu.data 25439.372452 # average overall miss latency
809system.cpu.dcache.demand_avg_miss_latency::total 25439.372452 # average overall miss latency
810system.cpu.dcache.overall_avg_miss_latency::cpu.data 25439.370035 # average overall miss latency
811system.cpu.dcache.overall_avg_miss_latency::total 25439.370035 # average overall miss latency
812system.cpu.dcache.blocked_cycles::no_mshrs 19976216 # number of cycles access was blocked
813system.cpu.dcache.blocked_cycles::no_targets 2938205 # number of cycles access was blocked
814system.cpu.dcache.blocked::no_mshrs 1014245 # number of cycles access was blocked
815system.cpu.dcache.blocked::no_targets 66761 # number of cycles access was blocked
816system.cpu.dcache.avg_blocked_cycles::no_mshrs 19.695651 # average number of cycles each access was blocked
817system.cpu.dcache.avg_blocked_cycles::no_targets 44.010800 # average number of cycles each access was blocked
818system.cpu.dcache.fast_writes 0 # number of fast writes performed
819system.cpu.dcache.cache_copies 0 # number of cache copies performed
820system.cpu.dcache.writebacks::writebacks 4837992 # number of writebacks
821system.cpu.dcache.writebacks::total 4837992 # number of writebacks
822system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2988204 # number of ReadReq MSHR hits
823system.cpu.dcache.ReadReq_mshr_hits::total 2988204 # number of ReadReq MSHR hits
824system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1053221 # number of WriteReq MSHR hits
825system.cpu.dcache.WriteReq_mshr_hits::total 1053221 # number of WriteReq MSHR hits
826system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 4 # number of LoadLockedReq MSHR hits
827system.cpu.dcache.LoadLockedReq_mshr_hits::total 4 # number of LoadLockedReq MSHR hits
828system.cpu.dcache.demand_mshr_hits::cpu.data 4041425 # number of demand (read+write) MSHR hits
829system.cpu.dcache.demand_mshr_hits::total 4041425 # number of demand (read+write) MSHR hits
830system.cpu.dcache.overall_mshr_hits::cpu.data 4041425 # number of overall MSHR hits
831system.cpu.dcache.overall_mshr_hits::total 4041425 # number of overall MSHR hits
832system.cpu.dcache.ReadReq_mshr_misses::cpu.data 14270355 # number of ReadReq MSHR misses
833system.cpu.dcache.ReadReq_mshr_misses::total 14270355 # number of ReadReq MSHR misses
834system.cpu.dcache.WriteReq_mshr_misses::cpu.data 2737453 # number of WriteReq MSHR misses
835system.cpu.dcache.WriteReq_mshr_misses::total 2737453 # number of WriteReq MSHR misses
836system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
837system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
838system.cpu.dcache.demand_mshr_misses::cpu.data 17007808 # number of demand (read+write) MSHR misses
839system.cpu.dcache.demand_mshr_misses::total 17007808 # number of demand (read+write) MSHR misses
840system.cpu.dcache.overall_mshr_misses::cpu.data 17007809 # number of overall MSHR misses
841system.cpu.dcache.overall_mshr_misses::total 17007809 # number of overall MSHR misses
842system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 303479537034 # number of ReadReq MSHR miss cycles
843system.cpu.dcache.ReadReq_mshr_miss_latency::total 303479537034 # number of ReadReq MSHR miss cycles
844system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 110174073244 # number of WriteReq MSHR miss cycles
845system.cpu.dcache.WriteReq_mshr_miss_latency::total 110174073244 # number of WriteReq MSHR miss cycles
846system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 62000 # number of SoftPFReq MSHR miss cycles
847system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 62000 # number of SoftPFReq MSHR miss cycles
848system.cpu.dcache.demand_mshr_miss_latency::cpu.data 413653610278 # number of demand (read+write) MSHR miss cycles
849system.cpu.dcache.demand_mshr_miss_latency::total 413653610278 # number of demand (read+write) MSHR miss cycles
850system.cpu.dcache.overall_mshr_miss_latency::cpu.data 413653672278 # number of overall MSHR miss cycles
851system.cpu.dcache.overall_mshr_miss_latency::total 413653672278 # number of overall MSHR miss cycles
852system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.029319 # mshr miss rate for ReadReq accesses
853system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029319 # mshr miss rate for ReadReq accesses
854system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015861 # mshr miss rate for WriteReq accesses
855system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015861 # mshr miss rate for WriteReq accesses
856system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for SoftPFReq accesses
857system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SoftPFReq accesses
858system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for demand accesses
859system.cpu.dcache.demand_mshr_miss_rate::total 0.025796 # mshr miss rate for demand accesses
860system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025796 # mshr miss rate for overall accesses
861system.cpu.dcache.overall_mshr_miss_rate::total 0.025796 # mshr miss rate for overall accesses
862system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21266.432197 # average ReadReq mshr miss latency
863system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21266.432197 # average ReadReq mshr miss latency
864system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40246.927799 # average WriteReq mshr miss latency
865system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40246.927799 # average WriteReq mshr miss latency
866system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 62000 # average SoftPFReq mshr miss latency
867system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 62000 # average SoftPFReq mshr miss latency
868system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24321.394637 # average overall mshr miss latency
869system.cpu.dcache.demand_avg_mshr_miss_latency::total 24321.394637 # average overall mshr miss latency
870system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24321.396852 # average overall mshr miss latency
871system.cpu.dcache.overall_avg_mshr_miss_latency::total 24321.396852 # average overall mshr miss latency
872system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
873system.cpu.icache.tags.replacements 591 # number of replacements
874system.cpu.icache.tags.tagsinuse 445.749905 # Cycle average of tags in use
875system.cpu.icache.tags.total_refs 656876635 # Total number of references to valid blocks.
876system.cpu.icache.tags.sampled_refs 1079 # Sample count of references to valid blocks.
877system.cpu.icache.tags.avg_refs 608782.794254 # Average number of references to valid blocks.
878system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
879system.cpu.icache.tags.occ_blocks::cpu.inst 445.749905 # Average occupied blocks per requestor
880system.cpu.icache.tags.occ_percent::cpu.inst 0.870605 # Average percentage of cache occupancy
881system.cpu.icache.tags.occ_percent::total 0.870605 # Average percentage of cache occupancy
882system.cpu.icache.tags.occ_task_id_blocks::1024 488 # Occupied blocks per task id
883system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
884system.cpu.icache.tags.age_task_id_blocks_1024::1 15 # Occupied blocks per task id
885system.cpu.icache.tags.age_task_id_blocks_1024::4 441 # Occupied blocks per task id
886system.cpu.icache.tags.occ_task_id_percent::1024 0.953125 # Percentage of cache occupancy per task id
887system.cpu.icache.tags.tag_accesses 1313757597 # Number of tag accesses
888system.cpu.icache.tags.data_accesses 1313757597 # Number of data accesses
889system.cpu.icache.ReadReq_hits::cpu.inst 656876635 # number of ReadReq hits
890system.cpu.icache.ReadReq_hits::total 656876635 # number of ReadReq hits
891system.cpu.icache.demand_hits::cpu.inst 656876635 # number of demand (read+write) hits
892system.cpu.icache.demand_hits::total 656876635 # number of demand (read+write) hits
893system.cpu.icache.overall_hits::cpu.inst 656876635 # number of overall hits
894system.cpu.icache.overall_hits::total 656876635 # number of overall hits
895system.cpu.icache.ReadReq_misses::cpu.inst 1624 # number of ReadReq misses
896system.cpu.icache.ReadReq_misses::total 1624 # number of ReadReq misses
897system.cpu.icache.demand_misses::cpu.inst 1624 # number of demand (read+write) misses
898system.cpu.icache.demand_misses::total 1624 # number of demand (read+write) misses
899system.cpu.icache.overall_misses::cpu.inst 1624 # number of overall misses
900system.cpu.icache.overall_misses::total 1624 # number of overall misses
901system.cpu.icache.ReadReq_miss_latency::cpu.inst 95182738 # number of ReadReq miss cycles
902system.cpu.icache.ReadReq_miss_latency::total 95182738 # number of ReadReq miss cycles
903system.cpu.icache.demand_miss_latency::cpu.inst 95182738 # number of demand (read+write) miss cycles
904system.cpu.icache.demand_miss_latency::total 95182738 # number of demand (read+write) miss cycles
905system.cpu.icache.overall_miss_latency::cpu.inst 95182738 # number of overall miss cycles
906system.cpu.icache.overall_miss_latency::total 95182738 # number of overall miss cycles
907system.cpu.icache.ReadReq_accesses::cpu.inst 656878259 # number of ReadReq accesses(hits+misses)
908system.cpu.icache.ReadReq_accesses::total 656878259 # number of ReadReq accesses(hits+misses)
909system.cpu.icache.demand_accesses::cpu.inst 656878259 # number of demand (read+write) accesses
910system.cpu.icache.demand_accesses::total 656878259 # number of demand (read+write) accesses
911system.cpu.icache.overall_accesses::cpu.inst 656878259 # number of overall (read+write) accesses
912system.cpu.icache.overall_accesses::total 656878259 # number of overall (read+write) accesses
913system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
914system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
915system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
916system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
917system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
918system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
919system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58610.060345 # average ReadReq miss latency
920system.cpu.icache.ReadReq_avg_miss_latency::total 58610.060345 # average ReadReq miss latency
921system.cpu.icache.demand_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency
922system.cpu.icache.demand_avg_miss_latency::total 58610.060345 # average overall miss latency
923system.cpu.icache.overall_avg_miss_latency::cpu.inst 58610.060345 # average overall miss latency
924system.cpu.icache.overall_avg_miss_latency::total 58610.060345 # average overall miss latency
925system.cpu.icache.blocked_cycles::no_mshrs 15932 # number of cycles access was blocked
926system.cpu.icache.blocked_cycles::no_targets 279 # number of cycles access was blocked
927system.cpu.icache.blocked::no_mshrs 193 # number of cycles access was blocked
928system.cpu.icache.blocked::no_targets 7 # number of cycles access was blocked
929system.cpu.icache.avg_blocked_cycles::no_mshrs 82.549223 # average number of cycles each access was blocked
930system.cpu.icache.avg_blocked_cycles::no_targets 39.857143 # average number of cycles each access was blocked
931system.cpu.icache.fast_writes 0 # number of fast writes performed
932system.cpu.icache.cache_copies 0 # number of cache copies performed
933system.cpu.icache.ReadReq_mshr_hits::cpu.inst 545 # number of ReadReq MSHR hits
934system.cpu.icache.ReadReq_mshr_hits::total 545 # number of ReadReq MSHR hits
935system.cpu.icache.demand_mshr_hits::cpu.inst 545 # number of demand (read+write) MSHR hits
936system.cpu.icache.demand_mshr_hits::total 545 # number of demand (read+write) MSHR hits
937system.cpu.icache.overall_mshr_hits::cpu.inst 545 # number of overall MSHR hits
938system.cpu.icache.overall_mshr_hits::total 545 # number of overall MSHR hits
939system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1079 # number of ReadReq MSHR misses
940system.cpu.icache.ReadReq_mshr_misses::total 1079 # number of ReadReq MSHR misses
941system.cpu.icache.demand_mshr_misses::cpu.inst 1079 # number of demand (read+write) MSHR misses
942system.cpu.icache.demand_mshr_misses::total 1079 # number of demand (read+write) MSHR misses
943system.cpu.icache.overall_mshr_misses::cpu.inst 1079 # number of overall MSHR misses
944system.cpu.icache.overall_mshr_misses::total 1079 # number of overall MSHR misses
945system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 69657739 # number of ReadReq MSHR miss cycles
946system.cpu.icache.ReadReq_mshr_miss_latency::total 69657739 # number of ReadReq MSHR miss cycles
947system.cpu.icache.demand_mshr_miss_latency::cpu.inst 69657739 # number of demand (read+write) MSHR miss cycles
948system.cpu.icache.demand_mshr_miss_latency::total 69657739 # number of demand (read+write) MSHR miss cycles
949system.cpu.icache.overall_mshr_miss_latency::cpu.inst 69657739 # number of overall MSHR miss cycles
950system.cpu.icache.overall_mshr_miss_latency::total 69657739 # number of overall MSHR miss cycles
951system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
952system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
953system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
954system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
955system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
956system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
957system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64557.682113 # average ReadReq mshr miss latency
958system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64557.682113 # average ReadReq mshr miss latency
959system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency
960system.cpu.icache.demand_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency
961system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64557.682113 # average overall mshr miss latency
962system.cpu.icache.overall_avg_mshr_miss_latency::total 64557.682113 # average overall mshr miss latency
963system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
964system.cpu.l2cache.prefetcher.num_hwpf_issued 10957108 # number of hwpf issued
965system.cpu.l2cache.prefetcher.pfIdentified 11640584 # number of prefetch candidates identified
966system.cpu.l2cache.prefetcher.pfBufferHit 428597 # number of redundant prefetches already in prefetch queue
967system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped
968system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size
969system.cpu.l2cache.prefetcher.pfSpanPage 4655192 # number of prefetches not generated due to page crossing
970system.cpu.l2cache.tags.replacements 4712285 # number of replacements
971system.cpu.l2cache.tags.tagsinuse 16126.126522 # Cycle average of tags in use
972system.cpu.l2cache.tags.total_refs 15322460 # Total number of references to valid blocks.
973system.cpu.l2cache.tags.sampled_refs 4728219 # Sample count of references to valid blocks.
974system.cpu.l2cache.tags.avg_refs 3.240641 # Average number of references to valid blocks.
975system.cpu.l2cache.tags.warmup_cycle 29457635500 # Cycle when the warmup percentage was hit.
976system.cpu.l2cache.tags.occ_blocks::writebacks 5257.920148 # Average occupied blocks per requestor
977system.cpu.l2cache.tags.occ_blocks::cpu.inst 18.981837 # Average occupied blocks per requestor
978system.cpu.l2cache.tags.occ_blocks::cpu.data 7532.490537 # Average occupied blocks per requestor
979system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 3316.734000 # Average occupied blocks per requestor
980system.cpu.l2cache.tags.occ_percent::writebacks 0.320918 # Average percentage of cache occupancy
981system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001159 # Average percentage of cache occupancy
982system.cpu.l2cache.tags.occ_percent::cpu.data 0.459747 # Average percentage of cache occupancy
983system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.202437 # Average percentage of cache occupancy
984system.cpu.l2cache.tags.occ_percent::total 0.984261 # Average percentage of cache occupancy
985system.cpu.l2cache.tags.occ_task_id_blocks::1022 762 # Occupied blocks per task id
986system.cpu.l2cache.tags.occ_task_id_blocks::1024 15172 # Occupied blocks per task id
987system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id
988system.cpu.l2cache.tags.age_task_id_blocks_1022::1 562 # Occupied blocks per task id
989system.cpu.l2cache.tags.age_task_id_blocks_1022::3 192 # Occupied blocks per task id
990system.cpu.l2cache.tags.age_task_id_blocks_1024::0 487 # Occupied blocks per task id
991system.cpu.l2cache.tags.age_task_id_blocks_1024::1 2381 # Occupied blocks per task id
992system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1270 # Occupied blocks per task id
993system.cpu.l2cache.tags.age_task_id_blocks_1024::3 9338 # Occupied blocks per task id
994system.cpu.l2cache.tags.age_task_id_blocks_1024::4 1696 # Occupied blocks per task id
995system.cpu.l2cache.tags.occ_task_id_percent::1022 0.046509 # Percentage of cache occupancy per task id
996system.cpu.l2cache.tags.occ_task_id_percent::1024 0.926025 # Percentage of cache occupancy per task id
997system.cpu.l2cache.tags.tag_accesses 357015786 # Number of tag accesses
998system.cpu.l2cache.tags.data_accesses 357015786 # Number of data accesses
999system.cpu.l2cache.ReadReq_hits::cpu.inst 43 # number of ReadReq hits
1000system.cpu.l2cache.ReadReq_hits::cpu.data 11478119 # number of ReadReq hits
1001system.cpu.l2cache.ReadReq_hits::total 11478162 # number of ReadReq hits
1002system.cpu.l2cache.Writeback_hits::writebacks 4837992 # number of Writeback hits
1003system.cpu.l2cache.Writeback_hits::total 4837992 # number of Writeback hits
1004system.cpu.l2cache.ReadExReq_hits::cpu.data 1752292 # number of ReadExReq hits
1005system.cpu.l2cache.ReadExReq_hits::total 1752292 # number of ReadExReq hits
1006system.cpu.l2cache.demand_hits::cpu.inst 43 # number of demand (read+write) hits
1007system.cpu.l2cache.demand_hits::cpu.data 13230411 # number of demand (read+write) hits
1008system.cpu.l2cache.demand_hits::total 13230454 # number of demand (read+write) hits
1009system.cpu.l2cache.overall_hits::cpu.inst 43 # number of overall hits
1010system.cpu.l2cache.overall_hits::cpu.data 13230411 # number of overall hits
1011system.cpu.l2cache.overall_hits::total 13230454 # number of overall hits
1012system.cpu.l2cache.ReadReq_misses::cpu.inst 1036 # number of ReadReq misses
1013system.cpu.l2cache.ReadReq_misses::cpu.data 2792203 # number of ReadReq misses
1014system.cpu.l2cache.ReadReq_misses::total 2793239 # number of ReadReq misses
1015system.cpu.l2cache.ReadExReq_misses::cpu.data 985195 # number of ReadExReq misses
1016system.cpu.l2cache.ReadExReq_misses::total 985195 # number of ReadExReq misses
1017system.cpu.l2cache.demand_misses::cpu.inst 1036 # number of demand (read+write) misses
1018system.cpu.l2cache.demand_misses::cpu.data 3777398 # number of demand (read+write) misses
1019system.cpu.l2cache.demand_misses::total 3778434 # number of demand (read+write) misses
1020system.cpu.l2cache.overall_misses::cpu.inst 1036 # number of overall misses
1021system.cpu.l2cache.overall_misses::cpu.data 3777398 # number of overall misses
1022system.cpu.l2cache.overall_misses::total 3778434 # number of overall misses
1023system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 68850750 # number of ReadReq miss cycles
1024system.cpu.l2cache.ReadReq_miss_latency::cpu.data 219170127718 # number of ReadReq miss cycles
1025system.cpu.l2cache.ReadReq_miss_latency::total 219238978468 # number of ReadReq miss cycles
1026system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 95974587720 # number of ReadExReq miss cycles
1027system.cpu.l2cache.ReadExReq_miss_latency::total 95974587720 # number of ReadExReq miss cycles
1028system.cpu.l2cache.demand_miss_latency::cpu.inst 68850750 # number of demand (read+write) miss cycles
1029system.cpu.l2cache.demand_miss_latency::cpu.data 315144715438 # number of demand (read+write) miss cycles
1030system.cpu.l2cache.demand_miss_latency::total 315213566188 # number of demand (read+write) miss cycles
1031system.cpu.l2cache.overall_miss_latency::cpu.inst 68850750 # number of overall miss cycles
1032system.cpu.l2cache.overall_miss_latency::cpu.data 315144715438 # number of overall miss cycles
1033system.cpu.l2cache.overall_miss_latency::total 315213566188 # number of overall miss cycles
1034system.cpu.l2cache.ReadReq_accesses::cpu.inst 1079 # number of ReadReq accesses(hits+misses)
1035system.cpu.l2cache.ReadReq_accesses::cpu.data 14270322 # number of ReadReq accesses(hits+misses)
1036system.cpu.l2cache.ReadReq_accesses::total 14271401 # number of ReadReq accesses(hits+misses)
1037system.cpu.l2cache.Writeback_accesses::writebacks 4837992 # number of Writeback accesses(hits+misses)
1038system.cpu.l2cache.Writeback_accesses::total 4837992 # number of Writeback accesses(hits+misses)
1039system.cpu.l2cache.ReadExReq_accesses::cpu.data 2737487 # number of ReadExReq accesses(hits+misses)
1040system.cpu.l2cache.ReadExReq_accesses::total 2737487 # number of ReadExReq accesses(hits+misses)
1041system.cpu.l2cache.demand_accesses::cpu.inst 1079 # number of demand (read+write) accesses
1042system.cpu.l2cache.demand_accesses::cpu.data 17007809 # number of demand (read+write) accesses
1043system.cpu.l2cache.demand_accesses::total 17008888 # number of demand (read+write) accesses
1044system.cpu.l2cache.overall_accesses::cpu.inst 1079 # number of overall (read+write) accesses
1045system.cpu.l2cache.overall_accesses::cpu.data 17007809 # number of overall (read+write) accesses
1046system.cpu.l2cache.overall_accesses::total 17008888 # number of overall (read+write) accesses
1047system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960148 # miss rate for ReadReq accesses
1048system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.195665 # miss rate for ReadReq accesses
1049system.cpu.l2cache.ReadReq_miss_rate::total 0.195723 # miss rate for ReadReq accesses
1050system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.359890 # miss rate for ReadExReq accesses
1051system.cpu.l2cache.ReadExReq_miss_rate::total 0.359890 # miss rate for ReadExReq accesses
1052system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960148 # miss rate for demand accesses
1053system.cpu.l2cache.demand_miss_rate::cpu.data 0.222098 # miss rate for demand accesses
1054system.cpu.l2cache.demand_miss_rate::total 0.222145 # miss rate for demand accesses
1055system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960148 # miss rate for overall accesses
1056system.cpu.l2cache.overall_miss_rate::cpu.data 0.222098 # miss rate for overall accesses
1057system.cpu.l2cache.overall_miss_rate::total 0.222145 # miss rate for overall accesses
1058system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66458.252896 # average ReadReq miss latency
1059system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78493.622318 # average ReadReq miss latency
1060system.cpu.l2cache.ReadReq_avg_miss_latency::total 78489.158453 # average ReadReq miss latency
1061system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 97416.844097 # average ReadExReq miss latency
1062system.cpu.l2cache.ReadExReq_avg_miss_latency::total 97416.844097 # average ReadExReq miss latency
1063system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66458.252896 # average overall miss latency
1064system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83429.047042 # average overall miss latency
1065system.cpu.l2cache.demand_avg_miss_latency::total 83424.393859 # average overall miss latency
1066system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66458.252896 # average overall miss latency
1067system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83429.047042 # average overall miss latency
1068system.cpu.l2cache.overall_avg_miss_latency::total 83424.393859 # average overall miss latency
1069system.cpu.l2cache.blocked_cycles::no_mshrs 69 # number of cycles access was blocked
1070system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
1071system.cpu.l2cache.blocked::no_mshrs 1 # number of cycles access was blocked
1072system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
1073system.cpu.l2cache.avg_blocked_cycles::no_mshrs 69 # average number of cycles each access was blocked
1074system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
1075system.cpu.l2cache.fast_writes 0 # number of fast writes performed
1076system.cpu.l2cache.cache_copies 0 # number of cache copies performed
1077system.cpu.l2cache.writebacks::writebacks 1638491 # number of writebacks
1078system.cpu.l2cache.writebacks::total 1638491 # number of writebacks
1079system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 43338 # number of ReadReq MSHR hits
1080system.cpu.l2cache.ReadReq_mshr_hits::total 43338 # number of ReadReq MSHR hits
1081system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 3740 # number of ReadExReq MSHR hits
1082system.cpu.l2cache.ReadExReq_mshr_hits::total 3740 # number of ReadExReq MSHR hits
1083system.cpu.l2cache.demand_mshr_hits::cpu.data 47078 # number of demand (read+write) MSHR hits
1084system.cpu.l2cache.demand_mshr_hits::total 47078 # number of demand (read+write) MSHR hits
1085system.cpu.l2cache.overall_mshr_hits::cpu.data 47078 # number of overall MSHR hits
1086system.cpu.l2cache.overall_mshr_hits::total 47078 # number of overall MSHR hits
1087system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1036 # number of ReadReq MSHR misses
1088system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 2748865 # number of ReadReq MSHR misses
1089system.cpu.l2cache.ReadReq_mshr_misses::total 2749901 # number of ReadReq MSHR misses
1090system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 993225 # number of HardPFReq MSHR misses
1091system.cpu.l2cache.HardPFReq_mshr_misses::total 993225 # number of HardPFReq MSHR misses
1092system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 981455 # number of ReadExReq MSHR misses
1093system.cpu.l2cache.ReadExReq_mshr_misses::total 981455 # number of ReadExReq MSHR misses
1094system.cpu.l2cache.demand_mshr_misses::cpu.inst 1036 # number of demand (read+write) MSHR misses
1095system.cpu.l2cache.demand_mshr_misses::cpu.data 3730320 # number of demand (read+write) MSHR misses
1096system.cpu.l2cache.demand_mshr_misses::total 3731356 # number of demand (read+write) MSHR misses
1097system.cpu.l2cache.overall_mshr_misses::cpu.inst 1036 # number of overall MSHR misses
1098system.cpu.l2cache.overall_mshr_misses::cpu.data 3730320 # number of overall MSHR misses
1099system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 993225 # number of overall MSHR misses
1100system.cpu.l2cache.overall_mshr_misses::total 4724581 # number of overall MSHR misses
1101system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 59969750 # number of ReadReq MSHR miss cycles
1102system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 193568757616 # number of ReadReq MSHR miss cycles
1103system.cpu.l2cache.ReadReq_mshr_miss_latency::total 193628727366 # number of ReadReq MSHR miss cycles
1104system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of HardPFReq MSHR miss cycles
1105system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 68540364307 # number of HardPFReq MSHR miss cycles
1106system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 87429015038 # number of ReadExReq MSHR miss cycles
1107system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 87429015038 # number of ReadExReq MSHR miss cycles
1108system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 59969750 # number of demand (read+write) MSHR miss cycles
1109system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 280997772654 # number of demand (read+write) MSHR miss cycles
1110system.cpu.l2cache.demand_mshr_miss_latency::total 281057742404 # number of demand (read+write) MSHR miss cycles
1111system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 59969750 # number of overall MSHR miss cycles
1112system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 280997772654 # number of overall MSHR miss cycles
1113system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 68540364307 # number of overall MSHR miss cycles
1114system.cpu.l2cache.overall_mshr_miss_latency::total 349598106711 # number of overall MSHR miss cycles
1115system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for ReadReq accesses
1116system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.192628 # mshr miss rate for ReadReq accesses
1117system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.192686 # mshr miss rate for ReadReq accesses
1118system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses
1119system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses
1120system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358524 # mshr miss rate for ReadExReq accesses
1121system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.358524 # mshr miss rate for ReadExReq accesses
1122system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for demand accesses
1123system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for demand accesses
1124system.cpu.l2cache.demand_mshr_miss_rate::total 0.219377 # mshr miss rate for demand accesses
1125system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.960148 # mshr miss rate for overall accesses
1126system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.219330 # mshr miss rate for overall accesses
1127system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses
1128system.cpu.l2cache.overall_mshr_miss_rate::total 0.277771 # mshr miss rate for overall accesses
1129system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57885.859073 # average ReadReq mshr miss latency
1130system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 70417.702439 # average ReadReq mshr miss latency
1131system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 70412.981182 # average ReadReq mshr miss latency
1132system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average HardPFReq mshr miss latency
1133system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 69007.892781 # average HardPFReq mshr miss latency
1134system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 89081.022602 # average ReadExReq mshr miss latency
1135system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 89081.022602 # average ReadExReq mshr miss latency
1136system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency
1137system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency
1138system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75323.218263 # average overall mshr miss latency
1139system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57885.859073 # average overall mshr miss latency
1140system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75328.061039 # average overall mshr miss latency
1141system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 69007.892781 # average overall mshr miss latency
1142system.cpu.l2cache.overall_avg_mshr_miss_latency::total 73995.579018 # average overall mshr miss latency
1143system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
1144system.cpu.toL2Bus.trans_dist::ReadReq 14271401 # Transaction distribution
1145system.cpu.toL2Bus.trans_dist::ReadResp 14271401 # Transaction distribution
1146system.cpu.toL2Bus.trans_dist::Writeback 4837992 # Transaction distribution
1147system.cpu.toL2Bus.trans_dist::HardPFReq 1352607 # Transaction distribution
1148system.cpu.toL2Bus.trans_dist::ReadExReq 2737487 # Transaction distribution
1149system.cpu.toL2Bus.trans_dist::ReadExResp 2737487 # Transaction distribution
1150system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2158 # Packet count per connected master and slave (bytes)
1151system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 38853610 # Packet count per connected master and slave (bytes)
1152system.cpu.toL2Bus.pkt_count::total 38855768 # Packet count per connected master and slave (bytes)
1153system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 69056 # Cumulative packet size per connected master and slave (bytes)
1154system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 1398131264 # Cumulative packet size per connected master and slave (bytes)
1155system.cpu.toL2Bus.pkt_size::total 1398200320 # Cumulative packet size per connected master and slave (bytes)
1156system.cpu.toL2Bus.snoops 1352607 # Total snoops (count)
1157system.cpu.toL2Bus.snoop_fanout::samples 23199492 # Request fanout histogram
1158system.cpu.toL2Bus.snoop_fanout::mean 5.058303 # Request fanout histogram
1159system.cpu.toL2Bus.snoop_fanout::stdev 0.234316 # Request fanout histogram
1160system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1161system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
1162system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
1163system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
1164system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
1165system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
1166system.cpu.toL2Bus.snoop_fanout::5 21846885 94.17% 94.17% # Request fanout histogram
1167system.cpu.toL2Bus.snoop_fanout::6 1352607 5.83% 100.00% # Request fanout histogram
1168system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1169system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
1170system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
1171system.cpu.toL2Bus.snoop_fanout::total 23199492 # Request fanout histogram
1172system.cpu.toL2Bus.reqLayer0.occupancy 15761436995 # Layer occupancy (ticks)
1173system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
1174system.cpu.toL2Bus.respLayer0.occupancy 1798250 # Layer occupancy (ticks)
1175system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
1176system.cpu.toL2Bus.respLayer1.occupancy 26002804288 # Layer occupancy (ticks)
1177system.cpu.toL2Bus.respLayer1.utilization 3.4 # Layer utilization (%)
1178system.membus.trans_dist::ReadReq 3738412 # Transaction distribution
1179system.membus.trans_dist::ReadResp 3738412 # Transaction distribution
1180system.membus.trans_dist::Writeback 1638491 # Transaction distribution
1181system.membus.trans_dist::ReadExReq 981933 # Transaction distribution
1182system.membus.trans_dist::ReadExResp 981933 # Transaction distribution
1183system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 11079181 # Packet count per connected master and slave (bytes)
1184system.membus.pkt_count::total 11079181 # Packet count per connected master and slave (bytes)
1185system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 406965504 # Cumulative packet size per connected master and slave (bytes)
1186system.membus.pkt_size::total 406965504 # Cumulative packet size per connected master and slave (bytes)
1187system.membus.snoops 0 # Total snoops (count)
1188system.membus.snoop_fanout::samples 6358836 # Request fanout histogram
1189system.membus.snoop_fanout::mean 0 # Request fanout histogram
1190system.membus.snoop_fanout::stdev 0 # Request fanout histogram
1191system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
1192system.membus.snoop_fanout::0 6358836 100.00% 100.00% # Request fanout histogram
1193system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
1194system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
1195system.membus.snoop_fanout::min_value 0 # Request fanout histogram
1196system.membus.snoop_fanout::max_value 0 # Request fanout histogram
1197system.membus.snoop_fanout::total 6358836 # Request fanout histogram
1198system.membus.reqLayer0.occupancy 20942586092 # Layer occupancy (ticks)
1199system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
1200system.membus.respLayer1.occupancy 44003891862 # Layer occupancy (ticks)
1201system.membus.respLayer1.utilization 5.8 # Layer utilization (%)
1202
1203---------- End Simulation Statistics ----------