1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.506591 # Number of seconds simulated
4sim_ticks 506591420000 # Number of ticks simulated
5final_tick 506591420000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 188296 # Simulator instruction rate (inst/s)
8host_op_rate 202861 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 61758141 # Simulator tick rate (ticks/s)
10host_mem_usage 254008 # Number of bytes of host memory used
11host_seconds 8202.83 # Real time elapsed on the host
12sim_insts 1544563023 # Number of instructions simulated
13sim_ops 1664032415 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 46336 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 143772736 # Number of bytes read from this memory
18system.physmem.bytes_read::total 143819072 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 46336 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 46336 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 70460288 # Number of bytes written to this memory
22system.physmem.bytes_written::total 70460288 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 724 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 2246449 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 2247173 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 1100942 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 1100942 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 91466 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 283804128 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 283895594 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 91466 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 91466 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 139087014 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 139087014 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 139087014 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 91466 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 283804128 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 422982608 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 2247174 # Number of read requests accepted
40system.physmem.writeReqs 1100942 # Number of write requests accepted
41system.physmem.readBursts 2247174 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 1100942 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 143725504 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 93632 # Total number of bytes read from write queue
45system.physmem.bytesWritten 70458432 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 143819136 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 70460288 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 1463 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 139870 # Per bank write bursts
52system.physmem.perBankRdBursts::1 136313 # Per bank write bursts
53system.physmem.perBankRdBursts::2 133717 # Per bank write bursts
54system.physmem.perBankRdBursts::3 136218 # Per bank write bursts
55system.physmem.perBankRdBursts::4 134833 # Per bank write bursts
56system.physmem.perBankRdBursts::5 135331 # Per bank write bursts
57system.physmem.perBankRdBursts::6 136159 # Per bank write bursts
58system.physmem.perBankRdBursts::7 136113 # Per bank write bursts
59system.physmem.perBankRdBursts::8 143820 # Per bank write bursts
60system.physmem.perBankRdBursts::9 146459 # Per bank write bursts
61system.physmem.perBankRdBursts::10 144333 # Per bank write bursts
62system.physmem.perBankRdBursts::11 146068 # Per bank write bursts
63system.physmem.perBankRdBursts::12 145787 # Per bank write bursts
64system.physmem.perBankRdBursts::13 145950 # Per bank write bursts
65system.physmem.perBankRdBursts::14 142167 # Per bank write bursts
66system.physmem.perBankRdBursts::15 142573 # Per bank write bursts
67system.physmem.perBankWrBursts::0 69256 # Per bank write bursts
68system.physmem.perBankWrBursts::1 67490 # Per bank write bursts
69system.physmem.perBankWrBursts::2 65701 # Per bank write bursts
70system.physmem.perBankWrBursts::3 66292 # Per bank write bursts
71system.physmem.perBankWrBursts::4 66182 # Per bank write bursts
72system.physmem.perBankWrBursts::5 66456 # Per bank write bursts
73system.physmem.perBankWrBursts::6 67905 # Per bank write bursts
74system.physmem.perBankWrBursts::7 68814 # Per bank write bursts
75system.physmem.perBankWrBursts::8 70409 # Per bank write bursts
76system.physmem.perBankWrBursts::9 70980 # Per bank write bursts
77system.physmem.perBankWrBursts::10 70565 # Per bank write bursts
78system.physmem.perBankWrBursts::11 70894 # Per bank write bursts
79system.physmem.perBankWrBursts::12 70329 # Per bank write bursts
80system.physmem.perBankWrBursts::13 70807 # Per bank write bursts
81system.physmem.perBankWrBursts::14 69706 # Per bank write bursts
82system.physmem.perBankWrBursts::15 69127 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 506591366500 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 2247174 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 1100942 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 1574104 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 476401 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 148213 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 46974 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 16 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see

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139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 22580 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 24088 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 48460 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 60043 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 65003 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 66811 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 67201 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 67231 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 67460 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 67663 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 67777 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 68170 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 69182 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 70669 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 67984 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 68233 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 66514 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::32 65455 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::33 246 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::34 63 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::35 18 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::36 8 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::37 5 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::40 4 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::41 3 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::42 3 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::43 3 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::44 6 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::45 4 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::46 4 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::47 4 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::48 6 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::49 3 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::50 3 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::51 3 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::52 3 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::53 2 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::54 2 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::55 1 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::56 1 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::57 1 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196system.physmem.bytesPerActivate::samples 2025013 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::mean 105.768407 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::gmean 82.613194 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::stdev 129.925028 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::0-127 1567130 77.39% 77.39% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::128-255 318117 15.71% 93.10% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::256-383 66732 3.30% 96.39% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::384-511 23886 1.18% 97.57% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::512-639 14001 0.69% 98.26% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::640-767 6496 0.32% 98.59% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::768-895 4833 0.24% 98.82% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::896-1023 3896 0.19% 99.02% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1024-1151 19922 0.98% 100.00% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::total 2025013 # Bytes accessed per row activation
210system.physmem.rdPerTurnAround::samples 65320 # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::mean 34.335441 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::stdev 154.678788 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::0-1023 65282 99.94% 99.94% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::1024-2047 11 0.02% 99.96% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
219system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
220system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
221system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
222system.physmem.rdPerTurnAround::total 65320 # Reads before turning the bus around for writes
223system.physmem.wrPerTurnAround::samples 65320 # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::mean 16.854149 # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::gmean 16.813582 # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::stdev 1.224401 # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::16-17 41990 64.28% 64.28% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::18-19 22168 33.94% 98.22% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::20-21 1073 1.64% 99.86% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::22-23 57 0.09% 99.95% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::24-25 8 0.01% 99.96% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::26-27 3 0.00% 99.97% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::28-29 2 0.00% 99.97% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::30-31 14 0.02% 99.99% # Writes before turning the bus around for reads
235system.physmem.wrPerTurnAround::32-33 2 0.00% 100.00% # Writes before turning the bus around for reads
236system.physmem.wrPerTurnAround::34-35 1 0.00% 100.00% # Writes before turning the bus around for reads
237system.physmem.wrPerTurnAround::44-45 1 0.00% 100.00% # Writes before turning the bus around for reads
238system.physmem.wrPerTurnAround::84-85 1 0.00% 100.00% # Writes before turning the bus around for reads
239system.physmem.wrPerTurnAround::total 65320 # Writes before turning the bus around for reads
240system.physmem.totQLat 50678676000 # Total ticks spent queuing
241system.physmem.totMemAccLat 92785757250 # Total ticks spent from burst creation until serviced by the DRAM
242system.physmem.totBusLat 11228555000 # Total ticks spent in databus transfers
243system.physmem.avgQLat 22566.87 # Average queueing delay per DRAM burst
244system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
245system.physmem.avgMemAccLat 41316.87 # Average memory access latency per DRAM burst
246system.physmem.avgRdBW 283.71 # Average DRAM read bandwidth in MiByte/s
247system.physmem.avgWrBW 139.08 # Average achieved write bandwidth in MiByte/s
248system.physmem.avgRdBWSys 283.90 # Average system read bandwidth in MiByte/s
249system.physmem.avgWrBWSys 139.09 # Average system write bandwidth in MiByte/s
250system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
251system.physmem.busUtil 3.30 # Data bus utilization in percentage
252system.physmem.busUtilRead 2.22 # Data bus utilization in percentage for reads
253system.physmem.busUtilWrite 1.09 # Data bus utilization in percentage for writes
254system.physmem.avgRdQLen 1.19 # Average read queue length when enqueuing
255system.physmem.avgWrQLen 25.41 # Average write queue length when enqueuing
256system.physmem.readRowHits 906473 # Number of row buffer hits during reads
257system.physmem.writeRowHits 415128 # Number of row buffer hits during writes
258system.physmem.readRowHitRate 40.36 # Row buffer hit rate for reads
259system.physmem.writeRowHitRate 37.71 # Row buffer hit rate for writes
260system.physmem.avgGap 151306.40 # Average gap between requests
261system.physmem.pageHitRate 39.49 # Row buffer hit rate, read and write combined
262system.physmem.memoryStateTime::IDLE 89126966500 # Time in different power states
263system.physmem.memoryStateTime::REF 16916120000 # Time in different power states
264system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
265system.physmem.memoryStateTime::ACT 400546526000 # Time in different power states
266system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
267system.membus.throughput 422982608 # Throughput (bytes/s)
268system.membus.trans_dist::ReadReq 1419539 # Transaction distribution
269system.membus.trans_dist::ReadResp 1419538 # Transaction distribution
270system.membus.trans_dist::Writeback 1100942 # Transaction distribution
271system.membus.trans_dist::ReadExReq 827635 # Transaction distribution
272system.membus.trans_dist::ReadExResp 827635 # Transaction distribution
273system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5595289 # Packet count per connected master and slave (bytes)
274system.membus.pkt_count::total 5595289 # Packet count per connected master and slave (bytes)
275system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 214279360 # Cumulative packet size per connected master and slave (bytes)
276system.membus.tot_pkt_size::total 214279360 # Cumulative packet size per connected master and slave (bytes)
277system.membus.data_through_bus 214279360 # Total data (bytes)
278system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
279system.membus.reqLayer0.occupancy 12858312000 # Layer occupancy (ticks)
280system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
281system.membus.respLayer1.occupancy 21011522750 # Layer occupancy (ticks)
282system.membus.respLayer1.utilization 4.1 # Layer utilization (%)
283system.cpu_clk_domain.clock 500 # Clock period in ticks
284system.cpu.branchPred.lookups 322479068 # Number of BP lookups
285system.cpu.branchPred.condPredicted 251697336 # Number of conditional branches predicted
286system.cpu.branchPred.condIncorrect 15342173 # Number of conditional branches incorrect
287system.cpu.branchPred.BTBLookups 182789015 # Number of BTB lookups
288system.cpu.branchPred.BTBHits 169211218 # Number of BTB hits
289system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
290system.cpu.branchPred.BTBHitPct 92.571875 # BTB Hit Percentage
291system.cpu.branchPred.usedRAS 19180311 # Number of times the RAS was used to get a target.
292system.cpu.branchPred.RASInCorrect 62 # Number of incorrect RAS predictions.
293system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
294system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
295system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
296system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
297system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
298system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
299system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
300system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

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370system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
371system.cpu.itb.read_accesses 0 # DTB read accesses
372system.cpu.itb.write_accesses 0 # DTB write accesses
373system.cpu.itb.inst_accesses 0 # ITB inst accesses
374system.cpu.itb.hits 0 # DTB hits
375system.cpu.itb.misses 0 # DTB misses
376system.cpu.itb.accesses 0 # DTB accesses
377system.cpu.workload.num_syscalls 46 # Number of system calls
378system.cpu.numCycles 1013182841 # number of cpu cycles simulated
379system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
380system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
381system.cpu.fetch.icacheStallCycles 309137299 # Number of cycles fetch is stalled on an Icache miss
382system.cpu.fetch.Insts 2319640214 # Number of instructions fetch has processed
383system.cpu.fetch.Branches 322479068 # Number of branches that fetch encountered
384system.cpu.fetch.predictedBranches 188391529 # Number of branches that fetch has predicted taken
385system.cpu.fetch.Cycles 688452374 # Number of cycles fetch has run and was not squashing or blocked
386system.cpu.fetch.SquashCycles 31084694 # Number of cycles fetch has spent squashing
387system.cpu.fetch.CacheLines 300792002 # Number of cache lines fetched
388system.cpu.fetch.IcacheSquashes 5498702 # Number of outstanding Icache misses that were squashed
389system.cpu.fetch.rateDist::samples 1013132020 # Number of instructions fetched each cycle (Total)
390system.cpu.fetch.rateDist::mean 2.455758 # Number of instructions fetched each cycle (Total)
391system.cpu.fetch.rateDist::stdev 3.154346 # Number of instructions fetched each cycle (Total)
392system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
393system.cpu.fetch.rateDist::0 555222202 54.80% 54.80% # Number of instructions fetched each cycle (Total)
394system.cpu.fetch.rateDist::1 28050197 2.77% 57.57% # Number of instructions fetched each cycle (Total)
395system.cpu.fetch.rateDist::2 43308558 4.27% 61.85% # Number of instructions fetched each cycle (Total)
396system.cpu.fetch.rateDist::3 56959165 5.62% 67.47% # Number of instructions fetched each cycle (Total)
397system.cpu.fetch.rateDist::4 42292761 4.17% 71.64% # Number of instructions fetched each cycle (Total)
398system.cpu.fetch.rateDist::5 51207543 5.05% 76.70% # Number of instructions fetched each cycle (Total)
399system.cpu.fetch.rateDist::6 41019007 4.05% 80.75% # Number of instructions fetched each cycle (Total)
400system.cpu.fetch.rateDist::7 29441196 2.91% 83.65% # Number of instructions fetched each cycle (Total)
401system.cpu.fetch.rateDist::8 165631391 16.35% 100.00% # Number of instructions fetched each cycle (Total)
402system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
403system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
404system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
405system.cpu.fetch.rateDist::total 1013132020 # Number of instructions fetched each cycle (Total)
406system.cpu.fetch.branchRate 0.318283 # Number of branch fetches per cycle
407system.cpu.fetch.rate 2.289459 # Number of inst fetches per cycle
408system.cpu.decode.IdleCycles 248682792 # Number of cycles decode is idle
409system.cpu.decode.BlockedCycles 345622952 # Number of cycles decode is blocked
410system.cpu.decode.RunCycles 359459924 # Number of cycles decode is running
411system.cpu.decode.UnblockCycles 43824601 # Number of cycles decode is unblocking
412system.cpu.decode.SquashCycles 15541751 # Number of cycles decode is squashing
413system.cpu.decode.BranchResolved 49856372 # Number of times decode resolved a branch
414system.cpu.decode.BranchMispred 610 # Number of times decode detected a branch misprediction
415system.cpu.decode.DecodedInsts 2395697302 # Number of instructions handled by decode
416system.cpu.decode.SquashedInsts 2189 # Number of squashed instructions handled by decode
417system.cpu.rename.SquashCycles 15541751 # Number of cycles rename is squashing
418system.cpu.rename.IdleCycles 269479595 # Number of cycles rename is idle
419system.cpu.rename.BlockCycles 192381996 # Number of cycles rename is blocking
420system.cpu.rename.serializeStallCycles 17471 # count of cycles rename stalled for serializing inst
421system.cpu.rename.RunCycles 380094168 # Number of cycles rename is running
422system.cpu.rename.UnblockCycles 155617039 # Number of cycles rename is unblocking
423system.cpu.rename.RenamedInsts 2338847400 # Number of instructions processed by rename
424system.cpu.rename.ROBFullEvents 939227 # Number of times rename has blocked due to ROB full
425system.cpu.rename.IQFullEvents 43524152 # Number of times rename has blocked due to IQ full
426system.cpu.rename.LQFullEvents 85831703 # Number of times rename has blocked due to LQ full
427system.cpu.rename.SQFullEvents 28336004 # Number of times rename has blocked due to SQ full
428system.cpu.rename.RenamedOperands 2341659219 # Number of destination operands rename has renamed
429system.cpu.rename.RenameLookups 10827293229 # Number of register rename lookups that rename has made
430system.cpu.rename.int_rename_lookups 2896191361 # Number of integer rename lookups
431system.cpu.rename.fp_rename_lookups 924 # Number of floating rename lookups
432system.cpu.rename.CommittedMaps 1674898945 # Number of HB maps that are committed
433system.cpu.rename.UndoneMaps 666760274 # Number of HB maps that are undone due to squashing
434system.cpu.rename.serializingInsts 297 # count of serializing insts renamed
435system.cpu.rename.tempSerializingInsts 295 # count of temporary serializing insts renamed
436system.cpu.rename.skidInsts 177584133 # count of insts added to the skid buffer
437system.cpu.memDep0.insertedLoads 623787680 # Number of loads inserted to the mem dependence unit.
438system.cpu.memDep0.insertedStores 234474986 # Number of stores inserted to the mem dependence unit.
439system.cpu.memDep0.conflictingLoads 103326529 # Number of conflicting loads.
440system.cpu.memDep0.conflictingStores 119861826 # Number of conflicting stores.
441system.cpu.iq.iqInstsAdded 2235979798 # Number of instructions added to the IQ (excludes non-spec)
442system.cpu.iq.iqNonSpecInstsAdded 279 # Number of non-speculative instructions added to the IQ
443system.cpu.iq.iqInstsIssued 2042453270 # Number of instructions issued
444system.cpu.iq.iqSquashedInstsIssued 1123672 # Number of squashed instructions issued
445system.cpu.iq.iqSquashedInstsExamined 568282292 # Number of squashed instructions iterated over during squash; mainly for profiling
446system.cpu.iq.iqSquashedOperandsExamined 1410742018 # Number of squashed operands that are examined and possibly removed from graph
447system.cpu.iq.iqSquashedNonSpecRemoved 109 # Number of squashed non-spec instructions that were removed
448system.cpu.iq.issued_per_cycle::samples 1013132020 # Number of insts issued each cycle
449system.cpu.iq.issued_per_cycle::mean 2.015979 # Number of insts issued each cycle
450system.cpu.iq.issued_per_cycle::stdev 2.060962 # Number of insts issued each cycle
451system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
452system.cpu.iq.issued_per_cycle::0 369509753 36.47% 36.47% # Number of insts issued each cycle
453system.cpu.iq.issued_per_cycle::1 122144381 12.06% 48.53% # Number of insts issued each cycle
454system.cpu.iq.issued_per_cycle::2 148105848 14.62% 63.15% # Number of insts issued each cycle
455system.cpu.iq.issued_per_cycle::3 116397380 11.49% 74.64% # Number of insts issued each cycle
456system.cpu.iq.issued_per_cycle::4 120158766 11.86% 86.50% # Number of insts issued each cycle
457system.cpu.iq.issued_per_cycle::5 67734855 6.69% 93.18% # Number of insts issued each cycle
458system.cpu.iq.issued_per_cycle::6 38716090 3.82% 97.00% # Number of insts issued each cycle
459system.cpu.iq.issued_per_cycle::7 19620402 1.94% 98.94% # Number of insts issued each cycle
460system.cpu.iq.issued_per_cycle::8 10744545 1.06% 100.00% # Number of insts issued each cycle
461system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
462system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
463system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
464system.cpu.iq.issued_per_cycle::total 1013132020 # Number of insts issued each cycle
465system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
466system.cpu.iq.fu_full::IntAlu 3650692 18.70% 18.70% # attempts to use FU when none available
467system.cpu.iq.fu_full::IntMult 890 0.00% 18.71% # attempts to use FU when none available
468system.cpu.iq.fu_full::IntDiv 0 0.00% 18.71% # attempts to use FU when none available
469system.cpu.iq.fu_full::FloatAdd 0 0.00% 18.71% # attempts to use FU when none available
470system.cpu.iq.fu_full::FloatCmp 0 0.00% 18.71% # attempts to use FU when none available
471system.cpu.iq.fu_full::FloatCvt 0 0.00% 18.71% # attempts to use FU when none available
472system.cpu.iq.fu_full::FloatMult 0 0.00% 18.71% # attempts to use FU when none available
473system.cpu.iq.fu_full::FloatDiv 0 0.00% 18.71% # attempts to use FU when none available
474system.cpu.iq.fu_full::FloatSqrt 0 0.00% 18.71% # attempts to use FU when none available
475system.cpu.iq.fu_full::SimdAdd 0 0.00% 18.71% # attempts to use FU when none available
476system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 18.71% # attempts to use FU when none available
477system.cpu.iq.fu_full::SimdAlu 0 0.00% 18.71% # attempts to use FU when none available
478system.cpu.iq.fu_full::SimdCmp 0 0.00% 18.71% # attempts to use FU when none available
479system.cpu.iq.fu_full::SimdCvt 0 0.00% 18.71% # attempts to use FU when none available
480system.cpu.iq.fu_full::SimdMisc 0 0.00% 18.71% # attempts to use FU when none available
481system.cpu.iq.fu_full::SimdMult 0 0.00% 18.71% # attempts to use FU when none available
482system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 18.71% # attempts to use FU when none available
483system.cpu.iq.fu_full::SimdShift 0 0.00% 18.71% # attempts to use FU when none available
484system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 18.71% # attempts to use FU when none available
485system.cpu.iq.fu_full::SimdSqrt 0 0.00% 18.71% # attempts to use FU when none available
486system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 18.71% # attempts to use FU when none available
487system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 18.71% # attempts to use FU when none available
488system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 18.71% # attempts to use FU when none available
489system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 18.71% # attempts to use FU when none available
490system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 18.71% # attempts to use FU when none available
491system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 18.71% # attempts to use FU when none available
492system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 18.71% # attempts to use FU when none available
493system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.71% # attempts to use FU when none available
494system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 18.71% # attempts to use FU when none available
495system.cpu.iq.fu_full::MemRead 15434151 79.07% 97.77% # attempts to use FU when none available
496system.cpu.iq.fu_full::MemWrite 434530 2.23% 100.00% # attempts to use FU when none available
497system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
498system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
499system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
500system.cpu.iq.FU_type_0::IntAlu 1227555044 60.10% 60.10% # Type of FU issued
501system.cpu.iq.FU_type_0::IntMult 999501 0.05% 60.15% # Type of FU issued
502system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.15% # Type of FU issued
503system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.15% # Type of FU issued
504system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.15% # Type of FU issued
505system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.15% # Type of FU issued
506system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.15% # Type of FU issued
507system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.15% # Type of FU issued
508system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.15% # Type of FU issued
509system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.15% # Type of FU issued
510system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.15% # Type of FU issued
511system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.15% # Type of FU issued
512system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.15% # Type of FU issued
513system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.15% # Type of FU issued
514system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.15% # Type of FU issued
515system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.15% # Type of FU issued
516system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.15% # Type of FU issued
517system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.15% # Type of FU issued
518system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.15% # Type of FU issued
519system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.15% # Type of FU issued
520system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.15% # Type of FU issued
521system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.15% # Type of FU issued
522system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.15% # Type of FU issued
523system.cpu.iq.FU_type_0::SimdFloatCvt 75 0.00% 60.15% # Type of FU issued
524system.cpu.iq.FU_type_0::SimdFloatDiv 3 0.00% 60.15% # Type of FU issued
525system.cpu.iq.FU_type_0::SimdFloatMisc 36 0.00% 60.15% # Type of FU issued
526system.cpu.iq.FU_type_0::SimdFloatMult 18 0.00% 60.15% # Type of FU issued
527system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.15% # Type of FU issued
528system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.15% # Type of FU issued
529system.cpu.iq.FU_type_0::MemRead 618802083 30.30% 90.45% # Type of FU issued
530system.cpu.iq.FU_type_0::MemWrite 195096510 9.55% 100.00% # Type of FU issued
531system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
532system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
533system.cpu.iq.FU_type_0::total 2042453270 # Type of FU issued
534system.cpu.iq.rate 2.015878 # Inst issue rate
535system.cpu.iq.fu_busy_cnt 19520263 # FU busy when requested
536system.cpu.iq.fu_busy_rate 0.009557 # FU busy rate (busy events/executed inst)
537system.cpu.iq.int_inst_queue_reads 5118681932 # Number of integer instruction queue reads
538system.cpu.iq.int_inst_queue_writes 2804481694 # Number of integer instruction queue writes
539system.cpu.iq.int_inst_queue_wakeup_accesses 1937195401 # Number of integer instruction queue wakeup accesses
540system.cpu.iq.fp_inst_queue_reads 563 # Number of floating instruction queue reads
541system.cpu.iq.fp_inst_queue_writes 772 # Number of floating instruction queue writes
542system.cpu.iq.fp_inst_queue_wakeup_accesses 222 # Number of floating instruction queue wakeup accesses
543system.cpu.iq.int_alu_accesses 2061973250 # Number of integer alu accesses
544system.cpu.iq.fp_alu_accesses 283 # Number of floating point alu accesses
545system.cpu.iew.lsq.thread0.forwLoads 29620868 # Number of loads that had data forwarded from stores
546system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
547system.cpu.iew.lsq.thread0.squashedLoads 165481346 # Number of loads squashed
548system.cpu.iew.lsq.thread0.ignoredResponses 152761 # Number of memory responses ignored because the instruction is squashed
549system.cpu.iew.lsq.thread0.memOrderViolation 223174 # Number of memory ordering violations
550system.cpu.iew.lsq.thread0.squashedStores 59627941 # Number of stores squashed
551system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
552system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
553system.cpu.iew.lsq.thread0.rescheduledLoads 27365932 # Number of loads that were rescheduled
554system.cpu.iew.lsq.thread0.cacheBlocked 20554693 # Number of times an access to memory failed due to the cache being blocked
555system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
556system.cpu.iew.iewSquashCycles 15541751 # Number of cycles IEW is squashing
557system.cpu.iew.iewBlockCycles 99594513 # Number of cycles IEW is blocking
558system.cpu.iew.iewUnblockCycles 79709192 # Number of cycles IEW is unblocking
559system.cpu.iew.iewDispatchedInsts 2235980127 # Number of instructions dispatched to IQ
560system.cpu.iew.iewDispSquashedInsts 3715851 # Number of squashed instructions skipped by dispatch
561system.cpu.iew.iewDispLoadInsts 623787680 # Number of dispatched load instructions
562system.cpu.iew.iewDispStoreInsts 234474986 # Number of dispatched store instructions
563system.cpu.iew.iewDispNonSpecInsts 217 # Number of dispatched non-speculative instructions
564system.cpu.iew.iewIQFullEvents 887425 # Number of times the IQ has become full, causing a stall
565system.cpu.iew.iewLSQFullEvents 78519079 # Number of times the LSQ has become full, causing a stall
566system.cpu.iew.memOrderViolationEvents 223174 # Number of memory order violations
567system.cpu.iew.predictedTakenIncorrect 8257753 # Number of branches that were predicted taken incorrectly
568system.cpu.iew.predictedNotTakenIncorrect 10408115 # Number of branches that were predicted not taken incorrectly
569system.cpu.iew.branchMispredicts 18665868 # Number of branch mispredicts detected at execute
570system.cpu.iew.iewExecutedInsts 2014561503 # Number of executed instructions
571system.cpu.iew.iewExecLoadInsts 604829298 # Number of load instructions executed
572system.cpu.iew.iewExecSquashedInsts 27891767 # Number of squashed instructions skipped in execute
573system.cpu.iew.exec_swp 0 # number of swp insts executed
574system.cpu.iew.exec_nop 50 # number of nop insts executed
575system.cpu.iew.exec_refs 796810326 # number of memory reference insts executed
576system.cpu.iew.exec_branches 245407289 # Number of branches executed
577system.cpu.iew.exec_stores 191981028 # Number of stores executed
578system.cpu.iew.exec_rate 1.988349 # Inst execution rate
579system.cpu.iew.wb_sent 1947397166 # cumulative count of insts sent to commit
580system.cpu.iew.wb_count 1937195623 # cumulative count of insts written-back
581system.cpu.iew.wb_producers 1312629106 # num instructions producing a value
582system.cpu.iew.wb_consumers 2061058840 # num instructions consuming a value
583system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
584system.cpu.iew.wb_rate 1.911990 # insts written-back per cycle
585system.cpu.iew.wb_fanout 0.636871 # average fanout of values written-back
586system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
587system.cpu.commit.commitSquashedInsts 572342091 # The number of squashed insts skipped by commit
588system.cpu.commit.commitNonSpecStalls 170 # The number of times commit has been forced to stall to communicate backwards
589system.cpu.commit.branchMispredicts 15341577 # The number of times a branch was mispredicted
590system.cpu.commit.committed_per_cycle::samples 933174586 # Number of insts commited each cycle
591system.cpu.commit.committed_per_cycle::mean 1.783195 # Number of insts commited each cycle
592system.cpu.commit.committed_per_cycle::stdev 2.675212 # Number of insts commited each cycle
593system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
594system.cpu.commit.committed_per_cycle::0 468896979 50.25% 50.25% # Number of insts commited each cycle
595system.cpu.commit.committed_per_cycle::1 178641910 19.14% 69.39% # Number of insts commited each cycle
596system.cpu.commit.committed_per_cycle::2 68227019 7.31% 76.70% # Number of insts commited each cycle
597system.cpu.commit.committed_per_cycle::3 32102473 3.44% 80.14% # Number of insts commited each cycle
598system.cpu.commit.committed_per_cycle::4 24397966 2.61% 82.76% # Number of insts commited each cycle
599system.cpu.commit.committed_per_cycle::5 27603302 2.96% 85.71% # Number of insts commited each cycle
600system.cpu.commit.committed_per_cycle::6 17322198 1.86% 87.57% # Number of insts commited each cycle
601system.cpu.commit.committed_per_cycle::7 14774408 1.58% 89.15% # Number of insts commited each cycle
602system.cpu.commit.committed_per_cycle::8 101208331 10.85% 100.00% # Number of insts commited each cycle
603system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
604system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
605system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
606system.cpu.commit.committed_per_cycle::total 933174586 # Number of insts commited each cycle
607system.cpu.commit.committedInsts 1544563041 # Number of instructions committed
608system.cpu.commit.committedOps 1664032433 # Number of ops (including micro ops) committed
609system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
610system.cpu.commit.refs 633153379 # Number of memory references committed
611system.cpu.commit.loads 458306334 # Number of loads committed
612system.cpu.commit.membars 62 # Number of memory barriers committed
613system.cpu.commit.branches 213462426 # Number of branches committed
614system.cpu.commit.fp_insts 36 # Number of committed floating point instructions.

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644system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction
645system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction
646system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
647system.cpu.commit.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
648system.cpu.commit.op_class_0::MemWrite 174847045 10.51% 100.00% # Class of committed instruction
649system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
650system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
651system.cpu.commit.op_class_0::total 1664032433 # Class of committed instruction
652system.cpu.commit.bw_lim_events 101208331 # number cycles where commit BW limit reached
653system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
654system.cpu.rob.rob_reads 3068340180 # The number of ROB reads
655system.cpu.rob.rob_writes 4552875899 # The number of ROB writes
656system.cpu.timesIdled 556 # Number of times that the entire CPU went into an idle state and unscheduled itself
657system.cpu.idleCycles 50821 # Total number of cycles that the CPU has spent unscheduled due to idling
658system.cpu.committedInsts 1544563023 # Number of Instructions Simulated
659system.cpu.committedOps 1664032415 # Number of Ops (including micro ops) Simulated
660system.cpu.cpi 0.655967 # CPI: Cycles Per Instruction
661system.cpu.cpi_total 0.655967 # CPI: Total CPI of All Threads
662system.cpu.ipc 1.524466 # IPC: Instructions Per Cycle
663system.cpu.ipc_total 1.524466 # IPC: Total IPC of All Threads
664system.cpu.int_regfile_reads 2376547647 # number of integer regfile reads
665system.cpu.int_regfile_writes 1366493054 # number of integer regfile writes
666system.cpu.fp_regfile_reads 209 # number of floating regfile reads
667system.cpu.fp_regfile_writes 233 # number of floating regfile writes
668system.cpu.cc_regfile_reads 7643535318 # number of cc regfile reads
669system.cpu.cc_regfile_writes 583887345 # number of cc regfile writes
670system.cpu.misc_regfile_reads 725285725 # number of misc regfile reads
671system.cpu.misc_regfile_writes 124 # number of misc regfile writes
672system.cpu.toL2Bus.throughput 1691907313 # Throughput (bytes/s)
673system.cpu.toL2Bus.trans_dist::ReadReq 7714547 # Transaction distribution
674system.cpu.toL2Bus.trans_dist::ReadResp 7714546 # Transaction distribution
675system.cpu.toL2Bus.trans_dist::Writeback 3783532 # Transaction distribution
676system.cpu.toL2Bus.trans_dist::ReadExReq 1894199 # Transaction distribution
677system.cpu.toL2Bus.trans_dist::ReadExResp 1894199 # Transaction distribution
678system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1502 # Packet count per connected master and slave (bytes)
679system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22999521 # Packet count per connected master and slave (bytes)
680system.cpu.toL2Bus.pkt_count::total 23001023 # Packet count per connected master and slave (bytes)
681system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48064 # Cumulative packet size per connected master and slave (bytes)
682system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 857057664 # Cumulative packet size per connected master and slave (bytes)
683system.cpu.toL2Bus.tot_pkt_size::total 857105728 # Cumulative packet size per connected master and slave (bytes)
684system.cpu.toL2Bus.data_through_bus 857105728 # Total data (bytes)
685system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
686system.cpu.toL2Bus.reqLayer0.occupancy 10479902270 # Layer occupancy (ticks)
687system.cpu.toL2Bus.reqLayer0.utilization 2.1 # Layer utilization (%)
688system.cpu.toL2Bus.respLayer0.occupancy 1252249 # Layer occupancy (ticks)
689system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
690system.cpu.toL2Bus.respLayer1.occupancy 14758141993 # Layer occupancy (ticks)
691system.cpu.toL2Bus.respLayer1.utilization 2.9 # Layer utilization (%)
692system.cpu.icache.tags.replacements 15 # number of replacements
693system.cpu.icache.tags.tagsinuse 614.894819 # Cycle average of tags in use
694system.cpu.icache.tags.total_refs 300790815 # Total number of references to valid blocks.
695system.cpu.icache.tags.sampled_refs 751 # Sample count of references to valid blocks.
696system.cpu.icache.tags.avg_refs 400520.392810 # Average number of references to valid blocks.
697system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
698system.cpu.icache.tags.occ_blocks::cpu.inst 614.894819 # Average occupied blocks per requestor
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700system.cpu.icache.tags.occ_percent::total 0.300242 # Average percentage of cache occupancy
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703system.cpu.icache.tags.age_task_id_blocks_1024::2 3 # Occupied blocks per task id
704system.cpu.icache.tags.age_task_id_blocks_1024::4 709 # Occupied blocks per task id
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709system.cpu.icache.ReadReq_hits::total 300790815 # number of ReadReq hits
710system.cpu.icache.demand_hits::cpu.inst 300790815 # number of demand (read+write) hits
711system.cpu.icache.demand_hits::total 300790815 # number of demand (read+write) hits
712system.cpu.icache.overall_hits::cpu.inst 300790815 # number of overall hits
713system.cpu.icache.overall_hits::total 300790815 # number of overall hits
714system.cpu.icache.ReadReq_misses::cpu.inst 1187 # number of ReadReq misses
715system.cpu.icache.ReadReq_misses::total 1187 # number of ReadReq misses
716system.cpu.icache.demand_misses::cpu.inst 1187 # number of demand (read+write) misses
717system.cpu.icache.demand_misses::total 1187 # number of demand (read+write) misses
718system.cpu.icache.overall_misses::cpu.inst 1187 # number of overall misses
719system.cpu.icache.overall_misses::total 1187 # number of overall misses
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721system.cpu.icache.ReadReq_miss_latency::total 83295499 # number of ReadReq miss cycles
722system.cpu.icache.demand_miss_latency::cpu.inst 83295499 # number of demand (read+write) miss cycles
723system.cpu.icache.demand_miss_latency::total 83295499 # number of demand (read+write) miss cycles
724system.cpu.icache.overall_miss_latency::cpu.inst 83295499 # number of overall miss cycles
725system.cpu.icache.overall_miss_latency::total 83295499 # number of overall miss cycles
726system.cpu.icache.ReadReq_accesses::cpu.inst 300792002 # number of ReadReq accesses(hits+misses)
727system.cpu.icache.ReadReq_accesses::total 300792002 # number of ReadReq accesses(hits+misses)
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729system.cpu.icache.demand_accesses::total 300792002 # number of demand (read+write) accesses
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733system.cpu.icache.ReadReq_miss_rate::total 0.000004 # miss rate for ReadReq accesses
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735system.cpu.icache.demand_miss_rate::total 0.000004 # miss rate for demand accesses
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737system.cpu.icache.overall_miss_rate::total 0.000004 # miss rate for overall accesses
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739system.cpu.icache.ReadReq_avg_miss_latency::total 70173.124684 # average ReadReq miss latency
740system.cpu.icache.demand_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency
741system.cpu.icache.demand_avg_miss_latency::total 70173.124684 # average overall miss latency
742system.cpu.icache.overall_avg_miss_latency::cpu.inst 70173.124684 # average overall miss latency
743system.cpu.icache.overall_avg_miss_latency::total 70173.124684 # average overall miss latency
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746system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
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749system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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759system.cpu.icache.ReadReq_mshr_misses::total 751 # number of ReadReq MSHR misses
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762system.cpu.icache.overall_mshr_misses::cpu.inst 751 # number of overall MSHR misses
763system.cpu.icache.overall_mshr_misses::total 751 # number of overall MSHR misses
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766system.cpu.icache.demand_mshr_miss_latency::cpu.inst 54758751 # number of demand (read+write) MSHR miss cycles
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768system.cpu.icache.overall_mshr_miss_latency::cpu.inst 54758751 # number of overall MSHR miss cycles
769system.cpu.icache.overall_mshr_miss_latency::total 54758751 # number of overall MSHR miss cycles
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774system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
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777system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72914.448735 # average ReadReq mshr miss latency
778system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72914.448735 # average overall mshr miss latency
779system.cpu.icache.demand_avg_mshr_miss_latency::total 72914.448735 # average overall mshr miss latency
780system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72914.448735 # average overall mshr miss latency
781system.cpu.icache.overall_avg_mshr_miss_latency::total 72914.448735 # average overall mshr miss latency
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783system.cpu.l2cache.tags.replacements 2214491 # number of replacements
784system.cpu.l2cache.tags.tagsinuse 31511.693387 # Cycle average of tags in use
785system.cpu.l2cache.tags.total_refs 9253081 # Total number of references to valid blocks.
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787system.cpu.l2cache.tags.avg_refs 4.122989 # Average number of references to valid blocks.
788system.cpu.l2cache.tags.warmup_cycle 21056926750 # Cycle when the warmup percentage was hit.
789system.cpu.l2cache.tags.occ_blocks::writebacks 14239.275305 # Average occupied blocks per requestor
790system.cpu.l2cache.tags.occ_blocks::cpu.inst 20.394558 # Average occupied blocks per requestor
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796system.cpu.l2cache.tags.occ_task_id_blocks::1024 29774 # Occupied blocks per task id
797system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
798system.cpu.l2cache.tags.age_task_id_blocks_1024::1 81 # Occupied blocks per task id
799system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1811 # Occupied blocks per task id
800system.cpu.l2cache.tags.age_task_id_blocks_1024::3 23310 # Occupied blocks per task id
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809system.cpu.l2cache.Writeback_hits::total 3783532 # number of Writeback hits
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844system.cpu.l2cache.Writeback_accesses::total 3783532 # number of Writeback accesses(hits+misses)
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865system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 84201.753462 # average ReadReq miss latency
866system.cpu.l2cache.ReadReq_avg_miss_latency::total 84196.607439 # average ReadReq miss latency
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868system.cpu.l2cache.ReadExReq_avg_miss_latency::total 86022.529557 # average ReadExReq miss latency
869system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74125.862069 # average overall miss latency
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872system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74125.862069 # average overall miss latency
873system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84872.559991 # average overall miss latency
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881system.cpu.l2cache.fast_writes 0 # number of fast writes performed
882system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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890system.cpu.l2cache.demand_mshr_hits::total 8 # number of demand (read+write) MSHR hits
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914system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162566982500 # number of overall MSHR miss cycles
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920system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.436931 # mshr miss rate for ReadExReq accesses
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924system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964048 # mshr miss rate for overall accesses
925system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.233810 # mshr miss rate for overall accesses
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928system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71685.561366 # average ReadReq mshr miss latency
929system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71680.394128 # average ReadReq mshr miss latency
930system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 73532.937527 # average ReadExReq mshr miss latency
931system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 73532.937527 # average ReadExReq mshr miss latency
932system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61554.212707 # average overall mshr miss latency
933system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 72366.169957 # average overall mshr miss latency
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935system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61554.212707 # average overall mshr miss latency
936system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 72366.169957 # average overall mshr miss latency
937system.cpu.l2cache.overall_avg_mshr_miss_latency::total 72362.686534 # average overall mshr miss latency
938system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
939system.cpu.dcache.tags.replacements 9603898 # number of replacements
940system.cpu.dcache.tags.tagsinuse 4087.677378 # Cycle average of tags in use
941system.cpu.dcache.tags.total_refs 678741158 # Total number of references to valid blocks.
942system.cpu.dcache.tags.sampled_refs 9607994 # Sample count of references to valid blocks.
943system.cpu.dcache.tags.avg_refs 70.643379 # Average number of references to valid blocks.
944system.cpu.dcache.tags.warmup_cycle 3511642250 # Cycle when the warmup percentage was hit.
945system.cpu.dcache.tags.occ_blocks::cpu.data 4087.677378 # Average occupied blocks per requestor
946system.cpu.dcache.tags.occ_percent::cpu.data 0.997968 # Average percentage of cache occupancy
947system.cpu.dcache.tags.occ_percent::total 0.997968 # Average percentage of cache occupancy
948system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
949system.cpu.dcache.tags.age_task_id_blocks_1024::0 657 # Occupied blocks per task id
950system.cpu.dcache.tags.age_task_id_blocks_1024::1 2421 # Occupied blocks per task id
951system.cpu.dcache.tags.age_task_id_blocks_1024::2 1017 # Occupied blocks per task id
952system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
953system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
954system.cpu.dcache.tags.tag_accesses 1403558154 # Number of tag accesses
955system.cpu.dcache.tags.data_accesses 1403558154 # Number of data accesses
956system.cpu.dcache.ReadReq_hits::cpu.data 511838800 # number of ReadReq hits
957system.cpu.dcache.ReadReq_hits::total 511838800 # number of ReadReq hits
958system.cpu.dcache.WriteReq_hits::cpu.data 166902232 # number of WriteReq hits
959system.cpu.dcache.WriteReq_hits::total 166902232 # number of WriteReq hits
960system.cpu.dcache.SoftPFReq_hits::cpu.data 2 # number of SoftPFReq hits
961system.cpu.dcache.SoftPFReq_hits::total 2 # number of SoftPFReq hits
962system.cpu.dcache.LoadLockedReq_hits::cpu.data 63 # number of LoadLockedReq hits
963system.cpu.dcache.LoadLockedReq_hits::total 63 # number of LoadLockedReq hits
964system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits
965system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
966system.cpu.dcache.demand_hits::cpu.data 678741032 # number of demand (read+write) hits
967system.cpu.dcache.demand_hits::total 678741032 # number of demand (read+write) hits
968system.cpu.dcache.overall_hits::cpu.data 678741034 # number of overall hits
969system.cpu.dcache.overall_hits::total 678741034 # number of overall hits
970system.cpu.dcache.ReadReq_misses::cpu.data 12550102 # number of ReadReq misses
971system.cpu.dcache.ReadReq_misses::total 12550102 # number of ReadReq misses
972system.cpu.dcache.WriteReq_misses::cpu.data 5683815 # number of WriteReq misses
973system.cpu.dcache.WriteReq_misses::total 5683815 # number of WriteReq misses
974system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses
975system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses
976system.cpu.dcache.LoadLockedReq_misses::cpu.data 3 # number of LoadLockedReq misses
977system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses
978system.cpu.dcache.demand_misses::cpu.data 18233917 # number of demand (read+write) misses
979system.cpu.dcache.demand_misses::total 18233917 # number of demand (read+write) misses
980system.cpu.dcache.overall_misses::cpu.data 18233919 # number of overall misses
981system.cpu.dcache.overall_misses::total 18233919 # number of overall misses
982system.cpu.dcache.ReadReq_miss_latency::cpu.data 378927155489 # number of ReadReq miss cycles
983system.cpu.dcache.ReadReq_miss_latency::total 378927155489 # number of ReadReq miss cycles
984system.cpu.dcache.WriteReq_miss_latency::cpu.data 307221007401 # number of WriteReq miss cycles
985system.cpu.dcache.WriteReq_miss_latency::total 307221007401 # number of WriteReq miss cycles
986system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 228000 # number of LoadLockedReq miss cycles
987system.cpu.dcache.LoadLockedReq_miss_latency::total 228000 # number of LoadLockedReq miss cycles
988system.cpu.dcache.demand_miss_latency::cpu.data 686148162890 # number of demand (read+write) miss cycles
989system.cpu.dcache.demand_miss_latency::total 686148162890 # number of demand (read+write) miss cycles
990system.cpu.dcache.overall_miss_latency::cpu.data 686148162890 # number of overall miss cycles
991system.cpu.dcache.overall_miss_latency::total 686148162890 # number of overall miss cycles
992system.cpu.dcache.ReadReq_accesses::cpu.data 524388902 # number of ReadReq accesses(hits+misses)
993system.cpu.dcache.ReadReq_accesses::total 524388902 # number of ReadReq accesses(hits+misses)
994system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses)
995system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
996system.cpu.dcache.SoftPFReq_accesses::cpu.data 4 # number of SoftPFReq accesses(hits+misses)
997system.cpu.dcache.SoftPFReq_accesses::total 4 # number of SoftPFReq accesses(hits+misses)
998system.cpu.dcache.LoadLockedReq_accesses::cpu.data 66 # number of LoadLockedReq accesses(hits+misses)
999system.cpu.dcache.LoadLockedReq_accesses::total 66 # number of LoadLockedReq accesses(hits+misses)
1000system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses)
1001system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
1002system.cpu.dcache.demand_accesses::cpu.data 696974949 # number of demand (read+write) accesses
1003system.cpu.dcache.demand_accesses::total 696974949 # number of demand (read+write) accesses
1004system.cpu.dcache.overall_accesses::cpu.data 696974953 # number of overall (read+write) accesses
1005system.cpu.dcache.overall_accesses::total 696974953 # number of overall (read+write) accesses
1006system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023933 # miss rate for ReadReq accesses
1007system.cpu.dcache.ReadReq_miss_rate::total 0.023933 # miss rate for ReadReq accesses
1008system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.032933 # miss rate for WriteReq accesses
1009system.cpu.dcache.WriteReq_miss_rate::total 0.032933 # miss rate for WriteReq accesses
1010system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.500000 # miss rate for SoftPFReq accesses
1011system.cpu.dcache.SoftPFReq_miss_rate::total 0.500000 # miss rate for SoftPFReq accesses
1012system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045455 # miss rate for LoadLockedReq accesses
1013system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045455 # miss rate for LoadLockedReq accesses
1014system.cpu.dcache.demand_miss_rate::cpu.data 0.026162 # miss rate for demand accesses
1015system.cpu.dcache.demand_miss_rate::total 0.026162 # miss rate for demand accesses
1016system.cpu.dcache.overall_miss_rate::cpu.data 0.026162 # miss rate for overall accesses
1017system.cpu.dcache.overall_miss_rate::total 0.026162 # miss rate for overall accesses
1018system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30193.153449 # average ReadReq miss latency
1019system.cpu.dcache.ReadReq_avg_miss_latency::total 30193.153449 # average ReadReq miss latency
1020system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54051.901302 # average WriteReq miss latency
1021system.cpu.dcache.WriteReq_avg_miss_latency::total 54051.901302 # average WriteReq miss latency
1022system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76000 # average LoadLockedReq miss latency
1023system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76000 # average LoadLockedReq miss latency
1024system.cpu.dcache.demand_avg_miss_latency::cpu.data 37630.321718 # average overall miss latency
1025system.cpu.dcache.demand_avg_miss_latency::total 37630.321718 # average overall miss latency
1026system.cpu.dcache.overall_avg_miss_latency::cpu.data 37630.317591 # average overall miss latency
1027system.cpu.dcache.overall_avg_miss_latency::total 37630.317591 # average overall miss latency
1028system.cpu.dcache.blocked_cycles::no_mshrs 28822616 # number of cycles access was blocked
1029system.cpu.dcache.blocked_cycles::no_targets 4626055 # number of cycles access was blocked
1030system.cpu.dcache.blocked::no_mshrs 1847693 # number of cycles access was blocked
1031system.cpu.dcache.blocked::no_targets 65151 # number of cycles access was blocked
1032system.cpu.dcache.avg_blocked_cycles::no_mshrs 15.599245 # average number of cycles each access was blocked
1033system.cpu.dcache.avg_blocked_cycles::no_targets 71.005127 # average number of cycles each access was blocked
1034system.cpu.dcache.fast_writes 0 # number of fast writes performed
1035system.cpu.dcache.cache_copies 0 # number of cache copies performed
1036system.cpu.dcache.writebacks::writebacks 3783532 # number of writebacks
1037system.cpu.dcache.writebacks::total 3783532 # number of writebacks
1038system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4836306 # number of ReadReq MSHR hits
1039system.cpu.dcache.ReadReq_mshr_hits::total 4836306 # number of ReadReq MSHR hits
1040system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3789617 # number of WriteReq MSHR hits
1041system.cpu.dcache.WriteReq_mshr_hits::total 3789617 # number of WriteReq MSHR hits
1042system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 3 # number of LoadLockedReq MSHR hits
1043system.cpu.dcache.LoadLockedReq_mshr_hits::total 3 # number of LoadLockedReq MSHR hits
1044system.cpu.dcache.demand_mshr_hits::cpu.data 8625923 # number of demand (read+write) MSHR hits
1045system.cpu.dcache.demand_mshr_hits::total 8625923 # number of demand (read+write) MSHR hits
1046system.cpu.dcache.overall_mshr_hits::cpu.data 8625923 # number of overall MSHR hits
1047system.cpu.dcache.overall_mshr_hits::total 8625923 # number of overall MSHR hits
1048system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7713796 # number of ReadReq MSHR misses
1049system.cpu.dcache.ReadReq_mshr_misses::total 7713796 # number of ReadReq MSHR misses
1050system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1894198 # number of WriteReq MSHR misses
1051system.cpu.dcache.WriteReq_mshr_misses::total 1894198 # number of WriteReq MSHR misses
1052system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses
1053system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses
1054system.cpu.dcache.demand_mshr_misses::cpu.data 9607994 # number of demand (read+write) MSHR misses
1055system.cpu.dcache.demand_mshr_misses::total 9607994 # number of demand (read+write) MSHR misses
1056system.cpu.dcache.overall_mshr_misses::cpu.data 9607995 # number of overall MSHR misses
1057system.cpu.dcache.overall_mshr_misses::total 9607995 # number of overall MSHR misses
1058system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 192253948507 # number of ReadReq MSHR miss cycles
1059system.cpu.dcache.ReadReq_mshr_miss_latency::total 192253948507 # number of ReadReq MSHR miss cycles
1060system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84881076130 # number of WriteReq MSHR miss cycles
1061system.cpu.dcache.WriteReq_mshr_miss_latency::total 84881076130 # number of WriteReq MSHR miss cycles
1062system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 69500 # number of SoftPFReq MSHR miss cycles
1063system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 69500 # number of SoftPFReq MSHR miss cycles
1064system.cpu.dcache.demand_mshr_miss_latency::cpu.data 277135024637 # number of demand (read+write) MSHR miss cycles
1065system.cpu.dcache.demand_mshr_miss_latency::total 277135024637 # number of demand (read+write) MSHR miss cycles
1066system.cpu.dcache.overall_mshr_miss_latency::cpu.data 277135094137 # number of overall MSHR miss cycles
1067system.cpu.dcache.overall_mshr_miss_latency::total 277135094137 # number of overall MSHR miss cycles
1068system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.014710 # mshr miss rate for ReadReq accesses
1069system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.014710 # mshr miss rate for ReadReq accesses
1070system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010975 # mshr miss rate for WriteReq accesses
1071system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010975 # mshr miss rate for WriteReq accesses
1072system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.250000 # mshr miss rate for SoftPFReq accesses
1073system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SoftPFReq accesses
1074system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for demand accesses
1075system.cpu.dcache.demand_mshr_miss_rate::total 0.013785 # mshr miss rate for demand accesses
1076system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.013785 # mshr miss rate for overall accesses
1077system.cpu.dcache.overall_mshr_miss_rate::total 0.013785 # mshr miss rate for overall accesses
1078system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24923.390314 # average ReadReq mshr miss latency
1079system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24923.390314 # average ReadReq mshr miss latency
1080system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44811.089511 # average WriteReq mshr miss latency
1081system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44811.089511 # average WriteReq mshr miss latency
1082system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 69500 # average SoftPFReq mshr miss latency
1083system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 69500 # average SoftPFReq mshr miss latency
1084system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28844.212917 # average overall mshr miss latency
1085system.cpu.dcache.demand_avg_mshr_miss_latency::total 28844.212917 # average overall mshr miss latency
1086system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28844.217148 # average overall mshr miss latency
1087system.cpu.dcache.overall_avg_mshr_miss_latency::total 28844.217148 # average overall mshr miss latency
1088system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
1089
1090---------- End Simulation Statistics ----------