| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System |
| 11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain |
| 12boot_osflags=a |
| 13cache_line_size=64 14clk_domain=system.clk_domain |
| 15init_param=0 16kernel= 17load_addr_mask=1099511627775 18mem_mode=timing 19mem_ranges= 20memories=system.physmem 21num_work_ids=16 22readfile= 23symbolfile= 24work_begin_ckpt_count=0 25work_begin_cpu_id_exit=-1 26work_begin_exit_count=0 27work_cpus_ckpt_count=0 28work_end_ckpt_count=0 29work_end_exit_count=0 30work_item_id=-1 31system_port=system.membus.slave[0] 32 |
| 33[system.clk_domain] 34type=SrcClockDomain 35clock=1000 36voltage_domain=system.voltage_domain 37 |
| 38[system.cpu] 39type=DerivO3CPU 40children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 41LFSTSize=1024 42LQEntries=32 43LSQCheckLoads=true 44LSQDepCheckShift=4 45SQEntries=32 46SSITSize=1024 47activity=0 48backComSize=5 49branchPred=system.cpu.branchPred 50cachePorts=200 51checker=Null |
| 52clk_domain=system.cpu_clk_domain |
| 53commitToDecodeDelay=1 54commitToFetchDelay=1 55commitToIEWDelay=1 56commitToRenameDelay=1 57commitWidth=8 58cpu_id=0 59decodeToFetchDelay=1 60decodeToRenameDelay=1 --- 32 unchanged lines hidden (view full) --- 93numThreads=1 94profile=0 95progress_interval=0 96renameToDecodeDelay=1 97renameToFetchDelay=1 98renameToIEWDelay=2 99renameToROBDelay=1 100renameWidth=8 |
| 101simpoint_start_insts= |
| 102smtCommitPolicy=RoundRobin 103smtFetchPolicy=SingleThread 104smtIQPolicy=Partitioned 105smtIQThreshold=100 106smtLSQPolicy=Partitioned 107smtLSQThreshold=100 108smtNumFetchingThreads=1 109smtROBPolicy=Partitioned --- 13 unchanged lines hidden (view full) --- 123[system.cpu.branchPred] 124type=BranchPredictor 125BTBEntries=4096 126BTBTagSize=16 127RASSize=16 128choiceCtrBits=2 129choicePredictorSize=8192 130globalCtrBits=2 |
| 131globalPredictorSize=8192 132instShiftAmt=2 133localCtrBits=2 |
| 134localHistoryTableSize=2048 135localPredictorSize=2048 136numThreads=1 137predType=tournament 138 139[system.cpu.dcache] 140type=BaseCache |
| 141children=tags |
| 142addr_ranges=0:18446744073709551615 143assoc=2 |
| 144clk_domain=system.cpu_clk_domain |
| 145forward_snoops=true 146hit_latency=2 147is_top_level=true 148max_miss_count=0 149mshrs=4 150prefetch_on_access=false 151prefetcher=Null 152response_latency=2 153size=262144 154system=system |
| 155tags=system.cpu.dcache.tags |
| 156tgts_per_mshr=20 157two_queue=false 158write_buffers=8 159cpu_side=system.cpu.dcache_port 160mem_side=system.cpu.toL2Bus.slave[1] 161 |
| 162[system.cpu.dcache.tags] 163type=LRU 164assoc=2 165block_size=64 166clk_domain=system.cpu_clk_domain 167hit_latency=2 168size=262144 169 |
| 170[system.cpu.dtb] 171type=ArmTLB 172children=walker 173size=64 174walker=system.cpu.dtb.walker 175 176[system.cpu.dtb.walker] 177type=ArmTableWalker |
| 178clk_domain=system.cpu_clk_domain |
| 179num_squash_per_cycle=2 180sys=system 181port=system.cpu.toL2Bus.slave[3] 182 183[system.cpu.fuPool] 184type=FUPool 185children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 186FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 --- 253 unchanged lines hidden (view full) --- 440[system.cpu.fuPool.FUList8.opList] 441type=OpDesc 442issueLat=3 443opClass=IprAccess 444opLat=3 445 446[system.cpu.icache] 447type=BaseCache |
| 448children=tags |
| 449addr_ranges=0:18446744073709551615 450assoc=2 |
| 451clk_domain=system.cpu_clk_domain |
| 452forward_snoops=true 453hit_latency=2 454is_top_level=true 455max_miss_count=0 456mshrs=4 457prefetch_on_access=false 458prefetcher=Null 459response_latency=2 460size=131072 461system=system |
| 462tags=system.cpu.icache.tags |
| 463tgts_per_mshr=20 464two_queue=false 465write_buffers=8 466cpu_side=system.cpu.icache_port 467mem_side=system.cpu.toL2Bus.slave[0] 468 |
| 469[system.cpu.icache.tags] 470type=LRU 471assoc=2 472block_size=64 473clk_domain=system.cpu_clk_domain 474hit_latency=2 475size=131072 476 |
| 477[system.cpu.interrupts] 478type=ArmInterrupts 479 480[system.cpu.isa] 481type=ArmISA 482fpsid=1090793632 483id_isar0=34607377 484id_isar1=34677009 --- 12 unchanged lines hidden (view full) --- 497[system.cpu.itb] 498type=ArmTLB 499children=walker 500size=64 501walker=system.cpu.itb.walker 502 503[system.cpu.itb.walker] 504type=ArmTableWalker |
| 505clk_domain=system.cpu_clk_domain |
| 506num_squash_per_cycle=2 507sys=system 508port=system.cpu.toL2Bus.slave[2] 509 510[system.cpu.l2cache] 511type=BaseCache |
| 512children=tags |
| 513addr_ranges=0:18446744073709551615 514assoc=8 |
| 515clk_domain=system.cpu_clk_domain |
| 516forward_snoops=true 517hit_latency=20 518is_top_level=false 519max_miss_count=0 520mshrs=20 521prefetch_on_access=false 522prefetcher=Null 523response_latency=20 524size=2097152 525system=system |
| 526tags=system.cpu.l2cache.tags |
| 527tgts_per_mshr=12 528two_queue=false 529write_buffers=8 530cpu_side=system.cpu.toL2Bus.master[0] 531mem_side=system.membus.slave[1] 532 |
| 533[system.cpu.l2cache.tags] 534type=LRU 535assoc=8 536block_size=64 537clk_domain=system.cpu_clk_domain 538hit_latency=20 539size=2097152 540 |
| 541[system.cpu.toL2Bus] 542type=CoherentBus |
| 543clk_domain=system.cpu_clk_domain |
| 544header_cycles=1 545system=system 546use_default_range=false 547width=32 548master=system.cpu.l2cache.cpu_side 549slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 550 551[system.cpu.tracer] 552type=ExeTracer 553 554[system.cpu.workload] 555type=LiveProcess 556cmd=bzip2 input.source 1 557cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing 558egid=100 559env= 560errout=cerr 561euid=100 |
| 562executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 |
| 563gid=100 564input=cin 565max_stack_size=67108864 566output=cout 567pid=100 568ppid=99 569simpoint=0 570system=system 571uid=100 572 |
| 573[system.cpu_clk_domain] 574type=SrcClockDomain 575clock=500 576voltage_domain=system.voltage_domain 577 |
| 578[system.membus] 579type=CoherentBus |
| 580clk_domain=system.clk_domain |
| 581header_cycles=1 582system=system 583use_default_range=false 584width=8 585master=system.physmem.port 586slave=system.system_port system.cpu.l2cache.mem_side 587 588[system.physmem] 589type=SimpleDRAM 590activation_limit=4 |
| 591addr_mapping=RaBaChCo |
| 592banks_per_rank=8 |
| 593burst_length=8 |
| 594channels=1 |
| 595clk_domain=system.clk_domain 596conf_table_reported=true 597device_bus_width=8 598device_rowbuffer_size=1024 599devices_per_rank=8 |
| 600in_addr_map=true |
| 601mem_sched_policy=frfcfs 602null=false 603page_policy=open 604range=0:134217727 605ranks_per_channel=2 606read_buffer_size=32 |
| 607static_backend_latency=10000 608static_frontend_latency=10000 |
| 609tBURST=5000 610tCL=13750 611tRCD=13750 612tREFI=7800000 613tRFC=300000 614tRP=13750 615tWTR=7500 616tXAW=40000 617write_buffer_size=32 618write_thresh_perc=70 |
| 619port=system.membus.master[0] 620 |
| 621[system.voltage_domain] 622type=VoltageDomain 623voltage=1.000000 624 |