| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 497 unchanged lines hidden (view full) --- 506cpu_side=system.cpu.toL2Bus.master[0] 507mem_side=system.membus.slave[1] 508 509[system.cpu.toL2Bus] 510type=CoherentBus 511block_size=64 512clock=500 513header_cycles=1 |
| 514system=system |
| 515use_default_range=false 516width=32 517master=system.cpu.l2cache.cpu_side 518slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 519 520[system.cpu.tracer] 521type=ExeTracer 522 523[system.cpu.workload] 524type=LiveProcess 525cmd=bzip2 input.source 1 526cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing 527egid=100 528env= 529errout=cerr 530euid=100 |
| 531executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2 |
| 532gid=100 533input=cin 534max_stack_size=67108864 535output=cout 536pid=100 537ppid=99 538simpoint=0 539system=system 540uid=100 541 542[system.membus] 543type=CoherentBus 544block_size=64 545clock=1000 546header_cycles=1 |
| 547system=system |
| 548use_default_range=false 549width=8 550master=system.physmem.port 551slave=system.system_port system.cpu.l2cache.mem_side 552 553[system.physmem] 554type=SimpleDRAM |
| 555activation_limit=4 |
| 556addr_mapping=openmap 557banks_per_rank=8 |
| 558channels=1 |
| 559clock=1000 560conf_table_reported=false 561in_addr_map=true |
| 562lines_per_rowbuffer=32 563mem_sched_policy=frfcfs |
| 564null=false 565page_policy=open 566range=0:134217727 567ranks_per_channel=2 568read_buffer_size=32 |
| 569tBURST=5000 570tCL=13750 571tRCD=13750 |
| 572tREFI=7800000 573tRFC=300000 |
| 574tRP=13750 575tWTR=7500 576tXAW=40000 |
| 577write_buffer_size=32 578write_thresh_perc=70 579zero=false 580port=system.membus.master[0] 581 |