1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 478 unchanged lines hidden (view full) --- 487tgts_per_mshr=5 488trace_addr=0 489two_queue=false 490write_buffers=8 491cpu_side=system.cpu.toL2Bus.master[0] 492mem_side=system.membus.slave[1] 493 494[system.cpu.toL2Bus] |
495type=CoherentBus |
496block_size=64 |
497clock=1000 498header_cycles=1 499use_default_range=false 500width=64 501master=system.cpu.l2cache.cpu_side 502slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port 503 504[system.cpu.tracer] --- 14 unchanged lines hidden (view full) --- 519output=cout 520pid=100 521ppid=99 522simpoint=0 523system=system 524uid=100 525 526[system.membus] |
527type=CoherentBus |
528block_size=64 |
529clock=1000 530header_cycles=1 531use_default_range=false 532width=64 533master=system.physmem.port[0] 534slave=system.system_port system.cpu.l2cache.mem_side 535 536[system.physmem] 537type=SimpleMemory 538conf_table_reported=false 539file= 540in_addr_map=true 541latency=30000 542latency_var=0 543null=false 544range=0:134217727 545zero=false 546port=system.membus.master[0] 547 |