| stats.txt (11687:b3d5f0e9e258) | stats.txt (11754:c209cb86278a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.150226 # Number of seconds simulated 4sim_ticks 1150225722500 # Number of ticks simulated 5final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.150228 # Number of seconds simulated 4sim_ticks 1150227786500 # Number of ticks simulated 5final_tick 1150227786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 386915 # Simulator instruction rate (inst/s) 8host_op_rate 416843 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 288133243 # Simulator tick rate (ticks/s) 10host_mem_usage 273608 # Number of bytes of host memory used 11host_seconds 3991.99 # Real time elapsed on the host | 7host_inst_rate 394229 # Simulator instruction rate (inst/s) 8host_op_rate 424722 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 293579950 # Simulator tick rate (ticks/s) 10host_mem_usage 273524 # Number of bytes of host memory used 11host_seconds 3917.94 # Real time elapsed on the host |
| 12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory 19system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 67849984 # Number of bytes written to this memory 23system.physmem.bytes_written::total 67849984 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 2063982 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 2064767 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 132094848 # Number of bytes read from this memory 19system.physmem.bytes_read::total 132145088 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 67849984 # Number of bytes written to this memory 23system.physmem.bytes_written::total 67849984 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 2063982 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 2064767 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 1060156 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 1060156 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 43678 # Total read bandwidth from this memory (bytes/s) |
| 30system.physmem.bw_read::cpu.data 114842544 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 114886222 # Total read bandwidth from this memory (bytes/s) | 30system.physmem.bw_read::cpu.data 114842338 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 114886016 # Total read bandwidth from this memory (bytes/s) |
| 32system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) | 32system.physmem.bw_inst_read::cpu.inst 43678 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 43678 # Instruction read bandwidth from this memory (bytes/s) |
| 34system.physmem.bw_write::writebacks 58988408 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 58988408 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 58988408 # Total bandwidth to/from this memory (bytes/s) | 34system.physmem.bw_write::writebacks 58988302 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 58988302 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 58988302 # Total bandwidth to/from this memory (bytes/s) |
| 37system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) | 37system.physmem.bw_total::cpu.inst 43678 # Total bandwidth to/from this memory (bytes/s) |
| 38system.physmem.bw_total::cpu.data 114842544 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 173874630 # Total bandwidth to/from this memory (bytes/s) | 38system.physmem.bw_total::cpu.data 114842338 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 173874318 # Total bandwidth to/from this memory (bytes/s) |
| 40system.physmem.readReqs 2064767 # Number of read requests accepted 41system.physmem.writeReqs 1060156 # Number of write requests accepted 42system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 1060156 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 132061888 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 83200 # Total number of bytes read from write queue 46system.physmem.bytesWritten 67848256 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 132145088 # Total read bytes from the system interface side --- 8 unchanged lines hidden (view full) --- 56system.physmem.perBankRdBursts::4 123572 # Per bank write bursts 57system.physmem.perBankRdBursts::5 123680 # Per bank write bursts 58system.physmem.perBankRdBursts::6 124357 # Per bank write bursts 59system.physmem.perBankRdBursts::7 124965 # Per bank write bursts 60system.physmem.perBankRdBursts::8 132488 # Per bank write bursts 61system.physmem.perBankRdBursts::9 134781 # Per bank write bursts 62system.physmem.perBankRdBursts::10 133246 # Per bank write bursts 63system.physmem.perBankRdBursts::11 134508 # Per bank write bursts | 40system.physmem.readReqs 2064767 # Number of read requests accepted 41system.physmem.writeReqs 1060156 # Number of write requests accepted 42system.physmem.readBursts 2064767 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 1060156 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 132061888 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 83200 # Total number of bytes read from write queue 46system.physmem.bytesWritten 67848256 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 132145088 # Total read bytes from the system interface side --- 8 unchanged lines hidden (view full) --- 56system.physmem.perBankRdBursts::4 123572 # Per bank write bursts 57system.physmem.perBankRdBursts::5 123680 # Per bank write bursts 58system.physmem.perBankRdBursts::6 124357 # Per bank write bursts 59system.physmem.perBankRdBursts::7 124965 # Per bank write bursts 60system.physmem.perBankRdBursts::8 132488 # Per bank write bursts 61system.physmem.perBankRdBursts::9 134781 # Per bank write bursts 62system.physmem.perBankRdBursts::10 133246 # Per bank write bursts 63system.physmem.perBankRdBursts::11 134508 # Per bank write bursts |
| 64system.physmem.perBankRdBursts::12 134524 # Per bank write bursts | 64system.physmem.perBankRdBursts::12 134523 # Per bank write bursts |
| 65system.physmem.perBankRdBursts::13 134597 # Per bank write bursts 66system.physmem.perBankRdBursts::14 130537 # Per bank write bursts | 65system.physmem.perBankRdBursts::13 134597 # Per bank write bursts 66system.physmem.perBankRdBursts::14 130537 # Per bank write bursts |
| 67system.physmem.perBankRdBursts::15 130646 # Per bank write bursts | 67system.physmem.perBankRdBursts::15 130647 # Per bank write bursts |
| 68system.physmem.perBankWrBursts::0 66781 # Per bank write bursts 69system.physmem.perBankWrBursts::1 64940 # Per bank write bursts 70system.physmem.perBankWrBursts::2 63173 # Per bank write bursts 71system.physmem.perBankWrBursts::3 63584 # Per bank write bursts 72system.physmem.perBankWrBursts::4 63558 # Per bank write bursts 73system.physmem.perBankWrBursts::5 63644 # Per bank write bursts 74system.physmem.perBankWrBursts::6 65047 # Per bank write bursts 75system.physmem.perBankWrBursts::7 66059 # Per bank write bursts 76system.physmem.perBankWrBursts::8 67975 # Per bank write bursts 77system.physmem.perBankWrBursts::9 68435 # Per bank write bursts 78system.physmem.perBankWrBursts::10 68155 # Per bank write bursts 79system.physmem.perBankWrBursts::11 68585 # Per bank write bursts 80system.physmem.perBankWrBursts::12 68036 # Per bank write bursts 81system.physmem.perBankWrBursts::13 68532 # Per bank write bursts 82system.physmem.perBankWrBursts::14 67159 # Per bank write bursts 83system.physmem.perBankWrBursts::15 66466 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 68system.physmem.perBankWrBursts::0 66781 # Per bank write bursts 69system.physmem.perBankWrBursts::1 64940 # Per bank write bursts 70system.physmem.perBankWrBursts::2 63173 # Per bank write bursts 71system.physmem.perBankWrBursts::3 63584 # Per bank write bursts 72system.physmem.perBankWrBursts::4 63558 # Per bank write bursts 73system.physmem.perBankWrBursts::5 63644 # Per bank write bursts 74system.physmem.perBankWrBursts::6 65047 # Per bank write bursts 75system.physmem.perBankWrBursts::7 66059 # Per bank write bursts 76system.physmem.perBankWrBursts::8 67975 # Per bank write bursts 77system.physmem.perBankWrBursts::9 68435 # Per bank write bursts 78system.physmem.perBankWrBursts::10 68155 # Per bank write bursts 79system.physmem.perBankWrBursts::11 68585 # Per bank write bursts 80system.physmem.perBankWrBursts::12 68036 # Per bank write bursts 81system.physmem.perBankWrBursts::13 68532 # Per bank write bursts 82system.physmem.perBankWrBursts::14 67159 # Per bank write bursts 83system.physmem.perBankWrBursts::15 66466 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 86system.physmem.totGap 1150225621500 # Total gap between requests | 86system.physmem.totGap 1150227685500 # Total gap between requests |
| 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 2064767 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 1060156 # Write request sizes (log2) | 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 2064767 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 1060156 # Write request sizes (log2) |
| 101system.physmem.rdQLenPdf::0 1919491 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 143962 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::0 1919511 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 143942 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 103system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::15 31061 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 32150 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 57332 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 62506 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 62721 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 62815 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 62684 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 62639 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 62591 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 62502 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 62571 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::15 31051 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 32142 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 57333 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 62501 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 62728 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 62816 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 62688 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 62636 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 62501 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 62570 # What write queue length does an incoming req see |
| 159system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see | 159system.physmem.wrQLenPdf::26 62618 # What write queue length does an incoming req see |
| 160system.physmem.wrQLenPdf::27 62657 # What write queue length does an incoming req see | 160system.physmem.wrQLenPdf::27 62659 # What write queue length does an incoming req see |
| 161system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see | 161system.physmem.wrQLenPdf::28 62645 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::29 62805 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 63052 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 62414 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 62339 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::29 62806 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 63061 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 62416 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 62338 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 166system.physmem.wrQLenPdf::33 38 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see --- 15 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 197system.physmem.bytesPerActivate::samples 1927680 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 103.704050 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 81.827428 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 125.877785 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 1497957 77.71% 77.71% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 310202 16.09% 93.80% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 52219 2.71% 96.51% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 20801 1.08% 97.59% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 13076 0.68% 98.27% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 7806 0.40% 98.67% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 5210 0.27% 98.94% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 5119 0.27% 99.21% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 15290 0.79% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 1927680 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 62182 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 33.137773 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 23.854622 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 150.738788 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 62143 99.94% 99.94% # Reads before turning the bus around for writes | 197system.physmem.bytesPerActivate::samples 1927678 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 103.704158 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 81.827351 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 125.878363 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 1497959 77.71% 77.71% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 310183 16.09% 93.80% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 52221 2.71% 96.51% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 20819 1.08% 97.59% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 7800 0.40% 98.67% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 5214 0.27% 98.94% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 5117 0.27% 99.21% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 15291 0.79% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 1927678 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 62183 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 33.137240 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 23.854238 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 150.737609 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 62144 99.94% 99.94% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::4096-5119 4 0.01% 99.99% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes | 216system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.97% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::4096-5119 4 0.01% 99.99% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::18432-19455 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 225system.physmem.rdPerTurnAround::total 62182 # Reads before turning the bus around for writes 226system.physmem.wrPerTurnAround::samples 62182 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::mean 17.048808 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::gmean 17.017651 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::stdev 1.031288 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::16 29885 48.06% 48.06% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::17 1078 1.73% 49.79% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::18 29552 47.53% 97.32% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::19 1636 2.63% 99.95% # Writes before turning the bus around for reads | 225system.physmem.rdPerTurnAround::total 62183 # Reads before turning the bus around for writes 226system.physmem.wrPerTurnAround::samples 62183 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::mean 17.048534 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::gmean 17.017369 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::stdev 1.031425 # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::16 29894 48.07% 48.07% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::17 1086 1.75% 49.82% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::18 29528 47.49% 97.31% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::19 1644 2.64% 99.95% # Writes before turning the bus around for reads |
| 234system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads | 234system.physmem.wrPerTurnAround::20 28 0.05% 100.00% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::21 3 0.00% 100.00% # Writes before turning the bus around for reads |
| 236system.physmem.wrPerTurnAround::total 62182 # Writes before turning the bus around for reads 237system.physmem.totQLat 59945214750 # Total ticks spent queuing 238system.physmem.totMemAccLat 98635221000 # Total ticks spent from burst creation until serviced by the DRAM | 236system.physmem.wrPerTurnAround::total 62183 # Writes before turning the bus around for reads 237system.physmem.totQLat 59946131250 # Total ticks spent queuing 238system.physmem.totMemAccLat 98636137500 # Total ticks spent from burst creation until serviced by the DRAM |
| 239system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers | 239system.physmem.totBusLat 10317335000 # Total ticks spent in databus transfers |
| 240system.physmem.avgQLat 29050.73 # Average queueing delay per DRAM burst | 240system.physmem.avgQLat 29051.17 # Average queueing delay per DRAM burst |
| 241system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 241system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 242system.physmem.avgMemAccLat 47800.73 # Average memory access latency per DRAM burst | 242system.physmem.avgMemAccLat 47801.17 # Average memory access latency per DRAM burst |
| 243system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s 244system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s 245system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s 246system.physmem.avgWrBWSys 58.99 # Average system write bandwidth in MiByte/s 247system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 248system.physmem.busUtil 1.36 # Data bus utilization in percentage 249system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads 250system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes 251system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 252system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing | 243system.physmem.avgRdBW 114.81 # Average DRAM read bandwidth in MiByte/s 244system.physmem.avgWrBW 58.99 # Average achieved write bandwidth in MiByte/s 245system.physmem.avgRdBWSys 114.89 # Average system read bandwidth in MiByte/s 246system.physmem.avgWrBWSys 58.99 # Average system write bandwidth in MiByte/s 247system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 248system.physmem.busUtil 1.36 # Data bus utilization in percentage 249system.physmem.busUtilRead 0.90 # Data bus utilization in percentage for reads 250system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes 251system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 252system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing |
| 253system.physmem.readRowHits 775403 # Number of row buffer hits during reads 254system.physmem.writeRowHits 420503 # Number of row buffer hits during writes | 253system.physmem.readRowHits 775435 # Number of row buffer hits during reads 254system.physmem.writeRowHits 420473 # Number of row buffer hits during writes |
| 255system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads 256system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes | 255system.physmem.readRowHitRate 37.58 # Row buffer hit rate for reads 256system.physmem.writeRowHitRate 39.66 # Row buffer hit rate for writes |
| 257system.physmem.avgGap 368081.27 # Average gap between requests | 257system.physmem.avgGap 368081.93 # Average gap between requests |
| 258system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined | 258system.physmem.pageHitRate 38.29 # Row buffer hit rate, read and write combined |
| 259system.physmem_0.actEnergy 6704024460 # Energy for activate commands per rank (pJ) 260system.physmem_0.preEnergy 3563246940 # Energy for precharge commands per rank (pJ) | 259system.physmem_0.actEnergy 6703938780 # Energy for activate commands per rank (pJ) 260system.physmem_0.preEnergy 3563201400 # Energy for precharge commands per rank (pJ) |
| 261system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) 262system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) | 261system.physmem_0.readEnergy 7126719600 # Energy for read commands per rank (pJ) 262system.physmem_0.writeEnergy 2697622920 # Energy for write commands per rank (pJ) |
| 263system.physmem_0.refreshEnergy 71584047600.000015 # Energy for refresh commands per rank (pJ) 264system.physmem_0.actBackEnergy 47598370410 # Energy for active background per rank (pJ) 265system.physmem_0.preBackEnergy 2598119520 # Energy for precharge background per rank (pJ) 266system.physmem_0.actPowerDownEnergy 242886973860 # Energy for active power-down per rank (pJ) 267system.physmem_0.prePowerDownEnergy 71929585440 # Energy for precharge power-down per rank (pJ) 268system.physmem_0.selfRefreshEnergy 82360762695 # Energy for self refresh per rank (pJ) 269system.physmem_0.totalEnergy 539073775965 # Total energy per rank (pJ) 270system.physmem_0.averagePower 468.667814 # Core power per rank (mW) 271system.physmem_0.totalIdleTime 1039023905500 # Total Idle time Per DRAM Rank 272system.physmem_0.memoryStateTime::IDLE 3501879500 # Time in different power states 273system.physmem_0.memoryStateTime::REF 30346756000 # Time in different power states 274system.physmem_0.memoryStateTime::SREF 319059811750 # Time in different power states 275system.physmem_0.memoryStateTime::PRE_PDN 187317352250 # Time in different power states 276system.physmem_0.memoryStateTime::ACT 77352878250 # Time in different power states 277system.physmem_0.memoryStateTime::ACT_PDN 532647044750 # Time in different power states 278system.physmem_1.actEnergy 7059682140 # Energy for activate commands per rank (pJ) 279system.physmem_1.preEnergy 3752298660 # Energy for precharge commands per rank (pJ) | 263system.physmem_0.refreshEnergy 71587735440.000015 # Energy for refresh commands per rank (pJ) 264system.physmem_0.actBackEnergy 47610368340 # Energy for active background per rank (pJ) 265system.physmem_0.preBackEnergy 2598027360 # Energy for precharge background per rank (pJ) 266system.physmem_0.actPowerDownEnergy 242891748180 # Energy for active power-down per rank (pJ) 267system.physmem_0.prePowerDownEnergy 71936235360 # Energy for precharge power-down per rank (pJ) 268system.physmem_0.selfRefreshEnergy 82347779655 # Energy for self refresh per rank (pJ) 269system.physmem_0.totalEnergy 539087705175 # Total energy per rank (pJ) 270system.physmem_0.averagePower 468.679083 # Core power per rank (mW) 271system.physmem_0.totalIdleTime 1039000185750 # Total Idle time Per DRAM Rank 272system.physmem_0.memoryStateTime::IDLE 3501543500 # Time in different power states 273system.physmem_0.memoryStateTime::REF 30348316000 # Time in different power states 274system.physmem_0.memoryStateTime::SREF 319007908000 # Time in different power states 275system.physmem_0.memoryStateTime::PRE_PDN 187335147250 # Time in different power states 276system.physmem_0.memoryStateTime::ACT 77377438000 # Time in different power states 277system.physmem_0.memoryStateTime::ACT_PDN 532657433750 # Time in different power states 278system.physmem_1.actEnergy 7059753540 # Energy for activate commands per rank (pJ) 279system.physmem_1.preEnergy 3752336610 # Energy for precharge commands per rank (pJ) |
| 280system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) 281system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) | 280system.physmem_1.readEnergy 7606434780 # Energy for read commands per rank (pJ) 281system.physmem_1.writeEnergy 2836250460 # Energy for write commands per rank (pJ) |
| 282system.physmem_1.refreshEnergy 71064062160.000015 # Energy for refresh commands per rank (pJ) 283system.physmem_1.actBackEnergy 47576528010 # Energy for active background per rank (pJ) 284system.physmem_1.preBackEnergy 2430223200 # Energy for precharge background per rank (pJ) 285system.physmem_1.actPowerDownEnergy 248601681570 # Energy for active power-down per rank (pJ) 286system.physmem_1.prePowerDownEnergy 68458810560 # Energy for precharge power-down per rank (pJ) 287system.physmem_1.selfRefreshEnergy 80907988260 # Energy for self refresh per rank (pJ) 288system.physmem_1.totalEnergy 540316908180 # Total energy per rank (pJ) 289system.physmem_1.averagePower 469.748583 # Core power per rank (mW) 290system.physmem_1.totalIdleTime 1039511813000 # Total Idle time Per DRAM Rank 291system.physmem_1.memoryStateTime::IDLE 3059644000 # Time in different power states 292system.physmem_1.memoryStateTime::REF 30118792000 # Time in different power states 293system.physmem_1.memoryStateTime::SREF 316054273750 # Time in different power states 294system.physmem_1.memoryStateTime::PRE_PDN 178278810500 # Time in different power states 295system.physmem_1.memoryStateTime::ACT 77535412750 # Time in different power states 296system.physmem_1.memoryStateTime::ACT_PDN 545178789500 # Time in different power states 297system.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states 298system.cpu.branchPred.lookups 240019882 # Number of BP lookups 299system.cpu.branchPred.condPredicted 186610383 # Number of conditional branches predicted | 282system.physmem_1.refreshEnergy 71062832880.000015 # Energy for refresh commands per rank (pJ) 283system.physmem_1.actBackEnergy 47583848520 # Energy for active background per rank (pJ) 284system.physmem_1.preBackEnergy 2430369600 # Energy for precharge background per rank (pJ) 285system.physmem_1.actPowerDownEnergy 248599905450 # Energy for active power-down per rank (pJ) 286system.physmem_1.prePowerDownEnergy 68453747040 # Energy for precharge power-down per rank (pJ) 287system.physmem_1.selfRefreshEnergy 80907358950 # Energy for self refresh per rank (pJ) 288system.physmem_1.totalEnergy 540315522360 # Total energy per rank (pJ) 289system.physmem_1.averagePower 469.746535 # Core power per rank (mW) 290system.physmem_1.totalIdleTime 1039499383250 # Total Idle time Per DRAM Rank 291system.physmem_1.memoryStateTime::IDLE 3059154750 # Time in different power states 292system.physmem_1.memoryStateTime::REF 30118266000 # Time in different power states 293system.physmem_1.memoryStateTime::SREF 316057409750 # Time in different power states 294system.physmem_1.memoryStateTime::PRE_PDN 178263690250 # Time in different power states 295system.physmem_1.memoryStateTime::ACT 77550921750 # Time in different power states 296system.physmem_1.memoryStateTime::ACT_PDN 545178344000 # Time in different power states 297system.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states 298system.cpu.branchPred.lookups 240019900 # Number of BP lookups 299system.cpu.branchPred.condPredicted 186610401 # Number of conditional branches predicted |
| 300system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect | 300system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect |
| 301system.cpu.branchPred.BTBLookups 131646647 # Number of BTB lookups 302system.cpu.branchPred.BTBHits 122324605 # Number of BTB hits | 301system.cpu.branchPred.BTBLookups 131646658 # Number of BTB lookups 302system.cpu.branchPred.BTBHits 122324616 # Number of BTB hits |
| 303system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 303system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 304system.cpu.branchPred.BTBHitPct 92.918891 # BTB Hit Percentage | 304system.cpu.branchPred.BTBHitPct 92.918892 # BTB Hit Percentage |
| 305system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. 306system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 307system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. 308system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. 309system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. 310system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. 311system.cpu_clk_domain.clock 500 # Clock period in ticks | 305system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. 306system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 307system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. 308system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. 309system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. 310system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. 311system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 312system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 312system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 313system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 334system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 335system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 336system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 337system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 338system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 339system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 340system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 341system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 313system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 314system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 315system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 316system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 317system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 318system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 319system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 320system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 334system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 335system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 336system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 337system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 338system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 339system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 340system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 341system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 342system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 342system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 343system.cpu.dtb.walker.walks 0 # Table walker walks requested 344system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 364system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 365system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 366system.cpu.dtb.read_accesses 0 # DTB read accesses 367system.cpu.dtb.write_accesses 0 # DTB write accesses 368system.cpu.dtb.inst_accesses 0 # ITB inst accesses 369system.cpu.dtb.hits 0 # DTB hits 370system.cpu.dtb.misses 0 # DTB misses 371system.cpu.dtb.accesses 0 # DTB accesses | 343system.cpu.dtb.walker.walks 0 # Table walker walks requested 344system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 345system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 346system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 347system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 348system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 349system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 350system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 364system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 365system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 366system.cpu.dtb.read_accesses 0 # DTB read accesses 367system.cpu.dtb.write_accesses 0 # DTB write accesses 368system.cpu.dtb.inst_accesses 0 # ITB inst accesses 369system.cpu.dtb.hits 0 # DTB hits 370system.cpu.dtb.misses 0 # DTB misses 371system.cpu.dtb.accesses 0 # DTB accesses |
| 372system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 372system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 373system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 394system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 395system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 397system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 398system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 399system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 400system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 401system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 373system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 374system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 375system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 376system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 377system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 378system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 379system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 380system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 394system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 395system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 396system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 397system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 398system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 399system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 400system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 401system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 402system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 402system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 403system.cpu.itb.walker.walks 0 # Table walker walks requested 404system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 409system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 410system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 425system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 426system.cpu.itb.read_accesses 0 # DTB read accesses 427system.cpu.itb.write_accesses 0 # DTB write accesses 428system.cpu.itb.inst_accesses 0 # ITB inst accesses 429system.cpu.itb.hits 0 # DTB hits 430system.cpu.itb.misses 0 # DTB misses 431system.cpu.itb.accesses 0 # DTB accesses 432system.cpu.workload.num_syscalls 46 # Number of system calls | 403system.cpu.itb.walker.walks 0 # Table walker walks requested 404system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 405system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 406system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 407system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 408system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 409system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 410system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 425system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 426system.cpu.itb.read_accesses 0 # DTB read accesses 427system.cpu.itb.write_accesses 0 # DTB write accesses 428system.cpu.itb.inst_accesses 0 # ITB inst accesses 429system.cpu.itb.hits 0 # DTB hits 430system.cpu.itb.misses 0 # DTB misses 431system.cpu.itb.accesses 0 # DTB accesses 432system.cpu.workload.num_syscalls 46 # Number of system calls |
| 433system.cpu.pwrStateResidencyTicks::ON 1150225722500 # Cumulative time (in ticks) in various power states 434system.cpu.numCycles 2300451445 # number of cpu cycles simulated | 433system.cpu.pwrStateResidencyTicks::ON 1150227786500 # Cumulative time (in ticks) in various power states 434system.cpu.numCycles 2300455573 # number of cpu cycles simulated |
| 435system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 436system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 437system.cpu.committedInsts 1544563088 # Number of instructions committed 438system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed | 435system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 436system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 437system.cpu.committedInsts 1544563088 # Number of instructions committed 438system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed |
| 439system.cpu.discardedOps 41363683 # Number of ops (including micro ops) which were discarded before commit | 439system.cpu.discardedOps 41363694 # Number of ops (including micro ops) which were discarded before commit |
| 440system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 440system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 441system.cpu.cpi 1.489387 # CPI: cycles per instruction 442system.cpu.ipc 0.671417 # IPC: instructions per cycle | 441system.cpu.cpi 1.489389 # CPI: cycles per instruction 442system.cpu.ipc 0.671416 # IPC: instructions per cycle |
| 443system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 444system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction 445system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 446system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 447system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 448system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 449system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 450system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 474system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 475system.cpu.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction 476system.cpu.op_class_0::MemWrite 174847022 10.51% 100.00% # Class of committed instruction 477system.cpu.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction 478system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction 479system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 480system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 481system.cpu.op_class_0::total 1664032481 # Class of committed instruction | 443system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 444system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction 445system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 446system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 447system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 448system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 449system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 450system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction --- 23 unchanged lines hidden (view full) --- 474system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 475system.cpu.op_class_0::MemRead 458306322 27.54% 89.49% # Class of committed instruction 476system.cpu.op_class_0::MemWrite 174847022 10.51% 100.00% # Class of committed instruction 477system.cpu.op_class_0::FloatMemRead 12 0.00% 100.00% # Class of committed instruction 478system.cpu.op_class_0::FloatMemWrite 24 0.00% 100.00% # Class of committed instruction 479system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 480system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 481system.cpu.op_class_0::total 1664032481 # Class of committed instruction |
| 482system.cpu.tickCycles 1845014986 # Number of cycles that the object actually ticked 483system.cpu.idleCycles 455436459 # Total number of cycles that the object has spent stopped 484system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 482system.cpu.tickCycles 1845015660 # Number of cycles that the object actually ticked 483system.cpu.idleCycles 455439913 # Total number of cycles that the object has spent stopped 484system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 485system.cpu.dcache.tags.replacements 9220107 # number of replacements | 485system.cpu.dcache.tags.replacements 9220107 # number of replacements |
| 486system.cpu.dcache.tags.tagsinuse 4085.805290 # Cycle average of tags in use 487system.cpu.dcache.tags.total_refs 624493165 # Total number of references to valid blocks. | 486system.cpu.dcache.tags.tagsinuse 4085.805308 # Cycle average of tags in use 487system.cpu.dcache.tags.total_refs 624493167 # Total number of references to valid blocks. |
| 488system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. 489system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. 490system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. | 488system.cpu.dcache.tags.sampled_refs 9224203 # Sample count of references to valid blocks. 489system.cpu.dcache.tags.avg_refs 67.701585 # Average number of references to valid blocks. 490system.cpu.dcache.tags.warmup_cycle 9872962500 # Cycle when the warmup percentage was hit. |
| 491system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805290 # Average occupied blocks per requestor | 491system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805308 # Average occupied blocks per requestor |
| 492system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy 493system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy 494system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 495system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id 496system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 # Occupied blocks per task id 497system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id 498system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id 499system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 492system.cpu.dcache.tags.occ_percent::cpu.data 0.997511 # Average percentage of cache occupancy 493system.cpu.dcache.tags.occ_percent::total 0.997511 # Average percentage of cache occupancy 494system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 495system.cpu.dcache.tags.age_task_id_blocks_1024::0 201 # Occupied blocks per task id 496system.cpu.dcache.tags.age_task_id_blocks_1024::1 1190 # Occupied blocks per task id 497system.cpu.dcache.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id 498system.cpu.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id 499system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 500system.cpu.dcache.tags.tag_accesses 1277391151 # Number of tag accesses 501system.cpu.dcache.tags.data_accesses 1277391151 # Number of data accesses 502system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states 503system.cpu.dcache.ReadReq_hits::cpu.data 454163885 # number of ReadReq hits 504system.cpu.dcache.ReadReq_hits::total 454163885 # number of ReadReq hits 505system.cpu.dcache.WriteReq_hits::cpu.data 170329157 # number of WriteReq hits 506system.cpu.dcache.WriteReq_hits::total 170329157 # number of WriteReq hits | 500system.cpu.dcache.tags.tag_accesses 1277391153 # Number of tag accesses 501system.cpu.dcache.tags.data_accesses 1277391153 # Number of data accesses 502system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states 503system.cpu.dcache.ReadReq_hits::cpu.data 454163886 # number of ReadReq hits 504system.cpu.dcache.ReadReq_hits::total 454163886 # number of ReadReq hits 505system.cpu.dcache.WriteReq_hits::cpu.data 170329158 # number of WriteReq hits 506system.cpu.dcache.WriteReq_hits::total 170329158 # number of WriteReq hits |
| 507system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 508system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 509system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 510system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 511system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 512system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits | 507system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 508system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 509system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 510system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 511system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 512system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits |
| 513system.cpu.dcache.demand_hits::cpu.data 624493042 # number of demand (read+write) hits 514system.cpu.dcache.demand_hits::total 624493042 # number of demand (read+write) hits 515system.cpu.dcache.overall_hits::cpu.data 624493043 # number of overall hits 516system.cpu.dcache.overall_hits::total 624493043 # number of overall hits | 513system.cpu.dcache.demand_hits::cpu.data 624493044 # number of demand (read+write) hits 514system.cpu.dcache.demand_hits::total 624493044 # number of demand (read+write) hits 515system.cpu.dcache.overall_hits::cpu.data 624493045 # number of overall hits 516system.cpu.dcache.overall_hits::total 624493045 # number of overall hits |
| 517system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses 518system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses | 517system.cpu.dcache.ReadReq_misses::cpu.data 7333417 # number of ReadReq misses 518system.cpu.dcache.ReadReq_misses::total 7333417 # number of ReadReq misses |
| 519system.cpu.dcache.WriteReq_misses::cpu.data 2256890 # number of WriteReq misses 520system.cpu.dcache.WriteReq_misses::total 2256890 # number of WriteReq misses | 519system.cpu.dcache.WriteReq_misses::cpu.data 2256889 # number of WriteReq misses 520system.cpu.dcache.WriteReq_misses::total 2256889 # number of WriteReq misses |
| 521system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 522system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses | 521system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 522system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses |
| 523system.cpu.dcache.demand_misses::cpu.data 9590307 # number of demand (read+write) misses 524system.cpu.dcache.demand_misses::total 9590307 # number of demand (read+write) misses 525system.cpu.dcache.overall_misses::cpu.data 9590309 # number of overall misses 526system.cpu.dcache.overall_misses::total 9590309 # number of overall misses 527system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500 # number of ReadReq miss cycles 528system.cpu.dcache.ReadReq_miss_latency::total 208195707500 # number of ReadReq miss cycles 529system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500 # number of WriteReq miss cycles 530system.cpu.dcache.WriteReq_miss_latency::total 119902321500 # number of WriteReq miss cycles 531system.cpu.dcache.demand_miss_latency::cpu.data 328098029000 # number of demand (read+write) miss cycles 532system.cpu.dcache.demand_miss_latency::total 328098029000 # number of demand (read+write) miss cycles 533system.cpu.dcache.overall_miss_latency::cpu.data 328098029000 # number of overall miss cycles 534system.cpu.dcache.overall_miss_latency::total 328098029000 # number of overall miss cycles 535system.cpu.dcache.ReadReq_accesses::cpu.data 461497302 # number of ReadReq accesses(hits+misses) 536system.cpu.dcache.ReadReq_accesses::total 461497302 # number of ReadReq accesses(hits+misses) | 523system.cpu.dcache.demand_misses::cpu.data 9590306 # number of demand (read+write) misses 524system.cpu.dcache.demand_misses::total 9590306 # number of demand (read+write) misses 525system.cpu.dcache.overall_misses::cpu.data 9590308 # number of overall misses 526system.cpu.dcache.overall_misses::total 9590308 # number of overall misses 527system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000 # number of ReadReq miss cycles 528system.cpu.dcache.ReadReq_miss_latency::total 208196327000 # number of ReadReq miss cycles 529system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000 # number of WriteReq miss cycles 530system.cpu.dcache.WriteReq_miss_latency::total 119903341000 # number of WriteReq miss cycles 531system.cpu.dcache.demand_miss_latency::cpu.data 328099668000 # number of demand (read+write) miss cycles 532system.cpu.dcache.demand_miss_latency::total 328099668000 # number of demand (read+write) miss cycles 533system.cpu.dcache.overall_miss_latency::cpu.data 328099668000 # number of overall miss cycles 534system.cpu.dcache.overall_miss_latency::total 328099668000 # number of overall miss cycles 535system.cpu.dcache.ReadReq_accesses::cpu.data 461497303 # number of ReadReq accesses(hits+misses) 536system.cpu.dcache.ReadReq_accesses::total 461497303 # number of ReadReq accesses(hits+misses) |
| 537system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 538system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 539system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) 540system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) 541system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 542system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 543system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 544system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) | 537system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 538system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 539system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) 540system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) 541system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 542system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 543system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 544system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) |
| 545system.cpu.dcache.demand_accesses::cpu.data 634083349 # number of demand (read+write) accesses 546system.cpu.dcache.demand_accesses::total 634083349 # number of demand (read+write) accesses 547system.cpu.dcache.overall_accesses::cpu.data 634083352 # number of overall (read+write) accesses 548system.cpu.dcache.overall_accesses::total 634083352 # number of overall (read+write) accesses | 545system.cpu.dcache.demand_accesses::cpu.data 634083350 # number of demand (read+write) accesses 546system.cpu.dcache.demand_accesses::total 634083350 # number of demand (read+write) accesses 547system.cpu.dcache.overall_accesses::cpu.data 634083353 # number of overall (read+write) accesses 548system.cpu.dcache.overall_accesses::total 634083353 # number of overall (read+write) accesses |
| 549system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses 550system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses 551system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses 552system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses 553system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses 554system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses 555system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 # miss rate for demand accesses 556system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses 557system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses 558system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses | 549system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses 550system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses 551system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013077 # miss rate for WriteReq accesses 552system.cpu.dcache.WriteReq_miss_rate::total 0.013077 # miss rate for WriteReq accesses 553system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses 554system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses 555system.cpu.dcache.demand_miss_rate::cpu.data 0.015125 # miss rate for demand accesses 556system.cpu.dcache.demand_miss_rate::total 0.015125 # miss rate for demand accesses 557system.cpu.dcache.overall_miss_rate::cpu.data 0.015125 # miss rate for overall accesses 558system.cpu.dcache.overall_miss_rate::total 0.015125 # miss rate for overall accesses |
| 559system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846 # average ReadReq miss latency 560system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846 # average ReadReq miss latency 561system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272 # average WriteReq miss latency 562system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272 # average WriteReq miss latency 563system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865 # average overall miss latency 564system.cpu.dcache.demand_avg_miss_latency::total 34211.420865 # average overall miss latency 565system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730 # average overall miss latency 566system.cpu.dcache.overall_avg_miss_latency::total 34211.413730 # average overall miss latency | 559system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322 # average ReadReq miss latency 560system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322 # average ReadReq miss latency 561system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540 # average WriteReq miss latency 562system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540 # average WriteReq miss latency 563system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334 # average overall miss latency 564system.cpu.dcache.demand_avg_miss_latency::total 34211.595334 # average overall miss latency 565system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199 # average overall miss latency 566system.cpu.dcache.overall_avg_miss_latency::total 34211.588199 # average overall miss latency |
| 567system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 568system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 569system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 570system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 571system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 572system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 573system.cpu.dcache.writebacks::writebacks 3670055 # number of writebacks 574system.cpu.dcache.writebacks::total 3670055 # number of writebacks 575system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 576system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits | 567system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 568system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 569system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 570system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 571system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 572system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 573system.cpu.dcache.writebacks::writebacks 3670055 # number of writebacks 574system.cpu.dcache.writebacks::total 3670055 # number of writebacks 575system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 576system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits |
| 577system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366056 # number of WriteReq MSHR hits 578system.cpu.dcache.WriteReq_mshr_hits::total 366056 # number of WriteReq MSHR hits 579system.cpu.dcache.demand_mshr_hits::cpu.data 366105 # number of demand (read+write) MSHR hits 580system.cpu.dcache.demand_mshr_hits::total 366105 # number of demand (read+write) MSHR hits 581system.cpu.dcache.overall_mshr_hits::cpu.data 366105 # number of overall MSHR hits 582system.cpu.dcache.overall_mshr_hits::total 366105 # number of overall MSHR hits | 577system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366055 # number of WriteReq MSHR hits 578system.cpu.dcache.WriteReq_mshr_hits::total 366055 # number of WriteReq MSHR hits 579system.cpu.dcache.demand_mshr_hits::cpu.data 366104 # number of demand (read+write) MSHR hits 580system.cpu.dcache.demand_mshr_hits::total 366104 # number of demand (read+write) MSHR hits 581system.cpu.dcache.overall_mshr_hits::cpu.data 366104 # number of overall MSHR hits 582system.cpu.dcache.overall_mshr_hits::total 366104 # number of overall MSHR hits |
| 583system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses 584system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses 585system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses 586system.cpu.dcache.WriteReq_mshr_misses::total 1890834 # number of WriteReq MSHR misses 587system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 588system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 589system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 # number of demand (read+write) MSHR misses 590system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses 591system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses 592system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses | 583system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333368 # number of ReadReq MSHR misses 584system.cpu.dcache.ReadReq_mshr_misses::total 7333368 # number of ReadReq MSHR misses 585system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890834 # number of WriteReq MSHR misses 586system.cpu.dcache.WriteReq_mshr_misses::total 1890834 # number of WriteReq MSHR misses 587system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 588system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 589system.cpu.dcache.demand_mshr_misses::cpu.data 9224202 # number of demand (read+write) MSHR misses 590system.cpu.dcache.demand_mshr_misses::total 9224202 # number of demand (read+write) MSHR misses 591system.cpu.dcache.overall_mshr_misses::cpu.data 9224203 # number of overall MSHR misses 592system.cpu.dcache.overall_mshr_misses::total 9224203 # number of overall MSHR misses |
| 593system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000 # number of ReadReq MSHR miss cycles 594system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000 # number of ReadReq MSHR miss cycles 595system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92466638500 # number of WriteReq MSHR miss cycles 596system.cpu.dcache.WriteReq_mshr_miss_latency::total 92466638500 # number of WriteReq MSHR miss cycles | 593system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000 # number of ReadReq MSHR miss cycles 594system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000 # number of ReadReq MSHR miss cycles 595system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92467008500 # number of WriteReq MSHR miss cycles 596system.cpu.dcache.WriteReq_mshr_miss_latency::total 92467008500 # number of WriteReq MSHR miss cycles |
| 597system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles 598system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles | 597system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 81000 # number of SoftPFReq MSHR miss cycles 598system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 81000 # number of SoftPFReq MSHR miss cycles |
| 599system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500 # number of demand (read+write) MSHR miss cycles 600system.cpu.dcache.demand_mshr_miss_latency::total 293324557500 # number of demand (read+write) MSHR miss cycles 601system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500 # number of overall MSHR miss cycles 602system.cpu.dcache.overall_mshr_miss_latency::total 293324638500 # number of overall MSHR miss cycles | 599system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500 # number of demand (read+write) MSHR miss cycles 600system.cpu.dcache.demand_mshr_miss_latency::total 293325546500 # number of demand (read+write) MSHR miss cycles 601system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500 # number of overall MSHR miss cycles 602system.cpu.dcache.overall_mshr_miss_latency::total 293325627500 # number of overall MSHR miss cycles |
| 603system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses 604system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses 605system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 606system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 607system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses 608system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses 609system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses 610system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses 611system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses 612system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses | 603system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses 604system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses 605system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 606system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 607system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses 608system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses 609system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses 610system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses 611system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses 612system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses |
| 613system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749 # average ReadReq mshr miss latency 614system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749 # average ReadReq mshr miss latency 615system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126 # average WriteReq mshr miss latency 616system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126 # average WriteReq mshr miss latency | 613system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158 # average ReadReq mshr miss latency 614system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158 # average ReadReq mshr miss latency 615system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807 # average WriteReq mshr miss latency 616system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807 # average WriteReq mshr miss latency |
| 617system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency 618system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency | 617system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 81000 # average SoftPFReq mshr miss latency 618system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 81000 # average SoftPFReq mshr miss latency |
| 619system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782 # average overall mshr miss latency 620system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782 # average overall mshr miss latency 621system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116 # average overall mshr miss latency 622system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116 # average overall mshr miss latency 623system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 619system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000 # average overall mshr miss latency 620system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000 # average overall mshr miss latency 621system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334 # average overall mshr miss latency 622system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334 # average overall mshr miss latency 623system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 624system.cpu.icache.tags.replacements 33 # number of replacements | 624system.cpu.icache.tags.replacements 33 # number of replacements |
| 625system.cpu.icache.tags.tagsinuse 660.478132 # Cycle average of tags in use 626system.cpu.icache.tags.total_refs 466274661 # Total number of references to valid blocks. | 625system.cpu.icache.tags.tagsinuse 660.477823 # Cycle average of tags in use 626system.cpu.icache.tags.total_refs 466274758 # Total number of references to valid blocks. |
| 627system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. | 627system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. |
| 628system.cpu.icache.tags.avg_refs 567244.113139 # Average number of references to valid blocks. | 628system.cpu.icache.tags.avg_refs 567244.231144 # Average number of references to valid blocks. |
| 629system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 629system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 630system.cpu.icache.tags.occ_blocks::cpu.inst 660.478132 # Average occupied blocks per requestor | 630system.cpu.icache.tags.occ_blocks::cpu.inst 660.477823 # Average occupied blocks per requestor |
| 631system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy 632system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy 633system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 635system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 636system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id 637system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id | 631system.cpu.icache.tags.occ_percent::cpu.inst 0.322499 # Average percentage of cache occupancy 632system.cpu.icache.tags.occ_percent::total 0.322499 # Average percentage of cache occupancy 633system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id 634system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 635system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 636system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id 637system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id |
| 638system.cpu.icache.tags.tag_accesses 932551788 # Number of tag accesses 639system.cpu.icache.tags.data_accesses 932551788 # Number of data accesses 640system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states 641system.cpu.icache.ReadReq_hits::cpu.inst 466274661 # number of ReadReq hits 642system.cpu.icache.ReadReq_hits::total 466274661 # number of ReadReq hits 643system.cpu.icache.demand_hits::cpu.inst 466274661 # number of demand (read+write) hits 644system.cpu.icache.demand_hits::total 466274661 # number of demand (read+write) hits 645system.cpu.icache.overall_hits::cpu.inst 466274661 # number of overall hits 646system.cpu.icache.overall_hits::total 466274661 # number of overall hits | 638system.cpu.icache.tags.tag_accesses 932551982 # Number of tag accesses 639system.cpu.icache.tags.data_accesses 932551982 # Number of data accesses 640system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states 641system.cpu.icache.ReadReq_hits::cpu.inst 466274758 # number of ReadReq hits 642system.cpu.icache.ReadReq_hits::total 466274758 # number of ReadReq hits 643system.cpu.icache.demand_hits::cpu.inst 466274758 # number of demand (read+write) hits 644system.cpu.icache.demand_hits::total 466274758 # number of demand (read+write) hits 645system.cpu.icache.overall_hits::cpu.inst 466274758 # number of overall hits 646system.cpu.icache.overall_hits::total 466274758 # number of overall hits |
| 647system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses 648system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses 649system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses 650system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses 651system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses 652system.cpu.icache.overall_misses::total 822 # number of overall misses 653system.cpu.icache.ReadReq_miss_latency::cpu.inst 74803000 # number of ReadReq miss cycles 654system.cpu.icache.ReadReq_miss_latency::total 74803000 # number of ReadReq miss cycles 655system.cpu.icache.demand_miss_latency::cpu.inst 74803000 # number of demand (read+write) miss cycles 656system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles 657system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles 658system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles | 647system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses 648system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses 649system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses 650system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses 651system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses 652system.cpu.icache.overall_misses::total 822 # number of overall misses 653system.cpu.icache.ReadReq_miss_latency::cpu.inst 74803000 # number of ReadReq miss cycles 654system.cpu.icache.ReadReq_miss_latency::total 74803000 # number of ReadReq miss cycles 655system.cpu.icache.demand_miss_latency::cpu.inst 74803000 # number of demand (read+write) miss cycles 656system.cpu.icache.demand_miss_latency::total 74803000 # number of demand (read+write) miss cycles 657system.cpu.icache.overall_miss_latency::cpu.inst 74803000 # number of overall miss cycles 658system.cpu.icache.overall_miss_latency::total 74803000 # number of overall miss cycles |
| 659system.cpu.icache.ReadReq_accesses::cpu.inst 466275483 # number of ReadReq accesses(hits+misses) 660system.cpu.icache.ReadReq_accesses::total 466275483 # number of ReadReq accesses(hits+misses) 661system.cpu.icache.demand_accesses::cpu.inst 466275483 # number of demand (read+write) accesses 662system.cpu.icache.demand_accesses::total 466275483 # number of demand (read+write) accesses 663system.cpu.icache.overall_accesses::cpu.inst 466275483 # number of overall (read+write) accesses 664system.cpu.icache.overall_accesses::total 466275483 # number of overall (read+write) accesses | 659system.cpu.icache.ReadReq_accesses::cpu.inst 466275580 # number of ReadReq accesses(hits+misses) 660system.cpu.icache.ReadReq_accesses::total 466275580 # number of ReadReq accesses(hits+misses) 661system.cpu.icache.demand_accesses::cpu.inst 466275580 # number of demand (read+write) accesses 662system.cpu.icache.demand_accesses::total 466275580 # number of demand (read+write) accesses 663system.cpu.icache.overall_accesses::cpu.inst 466275580 # number of overall (read+write) accesses 664system.cpu.icache.overall_accesses::total 466275580 # number of overall (read+write) accesses |
| 665system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 666system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 667system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 668system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 669system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 670system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 671system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91001.216545 # average ReadReq miss latency 672system.cpu.icache.ReadReq_avg_miss_latency::total 91001.216545 # average ReadReq miss latency --- 28 unchanged lines hidden (view full) --- 701system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 702system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90001.216545 # average ReadReq mshr miss latency 704system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90001.216545 # average ReadReq mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency 706system.cpu.icache.demand_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency 708system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency | 665system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 666system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 667system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 668system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 669system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 670system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 671system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 91001.216545 # average ReadReq miss latency 672system.cpu.icache.ReadReq_avg_miss_latency::total 91001.216545 # average ReadReq miss latency --- 28 unchanged lines hidden (view full) --- 701system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 702system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 703system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 90001.216545 # average ReadReq mshr miss latency 704system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 90001.216545 # average ReadReq mshr miss latency 705system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency 706system.cpu.icache.demand_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency 707system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 90001.216545 # average overall mshr miss latency 708system.cpu.icache.overall_avg_mshr_miss_latency::total 90001.216545 # average overall mshr miss latency |
| 709system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 709system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 710system.cpu.l2cache.tags.replacements 2032334 # number of replacements | 710system.cpu.l2cache.tags.replacements 2032334 # number of replacements |
| 711system.cpu.l2cache.tags.tagsinuse 31895.835750 # Cycle average of tags in use | 711system.cpu.l2cache.tags.tagsinuse 31895.837315 # Cycle average of tags in use |
| 712system.cpu.l2cache.tags.total_refs 16378248 # Total number of references to valid blocks. 713system.cpu.l2cache.tags.sampled_refs 2065102 # Sample count of references to valid blocks. 714system.cpu.l2cache.tags.avg_refs 7.930963 # Average number of references to valid blocks. 715system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. | 712system.cpu.l2cache.tags.total_refs 16378248 # Total number of references to valid blocks. 713system.cpu.l2cache.tags.sampled_refs 2065102 # Sample count of references to valid blocks. 714system.cpu.l2cache.tags.avg_refs 7.930963 # Average number of references to valid blocks. 715system.cpu.l2cache.tags.warmup_cycle 54709395000 # Cycle when the warmup percentage was hit. |
| 716system.cpu.l2cache.tags.occ_blocks::writebacks 10.372188 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535695 # Average occupied blocks per requestor 718system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.927867 # Average occupied blocks per requestor | 716system.cpu.l2cache.tags.occ_blocks::writebacks 10.372175 # Average occupied blocks per requestor 717system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535649 # Average occupied blocks per requestor 718system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.929491 # Average occupied blocks per requestor |
| 719system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy 720system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_percent::cpu.data 0.972288 # Average percentage of cache occupancy 722system.cpu.l2cache.tags.occ_percent::total 0.973384 # Average percentage of cache occupancy 723system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 724system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 725system.cpu.l2cache.tags.age_task_id_blocks_1024::1 831 # Occupied blocks per task id 726system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2946 # Occupied blocks per task id 727system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7191 # Occupied blocks per task id 728system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 # Occupied blocks per task id 729system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 730system.cpu.l2cache.tags.tag_accesses 149613670 # Number of tag accesses 731system.cpu.l2cache.tags.data_accesses 149613670 # Number of data accesses | 719system.cpu.l2cache.tags.occ_percent::writebacks 0.000317 # Average percentage of cache occupancy 720system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000779 # Average percentage of cache occupancy 721system.cpu.l2cache.tags.occ_percent::cpu.data 0.972288 # Average percentage of cache occupancy 722system.cpu.l2cache.tags.occ_percent::total 0.973384 # Average percentage of cache occupancy 723system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 724system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 725system.cpu.l2cache.tags.age_task_id_blocks_1024::1 831 # Occupied blocks per task id 726system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2946 # Occupied blocks per task id 727system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7191 # Occupied blocks per task id 728system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21752 # Occupied blocks per task id 729system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 730system.cpu.l2cache.tags.tag_accesses 149613670 # Number of tag accesses 731system.cpu.l2cache.tags.data_accesses 149613670 # Number of data accesses |
| 732system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 732system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 733system.cpu.l2cache.WritebackDirty_hits::writebacks 3670055 # number of WritebackDirty hits 734system.cpu.l2cache.WritebackDirty_hits::total 3670055 # number of WritebackDirty hits 735system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 736system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 737system.cpu.l2cache.ReadExReq_hits::cpu.data 1078511 # number of ReadExReq hits 738system.cpu.l2cache.ReadExReq_hits::total 1078511 # number of ReadExReq hits 739system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # number of ReadCleanReq hits 740system.cpu.l2cache.ReadCleanReq_hits::total 37 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 753system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251665 # number of ReadSharedReq misses 754system.cpu.l2cache.ReadSharedReq_misses::total 1251665 # number of ReadSharedReq misses 755system.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses 756system.cpu.l2cache.demand_misses::cpu.data 2063988 # number of demand (read+write) misses 757system.cpu.l2cache.demand_misses::total 2064773 # number of demand (read+write) misses 758system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses 759system.cpu.l2cache.overall_misses::cpu.data 2063988 # number of overall misses 760system.cpu.l2cache.overall_misses::total 2064773 # number of overall misses | 733system.cpu.l2cache.WritebackDirty_hits::writebacks 3670055 # number of WritebackDirty hits 734system.cpu.l2cache.WritebackDirty_hits::total 3670055 # number of WritebackDirty hits 735system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 736system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 737system.cpu.l2cache.ReadExReq_hits::cpu.data 1078511 # number of ReadExReq hits 738system.cpu.l2cache.ReadExReq_hits::total 1078511 # number of ReadExReq hits 739system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # number of ReadCleanReq hits 740system.cpu.l2cache.ReadCleanReq_hits::total 37 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 753system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251665 # number of ReadSharedReq misses 754system.cpu.l2cache.ReadSharedReq_misses::total 1251665 # number of ReadSharedReq misses 755system.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses 756system.cpu.l2cache.demand_misses::cpu.data 2063988 # number of demand (read+write) misses 757system.cpu.l2cache.demand_misses::total 2064773 # number of demand (read+write) misses 758system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses 759system.cpu.l2cache.overall_misses::cpu.data 2063988 # number of overall misses 760system.cpu.l2cache.overall_misses::total 2064773 # number of overall misses |
| 761system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282559500 # number of ReadExReq miss cycles 762system.cpu.l2cache.ReadExReq_miss_latency::total 78282559500 # number of ReadExReq miss cycles | 761system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282928500 # number of ReadExReq miss cycles 762system.cpu.l2cache.ReadExReq_miss_latency::total 78282928500 # number of ReadExReq miss cycles |
| 763system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72328000 # number of ReadCleanReq miss cycles 764system.cpu.l2cache.ReadCleanReq_miss_latency::total 72328000 # number of ReadCleanReq miss cycles | 763system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 72328000 # number of ReadCleanReq miss cycles 764system.cpu.l2cache.ReadCleanReq_miss_latency::total 72328000 # number of ReadCleanReq miss cycles |
| 765system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125996723500 # number of ReadSharedReq miss cycles 766system.cpu.l2cache.ReadSharedReq_miss_latency::total 125996723500 # number of ReadSharedReq miss cycles | 765system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125997338000 # number of ReadSharedReq miss cycles 766system.cpu.l2cache.ReadSharedReq_miss_latency::total 125997338000 # number of ReadSharedReq miss cycles |
| 767system.cpu.l2cache.demand_miss_latency::cpu.inst 72328000 # number of demand (read+write) miss cycles | 767system.cpu.l2cache.demand_miss_latency::cpu.inst 72328000 # number of demand (read+write) miss cycles |
| 768system.cpu.l2cache.demand_miss_latency::cpu.data 204279283000 # number of demand (read+write) miss cycles 769system.cpu.l2cache.demand_miss_latency::total 204351611000 # number of demand (read+write) miss cycles | 768system.cpu.l2cache.demand_miss_latency::cpu.data 204280266500 # number of demand (read+write) miss cycles 769system.cpu.l2cache.demand_miss_latency::total 204352594500 # number of demand (read+write) miss cycles |
| 770system.cpu.l2cache.overall_miss_latency::cpu.inst 72328000 # number of overall miss cycles | 770system.cpu.l2cache.overall_miss_latency::cpu.inst 72328000 # number of overall miss cycles |
| 771system.cpu.l2cache.overall_miss_latency::cpu.data 204279283000 # number of overall miss cycles 772system.cpu.l2cache.overall_miss_latency::total 204351611000 # number of overall miss cycles | 771system.cpu.l2cache.overall_miss_latency::cpu.data 204280266500 # number of overall miss cycles 772system.cpu.l2cache.overall_miss_latency::total 204352594500 # number of overall miss cycles |
| 773system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670055 # number of WritebackDirty accesses(hits+misses) 774system.cpu.l2cache.WritebackDirty_accesses::total 3670055 # number of WritebackDirty accesses(hits+misses) 775system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 776system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) 777system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890834 # number of ReadExReq accesses(hits+misses) 778system.cpu.l2cache.ReadExReq_accesses::total 1890834 # number of ReadExReq accesses(hits+misses) 779system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 822 # number of ReadCleanReq accesses(hits+misses) 780system.cpu.l2cache.ReadCleanReq_accesses::total 822 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 793system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170681 # miss rate for ReadSharedReq accesses 794system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.170681 # miss rate for ReadSharedReq accesses 795system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954988 # miss rate for demand accesses 796system.cpu.l2cache.demand_miss_rate::cpu.data 0.223758 # miss rate for demand accesses 797system.cpu.l2cache.demand_miss_rate::total 0.223823 # miss rate for demand accesses 798system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses 799system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses 800system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses | 773system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670055 # number of WritebackDirty accesses(hits+misses) 774system.cpu.l2cache.WritebackDirty_accesses::total 3670055 # number of WritebackDirty accesses(hits+misses) 775system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 776system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) 777system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890834 # number of ReadExReq accesses(hits+misses) 778system.cpu.l2cache.ReadExReq_accesses::total 1890834 # number of ReadExReq accesses(hits+misses) 779system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 822 # number of ReadCleanReq accesses(hits+misses) 780system.cpu.l2cache.ReadCleanReq_accesses::total 822 # number of ReadCleanReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 793system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170681 # miss rate for ReadSharedReq accesses 794system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.170681 # miss rate for ReadSharedReq accesses 795system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954988 # miss rate for demand accesses 796system.cpu.l2cache.demand_miss_rate::cpu.data 0.223758 # miss rate for demand accesses 797system.cpu.l2cache.demand_miss_rate::total 0.223823 # miss rate for demand accesses 798system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses 799system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses 800system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses |
| 801system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102 # average ReadExReq miss latency 802system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102 # average ReadExReq miss latency | 801system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96369.213355 # average ReadExReq miss latency 802system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96369.213355 # average ReadExReq miss latency |
| 803system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618 # average ReadCleanReq miss latency 804system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618 # average ReadCleanReq miss latency | 803system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 92137.579618 # average ReadCleanReq miss latency 804system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 92137.579618 # average ReadCleanReq miss latency |
| 805system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291 # average ReadSharedReq miss latency 806system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291 # average ReadSharedReq miss latency | 805system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.786237 # average ReadSharedReq miss latency 806system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.786237 # average ReadSharedReq miss latency |
| 807system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency | 807system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency |
| 808system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency 809system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483 # average overall miss latency | 808system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency 809system.cpu.l2cache.demand_avg_miss_latency::total 98970.973807 # average overall miss latency |
| 810system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency | 810system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 92137.579618 # average overall miss latency |
| 811system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency 812system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483 # average overall miss latency | 811system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency 812system.cpu.l2cache.overall_avg_miss_latency::total 98970.973807 # average overall miss latency |
| 813system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 814system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 815system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 816system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 817system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 818system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.cpu.l2cache.writebacks::writebacks 1060156 # number of writebacks 820system.cpu.l2cache.writebacks::total 1060156 # number of writebacks --- 12 unchanged lines hidden (view full) --- 833system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251659 # number of ReadSharedReq MSHR misses 834system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251659 # number of ReadSharedReq MSHR misses 835system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses 836system.cpu.l2cache.demand_mshr_misses::cpu.data 2063982 # number of demand (read+write) MSHR misses 837system.cpu.l2cache.demand_mshr_misses::total 2064767 # number of demand (read+write) MSHR misses 838system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses 839system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses 840system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses | 813system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 814system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 815system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 816system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 817system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 818system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 819system.cpu.l2cache.writebacks::writebacks 1060156 # number of writebacks 820system.cpu.l2cache.writebacks::total 1060156 # number of writebacks --- 12 unchanged lines hidden (view full) --- 833system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251659 # number of ReadSharedReq MSHR misses 834system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251659 # number of ReadSharedReq MSHR misses 835system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses 836system.cpu.l2cache.demand_mshr_misses::cpu.data 2063982 # number of demand (read+write) MSHR misses 837system.cpu.l2cache.demand_mshr_misses::total 2064767 # number of demand (read+write) MSHR misses 838system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses 839system.cpu.l2cache.overall_mshr_misses::cpu.data 2063982 # number of overall MSHR misses 840system.cpu.l2cache.overall_mshr_misses::total 2064767 # number of overall MSHR misses |
| 841system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159329500 # number of ReadExReq MSHR miss cycles 842system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159329500 # number of ReadExReq MSHR miss cycles | 841system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159698500 # number of ReadExReq MSHR miss cycles 842system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159698500 # number of ReadExReq MSHR miss cycles |
| 843system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles 844system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles | 843system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 64478000 # number of ReadCleanReq MSHR miss cycles 844system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 64478000 # number of ReadCleanReq MSHR miss cycles |
| 845system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000 # number of ReadSharedReq MSHR miss cycles 846system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000 # number of ReadSharedReq MSHR miss cycles | 845system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113480200500 # number of ReadSharedReq MSHR miss cycles 846system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113480200500 # number of ReadSharedReq MSHR miss cycles |
| 847system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles | 847system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 64478000 # number of demand (read+write) MSHR miss cycles |
| 848system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500 # number of demand (read+write) MSHR miss cycles 849system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500 # number of demand (read+write) MSHR miss cycles | 848system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183639899000 # number of demand (read+write) MSHR miss cycles 849system.cpu.l2cache.demand_mshr_miss_latency::total 183704377000 # number of demand (read+write) MSHR miss cycles |
| 850system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles | 850system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 64478000 # number of overall MSHR miss cycles |
| 851system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500 # number of overall MSHR miss cycles 852system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500 # number of overall MSHR miss cycles | 851system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183639899000 # number of overall MSHR miss cycles 852system.cpu.l2cache.overall_mshr_miss_latency::total 183704377000 # number of overall MSHR miss cycles |
| 853system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 854system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 855system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses 856system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429611 # mshr miss rate for ReadExReq accesses 857system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses 858system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses 859system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses 860system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses 861system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses 862system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for demand accesses 863system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 # mshr miss rate for demand accesses 864system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses 865system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses 866system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses | 853system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 854system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 855system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429611 # mshr miss rate for ReadExReq accesses 856system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429611 # mshr miss rate for ReadExReq accesses 857system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses 858system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses 859system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses 860system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses 861system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses 862system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for demand accesses 863system.cpu.l2cache.demand_mshr_miss_rate::total 0.223822 # mshr miss rate for demand accesses 864system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses 865system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223757 # mshr miss rate for overall accesses 866system.cpu.l2cache.overall_mshr_miss_rate::total 0.223822 # mshr miss rate for overall accesses |
| 867system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102 # average ReadExReq mshr miss latency 868system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102 # average ReadExReq mshr miss latency | 867system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355 # average ReadExReq mshr miss latency 868system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355 # average ReadExReq mshr miss latency |
| 869system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency 870system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency | 869system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 82137.579618 # average ReadCleanReq mshr miss latency 870system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 82137.579618 # average ReadCleanReq mshr miss latency |
| 871system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415 # average ReadSharedReq mshr miss latency 872system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415 # average ReadSharedReq mshr miss latency | 871system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363 # average ReadSharedReq mshr miss latency 872system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363 # average ReadSharedReq mshr miss latency |
| 873system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency | 873system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency |
| 874system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency 875system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency | 874system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency 875system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency |
| 876system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency | 876system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 82137.579618 # average overall mshr miss latency |
| 877system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency 878system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency | 877system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency 878system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency |
| 879system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. 880system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. 881system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 882system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. 883system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 884system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 879system.cpu.toL2Bus.snoop_filter.tot_requests 18445165 # Total number of requests made to the snoop filter. 880system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220152 # Number of requests hitting in the snoop filter with a single holder of the requested data. 881system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 882system.cpu.toL2Bus.snoop_filter.tot_snoops 1444 # Total number of snoops made to the snoop filter. 883system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1438 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 884system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 885system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 885system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 886system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution 887system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution 888system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::ReadExReq 1890834 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::ReadExResp 1890834 # Transaction distribution 892system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution 893system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333369 # Transaction distribution --- 23 unchanged lines hidden (view full) --- 917system.cpu.toL2Bus.respLayer1.occupancy 13836307494 # Layer occupancy (ticks) 918system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 919system.membus.snoop_filter.tot_requests 4095872 # Total number of requests made to the snoop filter. 920system.membus.snoop_filter.hit_single_requests 2031262 # Number of requests hitting in the snoop filter with a single holder of the requested data. 921system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 922system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 923system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 924system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 886system.cpu.toL2Bus.trans_dist::ReadResp 7334191 # Transaction distribution 887system.cpu.toL2Bus.trans_dist::WritebackDirty 4730211 # Transaction distribution 888system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution 889system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution 890system.cpu.toL2Bus.trans_dist::ReadExReq 1890834 # Transaction distribution 891system.cpu.toL2Bus.trans_dist::ReadExResp 1890834 # Transaction distribution 892system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution 893system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333369 # Transaction distribution --- 23 unchanged lines hidden (view full) --- 917system.cpu.toL2Bus.respLayer1.occupancy 13836307494 # Layer occupancy (ticks) 918system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 919system.membus.snoop_filter.tot_requests 4095872 # Total number of requests made to the snoop filter. 920system.membus.snoop_filter.hit_single_requests 2031262 # Number of requests hitting in the snoop filter with a single holder of the requested data. 921system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 922system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 923system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 924system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 925system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states | 925system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states |
| 926system.membus.trans_dist::ReadResp 1252444 # Transaction distribution 927system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution 928system.membus.trans_dist::CleanEvict 970949 # Transaction distribution 929system.membus.trans_dist::ReadExReq 812323 # Transaction distribution 930system.membus.trans_dist::ReadExResp 812323 # Transaction distribution 931system.membus.trans_dist::ReadSharedReq 1252444 # Transaction distribution 932system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160639 # Packet count per connected master and slave (bytes) 933system.membus.pkt_count::total 6160639 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 940system.membus.snoop_fanout::stdev 0 # Request fanout histogram 941system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 942system.membus.snoop_fanout::0 2064767 100.00% 100.00% # Request fanout histogram 943system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 944system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 945system.membus.snoop_fanout::min_value 0 # Request fanout histogram 946system.membus.snoop_fanout::max_value 0 # Request fanout histogram 947system.membus.snoop_fanout::total 2064767 # Request fanout histogram | 926system.membus.trans_dist::ReadResp 1252444 # Transaction distribution 927system.membus.trans_dist::WritebackDirty 1060156 # Transaction distribution 928system.membus.trans_dist::CleanEvict 970949 # Transaction distribution 929system.membus.trans_dist::ReadExReq 812323 # Transaction distribution 930system.membus.trans_dist::ReadExResp 812323 # Transaction distribution 931system.membus.trans_dist::ReadSharedReq 1252444 # Transaction distribution 932system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160639 # Packet count per connected master and slave (bytes) 933system.membus.pkt_count::total 6160639 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 940system.membus.snoop_fanout::stdev 0 # Request fanout histogram 941system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 942system.membus.snoop_fanout::0 2064767 100.00% 100.00% # Request fanout histogram 943system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 944system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 945system.membus.snoop_fanout::min_value 0 # Request fanout histogram 946system.membus.snoop_fanout::max_value 0 # Request fanout histogram 947system.membus.snoop_fanout::total 2064767 # Request fanout histogram |
| 948system.membus.reqLayer0.occupancy 8804910500 # Layer occupancy (ticks) | 948system.membus.reqLayer0.occupancy 8804919500 # Layer occupancy (ticks) |
| 949system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) | 949system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) |
| 950system.membus.respLayer1.occupancy 11285155750 # Layer occupancy (ticks) | 950system.membus.respLayer1.occupancy 11285149250 # Layer occupancy (ticks) |
| 951system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 952 953---------- End Simulation Statistics ---------- | 951system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 952 953---------- End Simulation Statistics ---------- |