| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.128034 # Number of seconds simulated 4sim_ticks 1128033563500 # Number of ticks simulated 5final_tick 1128033563500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.130744 # Number of seconds simulated 4sim_ticks 1130744162500 # Number of ticks simulated 5final_tick 1130744162500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 296898 # Simulator instruction rate (inst/s) 8host_op_rate 319862 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 216832014 # Simulator tick rate (ticks/s) 10host_mem_usage 266856 # Number of bytes of host memory used 11host_seconds 5202.34 # Real time elapsed on the host | 7host_inst_rate 210155 # Simulator instruction rate (inst/s) 8host_op_rate 226410 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 153850224 # Simulator tick rate (ticks/s) 10host_mem_usage 274312 # Number of bytes of host memory used 11host_seconds 7349.64 # Real time elapsed on the host |
| 12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 130888128 # Number of bytes read from this memory 19system.physmem.bytes_read::total 130938240 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 67194432 # Number of bytes written to this memory 23system.physmem.bytes_written::total 67194432 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 2045127 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 2045910 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 1049913 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 1049913 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 44424 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 116032122 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 116076546 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 44424 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 44424 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 59567759 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 59567759 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 59567759 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 44424 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 116032122 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 175644306 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 2045910 # Number of read requests accepted 41system.physmem.writeReqs 1049913 # Number of write requests accepted 42system.physmem.readBursts 2045910 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 1049913 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 130851840 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 86400 # Total number of bytes read from write queue 46system.physmem.bytesWritten 67192960 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 130938240 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 67194432 # Total written bytes from the system interface side 49system.physmem.servicedByWrQ 1350 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 50240 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 132094976 # Number of bytes read from this memory 19system.physmem.bytes_read::total 132145216 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 50240 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 50240 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 67850112 # Number of bytes written to this memory 23system.physmem.bytes_written::total 67850112 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 785 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 2063984 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 2064769 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 1060158 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 1060158 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 44431 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 116821276 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 116865707 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 44431 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 44431 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 60004831 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 60004831 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 60004831 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 44431 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 116821276 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 176870538 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 2064769 # Number of read requests accepted 41system.physmem.writeReqs 1060158 # Number of write requests accepted 42system.physmem.readBursts 2064769 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 1060158 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 132060352 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 84864 # Total number of bytes read from write queue 46system.physmem.bytesWritten 67848640 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 132145216 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 67850112 # Total written bytes from the system interface side 49system.physmem.servicedByWrQ 1326 # Number of DRAM read bursts serviced by the write queue |
| 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 52system.physmem.perBankRdBursts::0 127234 # Per bank write bursts 53system.physmem.perBankRdBursts::1 124635 # Per bank write bursts 54system.physmem.perBankRdBursts::2 121565 # Per bank write bursts 55system.physmem.perBankRdBursts::3 123578 # Per bank write bursts 56system.physmem.perBankRdBursts::4 122544 # Per bank write bursts 57system.physmem.perBankRdBursts::5 122632 # Per bank write bursts 58system.physmem.perBankRdBursts::6 123221 # Per bank write bursts 59system.physmem.perBankRdBursts::7 123735 # Per bank write bursts 60system.physmem.perBankRdBursts::8 131340 # Per bank write bursts 61system.physmem.perBankRdBursts::9 133478 # Per bank write bursts 62system.physmem.perBankRdBursts::10 132036 # Per bank write bursts 63system.physmem.perBankRdBursts::11 133242 # Per bank write bursts 64system.physmem.perBankRdBursts::12 133211 # Per bank write bursts 65system.physmem.perBankRdBursts::13 133326 # Per bank write bursts 66system.physmem.perBankRdBursts::14 129274 # Per bank write bursts 67system.physmem.perBankRdBursts::15 129509 # Per bank write bursts 68system.physmem.perBankWrBursts::0 66120 # Per bank write bursts 69system.physmem.perBankWrBursts::1 64398 # Per bank write bursts 70system.physmem.perBankWrBursts::2 62563 # Per bank write bursts 71system.physmem.perBankWrBursts::3 62980 # Per bank write bursts 72system.physmem.perBankWrBursts::4 62981 # Per bank write bursts 73system.physmem.perBankWrBursts::5 63086 # Per bank write bursts 74system.physmem.perBankWrBursts::6 64437 # Per bank write bursts 75system.physmem.perBankWrBursts::7 65431 # Per bank write bursts 76system.physmem.perBankWrBursts::8 67296 # Per bank write bursts 77system.physmem.perBankWrBursts::9 67792 # Per bank write bursts 78system.physmem.perBankWrBursts::10 67535 # Per bank write bursts 79system.physmem.perBankWrBursts::11 67858 # Per bank write bursts 80system.physmem.perBankWrBursts::12 67312 # Per bank write bursts 81system.physmem.perBankWrBursts::13 67784 # Per bank write bursts 82system.physmem.perBankWrBursts::14 66474 # Per bank write bursts 83system.physmem.perBankWrBursts::15 65843 # Per bank write bursts | 52system.physmem.perBankRdBursts::0 128520 # Per bank write bursts 53system.physmem.perBankRdBursts::1 125806 # Per bank write bursts 54system.physmem.perBankRdBursts::2 122672 # Per bank write bursts 55system.physmem.perBankRdBursts::3 124571 # Per bank write bursts 56system.physmem.perBankRdBursts::4 123572 # Per bank write bursts 57system.physmem.perBankRdBursts::5 123679 # Per bank write bursts 58system.physmem.perBankRdBursts::6 124365 # Per bank write bursts 59system.physmem.perBankRdBursts::7 124958 # Per bank write bursts 60system.physmem.perBankRdBursts::8 132489 # Per bank write bursts 61system.physmem.perBankRdBursts::9 134780 # Per bank write bursts 62system.physmem.perBankRdBursts::10 133233 # Per bank write bursts 63system.physmem.perBankRdBursts::11 134506 # Per bank write bursts 64system.physmem.perBankRdBursts::12 134518 # Per bank write bursts 65system.physmem.perBankRdBursts::13 134594 # Per bank write bursts 66system.physmem.perBankRdBursts::14 130540 # Per bank write bursts 67system.physmem.perBankRdBursts::15 130640 # Per bank write bursts 68system.physmem.perBankWrBursts::0 66781 # Per bank write bursts 69system.physmem.perBankWrBursts::1 64941 # Per bank write bursts 70system.physmem.perBankWrBursts::2 63173 # Per bank write bursts 71system.physmem.perBankWrBursts::3 63584 # Per bank write bursts 72system.physmem.perBankWrBursts::4 63558 # Per bank write bursts 73system.physmem.perBankWrBursts::5 63644 # Per bank write bursts 74system.physmem.perBankWrBursts::6 65047 # Per bank write bursts 75system.physmem.perBankWrBursts::7 66055 # Per bank write bursts 76system.physmem.perBankWrBursts::8 67972 # Per bank write bursts 77system.physmem.perBankWrBursts::9 68438 # Per bank write bursts 78system.physmem.perBankWrBursts::10 68161 # Per bank write bursts 79system.physmem.perBankWrBursts::11 68586 # Per bank write bursts 80system.physmem.perBankWrBursts::12 68040 # Per bank write bursts 81system.physmem.perBankWrBursts::13 68530 # Per bank write bursts 82system.physmem.perBankWrBursts::14 67159 # Per bank write bursts 83system.physmem.perBankWrBursts::15 66466 # Per bank write bursts |
| 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 86system.physmem.totGap 1128033469500 # Total gap between requests | 86system.physmem.totGap 1130744067500 # Total gap between requests |
| 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) | 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 93system.physmem.readPktSize::6 2045910 # Read request sizes (log2) | 93system.physmem.readPktSize::6 2064769 # Read request sizes (log2) |
| 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) | 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 100system.physmem.writePktSize::6 1049913 # Write request sizes (log2) 101system.physmem.rdQLenPdf::0 1917702 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 126844 # What read queue length does an incoming req see | 100system.physmem.writePktSize::6 1060158 # Write request sizes (log2) 101system.physmem.rdQLenPdf::0 1931837 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 131592 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 103system.physmem.rdQLenPdf::2 14 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::15 32849 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 34013 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 57015 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 61217 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 61623 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 61654 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 61600 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 61647 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 61568 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 61682 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 61684 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 62149 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 62542 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 61998 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 62533 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 61281 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 61114 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::15 32506 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 33515 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 57459 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 62386 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 62542 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 62618 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 62533 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 62474 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 62468 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 62484 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 62514 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 62444 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 62521 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 62600 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 62677 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 62255 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 62124 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 61991 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 32 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 197system.physmem.bytesPerActivate::samples 1910047 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 103.685692 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 81.827100 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 125.490486 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 1485463 77.77% 77.77% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 305174 15.98% 93.75% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 52509 2.75% 96.50% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 20929 1.10% 97.59% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 13256 0.69% 98.29% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 7619 0.40% 98.69% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 5519 0.29% 98.97% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 5102 0.27% 99.24% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 14476 0.76% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 1910047 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 61113 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 33.412400 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 159.518866 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 61065 99.92% 99.92% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::1024-2047 24 0.04% 99.96% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes | 197system.physmem.bytesPerActivate::samples 1925169 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 103.839212 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 81.850367 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 126.421931 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 1496084 77.71% 77.71% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 309482 16.08% 93.79% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 52255 2.71% 96.50% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 20716 1.08% 97.58% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 12793 0.66% 98.24% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 7748 0.40% 98.64% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 5753 0.30% 98.94% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 5054 0.26% 99.21% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 15284 0.79% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 1925169 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 61990 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 33.244314 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 23.928422 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 148.698604 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 61952 99.94% 99.94% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::1024-2047 16 0.03% 99.96% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::2048-3071 7 0.01% 99.98% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.98% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::4096-5119 5 0.01% 99.99% # Reads before turning the bus around for writes |
| 219system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes | 220system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes |
| 220system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes | 221system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 221system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes | 222system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 222system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes 223system.physmem.rdPerTurnAround::total 61113 # Reads before turning the bus around for writes 224system.physmem.wrPerTurnAround::samples 61113 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::mean 17.179487 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::gmean 17.144319 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::stdev 1.100540 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::16 26981 44.15% 44.15% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::17 1028 1.68% 45.83% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::18 28814 47.15% 92.98% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::19 3825 6.26% 99.24% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::20 400 0.65% 99.89% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::21 47 0.08% 99.97% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::22 11 0.02% 99.99% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::23 6 0.01% 100.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads 237system.physmem.wrPerTurnAround::total 61113 # Writes before turning the bus around for reads 238system.physmem.totQLat 38097515250 # Total ticks spent queuing 239system.physmem.totMemAccLat 76433015250 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 10222800000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 18633.60 # Average queueing delay per DRAM burst | 223system.physmem.rdPerTurnAround::17408-18431 1 0.00% 100.00% # Reads before turning the bus around for writes 224system.physmem.rdPerTurnAround::total 61990 # Reads before turning the bus around for writes 225system.physmem.wrPerTurnAround::samples 61990 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::mean 17.101710 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::gmean 17.070337 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::stdev 1.034747 # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::16 28322 45.69% 45.69% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::17 1015 1.64% 47.33% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::18 30732 49.58% 96.90% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::19 1873 3.02% 99.92% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::20 43 0.07% 99.99% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::21 5 0.01% 100.00% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::total 61990 # Writes before turning the bus around for reads 236system.physmem.totQLat 38536102500 # Total ticks spent queuing 237system.physmem.totMemAccLat 77225658750 # Total ticks spent from burst creation until serviced by the DRAM 238system.physmem.totBusLat 10317215000 # Total ticks spent in databus transfers 239system.physmem.avgQLat 18675.63 # Average queueing delay per DRAM burst |
| 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 240system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 243system.physmem.avgMemAccLat 37383.60 # Average memory access latency per DRAM burst 244system.physmem.avgRdBW 116.00 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 59.57 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 116.08 # Average system read bandwidth in MiByte/s 247system.physmem.avgWrBWSys 59.57 # Average system write bandwidth in MiByte/s | 241system.physmem.avgMemAccLat 37425.63 # Average memory access latency per DRAM burst 242system.physmem.avgRdBW 116.79 # Average DRAM read bandwidth in MiByte/s 243system.physmem.avgWrBW 60.00 # Average achieved write bandwidth in MiByte/s 244system.physmem.avgRdBWSys 116.87 # Average system read bandwidth in MiByte/s 245system.physmem.avgWrBWSys 60.00 # Average system write bandwidth in MiByte/s |
| 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 246system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 249system.physmem.busUtil 1.37 # Data bus utilization in percentage | 247system.physmem.busUtil 1.38 # Data bus utilization in percentage |
| 250system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing | 248system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads 249system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes 250system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing |
| 253system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing 254system.physmem.readRowHits 772369 # Number of row buffer hits during reads 255system.physmem.writeRowHits 412032 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 37.78 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 39.24 # Row buffer hit rate for writes 258system.physmem.avgGap 364372.73 # Average gap between requests 259system.physmem.pageHitRate 38.27 # Row buffer hit rate, read and write combined 260system.physmem_0.actEnergy 7040703600 # Energy for activate commands per rank (pJ) 261system.physmem_0.preEnergy 3841653750 # Energy for precharge commands per rank (pJ) 262system.physmem_0.readEnergy 7715315400 # Energy for read commands per rank (pJ) 263system.physmem_0.writeEnergy 3317734080 # Energy for write commands per rank (pJ) 264system.physmem_0.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ) 265system.physmem_0.actBackEnergy 423036881190 # Energy for active background per rank (pJ) 266system.physmem_0.preBackEnergy 305734953750 # Energy for precharge background per rank (pJ) 267system.physmem_0.totalEnergy 824364871770 # Total energy per rank (pJ) 268system.physmem_0.averagePower 730.798394 # Core power per rank (mW) 269system.physmem_0.memoryStateTime::IDLE 505893058250 # Time in different power states 270system.physmem_0.memoryStateTime::REF 37667500000 # Time in different power states | 251system.physmem.avgWrQLen 25.42 # Average write queue length when enqueuing 252system.physmem.readRowHits 775929 # Number of row buffer hits during reads 253system.physmem.writeRowHits 422476 # Number of row buffer hits during writes 254system.physmem.readRowHitRate 37.60 # Row buffer hit rate for reads 255system.physmem.writeRowHitRate 39.85 # Row buffer hit rate for writes 256system.physmem.avgGap 361846.55 # Average gap between requests 257system.physmem.pageHitRate 38.37 # Row buffer hit rate, read and write combined 258system.physmem_0.actEnergy 7091695800 # Energy for activate commands per rank (pJ) 259system.physmem_0.preEnergy 3869476875 # Energy for precharge commands per rank (pJ) 260system.physmem_0.readEnergy 7785421800 # Energy for read commands per rank (pJ) 261system.physmem_0.writeEnergy 3348753840 # Energy for write commands per rank (pJ) 262system.physmem_0.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) 263system.physmem_0.actBackEnergy 423921506085 # Energy for active background per rank (pJ) 264system.physmem_0.preBackEnergy 306584736000 # Energy for precharge background per rank (pJ) 265system.physmem_0.totalEnergy 826456199280 # Total energy per rank (pJ) 266system.physmem_0.averagePower 730.896688 # Core power per rank (mW) 267system.physmem_0.memoryStateTime::IDLE 507283799000 # Time in different power states 268system.physmem_0.memoryStateTime::REF 37757980000 # Time in different power states |
| 271system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 269system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 272system.physmem_0.memoryStateTime::ACT 584472684250 # Time in different power states | 270system.physmem_0.memoryStateTime::ACT 585701078500 # Time in different power states |
| 273system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 271system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 274system.physmem_1.actEnergy 7399251720 # Energy for activate commands per rank (pJ) 275system.physmem_1.preEnergy 4037290125 # Energy for precharge commands per rank (pJ) 276system.physmem_1.readEnergy 8232221400 # Energy for read commands per rank (pJ) 277system.physmem_1.writeEnergy 3485553120 # Energy for write commands per rank (pJ) 278system.physmem_1.refreshEnergy 73677630000 # Energy for refresh commands per rank (pJ) 279system.physmem_1.actBackEnergy 432494110575 # Energy for active background per rank (pJ) 280system.physmem_1.preBackEnergy 297439138500 # Energy for precharge background per rank (pJ) 281system.physmem_1.totalEnergy 826765195440 # Total energy per rank (pJ) 282system.physmem_1.averagePower 732.926278 # Core power per rank (mW) 283system.physmem_1.memoryStateTime::IDLE 492041493250 # Time in different power states 284system.physmem_1.memoryStateTime::REF 37667500000 # Time in different power states | 272system.physmem_1.actEnergy 7462581840 # Energy for activate commands per rank (pJ) 273system.physmem_1.preEnergy 4071845250 # Energy for precharge commands per rank (pJ) 274system.physmem_1.readEnergy 8309316600 # Energy for read commands per rank (pJ) 275system.physmem_1.writeEnergy 3520920960 # Energy for write commands per rank (pJ) 276system.physmem_1.refreshEnergy 73854608880 # Energy for refresh commands per rank (pJ) 277system.physmem_1.actBackEnergy 432965070225 # Energy for active background per rank (pJ) 278system.physmem_1.preBackEnergy 298651785000 # Energy for precharge background per rank (pJ) 279system.physmem_1.totalEnergy 828836128755 # Total energy per rank (pJ) 280system.physmem_1.averagePower 733.001436 # Core power per rank (mW) 281system.physmem_1.memoryStateTime::IDLE 494051909000 # Time in different power states 282system.physmem_1.memoryStateTime::REF 37757980000 # Time in different power states |
| 285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 283system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 286system.physmem_1.memoryStateTime::ACT 598324400250 # Time in different power states | 284system.physmem_1.memoryStateTime::ACT 598934101500 # Time in different power states |
| 287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 285system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 288system.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states 289system.cpu.branchPred.lookups 240019627 # Number of BP lookups 290system.cpu.branchPred.condPredicted 186610234 # Number of conditional branches predicted | 286system.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 287system.cpu.branchPred.lookups 240019432 # Number of BP lookups 288system.cpu.branchPred.condPredicted 186610009 # Number of conditional branches predicted |
| 291system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect | 289system.cpu.branchPred.condIncorrect 14528957 # Number of conditional branches incorrect |
| 292system.cpu.branchPred.BTBLookups 131647639 # Number of BTB lookups 293system.cpu.branchPred.BTBHits 122324320 # Number of BTB hits | 290system.cpu.branchPred.BTBLookups 131647101 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 122324380 # Number of BTB hits |
| 294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 295system.cpu.branchPred.BTBHitPct 92.917975 # BTB Hit Percentage 296system.cpu.branchPred.usedRAS 15657430 # Number of times the RAS was used to get a target. | 293system.cpu.branchPred.BTBHitPct 92.918400 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 15657431 # Number of times the RAS was used to get a target. |
| 297system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. | 295system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. |
| 298system.cpu.branchPred.indirectLookups 534 # Number of indirect predictor lookups. | 296system.cpu.branchPred.indirectLookups 535 # Number of indirect predictor lookups. |
| 299system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. | 297system.cpu.branchPred.indirectHits 232 # Number of indirect target hits. |
| 300system.cpu.branchPred.indirectMisses 302 # Number of indirect misses. | 298system.cpu.branchPred.indirectMisses 303 # Number of indirect misses. |
| 301system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. 302system.cpu_clk_domain.clock 500 # Clock period in ticks | 299system.cpu.branchPredindirectMispredicted 162 # Number of mispredicted indirect branches. 300system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 303system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states | 301system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states |
| 304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 302system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 323system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 324system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 325system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 326system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 327system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 328system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 329system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 330system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 333system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states | 331system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states |
| 334system.cpu.dtb.walker.walks 0 # Table walker walks requested 335system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.dtb.read_accesses 0 # DTB read accesses 358system.cpu.dtb.write_accesses 0 # DTB write accesses 359system.cpu.dtb.inst_accesses 0 # ITB inst accesses 360system.cpu.dtb.hits 0 # DTB hits 361system.cpu.dtb.misses 0 # DTB misses 362system.cpu.dtb.accesses 0 # DTB accesses | 332system.cpu.dtb.walker.walks 0 # Table walker walks requested 333system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 353system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 354system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 355system.cpu.dtb.read_accesses 0 # DTB read accesses 356system.cpu.dtb.write_accesses 0 # DTB write accesses 357system.cpu.dtb.inst_accesses 0 # ITB inst accesses 358system.cpu.dtb.hits 0 # DTB hits 359system.cpu.dtb.misses 0 # DTB misses 360system.cpu.dtb.accesses 0 # DTB accesses |
| 363system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states | 361system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states |
| 364system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 385system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 386system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 388system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 389system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 390system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 391system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 392system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 362system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 383system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 384system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 385system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 386system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 387system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 388system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 389system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 390system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 393system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states | 391system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states |
| 394system.cpu.itb.walker.walks 0 # Table walker walks requested 395system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 416system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu.itb.read_accesses 0 # DTB read accesses 418system.cpu.itb.write_accesses 0 # DTB write accesses 419system.cpu.itb.inst_accesses 0 # ITB inst accesses 420system.cpu.itb.hits 0 # DTB hits 421system.cpu.itb.misses 0 # DTB misses 422system.cpu.itb.accesses 0 # DTB accesses 423system.cpu.workload.num_syscalls 46 # Number of system calls | 392system.cpu.itb.walker.walks 0 # Table walker walks requested 393system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 414system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 415system.cpu.itb.read_accesses 0 # DTB read accesses 416system.cpu.itb.write_accesses 0 # DTB write accesses 417system.cpu.itb.inst_accesses 0 # ITB inst accesses 418system.cpu.itb.hits 0 # DTB hits 419system.cpu.itb.misses 0 # DTB misses 420system.cpu.itb.accesses 0 # DTB accesses 421system.cpu.workload.num_syscalls 46 # Number of system calls |
| 424system.cpu.pwrStateResidencyTicks::ON 1128033563500 # Cumulative time (in ticks) in various power states 425system.cpu.numCycles 2256067127 # number of cpu cycles simulated | 422system.cpu.pwrStateResidencyTicks::ON 1130744162500 # Cumulative time (in ticks) in various power states 423system.cpu.numCycles 2261488325 # number of cpu cycles simulated |
| 426system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 427system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 428system.cpu.committedInsts 1544563088 # Number of instructions committed 429system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed | 424system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 425system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 426system.cpu.committedInsts 1544563088 # Number of instructions committed 427system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed |
| 430system.cpu.discardedOps 41363716 # Number of ops (including micro ops) which were discarded before commit | 428system.cpu.discardedOps 41363718 # Number of ops (including micro ops) which were discarded before commit |
| 431system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 429system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 432system.cpu.cpi 1.460651 # CPI: cycles per instruction 433system.cpu.ipc 0.684626 # IPC: instructions per cycle | 430system.cpu.cpi 1.464161 # CPI: cycles per instruction 431system.cpu.ipc 0.682985 # IPC: instructions per cycle |
| 434system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 435system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction 436system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 437system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 438system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 439system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 440system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 441system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 461system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 462system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 463system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 464system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 465system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction 466system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 467system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 468system.cpu.op_class_0::total 1664032481 # Class of committed instruction | 432system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 433system.cpu.op_class_0::IntAlu 1030178776 61.91% 61.91% # Class of committed instruction 434system.cpu.op_class_0::IntMult 700322 0.04% 61.95% # Class of committed instruction 435system.cpu.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction 436system.cpu.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction 437system.cpu.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction 438system.cpu.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction 439system.cpu.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 459system.cpu.op_class_0::SimdFloatMult 0 0.00% 61.95% # Class of committed instruction 460system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 61.95% # Class of committed instruction 461system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 462system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 463system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction 464system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 465system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 466system.cpu.op_class_0::total 1664032481 # Class of committed instruction |
| 469system.cpu.tickCycles 1844612574 # Number of cycles that the object actually ticked 470system.cpu.idleCycles 411454553 # Total number of cycles that the object has spent stopped 471system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states 472system.cpu.dcache.tags.replacements 9220101 # number of replacements 473system.cpu.dcache.tags.tagsinuse 4085.702912 # Cycle average of tags in use 474system.cpu.dcache.tags.total_refs 624495427 # Total number of references to valid blocks. 475system.cpu.dcache.tags.sampled_refs 9224197 # Sample count of references to valid blocks. 476system.cpu.dcache.tags.avg_refs 67.701874 # Average number of references to valid blocks. 477system.cpu.dcache.tags.warmup_cycle 9818932500 # Cycle when the warmup percentage was hit. 478system.cpu.dcache.tags.occ_blocks::cpu.data 4085.702912 # Average occupied blocks per requestor 479system.cpu.dcache.tags.occ_percent::cpu.data 0.997486 # Average percentage of cache occupancy 480system.cpu.dcache.tags.occ_percent::total 0.997486 # Average percentage of cache occupancy | 467system.cpu.tickCycles 1844743027 # Number of cycles that the object actually ticked 468system.cpu.idleCycles 416745298 # Total number of cycles that the object has spent stopped 469system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 470system.cpu.dcache.tags.replacements 9220102 # number of replacements 471system.cpu.dcache.tags.tagsinuse 4085.712457 # Cycle average of tags in use 472system.cpu.dcache.tags.total_refs 624495296 # Total number of references to valid blocks. 473system.cpu.dcache.tags.sampled_refs 9224198 # Sample count of references to valid blocks. 474system.cpu.dcache.tags.avg_refs 67.701853 # Average number of references to valid blocks. 475system.cpu.dcache.tags.warmup_cycle 9823555500 # Cycle when the warmup percentage was hit. 476system.cpu.dcache.tags.occ_blocks::cpu.data 4085.712457 # Average occupied blocks per requestor 477system.cpu.dcache.tags.occ_percent::cpu.data 0.997488 # Average percentage of cache occupancy 478system.cpu.dcache.tags.occ_percent::total 0.997488 # Average percentage of cache occupancy |
| 481system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 479system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 482system.cpu.dcache.tags.age_task_id_blocks_1024::0 241 # Occupied blocks per task id 483system.cpu.dcache.tags.age_task_id_blocks_1024::1 1240 # Occupied blocks per task id 484system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id 485system.cpu.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id | 480system.cpu.dcache.tags.age_task_id_blocks_1024::0 239 # Occupied blocks per task id 481system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id 482system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id 483system.cpu.dcache.tags.age_task_id_blocks_1024::3 63 # Occupied blocks per task id |
| 486system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 484system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 487system.cpu.dcache.tags.tag_accesses 1277391791 # Number of tag accesses 488system.cpu.dcache.tags.data_accesses 1277391791 # Number of data accesses 489system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states 490system.cpu.dcache.ReadReq_hits::cpu.data 454164210 # number of ReadReq hits 491system.cpu.dcache.ReadReq_hits::total 454164210 # number of ReadReq hits 492system.cpu.dcache.WriteReq_hits::cpu.data 170331094 # number of WriteReq hits 493system.cpu.dcache.WriteReq_hits::total 170331094 # number of WriteReq hits | 485system.cpu.dcache.tags.tag_accesses 1277391740 # Number of tag accesses 486system.cpu.dcache.tags.data_accesses 1277391740 # Number of data accesses 487system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 488system.cpu.dcache.ReadReq_hits::cpu.data 454164183 # number of ReadReq hits 489system.cpu.dcache.ReadReq_hits::total 454164183 # number of ReadReq hits 490system.cpu.dcache.WriteReq_hits::cpu.data 170330990 # number of WriteReq hits 491system.cpu.dcache.WriteReq_hits::total 170330990 # number of WriteReq hits |
| 494system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 495system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 496system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 497system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 498system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 499system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits | 492system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 493system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 494system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 495system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 496system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 497system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits |
| 500system.cpu.dcache.demand_hits::cpu.data 624495304 # number of demand (read+write) hits 501system.cpu.dcache.demand_hits::total 624495304 # number of demand (read+write) hits 502system.cpu.dcache.overall_hits::cpu.data 624495305 # number of overall hits 503system.cpu.dcache.overall_hits::total 624495305 # number of overall hits 504system.cpu.dcache.ReadReq_misses::cpu.data 7333415 # number of ReadReq misses 505system.cpu.dcache.ReadReq_misses::total 7333415 # number of ReadReq misses 506system.cpu.dcache.WriteReq_misses::cpu.data 2254953 # number of WriteReq misses 507system.cpu.dcache.WriteReq_misses::total 2254953 # number of WriteReq misses | 498system.cpu.dcache.demand_hits::cpu.data 624495173 # number of demand (read+write) hits 499system.cpu.dcache.demand_hits::total 624495173 # number of demand (read+write) hits 500system.cpu.dcache.overall_hits::cpu.data 624495174 # number of overall hits 501system.cpu.dcache.overall_hits::total 624495174 # number of overall hits 502system.cpu.dcache.ReadReq_misses::cpu.data 7333416 # number of ReadReq misses 503system.cpu.dcache.ReadReq_misses::total 7333416 # number of ReadReq misses 504system.cpu.dcache.WriteReq_misses::cpu.data 2255057 # number of WriteReq misses 505system.cpu.dcache.WriteReq_misses::total 2255057 # number of WriteReq misses |
| 508system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 509system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses | 506system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 507system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses |
| 510system.cpu.dcache.demand_misses::cpu.data 9588368 # number of demand (read+write) misses 511system.cpu.dcache.demand_misses::total 9588368 # number of demand (read+write) misses 512system.cpu.dcache.overall_misses::cpu.data 9588370 # number of overall misses 513system.cpu.dcache.overall_misses::total 9588370 # number of overall misses 514system.cpu.dcache.ReadReq_miss_latency::cpu.data 190988166000 # number of ReadReq miss cycles 515system.cpu.dcache.ReadReq_miss_latency::total 190988166000 # number of ReadReq miss cycles 516system.cpu.dcache.WriteReq_miss_latency::cpu.data 108977258000 # number of WriteReq miss cycles 517system.cpu.dcache.WriteReq_miss_latency::total 108977258000 # number of WriteReq miss cycles 518system.cpu.dcache.demand_miss_latency::cpu.data 299965424000 # number of demand (read+write) miss cycles 519system.cpu.dcache.demand_miss_latency::total 299965424000 # number of demand (read+write) miss cycles 520system.cpu.dcache.overall_miss_latency::cpu.data 299965424000 # number of overall miss cycles 521system.cpu.dcache.overall_miss_latency::total 299965424000 # number of overall miss cycles 522system.cpu.dcache.ReadReq_accesses::cpu.data 461497625 # number of ReadReq accesses(hits+misses) 523system.cpu.dcache.ReadReq_accesses::total 461497625 # number of ReadReq accesses(hits+misses) | 508system.cpu.dcache.demand_misses::cpu.data 9588473 # number of demand (read+write) misses 509system.cpu.dcache.demand_misses::total 9588473 # number of demand (read+write) misses 510system.cpu.dcache.overall_misses::cpu.data 9588475 # number of overall misses 511system.cpu.dcache.overall_misses::total 9588475 # number of overall misses 512system.cpu.dcache.ReadReq_miss_latency::cpu.data 192638967000 # number of ReadReq miss cycles 513system.cpu.dcache.ReadReq_miss_latency::total 192638967000 # number of ReadReq miss cycles 514system.cpu.dcache.WriteReq_miss_latency::cpu.data 111261397000 # number of WriteReq miss cycles 515system.cpu.dcache.WriteReq_miss_latency::total 111261397000 # number of WriteReq miss cycles 516system.cpu.dcache.demand_miss_latency::cpu.data 303900364000 # number of demand (read+write) miss cycles 517system.cpu.dcache.demand_miss_latency::total 303900364000 # number of demand (read+write) miss cycles 518system.cpu.dcache.overall_miss_latency::cpu.data 303900364000 # number of overall miss cycles 519system.cpu.dcache.overall_miss_latency::total 303900364000 # number of overall miss cycles 520system.cpu.dcache.ReadReq_accesses::cpu.data 461497599 # number of ReadReq accesses(hits+misses) 521system.cpu.dcache.ReadReq_accesses::total 461497599 # number of ReadReq accesses(hits+misses) |
| 524system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 525system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 526system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) 527system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) 528system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 529system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 530system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 531system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) | 522system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 523system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 524system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) 525system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) 526system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 527system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 528system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 529system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) |
| 532system.cpu.dcache.demand_accesses::cpu.data 634083672 # number of demand (read+write) accesses 533system.cpu.dcache.demand_accesses::total 634083672 # number of demand (read+write) accesses 534system.cpu.dcache.overall_accesses::cpu.data 634083675 # number of overall (read+write) accesses 535system.cpu.dcache.overall_accesses::total 634083675 # number of overall (read+write) accesses | 530system.cpu.dcache.demand_accesses::cpu.data 634083646 # number of demand (read+write) accesses 531system.cpu.dcache.demand_accesses::total 634083646 # number of demand (read+write) accesses 532system.cpu.dcache.overall_accesses::cpu.data 634083649 # number of overall (read+write) accesses 533system.cpu.dcache.overall_accesses::total 634083649 # number of overall (read+write) accesses |
| 536system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses 537system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses 538system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses 539system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses 540system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses 541system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses 542system.cpu.dcache.demand_miss_rate::cpu.data 0.015122 # miss rate for demand accesses 543system.cpu.dcache.demand_miss_rate::total 0.015122 # miss rate for demand accesses 544system.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses 545system.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses | 534system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015890 # miss rate for ReadReq accesses 535system.cpu.dcache.ReadReq_miss_rate::total 0.015890 # miss rate for ReadReq accesses 536system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses 537system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses 538system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses 539system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses 540system.cpu.dcache.demand_miss_rate::cpu.data 0.015122 # miss rate for demand accesses 541system.cpu.dcache.demand_miss_rate::total 0.015122 # miss rate for demand accesses 542system.cpu.dcache.overall_miss_rate::cpu.data 0.015122 # miss rate for overall accesses 543system.cpu.dcache.overall_miss_rate::total 0.015122 # miss rate for overall accesses |
| 546system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26043.550788 # average ReadReq miss latency 547system.cpu.dcache.ReadReq_avg_miss_latency::total 26043.550788 # average ReadReq miss latency 548system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48327.950960 # average WriteReq miss latency 549system.cpu.dcache.WriteReq_avg_miss_latency::total 48327.950960 # average WriteReq miss latency 550system.cpu.dcache.demand_avg_miss_latency::cpu.data 31284.304482 # average overall miss latency 551system.cpu.dcache.demand_avg_miss_latency::total 31284.304482 # average overall miss latency 552system.cpu.dcache.overall_avg_miss_latency::cpu.data 31284.297957 # average overall miss latency 553system.cpu.dcache.overall_avg_miss_latency::total 31284.297957 # average overall miss latency | 544system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26268.653926 # average ReadReq miss latency 545system.cpu.dcache.ReadReq_avg_miss_latency::total 26268.653926 # average ReadReq miss latency 546system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 49338.618492 # average WriteReq miss latency 547system.cpu.dcache.WriteReq_avg_miss_latency::total 49338.618492 # average WriteReq miss latency 548system.cpu.dcache.demand_avg_miss_latency::cpu.data 31694.344240 # average overall miss latency 549system.cpu.dcache.demand_avg_miss_latency::total 31694.344240 # average overall miss latency 550system.cpu.dcache.overall_avg_miss_latency::cpu.data 31694.337629 # average overall miss latency 551system.cpu.dcache.overall_avg_miss_latency::total 31694.337629 # average overall miss latency |
| 554system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 555system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 556system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 557system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 558system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 559system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 552system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 553system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 554system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 555system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 556system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 557system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 560system.cpu.dcache.writebacks::writebacks 3684499 # number of writebacks 561system.cpu.dcache.writebacks::total 3684499 # number of writebacks | 558system.cpu.dcache.writebacks::writebacks 3670051 # number of writebacks 559system.cpu.dcache.writebacks::total 3670051 # number of writebacks |
| 562system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 563system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits | 560system.cpu.dcache.ReadReq_mshr_hits::cpu.data 49 # number of ReadReq MSHR hits 561system.cpu.dcache.ReadReq_mshr_hits::total 49 # number of ReadReq MSHR hits |
| 564system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364123 # number of WriteReq MSHR hits 565system.cpu.dcache.WriteReq_mshr_hits::total 364123 # number of WriteReq MSHR hits 566system.cpu.dcache.demand_mshr_hits::cpu.data 364172 # number of demand (read+write) MSHR hits 567system.cpu.dcache.demand_mshr_hits::total 364172 # number of demand (read+write) MSHR hits 568system.cpu.dcache.overall_mshr_hits::cpu.data 364172 # number of overall MSHR hits 569system.cpu.dcache.overall_mshr_hits::total 364172 # number of overall MSHR hits 570system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333366 # number of ReadReq MSHR misses 571system.cpu.dcache.ReadReq_mshr_misses::total 7333366 # number of ReadReq MSHR misses | 562system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364227 # number of WriteReq MSHR hits 563system.cpu.dcache.WriteReq_mshr_hits::total 364227 # number of WriteReq MSHR hits 564system.cpu.dcache.demand_mshr_hits::cpu.data 364276 # number of demand (read+write) MSHR hits 565system.cpu.dcache.demand_mshr_hits::total 364276 # number of demand (read+write) MSHR hits 566system.cpu.dcache.overall_mshr_hits::cpu.data 364276 # number of overall MSHR hits 567system.cpu.dcache.overall_mshr_hits::total 364276 # number of overall MSHR hits 568system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7333367 # number of ReadReq MSHR misses 569system.cpu.dcache.ReadReq_mshr_misses::total 7333367 # number of ReadReq MSHR misses |
| 572system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses 573system.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses 574system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 575system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses | 570system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890830 # number of WriteReq MSHR misses 571system.cpu.dcache.WriteReq_mshr_misses::total 1890830 # number of WriteReq MSHR misses 572system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 573system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses |
| 576system.cpu.dcache.demand_mshr_misses::cpu.data 9224196 # number of demand (read+write) MSHR misses 577system.cpu.dcache.demand_mshr_misses::total 9224196 # number of demand (read+write) MSHR misses 578system.cpu.dcache.overall_mshr_misses::cpu.data 9224197 # number of overall MSHR misses 579system.cpu.dcache.overall_mshr_misses::total 9224197 # number of overall MSHR misses 580system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183652478000 # number of ReadReq MSHR miss cycles 581system.cpu.dcache.ReadReq_mshr_miss_latency::total 183652478000 # number of ReadReq MSHR miss cycles 582system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84692070000 # number of WriteReq MSHR miss cycles 583system.cpu.dcache.WriteReq_mshr_miss_latency::total 84692070000 # number of WriteReq MSHR miss cycles 584system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles 585system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles 586system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268344548000 # number of demand (read+write) MSHR miss cycles 587system.cpu.dcache.demand_mshr_miss_latency::total 268344548000 # number of demand (read+write) MSHR miss cycles 588system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268344622000 # number of overall MSHR miss cycles 589system.cpu.dcache.overall_mshr_miss_latency::total 268344622000 # number of overall MSHR miss cycles | 574system.cpu.dcache.demand_mshr_misses::cpu.data 9224197 # number of demand (read+write) MSHR misses 575system.cpu.dcache.demand_mshr_misses::total 9224197 # number of demand (read+write) MSHR misses 576system.cpu.dcache.overall_mshr_misses::cpu.data 9224198 # number of overall MSHR misses 577system.cpu.dcache.overall_mshr_misses::total 9224198 # number of overall MSHR misses 578system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 185303496000 # number of ReadReq MSHR miss cycles 579system.cpu.dcache.ReadReq_mshr_miss_latency::total 185303496000 # number of ReadReq MSHR miss cycles 580system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 86626211500 # number of WriteReq MSHR miss cycles 581system.cpu.dcache.WriteReq_mshr_miss_latency::total 86626211500 # number of WriteReq MSHR miss cycles 582system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 75000 # number of SoftPFReq MSHR miss cycles 583system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 75000 # number of SoftPFReq MSHR miss cycles 584system.cpu.dcache.demand_mshr_miss_latency::cpu.data 271929707500 # number of demand (read+write) MSHR miss cycles 585system.cpu.dcache.demand_mshr_miss_latency::total 271929707500 # number of demand (read+write) MSHR miss cycles 586system.cpu.dcache.overall_mshr_miss_latency::cpu.data 271929782500 # number of overall MSHR miss cycles 587system.cpu.dcache.overall_mshr_miss_latency::total 271929782500 # number of overall MSHR miss cycles |
| 590system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses 591system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses 592system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 593system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 594system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses 595system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses 596system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses 597system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses 598system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses 599system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses | 588system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015890 # mshr miss rate for ReadReq accesses 589system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015890 # mshr miss rate for ReadReq accesses 590system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 591system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 592system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses 593system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses 594system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for demand accesses 595system.cpu.dcache.demand_mshr_miss_rate::total 0.014547 # mshr miss rate for demand accesses 596system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014547 # mshr miss rate for overall accesses 597system.cpu.dcache.overall_mshr_miss_rate::total 0.014547 # mshr miss rate for overall accesses |
| 600system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25043.408170 # average ReadReq mshr miss latency 601system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25043.408170 # average ReadReq mshr miss latency 602system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44790.948948 # average WriteReq mshr miss latency 603system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44790.948948 # average WriteReq mshr miss latency 604system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency 605system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency 606system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.375335 # average overall mshr miss latency 607system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.375335 # average overall mshr miss latency 608system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.380204 # average overall mshr miss latency 609system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.380204 # average overall mshr miss latency 610system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states 611system.cpu.icache.tags.replacements 30 # number of replacements 612system.cpu.icache.tags.tagsinuse 660.287317 # Cycle average of tags in use 613system.cpu.icache.tags.total_refs 466254411 # Total number of references to valid blocks. 614system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. 615system.cpu.icache.tags.avg_refs 569297.205128 # Average number of references to valid blocks. | 598system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25268.542540 # average ReadReq mshr miss latency 599system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25268.542540 # average ReadReq mshr miss latency 600system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45813.855027 # average WriteReq mshr miss latency 601system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45813.855027 # average WriteReq mshr miss latency 602system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 75000 # average SoftPFReq mshr miss latency 603system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 75000 # average SoftPFReq mshr miss latency 604system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29480.041189 # average overall mshr miss latency 605system.cpu.dcache.demand_avg_mshr_miss_latency::total 29480.041189 # average overall mshr miss latency 606system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29480.046124 # average overall mshr miss latency 607system.cpu.dcache.overall_avg_mshr_miss_latency::total 29480.046124 # average overall mshr miss latency 608system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 609system.cpu.icache.tags.replacements 33 # number of replacements 610system.cpu.icache.tags.tagsinuse 660.343836 # Cycle average of tags in use 611system.cpu.icache.tags.total_refs 466264831 # Total number of references to valid blocks. 612system.cpu.icache.tags.sampled_refs 822 # Sample count of references to valid blocks. 613system.cpu.icache.tags.avg_refs 567232.154501 # Average number of references to valid blocks. |
| 616system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 614system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 617system.cpu.icache.tags.occ_blocks::cpu.inst 660.287317 # Average occupied blocks per requestor 618system.cpu.icache.tags.occ_percent::cpu.inst 0.322406 # Average percentage of cache occupancy 619system.cpu.icache.tags.occ_percent::total 0.322406 # Average percentage of cache occupancy | 615system.cpu.icache.tags.occ_blocks::cpu.inst 660.343836 # Average occupied blocks per requestor 616system.cpu.icache.tags.occ_percent::cpu.inst 0.322434 # Average percentage of cache occupancy 617system.cpu.icache.tags.occ_percent::total 0.322434 # Average percentage of cache occupancy |
| 620system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id 621system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id | 618system.cpu.icache.tags.occ_task_id_blocks::1024 789 # Occupied blocks per task id 619system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id |
| 622system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 623system.cpu.icache.tags.age_task_id_blocks_1024::4 752 # Occupied blocks per task id | 620system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id 621system.cpu.icache.tags.age_task_id_blocks_1024::4 751 # Occupied blocks per task id |
| 624system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id | 622system.cpu.icache.tags.occ_task_id_percent::1024 0.385254 # Percentage of cache occupancy per task id |
| 625system.cpu.icache.tags.tag_accesses 932511279 # Number of tag accesses 626system.cpu.icache.tags.data_accesses 932511279 # Number of data accesses 627system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states 628system.cpu.icache.ReadReq_hits::cpu.inst 466254411 # number of ReadReq hits 629system.cpu.icache.ReadReq_hits::total 466254411 # number of ReadReq hits 630system.cpu.icache.demand_hits::cpu.inst 466254411 # number of demand (read+write) hits 631system.cpu.icache.demand_hits::total 466254411 # number of demand (read+write) hits 632system.cpu.icache.overall_hits::cpu.inst 466254411 # number of overall hits 633system.cpu.icache.overall_hits::total 466254411 # number of overall hits 634system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses 635system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses 636system.cpu.icache.demand_misses::cpu.inst 819 # number of demand (read+write) misses 637system.cpu.icache.demand_misses::total 819 # number of demand (read+write) misses 638system.cpu.icache.overall_misses::cpu.inst 819 # number of overall misses 639system.cpu.icache.overall_misses::total 819 # number of overall misses 640system.cpu.icache.ReadReq_miss_latency::cpu.inst 61690000 # number of ReadReq miss cycles 641system.cpu.icache.ReadReq_miss_latency::total 61690000 # number of ReadReq miss cycles 642system.cpu.icache.demand_miss_latency::cpu.inst 61690000 # number of demand (read+write) miss cycles 643system.cpu.icache.demand_miss_latency::total 61690000 # number of demand (read+write) miss cycles 644system.cpu.icache.overall_miss_latency::cpu.inst 61690000 # number of overall miss cycles 645system.cpu.icache.overall_miss_latency::total 61690000 # number of overall miss cycles 646system.cpu.icache.ReadReq_accesses::cpu.inst 466255230 # number of ReadReq accesses(hits+misses) 647system.cpu.icache.ReadReq_accesses::total 466255230 # number of ReadReq accesses(hits+misses) 648system.cpu.icache.demand_accesses::cpu.inst 466255230 # number of demand (read+write) accesses 649system.cpu.icache.demand_accesses::total 466255230 # number of demand (read+write) accesses 650system.cpu.icache.overall_accesses::cpu.inst 466255230 # number of overall (read+write) accesses 651system.cpu.icache.overall_accesses::total 466255230 # number of overall (read+write) accesses | 623system.cpu.icache.tags.tag_accesses 932532128 # Number of tag accesses 624system.cpu.icache.tags.data_accesses 932532128 # Number of data accesses 625system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 626system.cpu.icache.ReadReq_hits::cpu.inst 466264831 # number of ReadReq hits 627system.cpu.icache.ReadReq_hits::total 466264831 # number of ReadReq hits 628system.cpu.icache.demand_hits::cpu.inst 466264831 # number of demand (read+write) hits 629system.cpu.icache.demand_hits::total 466264831 # number of demand (read+write) hits 630system.cpu.icache.overall_hits::cpu.inst 466264831 # number of overall hits 631system.cpu.icache.overall_hits::total 466264831 # number of overall hits 632system.cpu.icache.ReadReq_misses::cpu.inst 822 # number of ReadReq misses 633system.cpu.icache.ReadReq_misses::total 822 # number of ReadReq misses 634system.cpu.icache.demand_misses::cpu.inst 822 # number of demand (read+write) misses 635system.cpu.icache.demand_misses::total 822 # number of demand (read+write) misses 636system.cpu.icache.overall_misses::cpu.inst 822 # number of overall misses 637system.cpu.icache.overall_misses::total 822 # number of overall misses 638system.cpu.icache.ReadReq_miss_latency::cpu.inst 62977000 # number of ReadReq miss cycles 639system.cpu.icache.ReadReq_miss_latency::total 62977000 # number of ReadReq miss cycles 640system.cpu.icache.demand_miss_latency::cpu.inst 62977000 # number of demand (read+write) miss cycles 641system.cpu.icache.demand_miss_latency::total 62977000 # number of demand (read+write) miss cycles 642system.cpu.icache.overall_miss_latency::cpu.inst 62977000 # number of overall miss cycles 643system.cpu.icache.overall_miss_latency::total 62977000 # number of overall miss cycles 644system.cpu.icache.ReadReq_accesses::cpu.inst 466265653 # number of ReadReq accesses(hits+misses) 645system.cpu.icache.ReadReq_accesses::total 466265653 # number of ReadReq accesses(hits+misses) 646system.cpu.icache.demand_accesses::cpu.inst 466265653 # number of demand (read+write) accesses 647system.cpu.icache.demand_accesses::total 466265653 # number of demand (read+write) accesses 648system.cpu.icache.overall_accesses::cpu.inst 466265653 # number of overall (read+write) accesses 649system.cpu.icache.overall_accesses::total 466265653 # number of overall (read+write) accesses |
| 652system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 653system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 654system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 655system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 656system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 657system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses | 650system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 651system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 652system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 653system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 654system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 655system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses |
| 658system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75323.565324 # average ReadReq miss latency 659system.cpu.icache.ReadReq_avg_miss_latency::total 75323.565324 # average ReadReq miss latency 660system.cpu.icache.demand_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency 661system.cpu.icache.demand_avg_miss_latency::total 75323.565324 # average overall miss latency 662system.cpu.icache.overall_avg_miss_latency::cpu.inst 75323.565324 # average overall miss latency 663system.cpu.icache.overall_avg_miss_latency::total 75323.565324 # average overall miss latency | 656system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76614.355231 # average ReadReq miss latency 657system.cpu.icache.ReadReq_avg_miss_latency::total 76614.355231 # average ReadReq miss latency 658system.cpu.icache.demand_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency 659system.cpu.icache.demand_avg_miss_latency::total 76614.355231 # average overall miss latency 660system.cpu.icache.overall_avg_miss_latency::cpu.inst 76614.355231 # average overall miss latency 661system.cpu.icache.overall_avg_miss_latency::total 76614.355231 # average overall miss latency |
| 664system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 665system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 666system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 667system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 668system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 669system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 662system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 663system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 664system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 665system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 666system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 667system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 670system.cpu.icache.writebacks::writebacks 30 # number of writebacks 671system.cpu.icache.writebacks::total 30 # number of writebacks 672system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses 673system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses 674system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses 675system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses 676system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses 677system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses 678system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 60871000 # number of ReadReq MSHR miss cycles 679system.cpu.icache.ReadReq_mshr_miss_latency::total 60871000 # number of ReadReq MSHR miss cycles 680system.cpu.icache.demand_mshr_miss_latency::cpu.inst 60871000 # number of demand (read+write) MSHR miss cycles 681system.cpu.icache.demand_mshr_miss_latency::total 60871000 # number of demand (read+write) MSHR miss cycles 682system.cpu.icache.overall_mshr_miss_latency::cpu.inst 60871000 # number of overall MSHR miss cycles 683system.cpu.icache.overall_mshr_miss_latency::total 60871000 # number of overall MSHR miss cycles | 668system.cpu.icache.writebacks::writebacks 33 # number of writebacks 669system.cpu.icache.writebacks::total 33 # number of writebacks 670system.cpu.icache.ReadReq_mshr_misses::cpu.inst 822 # number of ReadReq MSHR misses 671system.cpu.icache.ReadReq_mshr_misses::total 822 # number of ReadReq MSHR misses 672system.cpu.icache.demand_mshr_misses::cpu.inst 822 # number of demand (read+write) MSHR misses 673system.cpu.icache.demand_mshr_misses::total 822 # number of demand (read+write) MSHR misses 674system.cpu.icache.overall_mshr_misses::cpu.inst 822 # number of overall MSHR misses 675system.cpu.icache.overall_mshr_misses::total 822 # number of overall MSHR misses 676system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62155000 # number of ReadReq MSHR miss cycles 677system.cpu.icache.ReadReq_mshr_miss_latency::total 62155000 # number of ReadReq MSHR miss cycles 678system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62155000 # number of demand (read+write) MSHR miss cycles 679system.cpu.icache.demand_mshr_miss_latency::total 62155000 # number of demand (read+write) MSHR miss cycles 680system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62155000 # number of overall MSHR miss cycles 681system.cpu.icache.overall_mshr_miss_latency::total 62155000 # number of overall MSHR miss cycles |
| 684system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 685system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 686system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 687system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 688system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 689system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses | 682system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 683system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 684system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 685system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 686system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 687system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses |
| 690system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74323.565324 # average ReadReq mshr miss latency 691system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74323.565324 # average ReadReq mshr miss latency 692system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74323.565324 # average overall mshr miss latency 693system.cpu.icache.demand_avg_mshr_miss_latency::total 74323.565324 # average overall mshr miss latency 694system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74323.565324 # average overall mshr miss latency 695system.cpu.icache.overall_avg_mshr_miss_latency::total 74323.565324 # average overall mshr miss latency 696system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states 697system.cpu.l2cache.tags.replacements 2013239 # number of replacements 698system.cpu.l2cache.tags.tagsinuse 31266.385554 # Cycle average of tags in use 699system.cpu.l2cache.tags.total_refs 14508014 # Total number of references to valid blocks. 700system.cpu.l2cache.tags.sampled_refs 2043015 # Sample count of references to valid blocks. 701system.cpu.l2cache.tags.avg_refs 7.101276 # Average number of references to valid blocks. 702system.cpu.l2cache.tags.warmup_cycle 59831992000 # Cycle when the warmup percentage was hit. 703system.cpu.l2cache.tags.occ_blocks::writebacks 14855.828649 # Average occupied blocks per requestor 704system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.313947 # Average occupied blocks per requestor 705system.cpu.l2cache.tags.occ_blocks::cpu.data 16384.242958 # Average occupied blocks per requestor 706system.cpu.l2cache.tags.occ_percent::writebacks 0.453364 # Average percentage of cache occupancy 707system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000803 # Average percentage of cache occupancy 708system.cpu.l2cache.tags.occ_percent::cpu.data 0.500007 # Average percentage of cache occupancy 709system.cpu.l2cache.tags.occ_percent::total 0.954174 # Average percentage of cache occupancy 710system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id 711system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 712system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 713system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id 714system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12853 # Occupied blocks per task id 715system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id 716system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id 717system.cpu.l2cache.tags.tag_accesses 151482269 # Number of tag accesses 718system.cpu.l2cache.tags.data_accesses 151482269 # Number of data accesses 719system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states 720system.cpu.l2cache.WritebackDirty_hits::writebacks 3684499 # number of WritebackDirty hits 721system.cpu.l2cache.WritebackDirty_hits::total 3684499 # number of WritebackDirty hits 722system.cpu.l2cache.WritebackClean_hits::writebacks 30 # number of WritebackClean hits 723system.cpu.l2cache.WritebackClean_hits::total 30 # number of WritebackClean hits 724system.cpu.l2cache.ReadExReq_hits::cpu.data 1089818 # number of ReadExReq hits 725system.cpu.l2cache.ReadExReq_hits::total 1089818 # number of ReadExReq hits 726system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits 727system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits 728system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089246 # number of ReadSharedReq hits 729system.cpu.l2cache.ReadSharedReq_hits::total 6089246 # number of ReadSharedReq hits 730system.cpu.l2cache.demand_hits::cpu.inst 36 # number of demand (read+write) hits 731system.cpu.l2cache.demand_hits::cpu.data 7179064 # number of demand (read+write) hits 732system.cpu.l2cache.demand_hits::total 7179100 # number of demand (read+write) hits 733system.cpu.l2cache.overall_hits::cpu.inst 36 # number of overall hits 734system.cpu.l2cache.overall_hits::cpu.data 7179064 # number of overall hits 735system.cpu.l2cache.overall_hits::total 7179100 # number of overall hits 736system.cpu.l2cache.ReadExReq_misses::cpu.data 801012 # number of ReadExReq misses 737system.cpu.l2cache.ReadExReq_misses::total 801012 # number of ReadExReq misses 738system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 783 # number of ReadCleanReq misses 739system.cpu.l2cache.ReadCleanReq_misses::total 783 # number of ReadCleanReq misses 740system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244121 # number of ReadSharedReq misses 741system.cpu.l2cache.ReadSharedReq_misses::total 1244121 # number of ReadSharedReq misses 742system.cpu.l2cache.demand_misses::cpu.inst 783 # number of demand (read+write) misses 743system.cpu.l2cache.demand_misses::cpu.data 2045133 # number of demand (read+write) misses 744system.cpu.l2cache.demand_misses::total 2045916 # number of demand (read+write) misses 745system.cpu.l2cache.overall_misses::cpu.inst 783 # number of overall misses 746system.cpu.l2cache.overall_misses::cpu.data 2045133 # number of overall misses 747system.cpu.l2cache.overall_misses::total 2045916 # number of overall misses 748system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70389294000 # number of ReadExReq miss cycles 749system.cpu.l2cache.ReadExReq_miss_latency::total 70389294000 # number of ReadExReq miss cycles 750system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59232000 # number of ReadCleanReq miss cycles 751system.cpu.l2cache.ReadCleanReq_miss_latency::total 59232000 # number of ReadCleanReq miss cycles 752system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108712178500 # number of ReadSharedReq miss cycles 753system.cpu.l2cache.ReadSharedReq_miss_latency::total 108712178500 # number of ReadSharedReq miss cycles 754system.cpu.l2cache.demand_miss_latency::cpu.inst 59232000 # number of demand (read+write) miss cycles 755system.cpu.l2cache.demand_miss_latency::cpu.data 179101472500 # number of demand (read+write) miss cycles 756system.cpu.l2cache.demand_miss_latency::total 179160704500 # number of demand (read+write) miss cycles 757system.cpu.l2cache.overall_miss_latency::cpu.inst 59232000 # number of overall miss cycles 758system.cpu.l2cache.overall_miss_latency::cpu.data 179101472500 # number of overall miss cycles 759system.cpu.l2cache.overall_miss_latency::total 179160704500 # number of overall miss cycles 760system.cpu.l2cache.WritebackDirty_accesses::writebacks 3684499 # number of WritebackDirty accesses(hits+misses) 761system.cpu.l2cache.WritebackDirty_accesses::total 3684499 # number of WritebackDirty accesses(hits+misses) 762system.cpu.l2cache.WritebackClean_accesses::writebacks 30 # number of WritebackClean accesses(hits+misses) 763system.cpu.l2cache.WritebackClean_accesses::total 30 # number of WritebackClean accesses(hits+misses) | 688system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75614.355231 # average ReadReq mshr miss latency 689system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75614.355231 # average ReadReq mshr miss latency 690system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75614.355231 # average overall mshr miss latency 691system.cpu.icache.demand_avg_mshr_miss_latency::total 75614.355231 # average overall mshr miss latency 692system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75614.355231 # average overall mshr miss latency 693system.cpu.icache.overall_avg_mshr_miss_latency::total 75614.355231 # average overall mshr miss latency 694system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 695system.cpu.l2cache.tags.replacements 2032337 # number of replacements 696system.cpu.l2cache.tags.tagsinuse 31884.361365 # Cycle average of tags in use 697system.cpu.l2cache.tags.total_refs 16378235 # Total number of references to valid blocks. 698system.cpu.l2cache.tags.sampled_refs 2065105 # Sample count of references to valid blocks. 699system.cpu.l2cache.tags.avg_refs 7.930945 # Average number of references to valid blocks. 700system.cpu.l2cache.tags.warmup_cycle 54418076000 # Cycle when the warmup percentage was hit. 701system.cpu.l2cache.tags.occ_blocks::writebacks 10.408988 # Average occupied blocks per requestor 702system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.813492 # Average occupied blocks per requestor 703system.cpu.l2cache.tags.occ_blocks::cpu.data 31848.138885 # Average occupied blocks per requestor 704system.cpu.l2cache.tags.occ_percent::writebacks 0.000318 # Average percentage of cache occupancy 705system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000788 # Average percentage of cache occupancy 706system.cpu.l2cache.tags.occ_percent::cpu.data 0.971928 # Average percentage of cache occupancy 707system.cpu.l2cache.tags.occ_percent::total 0.973033 # Average percentage of cache occupancy 708system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 709system.cpu.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id 710system.cpu.l2cache.tags.age_task_id_blocks_1024::1 912 # Occupied blocks per task id 711system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2876 # Occupied blocks per task id 712system.cpu.l2cache.tags.age_task_id_blocks_1024::3 7195 # Occupied blocks per task id 713system.cpu.l2cache.tags.age_task_id_blocks_1024::4 21737 # Occupied blocks per task id 714system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 715system.cpu.l2cache.tags.tag_accesses 149613593 # Number of tag accesses 716system.cpu.l2cache.tags.data_accesses 149613593 # Number of data accesses 717system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 718system.cpu.l2cache.WritebackDirty_hits::writebacks 3670051 # number of WritebackDirty hits 719system.cpu.l2cache.WritebackDirty_hits::total 3670051 # number of WritebackDirty hits 720system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 721system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 722system.cpu.l2cache.ReadExReq_hits::cpu.data 1078506 # number of ReadExReq hits 723system.cpu.l2cache.ReadExReq_hits::total 1078506 # number of ReadExReq hits 724system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 37 # number of ReadCleanReq hits 725system.cpu.l2cache.ReadCleanReq_hits::total 37 # number of ReadCleanReq hits 726system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6081702 # number of ReadSharedReq hits 727system.cpu.l2cache.ReadSharedReq_hits::total 6081702 # number of ReadSharedReq hits 728system.cpu.l2cache.demand_hits::cpu.inst 37 # number of demand (read+write) hits 729system.cpu.l2cache.demand_hits::cpu.data 7160208 # number of demand (read+write) hits 730system.cpu.l2cache.demand_hits::total 7160245 # number of demand (read+write) hits 731system.cpu.l2cache.overall_hits::cpu.inst 37 # number of overall hits 732system.cpu.l2cache.overall_hits::cpu.data 7160208 # number of overall hits 733system.cpu.l2cache.overall_hits::total 7160245 # number of overall hits 734system.cpu.l2cache.ReadExReq_misses::cpu.data 812324 # number of ReadExReq misses 735system.cpu.l2cache.ReadExReq_misses::total 812324 # number of ReadExReq misses 736system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 785 # number of ReadCleanReq misses 737system.cpu.l2cache.ReadCleanReq_misses::total 785 # number of ReadCleanReq misses 738system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1251666 # number of ReadSharedReq misses 739system.cpu.l2cache.ReadSharedReq_misses::total 1251666 # number of ReadSharedReq misses 740system.cpu.l2cache.demand_misses::cpu.inst 785 # number of demand (read+write) misses 741system.cpu.l2cache.demand_misses::cpu.data 2063990 # number of demand (read+write) misses 742system.cpu.l2cache.demand_misses::total 2064775 # number of demand (read+write) misses 743system.cpu.l2cache.overall_misses::cpu.inst 785 # number of overall misses 744system.cpu.l2cache.overall_misses::cpu.data 2063990 # number of overall misses 745system.cpu.l2cache.overall_misses::total 2064775 # number of overall misses 746system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 72440693500 # number of ReadExReq miss cycles 747system.cpu.l2cache.ReadExReq_miss_latency::total 72440693500 # number of ReadExReq miss cycles 748system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 60501000 # number of ReadCleanReq miss cycles 749system.cpu.l2cache.ReadCleanReq_miss_latency::total 60501000 # number of ReadCleanReq miss cycles 750system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 110442540000 # number of ReadSharedReq miss cycles 751system.cpu.l2cache.ReadSharedReq_miss_latency::total 110442540000 # number of ReadSharedReq miss cycles 752system.cpu.l2cache.demand_miss_latency::cpu.inst 60501000 # number of demand (read+write) miss cycles 753system.cpu.l2cache.demand_miss_latency::cpu.data 182883233500 # number of demand (read+write) miss cycles 754system.cpu.l2cache.demand_miss_latency::total 182943734500 # number of demand (read+write) miss cycles 755system.cpu.l2cache.overall_miss_latency::cpu.inst 60501000 # number of overall miss cycles 756system.cpu.l2cache.overall_miss_latency::cpu.data 182883233500 # number of overall miss cycles 757system.cpu.l2cache.overall_miss_latency::total 182943734500 # number of overall miss cycles 758system.cpu.l2cache.WritebackDirty_accesses::writebacks 3670051 # number of WritebackDirty accesses(hits+misses) 759system.cpu.l2cache.WritebackDirty_accesses::total 3670051 # number of WritebackDirty accesses(hits+misses) 760system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 761system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) |
| 764system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890830 # number of ReadExReq accesses(hits+misses) 765system.cpu.l2cache.ReadExReq_accesses::total 1890830 # number of ReadExReq accesses(hits+misses) | 762system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890830 # number of ReadExReq accesses(hits+misses) 763system.cpu.l2cache.ReadExReq_accesses::total 1890830 # number of ReadExReq accesses(hits+misses) |
| 766system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 819 # number of ReadCleanReq accesses(hits+misses) 767system.cpu.l2cache.ReadCleanReq_accesses::total 819 # number of ReadCleanReq accesses(hits+misses) 768system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333367 # number of ReadSharedReq accesses(hits+misses) 769system.cpu.l2cache.ReadSharedReq_accesses::total 7333367 # number of ReadSharedReq accesses(hits+misses) 770system.cpu.l2cache.demand_accesses::cpu.inst 819 # number of demand (read+write) accesses 771system.cpu.l2cache.demand_accesses::cpu.data 9224197 # number of demand (read+write) accesses 772system.cpu.l2cache.demand_accesses::total 9225016 # number of demand (read+write) accesses 773system.cpu.l2cache.overall_accesses::cpu.inst 819 # number of overall (read+write) accesses 774system.cpu.l2cache.overall_accesses::cpu.data 9224197 # number of overall (read+write) accesses 775system.cpu.l2cache.overall_accesses::total 9225016 # number of overall (read+write) accesses 776system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423630 # miss rate for ReadExReq accesses 777system.cpu.l2cache.ReadExReq_miss_rate::total 0.423630 # miss rate for ReadExReq accesses 778system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.956044 # miss rate for ReadCleanReq accesses 779system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.956044 # miss rate for ReadCleanReq accesses 780system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169652 # miss rate for ReadSharedReq accesses 781system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169652 # miss rate for ReadSharedReq accesses 782system.cpu.l2cache.demand_miss_rate::cpu.inst 0.956044 # miss rate for demand accesses 783system.cpu.l2cache.demand_miss_rate::cpu.data 0.221714 # miss rate for demand accesses 784system.cpu.l2cache.demand_miss_rate::total 0.221779 # miss rate for demand accesses 785system.cpu.l2cache.overall_miss_rate::cpu.inst 0.956044 # miss rate for overall accesses 786system.cpu.l2cache.overall_miss_rate::cpu.data 0.221714 # miss rate for overall accesses 787system.cpu.l2cache.overall_miss_rate::total 0.221779 # miss rate for overall accesses 788system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87875.455049 # average ReadExReq miss latency 789system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87875.455049 # average ReadExReq miss latency 790system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75647.509579 # average ReadCleanReq miss latency 791system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75647.509579 # average ReadCleanReq miss latency 792system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87380.711764 # average ReadSharedReq miss latency 793system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87380.711764 # average ReadSharedReq miss latency 794system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75647.509579 # average overall miss latency 795system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87574.486598 # average overall miss latency 796system.cpu.l2cache.demand_avg_miss_latency::total 87569.921981 # average overall miss latency 797system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75647.509579 # average overall miss latency 798system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87574.486598 # average overall miss latency 799system.cpu.l2cache.overall_avg_miss_latency::total 87569.921981 # average overall miss latency | 764system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 822 # number of ReadCleanReq accesses(hits+misses) 765system.cpu.l2cache.ReadCleanReq_accesses::total 822 # number of ReadCleanReq accesses(hits+misses) 766system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7333368 # number of ReadSharedReq accesses(hits+misses) 767system.cpu.l2cache.ReadSharedReq_accesses::total 7333368 # number of ReadSharedReq accesses(hits+misses) 768system.cpu.l2cache.demand_accesses::cpu.inst 822 # number of demand (read+write) accesses 769system.cpu.l2cache.demand_accesses::cpu.data 9224198 # number of demand (read+write) accesses 770system.cpu.l2cache.demand_accesses::total 9225020 # number of demand (read+write) accesses 771system.cpu.l2cache.overall_accesses::cpu.inst 822 # number of overall (read+write) accesses 772system.cpu.l2cache.overall_accesses::cpu.data 9224198 # number of overall (read+write) accesses 773system.cpu.l2cache.overall_accesses::total 9225020 # number of overall (read+write) accesses 774system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.429612 # miss rate for ReadExReq accesses 775system.cpu.l2cache.ReadExReq_miss_rate::total 0.429612 # miss rate for ReadExReq accesses 776system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.954988 # miss rate for ReadCleanReq accesses 777system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.954988 # miss rate for ReadCleanReq accesses 778system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.170681 # miss rate for ReadSharedReq accesses 779system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.170681 # miss rate for ReadSharedReq accesses 780system.cpu.l2cache.demand_miss_rate::cpu.inst 0.954988 # miss rate for demand accesses 781system.cpu.l2cache.demand_miss_rate::cpu.data 0.223758 # miss rate for demand accesses 782system.cpu.l2cache.demand_miss_rate::total 0.223823 # miss rate for demand accesses 783system.cpu.l2cache.overall_miss_rate::cpu.inst 0.954988 # miss rate for overall accesses 784system.cpu.l2cache.overall_miss_rate::cpu.data 0.223758 # miss rate for overall accesses 785system.cpu.l2cache.overall_miss_rate::total 0.223823 # miss rate for overall accesses 786system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 89177.093746 # average ReadExReq miss latency 787system.cpu.l2cache.ReadExReq_avg_miss_latency::total 89177.093746 # average ReadExReq miss latency 788system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77071.337580 # average ReadCleanReq miss latency 789system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77071.337580 # average ReadCleanReq miss latency 790system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88236.430485 # average ReadSharedReq miss latency 791system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88236.430485 # average ReadSharedReq miss latency 792system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77071.337580 # average overall miss latency 793system.cpu.l2cache.demand_avg_miss_latency::cpu.data 88606.647077 # average overall miss latency 794system.cpu.l2cache.demand_avg_miss_latency::total 88602.261505 # average overall miss latency 795system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77071.337580 # average overall miss latency 796system.cpu.l2cache.overall_avg_miss_latency::cpu.data 88606.647077 # average overall miss latency 797system.cpu.l2cache.overall_avg_miss_latency::total 88602.261505 # average overall miss latency |
| 800system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 801system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 802system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 803system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 804system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 805system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 798system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 799system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 800system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 801system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 802system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 803system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 806system.cpu.l2cache.writebacks::writebacks 1049913 # number of writebacks 807system.cpu.l2cache.writebacks::total 1049913 # number of writebacks | 804system.cpu.l2cache.writebacks::writebacks 1060158 # number of writebacks 805system.cpu.l2cache.writebacks::total 1060158 # number of writebacks |
| 808system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 809system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 810system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 811system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 812system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 813system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits | 806system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 6 # number of ReadSharedReq MSHR hits 807system.cpu.l2cache.ReadSharedReq_mshr_hits::total 6 # number of ReadSharedReq MSHR hits 808system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 809system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 810system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 811system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits |
| 814system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 214 # number of CleanEvict MSHR misses 815system.cpu.l2cache.CleanEvict_mshr_misses::total 214 # number of CleanEvict MSHR misses 816system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801012 # number of ReadExReq MSHR misses 817system.cpu.l2cache.ReadExReq_mshr_misses::total 801012 # number of ReadExReq MSHR misses 818system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 783 # number of ReadCleanReq MSHR misses 819system.cpu.l2cache.ReadCleanReq_mshr_misses::total 783 # number of ReadCleanReq MSHR misses 820system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244115 # number of ReadSharedReq MSHR misses 821system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244115 # number of ReadSharedReq MSHR misses 822system.cpu.l2cache.demand_mshr_misses::cpu.inst 783 # number of demand (read+write) MSHR misses 823system.cpu.l2cache.demand_mshr_misses::cpu.data 2045127 # number of demand (read+write) MSHR misses 824system.cpu.l2cache.demand_mshr_misses::total 2045910 # number of demand (read+write) MSHR misses 825system.cpu.l2cache.overall_mshr_misses::cpu.inst 783 # number of overall MSHR misses 826system.cpu.l2cache.overall_mshr_misses::cpu.data 2045127 # number of overall MSHR misses 827system.cpu.l2cache.overall_mshr_misses::total 2045910 # number of overall MSHR misses 828system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62379174000 # number of ReadExReq MSHR miss cycles 829system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62379174000 # number of ReadExReq MSHR miss cycles 830system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51402000 # number of ReadCleanReq MSHR miss cycles 831system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51402000 # number of ReadCleanReq MSHR miss cycles 832system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96270618000 # number of ReadSharedReq MSHR miss cycles 833system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96270618000 # number of ReadSharedReq MSHR miss cycles 834system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51402000 # number of demand (read+write) MSHR miss cycles 835system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158649792000 # number of demand (read+write) MSHR miss cycles 836system.cpu.l2cache.demand_mshr_miss_latency::total 158701194000 # number of demand (read+write) MSHR miss cycles 837system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51402000 # number of overall MSHR miss cycles 838system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158649792000 # number of overall MSHR miss cycles 839system.cpu.l2cache.overall_mshr_miss_latency::total 158701194000 # number of overall MSHR miss cycles | 812system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 215 # number of CleanEvict MSHR misses 813system.cpu.l2cache.CleanEvict_mshr_misses::total 215 # number of CleanEvict MSHR misses 814system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 812324 # number of ReadExReq MSHR misses 815system.cpu.l2cache.ReadExReq_mshr_misses::total 812324 # number of ReadExReq MSHR misses 816system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 785 # number of ReadCleanReq MSHR misses 817system.cpu.l2cache.ReadCleanReq_mshr_misses::total 785 # number of ReadCleanReq MSHR misses 818system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1251660 # number of ReadSharedReq MSHR misses 819system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1251660 # number of ReadSharedReq MSHR misses 820system.cpu.l2cache.demand_mshr_misses::cpu.inst 785 # number of demand (read+write) MSHR misses 821system.cpu.l2cache.demand_mshr_misses::cpu.data 2063984 # number of demand (read+write) MSHR misses 822system.cpu.l2cache.demand_mshr_misses::total 2064769 # number of demand (read+write) MSHR misses 823system.cpu.l2cache.overall_mshr_misses::cpu.inst 785 # number of overall MSHR misses 824system.cpu.l2cache.overall_mshr_misses::cpu.data 2063984 # number of overall MSHR misses 825system.cpu.l2cache.overall_mshr_misses::total 2064769 # number of overall MSHR misses 826system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 64317453500 # number of ReadExReq MSHR miss cycles 827system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 64317453500 # number of ReadExReq MSHR miss cycles 828system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52651000 # number of ReadCleanReq MSHR miss cycles 829system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52651000 # number of ReadCleanReq MSHR miss cycles 830system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 97925523500 # number of ReadSharedReq MSHR miss cycles 831system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 97925523500 # number of ReadSharedReq MSHR miss cycles 832system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52651000 # number of demand (read+write) MSHR miss cycles 833system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 162242977000 # number of demand (read+write) MSHR miss cycles 834system.cpu.l2cache.demand_mshr_miss_latency::total 162295628000 # number of demand (read+write) MSHR miss cycles 835system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52651000 # number of overall MSHR miss cycles 836system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 162242977000 # number of overall MSHR miss cycles 837system.cpu.l2cache.overall_mshr_miss_latency::total 162295628000 # number of overall MSHR miss cycles |
| 840system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 841system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 838system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 839system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 842system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423630 # mshr miss rate for ReadExReq accesses 843system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423630 # mshr miss rate for ReadExReq accesses 844system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for ReadCleanReq accesses 845system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.956044 # mshr miss rate for ReadCleanReq accesses 846system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169651 # mshr miss rate for ReadSharedReq accesses 847system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169651 # mshr miss rate for ReadSharedReq accesses 848system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for demand accesses 849system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221713 # mshr miss rate for demand accesses 850system.cpu.l2cache.demand_mshr_miss_rate::total 0.221778 # mshr miss rate for demand accesses 851system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.956044 # mshr miss rate for overall accesses 852system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221713 # mshr miss rate for overall accesses 853system.cpu.l2cache.overall_mshr_miss_rate::total 0.221778 # mshr miss rate for overall accesses 854system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77875.455049 # average ReadExReq mshr miss latency 855system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77875.455049 # average ReadExReq mshr miss latency 856system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65647.509579 # average ReadCleanReq mshr miss latency 857system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65647.509579 # average ReadCleanReq mshr miss latency 858system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77380.803222 # average ReadSharedReq mshr miss latency 859system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77380.803222 # average ReadSharedReq mshr miss latency 860system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency 861system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency 862system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency 863system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65647.509579 # average overall mshr miss latency 864system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77574.542803 # average overall mshr miss latency 865system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77569.978152 # average overall mshr miss latency 866system.cpu.toL2Bus.snoop_filter.tot_requests 18445147 # Total number of requests made to the snoop filter. 867system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220143 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 840system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.429612 # mshr miss rate for ReadExReq accesses 841system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.429612 # mshr miss rate for ReadExReq accesses 842system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for ReadCleanReq accesses 843system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.954988 # mshr miss rate for ReadCleanReq accesses 844system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.170680 # mshr miss rate for ReadSharedReq accesses 845system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.170680 # mshr miss rate for ReadSharedReq accesses 846system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for demand accesses 847system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for demand accesses 848system.cpu.l2cache.demand_mshr_miss_rate::total 0.223823 # mshr miss rate for demand accesses 849system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.954988 # mshr miss rate for overall accesses 850system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223758 # mshr miss rate for overall accesses 851system.cpu.l2cache.overall_mshr_miss_rate::total 0.223823 # mshr miss rate for overall accesses 852system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79177.093746 # average ReadExReq mshr miss latency 853system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 79177.093746 # average ReadExReq mshr miss latency 854system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67071.337580 # average ReadCleanReq mshr miss latency 855system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67071.337580 # average ReadCleanReq mshr miss latency 856system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78236.520701 # average ReadSharedReq mshr miss latency 857system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78236.520701 # average ReadSharedReq mshr miss latency 858system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency 859system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency 860system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency 861system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67071.337580 # average overall mshr miss latency 862system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 78606.702862 # average overall mshr miss latency 863system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78602.317257 # average overall mshr miss latency 864system.cpu.toL2Bus.snoop_filter.tot_requests 18445155 # Total number of requests made to the snoop filter. 865system.cpu.toL2Bus.snoop_filter.hit_single_requests 9220147 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 868system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 866system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 869system.cpu.toL2Bus.snoop_filter.tot_snoops 1285 # Total number of snoops made to the snoop filter. 870system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1279 # Number of snoops hitting in the snoop filter with a single holder of the requested data. | 867system.cpu.toL2Bus.snoop_filter.tot_snoops 1445 # Total number of snoops made to the snoop filter. 868system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1439 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| 871system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 869system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 872system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states 873system.cpu.toL2Bus.trans_dist::ReadResp 7334186 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::WritebackDirty 4734412 # Transaction distribution 875system.cpu.toL2Bus.trans_dist::WritebackClean 30 # Transaction distribution 876system.cpu.toL2Bus.trans_dist::CleanEvict 6498928 # Transaction distribution | 870system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 871system.cpu.toL2Bus.trans_dist::ReadResp 7334190 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::WritebackDirty 4730209 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::WritebackClean 33 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::CleanEvict 6522230 # Transaction distribution |
| 877system.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution | 875system.cpu.toL2Bus.trans_dist::ReadExReq 1890830 # Transaction distribution 876system.cpu.toL2Bus.trans_dist::ReadExResp 1890830 # Transaction distribution |
| 879system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution 880system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333367 # Transaction distribution 881system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1668 # Packet count per connected master and slave (bytes) 882system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668495 # Packet count per connected master and slave (bytes) 883system.cpu.toL2Bus.pkt_count::total 27670163 # Packet count per connected master and slave (bytes) 884system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54336 # Cumulative packet size per connected master and slave (bytes) 885system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826156544 # Cumulative packet size per connected master and slave (bytes) 886system.cpu.toL2Bus.pkt_size::total 826210880 # Cumulative packet size per connected master and slave (bytes) 887system.cpu.toL2Bus.snoops 2013239 # Total snoops (count) 888system.cpu.toL2Bus.snoopTraffic 67194432 # Total snoop traffic (bytes) 889system.cpu.toL2Bus.snoop_fanout::samples 11238255 # Request fanout histogram 890system.cpu.toL2Bus.snoop_fanout::mean 0.000258 # Request fanout histogram 891system.cpu.toL2Bus.snoop_fanout::stdev 0.016087 # Request fanout histogram | 877system.cpu.toL2Bus.trans_dist::ReadCleanReq 822 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::ReadSharedReq 7333368 # Transaction distribution 879system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1677 # Packet count per connected master and slave (bytes) 880system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27668498 # Packet count per connected master and slave (bytes) 881system.cpu.toL2Bus.pkt_count::total 27670175 # Packet count per connected master and slave (bytes) 882system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54720 # Cumulative packet size per connected master and slave (bytes) 883system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 825231936 # Cumulative packet size per connected master and slave (bytes) 884system.cpu.toL2Bus.pkt_size::total 825286656 # Cumulative packet size per connected master and slave (bytes) 885system.cpu.toL2Bus.snoops 2032337 # Total snoops (count) 886system.cpu.toL2Bus.snoopTraffic 67850112 # Total snoop traffic (bytes) 887system.cpu.toL2Bus.snoop_fanout::samples 11257357 # Request fanout histogram 888system.cpu.toL2Bus.snoop_fanout::mean 0.000272 # Request fanout histogram 889system.cpu.toL2Bus.snoop_fanout::stdev 0.016509 # Request fanout histogram |
| 892system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 890system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 893system.cpu.toL2Bus.snoop_fanout::0 11235364 99.97% 99.97% # Request fanout histogram 894system.cpu.toL2Bus.snoop_fanout::1 2885 0.03% 100.00% # Request fanout histogram | 891system.cpu.toL2Bus.snoop_fanout::0 11254306 99.97% 99.97% # Request fanout histogram 892system.cpu.toL2Bus.snoop_fanout::1 3045 0.03% 100.00% # Request fanout histogram |
| 895system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 896system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 897system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 898system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 893system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram 894system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 895system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 896system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 899system.cpu.toL2Bus.snoop_fanout::total 11238255 # Request fanout histogram 900system.cpu.toL2Bus.reqLayer0.occupancy 12907102500 # Layer occupancy (ticks) | 897system.cpu.toL2Bus.snoop_fanout::total 11257357 # Request fanout histogram 898system.cpu.toL2Bus.reqLayer0.occupancy 12892661500 # Layer occupancy (ticks) |
| 901system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) | 899system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) |
| 902system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) | 900system.cpu.toL2Bus.respLayer0.occupancy 1233000 # Layer occupancy (ticks) |
| 903system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 901system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 904system.cpu.toL2Bus.respLayer1.occupancy 13836298494 # Layer occupancy (ticks) | 902system.cpu.toL2Bus.respLayer1.occupancy 13836299994 # Layer occupancy (ticks) |
| 905system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) | 903system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) |
| 906system.membus.pwrStateResidencyTicks::UNDEFINED 1128033563500 # Cumulative time (in ticks) in various power states 907system.membus.trans_dist::ReadResp 1244898 # Transaction distribution 908system.membus.trans_dist::WritebackDirty 1049913 # Transaction distribution 909system.membus.trans_dist::CleanEvict 962255 # Transaction distribution 910system.membus.trans_dist::ReadExReq 801012 # Transaction distribution 911system.membus.trans_dist::ReadExResp 801012 # Transaction distribution 912system.membus.trans_dist::ReadSharedReq 1244898 # Transaction distribution 913system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6103988 # Packet count per connected master and slave (bytes) 914system.membus.pkt_count::total 6103988 # Packet count per connected master and slave (bytes) 915system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198132672 # Cumulative packet size per connected master and slave (bytes) 916system.membus.pkt_size::total 198132672 # Cumulative packet size per connected master and slave (bytes) | 904system.membus.snoop_filter.tot_requests 4095876 # Total number of requests made to the snoop filter. 905system.membus.snoop_filter.hit_single_requests 2031264 # Number of requests hitting in the snoop filter with a single holder of the requested data. 906system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 907system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 908system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 909system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 910system.membus.pwrStateResidencyTicks::UNDEFINED 1130744162500 # Cumulative time (in ticks) in various power states 911system.membus.trans_dist::ReadResp 1252445 # Transaction distribution 912system.membus.trans_dist::WritebackDirty 1060158 # Transaction distribution 913system.membus.trans_dist::CleanEvict 970949 # Transaction distribution 914system.membus.trans_dist::ReadExReq 812324 # Transaction distribution 915system.membus.trans_dist::ReadExResp 812324 # Transaction distribution 916system.membus.trans_dist::ReadSharedReq 1252445 # Transaction distribution 917system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6160645 # Packet count per connected master and slave (bytes) 918system.membus.pkt_count::total 6160645 # Packet count per connected master and slave (bytes) 919system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 199995328 # Cumulative packet size per connected master and slave (bytes) 920system.membus.pkt_size::total 199995328 # Cumulative packet size per connected master and slave (bytes) |
| 917system.membus.snoops 0 # Total snoops (count) 918system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 921system.membus.snoops 0 # Total snoops (count) 922system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 919system.membus.snoop_fanout::samples 4058078 # Request fanout histogram | 923system.membus.snoop_fanout::samples 2064769 # Request fanout histogram |
| 920system.membus.snoop_fanout::mean 0 # Request fanout histogram 921system.membus.snoop_fanout::stdev 0 # Request fanout histogram 922system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 924system.membus.snoop_fanout::mean 0 # Request fanout histogram 925system.membus.snoop_fanout::stdev 0 # Request fanout histogram 926system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 923system.membus.snoop_fanout::0 4058078 100.00% 100.00% # Request fanout histogram | 927system.membus.snoop_fanout::0 2064769 100.00% 100.00% # Request fanout histogram |
| 924system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 925system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 926system.membus.snoop_fanout::min_value 0 # Request fanout histogram 927system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 928system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 929system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 930system.membus.snoop_fanout::min_value 0 # Request fanout histogram 931system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 928system.membus.snoop_fanout::total 4058078 # Request fanout histogram 929system.membus.reqLayer0.occupancy 8755432500 # Layer occupancy (ticks) | 932system.membus.snoop_fanout::total 2064769 # Request fanout histogram 933system.membus.reqLayer0.occupancy 8803577000 # Layer occupancy (ticks) |
| 930system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) | 934system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) |
| 931system.membus.respLayer1.occupancy 11187827500 # Layer occupancy (ticks) | 935system.membus.respLayer1.occupancy 11289358000 # Layer occupancy (ticks) |
| 932system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 933 934---------- End Simulation Statistics ---------- | 936system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 937 938---------- End Simulation Statistics ---------- |