Cross Reference: /gem5/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt

stats.txt (11507:be6065c1d8d2)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.116866 # Number of seconds simulated 4sim_ticks 1116865668500 # Number of ticks simulated 5final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.116866 # Number of seconds simulated 4sim_ticks 1116865668500 # Number of ticks simulated 5final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 243832 # Simulator instruction rate (inst/s) 8host_op_rate 262692 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 176313668 # Simulator tick rate (ticks/s) 10host_mem_usage 266900 # Number of bytes of host memory used 11host_seconds 6334.54 # Real time elapsed on the host	7host_inst_rate 380135 # Simulator instruction rate (inst/s) 8host_op_rate 409538 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 274873670 # Simulator tick rate (ticks/s) 10host_mem_usage 314372 # Number of bytes of host memory used 11host_seconds 4063.20 # Real time elapsed on the host
12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory 18system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory 22system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory --- 255 unchanged lines hidden (view full) --- 279system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ) 280system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ) 281system.physmem_1.averagePower 733.256935 # Core power per rank (mW) 282system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states 283system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states 284system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 285system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states 286system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states	17system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory 19system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory 23system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory --- 255 unchanged lines hidden (view full) --- 280system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ) 281system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ) 282system.physmem_1.averagePower 733.256935 # Core power per rank (mW) 283system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states 284system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states 285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 286system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states 287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
	288system.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
287system.cpu.branchPred.lookups 239639355 # Number of BP lookups 288system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted 289system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect 290system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups 291system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits 292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 293system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage 294system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target. 295system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 296system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups. 297system.cpu.branchPred.indirectHits 230 # Number of indirect target hits. 298system.cpu.branchPred.indirectMisses 307 # Number of indirect misses. 299system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches. 300system.cpu_clk_domain.clock 500 # Clock period in ticks	289system.cpu.branchPred.lookups 239639355 # Number of BP lookups 290system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted 291system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect 292system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups 293system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits 294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 295system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage 296system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target. 297system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 298system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups. 299system.cpu.branchPred.indirectHits 230 # Number of indirect target hits. 300system.cpu.branchPred.indirectMisses 307 # Number of indirect misses. 301system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches. 302system.cpu_clk_domain.clock 500 # Clock period in ticks
	303system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
301system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 322system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 323system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 324system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 325system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 326system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 327system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 328system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 329system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	333system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
330system.cpu.dtb.walker.walks 0 # Table walker walks requested 331system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 351system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 352system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 353system.cpu.dtb.read_accesses 0 # DTB read accesses 354system.cpu.dtb.write_accesses 0 # DTB write accesses 355system.cpu.dtb.inst_accesses 0 # ITB inst accesses 356system.cpu.dtb.hits 0 # DTB hits 357system.cpu.dtb.misses 0 # DTB misses 358system.cpu.dtb.accesses 0 # DTB accesses	334system.cpu.dtb.walker.walks 0 # Table walker walks requested 335system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.dtb.read_accesses 0 # DTB read accesses 358system.cpu.dtb.write_accesses 0 # DTB write accesses 359system.cpu.dtb.inst_accesses 0 # ITB inst accesses 360system.cpu.dtb.hits 0 # DTB hits 361system.cpu.dtb.misses 0 # DTB misses 362system.cpu.dtb.accesses 0 # DTB accesses
	363system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
359system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 380system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 381system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 382system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 383system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 384system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 385system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 386system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 387system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	364system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 385system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 386system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 388system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 389system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 390system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 391system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 392system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	393system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
388system.cpu.itb.walker.walks 0 # Table walker walks requested 389system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 410system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 411system.cpu.itb.read_accesses 0 # DTB read accesses 412system.cpu.itb.write_accesses 0 # DTB write accesses 413system.cpu.itb.inst_accesses 0 # ITB inst accesses 414system.cpu.itb.hits 0 # DTB hits 415system.cpu.itb.misses 0 # DTB misses 416system.cpu.itb.accesses 0 # DTB accesses 417system.cpu.workload.num_syscalls 46 # Number of system calls	394system.cpu.itb.walker.walks 0 # Table walker walks requested 395system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 397system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 416system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 417system.cpu.itb.read_accesses 0 # DTB read accesses 418system.cpu.itb.write_accesses 0 # DTB write accesses 419system.cpu.itb.inst_accesses 0 # ITB inst accesses 420system.cpu.itb.hits 0 # DTB hits 421system.cpu.itb.misses 0 # DTB misses 422system.cpu.itb.accesses 0 # DTB accesses 423system.cpu.workload.num_syscalls 46 # Number of system calls
	424system.cpu.pwrStateResidencyTicks::ON 1116865668500 # Cumulative time (in ticks) in various power states
418system.cpu.numCycles 2233731337 # number of cpu cycles simulated 419system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 420system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 421system.cpu.committedInsts 1544563088 # Number of instructions committed 422system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed 423system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit 424system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 425system.cpu.cpi 1.446190 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 456system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 457system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 458system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction 459system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 460system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 461system.cpu.op_class_0::total 1664032481 # Class of committed instruction 462system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked 463system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped	425system.cpu.numCycles 2233731337 # number of cpu cycles simulated 426system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 427system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 428system.cpu.committedInsts 1544563088 # Number of instructions committed 429system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed 430system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit 431system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 432system.cpu.cpi 1.446190 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 463system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction 464system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction 465system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction 466system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 467system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 468system.cpu.op_class_0::total 1664032481 # Class of committed instruction 469system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked 470system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped
	471system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
464system.cpu.dcache.tags.replacements 9221041 # number of replacements 465system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use 466system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks. 467system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks. 468system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks. 469system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. 470system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor 471system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy 472system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy 473system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 474system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id 475system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id 476system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id 477system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 478system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 479system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses 480system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses	472system.cpu.dcache.tags.replacements 9221041 # number of replacements 473system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use 474system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks. 475system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks. 476system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks. 477system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. 478system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor 479system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy 480system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy 481system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 482system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id 483system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id 484system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id 485system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 486system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 487system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses 488system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses
	489system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
481system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits 482system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits 483system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits 484system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits 485system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 486system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 487system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 488system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 593system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency 594system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency 595system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency 596system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency 597system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency 598system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency 599system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency 600system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency	490system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits 491system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits 492system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits 493system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits 494system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 495system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 496system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 497system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 602system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency 603system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency 604system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency 605system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency 606system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency 607system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency 608system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency 609system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency
	610system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
601system.cpu.icache.tags.replacements 29 # number of replacements 602system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use 603system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. 604system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. 605system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks. 606system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 607system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor 608system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy 609system.cpu.icache.tags.occ_percent::total 0.322454 # Average percentage of cache occupancy 610system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id 611system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id 614system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id 615system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses 616system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses	611system.cpu.icache.tags.replacements 29 # number of replacements 612system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use 613system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. 614system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. 615system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks. 616system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 617system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor 618system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy 619system.cpu.icache.tags.occ_percent::total 0.322454 # Average percentage of cache occupancy 620system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id 621system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 622system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 623system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id 624system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id 625system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses 626system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses
	627system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
617system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits 618system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits 619system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits 620system.cpu.icache.demand_hits::total 465281510 # number of demand (read+write) hits 621system.cpu.icache.overall_hits::cpu.inst 465281510 # number of overall hits 622system.cpu.icache.overall_hits::total 465281510 # number of overall hits 623system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses 624system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 677system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 678system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 679system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency 680system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency 681system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency 682system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency 683system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency 684system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency	628system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits 629system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits 630system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits 631system.cpu.icache.demand_hits::total 465281510 # number of demand (read+write) hits 632system.cpu.icache.overall_hits::cpu.inst 465281510 # number of overall hits 633system.cpu.icache.overall_hits::total 465281510 # number of overall hits 634system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses 635system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 688system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 689system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 690system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency 691system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency 692system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency 693system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency 694system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency 695system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
	696system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
685system.cpu.l2cache.tags.replacements 2013919 # number of replacements 686system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use 687system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. 688system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks. 689system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks. 690system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. 691system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor 692system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 699system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 700system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 701system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id 702system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id 704system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id 705system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses 706system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses	697system.cpu.l2cache.tags.replacements 2013919 # number of replacements 698system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use 699system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. 700system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks. 701system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks. 702system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. 703system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor 704system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 711system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id 712system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 713system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id 714system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id 715system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id 716system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id 717system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses 718system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses
	719system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
707system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits 708system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits 709system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits 710system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits 711system.cpu.l2cache.ReadExReq_hits::cpu.data 1089694 # number of ReadExReq hits 712system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits 713system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits 714system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits --- 136 unchanged lines hidden (view full) --- 851system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency 852system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency 853system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter. 854system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. 855system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 856system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. 857system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 858system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	720system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits 721system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits 722system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits 723system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits 724system.cpu.l2cache.ReadExReq_hits::cpu.data 1089694 # number of ReadExReq hits 725system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits 726system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits 727system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits --- 136 unchanged lines hidden (view full) --- 864system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency 865system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency 866system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter. 867system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. 868system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 869system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. 870system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 871system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	872system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
859system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution 860system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution 861system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution 862system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution 866system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 883system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 884system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram 885system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks) 886system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 887system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) 888system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 889system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks) 890system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)	873system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution 875system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution 876system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution 877system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution 879system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution 880system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 897system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 898system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram 899system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks) 900system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 901system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks) 902system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 903system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks) 904system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)
	905system.membus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states
891system.membus.trans_dist::ReadResp 1245432 # Transaction distribution 892system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution 893system.membus.trans_dist::CleanEvict 962724 # Transaction distribution 894system.membus.trans_dist::ReadExReq 801159 # Transaction distribution 895system.membus.trans_dist::ReadExResp 801159 # Transaction distribution 896system.membus.trans_dist::ReadSharedReq 1245432 # Transaction distribution 897system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106029 # Packet count per connected master and slave (bytes) 898system.membus.pkt_count::total 6106029 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden ---	906system.membus.trans_dist::ReadResp 1245432 # Transaction distribution 907system.membus.trans_dist::WritebackDirty 1050123 # Transaction distribution 908system.membus.trans_dist::CleanEvict 962724 # Transaction distribution 909system.membus.trans_dist::ReadExReq 801159 # Transaction distribution 910system.membus.trans_dist::ReadExResp 801159 # Transaction distribution 911system.membus.trans_dist::ReadSharedReq 1245432 # Transaction distribution 912system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106029 # Packet count per connected master and slave (bytes) 913system.membus.pkt_count::total 6106029 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.116866 # Number of seconds simulated
4sim_ticks 1116865668500 # Number of ticks simulated
5final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 243832 # Simulator instruction rate (inst/s)
8host_op_rate 262692 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 176313668 # Simulator tick rate (ticks/s)
10host_mem_usage 266900 # Number of bytes of host memory used
11host_seconds 6334.54 # Real time elapsed on the host

7host_inst_rate 380135 # Simulator instruction rate (inst/s)
8host_op_rate 409538 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 274873670 # Simulator tick rate (ticks/s)
10host_mem_usage 314372 # Number of bytes of host memory used
11host_seconds 4063.20 # Real time elapsed on the host

12sim_insts 1544563088 # Number of instructions simulated
13sim_ops 1664032481 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory
18system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory
22system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory

--- 255 unchanged lines hidden (view full) ---

279system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ)
280system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ)
281system.physmem_1.averagePower 733.256935 # Core power per rank (mW)
282system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states
283system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states
284system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
285system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states
286system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

17system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory
19system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 50112 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory
23system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 783 # Number of read requests responded to by this memory

--- 255 unchanged lines hidden (view full) ---

280system.physmem_1.preBackEnergy 293542830000 # Energy for precharge background per rank (pJ)
281system.physmem_1.totalEnergy 818945301360 # Total energy per rank (pJ)
282system.physmem_1.averagePower 733.256935 # Core power per rank (mW)
283system.physmem_1.memoryStateTime::IDLE 485580062750 # Time in different power states
284system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states
285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
286system.physmem_1.memoryStateTime::ACT 593987729250 # Time in different power states
287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

288system.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

287system.cpu.branchPred.lookups 239639355 # Number of BP lookups
288system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted
289system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect
290system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups
291system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits
292system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
293system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage
294system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target.
295system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
296system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups.
297system.cpu.branchPred.indirectHits 230 # Number of indirect target hits.
298system.cpu.branchPred.indirectMisses 307 # Number of indirect misses.
299system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches.
300system.cpu_clk_domain.clock 500 # Clock period in ticks

289system.cpu.branchPred.lookups 239639355 # Number of BP lookups
290system.cpu.branchPred.condPredicted 186342486 # Number of conditional branches predicted
291system.cpu.branchPred.condIncorrect 14526193 # Number of conditional branches incorrect
292system.cpu.branchPred.BTBLookups 130646338 # Number of BTB lookups
293system.cpu.branchPred.BTBHits 122079091 # Number of BTB hits
294system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
295system.cpu.branchPred.BTBHitPct 93.442413 # BTB Hit Percentage
296system.cpu.branchPred.usedRAS 15657057 # Number of times the RAS was used to get a target.
297system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
298system.cpu.branchPred.indirectLookups 537 # Number of indirect predictor lookups.
299system.cpu.branchPred.indirectHits 230 # Number of indirect target hits.
300system.cpu.branchPred.indirectMisses 307 # Number of indirect misses.
301system.cpu.branchPredindirectMispredicted 164 # Number of mispredicted indirect branches.
302system.cpu_clk_domain.clock 500 # Clock period in ticks

303system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

301system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

322system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
323system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
324system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
325system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
326system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
327system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
328system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
329system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

304system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

325system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
326system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
327system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
328system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
329system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
330system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
331system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
332system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

333system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

330system.cpu.dtb.walker.walks 0 # Table walker walks requested
331system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
332system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
333system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
334system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
335system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
336system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
337system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

351system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
352system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
353system.cpu.dtb.read_accesses 0 # DTB read accesses
354system.cpu.dtb.write_accesses 0 # DTB write accesses
355system.cpu.dtb.inst_accesses 0 # ITB inst accesses
356system.cpu.dtb.hits 0 # DTB hits
357system.cpu.dtb.misses 0 # DTB misses
358system.cpu.dtb.accesses 0 # DTB accesses

334system.cpu.dtb.walker.walks 0 # Table walker walks requested
335system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
336system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
337system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
338system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
339system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
340system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
341system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

355system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
356system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
357system.cpu.dtb.read_accesses 0 # DTB read accesses
358system.cpu.dtb.write_accesses 0 # DTB write accesses
359system.cpu.dtb.inst_accesses 0 # ITB inst accesses
360system.cpu.dtb.hits 0 # DTB hits
361system.cpu.dtb.misses 0 # DTB misses
362system.cpu.dtb.accesses 0 # DTB accesses

363system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

359system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

380system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
381system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
382system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
383system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
384system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
385system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
386system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
387system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

364system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

385system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
386system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
387system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
388system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
389system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
390system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
391system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
392system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

393system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

388system.cpu.itb.walker.walks 0 # Table walker walks requested
389system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
390system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
391system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
392system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
393system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
394system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
395system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

410system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
411system.cpu.itb.read_accesses 0 # DTB read accesses
412system.cpu.itb.write_accesses 0 # DTB write accesses
413system.cpu.itb.inst_accesses 0 # ITB inst accesses
414system.cpu.itb.hits 0 # DTB hits
415system.cpu.itb.misses 0 # DTB misses
416system.cpu.itb.accesses 0 # DTB accesses
417system.cpu.workload.num_syscalls 46 # Number of system calls

394system.cpu.itb.walker.walks 0 # Table walker walks requested
395system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
396system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
397system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
398system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
399system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
400system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
401system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

416system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
417system.cpu.itb.read_accesses 0 # DTB read accesses
418system.cpu.itb.write_accesses 0 # DTB write accesses
419system.cpu.itb.inst_accesses 0 # ITB inst accesses
420system.cpu.itb.hits 0 # DTB hits
421system.cpu.itb.misses 0 # DTB misses
422system.cpu.itb.accesses 0 # DTB accesses
423system.cpu.workload.num_syscalls 46 # Number of system calls

424system.cpu.pwrStateResidencyTicks::ON 1116865668500 # Cumulative time (in ticks) in various power states

418system.cpu.numCycles 2233731337 # number of cpu cycles simulated
419system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
420system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
421system.cpu.committedInsts 1544563088 # Number of instructions committed
422system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed
423system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit
424system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
425system.cpu.cpi 1.446190 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

456system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
457system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
458system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction
459system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
460system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
461system.cpu.op_class_0::total 1664032481 # Class of committed instruction
462system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked
463system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped

425system.cpu.numCycles 2233731337 # number of cpu cycles simulated
426system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
427system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
428system.cpu.committedInsts 1544563088 # Number of instructions committed
429system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed
430system.cpu.discardedOps 41470388 # Number of ops (including micro ops) which were discarded before commit
431system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
432system.cpu.cpi 1.446190 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

463system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 61.95% # Class of committed instruction
464system.cpu.op_class_0::MemRead 458306334 27.54% 89.49% # Class of committed instruction
465system.cpu.op_class_0::MemWrite 174847046 10.51% 100.00% # Class of committed instruction
466system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
467system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
468system.cpu.op_class_0::total 1664032481 # Class of committed instruction
469system.cpu.tickCycles 1834123667 # Number of cycles that the object actually ticked
470system.cpu.idleCycles 399607670 # Total number of cycles that the object has spent stopped

471system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

464system.cpu.dcache.tags.replacements 9221041 # number of replacements
465system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use
466system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks.
467system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks.
468system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks.
469system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit.
470system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor
471system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy
472system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy
473system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
474system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id
475system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id
476system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id
477system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
478system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
479system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses
480system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses

472system.cpu.dcache.tags.replacements 9221041 # number of replacements
473system.cpu.dcache.tags.tagsinuse 4085.616095 # Cycle average of tags in use
474system.cpu.dcache.tags.total_refs 624218928 # Total number of references to valid blocks.
475system.cpu.dcache.tags.sampled_refs 9225137 # Sample count of references to valid blocks.
476system.cpu.dcache.tags.avg_refs 67.665004 # Average number of references to valid blocks.
477system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit.
478system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616095 # Average occupied blocks per requestor
479system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy
480system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy
481system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
482system.cpu.dcache.tags.age_task_id_blocks_1024::0 251 # Occupied blocks per task id
483system.cpu.dcache.tags.age_task_id_blocks_1024::1 1231 # Occupied blocks per task id
484system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id
485system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
486system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
487system.cpu.dcache.tags.tag_accesses 1276841941 # Number of tag accesses
488system.cpu.dcache.tags.data_accesses 1276841941 # Number of data accesses

489system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

481system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits
482system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits
483system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits
484system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits
485system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
486system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
487system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
488system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

593system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency
594system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency
595system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency
596system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency
597system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency
598system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency
599system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency
600system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency

490system.cpu.dcache.ReadReq_hits::cpu.data 453887732 # number of ReadReq hits
491system.cpu.dcache.ReadReq_hits::total 453887732 # number of ReadReq hits
492system.cpu.dcache.WriteReq_hits::cpu.data 170331073 # number of WriteReq hits
493system.cpu.dcache.WriteReq_hits::total 170331073 # number of WriteReq hits
494system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits
495system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits
496system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits
497system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

602system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency
603system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency
604system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency
605system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency
606system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency
607system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency
608system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency
609system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency

610system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

601system.cpu.icache.tags.replacements 29 # number of replacements
602system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use
603system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks.
604system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks.
605system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks.
606system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
607system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor
608system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy
609system.cpu.icache.tags.occ_percent::total 0.322454 # Average percentage of cache occupancy
610system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id
611system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
612system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
613system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id
614system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id
615system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses
616system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses

611system.cpu.icache.tags.replacements 29 # number of replacements
612system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use
613system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks.
614system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks.
615system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks.
616system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
617system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor
618system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy
619system.cpu.icache.tags.occ_percent::total 0.322454 # Average percentage of cache occupancy
620system.cpu.icache.tags.occ_task_id_blocks::1024 790 # Occupied blocks per task id
621system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
622system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
623system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id
624system.cpu.icache.tags.occ_task_id_percent::1024 0.385742 # Percentage of cache occupancy per task id
625system.cpu.icache.tags.tag_accesses 930565477 # Number of tag accesses
626system.cpu.icache.tags.data_accesses 930565477 # Number of data accesses

627system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

617system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits
618system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits
619system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits
620system.cpu.icache.demand_hits::total 465281510 # number of demand (read+write) hits
621system.cpu.icache.overall_hits::cpu.inst 465281510 # number of overall hits
622system.cpu.icache.overall_hits::total 465281510 # number of overall hits
623system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses
624system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

677system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
678system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
679system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency
680system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency
681system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency
682system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
683system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency
684system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency

628system.cpu.icache.ReadReq_hits::cpu.inst 465281510 # number of ReadReq hits
629system.cpu.icache.ReadReq_hits::total 465281510 # number of ReadReq hits
630system.cpu.icache.demand_hits::cpu.inst 465281510 # number of demand (read+write) hits
631system.cpu.icache.demand_hits::total 465281510 # number of demand (read+write) hits
632system.cpu.icache.overall_hits::cpu.inst 465281510 # number of overall hits
633system.cpu.icache.overall_hits::total 465281510 # number of overall hits
634system.cpu.icache.ReadReq_misses::cpu.inst 819 # number of ReadReq misses
635system.cpu.icache.ReadReq_misses::total 819 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

688system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
689system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
690system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency
691system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency
692system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency
693system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency
694system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency
695system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency

696system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

685system.cpu.l2cache.tags.replacements 2013919 # number of replacements
686system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use
687system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks.
688system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks.
689system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks.
690system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit.
691system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor
692system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor

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699system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
700system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
701system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id
702system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
703system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id
704system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
705system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses
706system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses

697system.cpu.l2cache.tags.replacements 2013919 # number of replacements
698system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use
699system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks.
700system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks.
701system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks.
702system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit.
703system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor
704system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

711system.cpu.l2cache.tags.age_task_id_blocks_1024::0 93 # Occupied blocks per task id
712system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
713system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1250 # Occupied blocks per task id
714system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
715system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15553 # Occupied blocks per task id
716system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
717system.cpu.l2cache.tags.tag_accesses 151498004 # Number of tag accesses
718system.cpu.l2cache.tags.data_accesses 151498004 # Number of data accesses

719system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

707system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits
708system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits
709system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits
710system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits
711system.cpu.l2cache.ReadExReq_hits::cpu.data 1089694 # number of ReadExReq hits
712system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits
713system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits
714system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits

--- 136 unchanged lines hidden (view full) ---

851system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency
852system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency
853system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter.
854system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data.
855system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
856system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter.
857system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
858system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

720system.cpu.l2cache.WritebackDirty_hits::writebacks 3684567 # number of WritebackDirty hits
721system.cpu.l2cache.WritebackDirty_hits::total 3684567 # number of WritebackDirty hits
722system.cpu.l2cache.WritebackClean_hits::writebacks 29 # number of WritebackClean hits
723system.cpu.l2cache.WritebackClean_hits::total 29 # number of WritebackClean hits
724system.cpu.l2cache.ReadExReq_hits::cpu.data 1089694 # number of ReadExReq hits
725system.cpu.l2cache.ReadExReq_hits::total 1089694 # number of ReadExReq hits
726system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 36 # number of ReadCleanReq hits
727system.cpu.l2cache.ReadCleanReq_hits::total 36 # number of ReadCleanReq hits

--- 136 unchanged lines hidden (view full) ---

864system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency
865system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency
866system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter.
867system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data.
868system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
869system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter.
870system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
871system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

872system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states

859system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution
860system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution
861system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution
862system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution
863system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution
864system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution
865system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution
866system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution

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883system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
884system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram
885system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks)
886system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
887system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks)
888system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
889system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks)
890system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)

873system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution
874system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution
875system.cpu.toL2Bus.trans_dist::WritebackClean 29 # Transaction distribution
876system.cpu.toL2Bus.trans_dist::CleanEvict 6500270 # Transaction distribution
877system.cpu.toL2Bus.trans_dist::ReadExReq 1890853 # Transaction distribution
878system.cpu.toL2Bus.trans_dist::ReadExResp 1890853 # Transaction distribution
879system.cpu.toL2Bus.trans_dist::ReadCleanReq 819 # Transaction distribution
880system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334284 # Transaction distribution

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897system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
898system.cpu.toL2Bus.snoop_fanout::total 11239875 # Request fanout histogram
899system.cpu.toL2Bus.reqLayer0.occupancy 12908109000 # Layer occupancy (ticks)
900system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
901system.cpu.toL2Bus.respLayer0.occupancy 1228500 # Layer occupancy (ticks)
902system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
903system.cpu.toL2Bus.respLayer1.occupancy 13837707995 # Layer occupancy (ticks)
904system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%)

905system.membus.pwrStateResidencyTicks::UNDEFINED 1116865668500 # Cumulative time (in ticks) in various power states