| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.116866 # Number of seconds simulated 4sim_ticks 1116865668500 # Number of ticks simulated 5final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 1.116866 # Number of seconds simulated 4sim_ticks 1116865668500 # Number of ticks simulated 5final_tick 1116865668500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 315195 # Simulator instruction rate (inst/s) 8host_op_rate 339575 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 227915704 # Simulator tick rate (ticks/s) 10host_mem_usage 272300 # Number of bytes of host memory used 11host_seconds 4900.35 # Real time elapsed on the host | 7host_inst_rate 304077 # Simulator instruction rate (inst/s) 8host_op_rate 327597 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 219876370 # Simulator tick rate (ticks/s) 10host_mem_usage 272296 # Number of bytes of host memory used 11host_seconds 5079.52 # Real time elapsed on the host |
| 12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory 18system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory --- 523 unchanged lines hidden (view full) --- 543system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809 # average overall miss latency 544system.cpu.dcache.overall_avg_miss_latency::total 31285.404809 # average overall miss latency 545system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 546system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 547system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 548system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 549system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 550system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 50112 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 130931712 # Number of bytes read from this memory 18system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 50112 # Number of instructions bytes read from this memory --- 523 unchanged lines hidden (view full) --- 543system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.404809 # average overall miss latency 544system.cpu.dcache.overall_avg_miss_latency::total 31285.404809 # average overall miss latency 545system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 546system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 547system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 548system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 549system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 550system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 551system.cpu.dcache.fast_writes 0 # number of fast writes performed 552system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 553system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks 554system.cpu.dcache.writebacks::total 3684567 # number of writebacks 555system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits 556system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits 557system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364121 # number of WriteReq MSHR hits 558system.cpu.dcache.WriteReq_mshr_hits::total 364121 # number of WriteReq MSHR hits 559system.cpu.dcache.demand_mshr_hits::cpu.data 364336 # number of demand (read+write) MSHR hits 560system.cpu.dcache.demand_mshr_hits::total 364336 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 595system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency 596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency 597system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency 598system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency 599system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency 600system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency 601system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency 602system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency | 551system.cpu.dcache.writebacks::writebacks 3684567 # number of writebacks 552system.cpu.dcache.writebacks::total 3684567 # number of writebacks 553system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits 554system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits 555system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364121 # number of WriteReq MSHR hits 556system.cpu.dcache.WriteReq_mshr_hits::total 364121 # number of WriteReq MSHR hits 557system.cpu.dcache.demand_mshr_hits::cpu.data 364336 # number of demand (read+write) MSHR hits 558system.cpu.dcache.demand_mshr_hits::total 364336 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 593system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44836.568998 # average WriteReq mshr miss latency 594system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44836.568998 # average WriteReq mshr miss latency 595system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency 596system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency 597system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29090.718934 # average overall mshr miss latency 598system.cpu.dcache.demand_avg_mshr_miss_latency::total 29090.718934 # average overall mshr miss latency 599system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29090.723802 # average overall mshr miss latency 600system.cpu.dcache.overall_avg_mshr_miss_latency::total 29090.723802 # average overall mshr miss latency |
| 603system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 604system.cpu.icache.tags.replacements 29 # number of replacements 605system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use 606system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. 607system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. 608system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks. 609system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 610system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor 611system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 654system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency 655system.cpu.icache.overall_avg_miss_latency::total 76193.528694 # average overall miss latency 656system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 657system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 659system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 660system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 661system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 601system.cpu.icache.tags.replacements 29 # number of replacements 602system.cpu.icache.tags.tagsinuse 660.385482 # Cycle average of tags in use 603system.cpu.icache.tags.total_refs 465281510 # Total number of references to valid blocks. 604system.cpu.icache.tags.sampled_refs 819 # Sample count of references to valid blocks. 605system.cpu.icache.tags.avg_refs 568109.291819 # Average number of references to valid blocks. 606system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 607system.cpu.icache.tags.occ_blocks::cpu.inst 660.385482 # Average occupied blocks per requestor 608system.cpu.icache.tags.occ_percent::cpu.inst 0.322454 # Average percentage of cache occupancy --- 42 unchanged lines hidden (view full) --- 651system.cpu.icache.overall_avg_miss_latency::cpu.inst 76193.528694 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::total 76193.528694 # average overall miss latency 653system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 658system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 662system.cpu.icache.fast_writes 0 # number of fast writes performed 663system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 664system.cpu.icache.writebacks::writebacks 29 # number of writebacks 665system.cpu.icache.writebacks::total 29 # number of writebacks 666system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses 667system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses 668system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses 669system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses 670system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses 671system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 682system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 683system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 684system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency 686system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency 688system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency | 659system.cpu.icache.writebacks::writebacks 29 # number of writebacks 660system.cpu.icache.writebacks::total 29 # number of writebacks 661system.cpu.icache.ReadReq_mshr_misses::cpu.inst 819 # number of ReadReq MSHR misses 662system.cpu.icache.ReadReq_mshr_misses::total 819 # number of ReadReq MSHR misses 663system.cpu.icache.demand_mshr_misses::cpu.inst 819 # number of demand (read+write) MSHR misses 664system.cpu.icache.demand_mshr_misses::total 819 # number of demand (read+write) MSHR misses 665system.cpu.icache.overall_mshr_misses::cpu.inst 819 # number of overall MSHR misses 666system.cpu.icache.overall_mshr_misses::total 819 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 677system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 678system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 679system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75193.528694 # average ReadReq mshr miss latency 680system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75193.528694 # average ReadReq mshr miss latency 681system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency 682system.cpu.icache.demand_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency 683system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75193.528694 # average overall mshr miss latency 684system.cpu.icache.overall_avg_mshr_miss_latency::total 75193.528694 # average overall mshr miss latency |
| 690system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 691system.cpu.l2cache.tags.replacements 2013919 # number of replacements 692system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use 693system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. 694system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks. 695system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks. 696system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. 697system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 791system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency 792system.cpu.l2cache.overall_avg_miss_latency::total 87530.028887 # average overall miss latency 793system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 794system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 795system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 796system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 797system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 798system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 685system.cpu.l2cache.tags.replacements 2013919 # number of replacements 686system.cpu.l2cache.tags.tagsinuse 31258.258362 # Cycle average of tags in use 687system.cpu.l2cache.tags.total_refs 14509191 # Total number of references to valid blocks. 688system.cpu.l2cache.tags.sampled_refs 2043695 # Sample count of references to valid blocks. 689system.cpu.l2cache.tags.avg_refs 7.099489 # Average number of references to valid blocks. 690system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. 691system.cpu.l2cache.tags.occ_blocks::writebacks 14832.909506 # Average occupied blocks per requestor 692system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.456768 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 785system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87534.228202 # average overall miss latency 786system.cpu.l2cache.overall_avg_miss_latency::total 87530.028887 # average overall miss latency 787system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 788system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 789system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 790system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 791system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 792system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 799system.cpu.l2cache.fast_writes 0 # number of fast writes performed 800system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 801system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks 802system.cpu.l2cache.writebacks::total 1050123 # number of writebacks 803system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits 804system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 805system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 806system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 807system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 808system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits --- 44 unchanged lines hidden (view full) --- 853system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77283.148502 # average ReadSharedReq mshr miss latency 854system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77283.148502 # average ReadSharedReq mshr miss latency 855system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency 856system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency 857system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency 858system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency 859system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency 860system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency | 793system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks 794system.cpu.l2cache.writebacks::total 1050123 # number of writebacks 795system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits 796system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 797system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 798system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 799system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 800system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits --- 44 unchanged lines hidden (view full) --- 845system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77283.148502 # average ReadSharedReq mshr miss latency 846system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77283.148502 # average ReadSharedReq mshr miss latency 847system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency 848system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency 849system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency 850system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66558.109834 # average overall mshr miss latency 851system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77534.274477 # average overall mshr miss latency 852system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77530.075135 # average overall mshr miss latency |
| 861system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 862system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter. 863system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. 864system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 865system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. 866system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 867system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 868system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution 869system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution --- 57 unchanged lines hidden --- | 853system.cpu.toL2Bus.snoop_filter.tot_requests 18447026 # Total number of requests made to the snoop filter. 854system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221082 # Number of requests hitting in the snoop filter with a single holder of the requested data. 855system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 856system.cpu.toL2Bus.snoop_filter.tot_snoops 1286 # Total number of snoops made to the snoop filter. 857system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1280 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 858system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 859system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution 860system.cpu.toL2Bus.trans_dist::WritebackDirty 4734690 # Transaction distribution --- 57 unchanged lines hidden --- |