| stats.txt (11103:38f6188421e0) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.116876 # Number of seconds simulated 4sim_ticks 1116876142500 # Number of ticks simulated 5final_tick 1116876142500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.116866 # Number of seconds simulated 4sim_ticks 1116865669500 # Number of ticks simulated 5final_tick 1116865669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 161785 # Simulator instruction rate (inst/s) 8host_op_rate 174299 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 116987267 # Simulator tick rate (ticks/s) 10host_mem_usage 309392 # Number of bytes of host memory used 11host_seconds 9546.99 # Real time elapsed on the host | 7host_inst_rate 226280 # Simulator instruction rate (inst/s) 8host_op_rate 243783 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 163622006 # Simulator tick rate (ticks/s) 10host_mem_usage 317884 # Number of bytes of host memory used 11host_seconds 6825.89 # Real time elapsed on the host |
| 12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory | 12sim_insts 1544563088 # Number of instructions simulated 13sim_ops 1664032481 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 130931520 # Number of bytes read from this memory 18system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 130931456 # Number of bytes read from this memory 18system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory |
| 19system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory | 19system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory |
| 21system.physmem.bytes_written::writebacks 67207936 # Number of bytes written to this memory 22system.physmem.bytes_written::total 67207936 # Number of bytes written to this memory | 21system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory 22system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory |
| 23system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory | 23system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::cpu.data 2045805 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1050124 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1050124 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 45097 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 117230116 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 117275213 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 45097 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 45097 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 60174923 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 60174923 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 60174923 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 45097 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 117230116 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 177450137 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 2046592 # Number of read requests accepted 40system.physmem.writeReqs 1050124 # Number of write requests accepted 41system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 1050124 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 130897216 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 84672 # Total number of bytes read from write queue 45system.physmem.bytesWritten 67206464 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 67207936 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 1323 # Number of DRAM read bursts serviced by the write queue | 24system.physmem.num_reads::cpu.data 2045804 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 45098 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 117231158 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 45098 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 45098 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 45098 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 117231158 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 2046591 # Number of read requests accepted 40system.physmem.writeReqs 1050123 # Number of write requests accepted 41system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 130897024 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 84800 # Total number of bytes read from write queue 45system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 1325 # Number of DRAM read bursts serviced by the write queue |
| 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 51system.physmem.perBankRdBursts::0 127284 # Per bank write bursts 52system.physmem.perBankRdBursts::1 124662 # Per bank write bursts 53system.physmem.perBankRdBursts::2 121597 # Per bank write bursts | 51system.physmem.perBankRdBursts::0 127282 # Per bank write bursts 52system.physmem.perBankRdBursts::1 124660 # Per bank write bursts 53system.physmem.perBankRdBursts::2 121599 # Per bank write bursts |
| 54system.physmem.perBankRdBursts::3 123658 # Per bank write bursts | 54system.physmem.perBankRdBursts::3 123658 # Per bank write bursts |
| 55system.physmem.perBankRdBursts::4 122617 # Per bank write bursts | 55system.physmem.perBankRdBursts::4 122616 # Per bank write bursts |
| 56system.physmem.perBankRdBursts::5 122675 # Per bank write bursts 57system.physmem.perBankRdBursts::6 123246 # Per bank write bursts | 56system.physmem.perBankRdBursts::5 122675 # Per bank write bursts 57system.physmem.perBankRdBursts::6 123246 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::7 123759 # Per bank write bursts | 58system.physmem.perBankRdBursts::7 123764 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::8 131397 # Per bank write bursts | 59system.physmem.perBankRdBursts::8 131397 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::9 133511 # Per bank write bursts 61system.physmem.perBankRdBursts::10 132080 # Per bank write bursts 62system.physmem.perBankRdBursts::11 133309 # Per bank write bursts 63system.physmem.perBankRdBursts::12 133252 # Per bank write bursts 64system.physmem.perBankRdBursts::13 133368 # Per bank write bursts 65system.physmem.perBankRdBursts::14 129308 # Per bank write bursts 66system.physmem.perBankRdBursts::15 129546 # Per bank write bursts | 60system.physmem.perBankRdBursts::9 133514 # Per bank write bursts 61system.physmem.perBankRdBursts::10 132084 # Per bank write bursts 62system.physmem.perBankRdBursts::11 133304 # Per bank write bursts 63system.physmem.perBankRdBursts::12 133248 # Per bank write bursts 64system.physmem.perBankRdBursts::13 133365 # Per bank write bursts 65system.physmem.perBankRdBursts::14 129309 # Per bank write bursts 66system.physmem.perBankRdBursts::15 129545 # Per bank write bursts |
| 67system.physmem.perBankWrBursts::0 66136 # Per bank write bursts 68system.physmem.perBankWrBursts::1 64410 # Per bank write bursts 69system.physmem.perBankWrBursts::2 62576 # Per bank write bursts 70system.physmem.perBankWrBursts::3 63006 # Per bank write bursts 71system.physmem.perBankWrBursts::4 63000 # Per bank write bursts 72system.physmem.perBankWrBursts::5 63100 # Per bank write bursts 73system.physmem.perBankWrBursts::6 64443 # Per bank write bursts | 67system.physmem.perBankWrBursts::0 66136 # Per bank write bursts 68system.physmem.perBankWrBursts::1 64410 # Per bank write bursts 69system.physmem.perBankWrBursts::2 62576 # Per bank write bursts 70system.physmem.perBankWrBursts::3 63006 # Per bank write bursts 71system.physmem.perBankWrBursts::4 63000 # Per bank write bursts 72system.physmem.perBankWrBursts::5 63100 # Per bank write bursts 73system.physmem.perBankWrBursts::6 64443 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::7 65435 # Per bank write bursts 75system.physmem.perBankWrBursts::8 67311 # Per bank write bursts 76system.physmem.perBankWrBursts::9 67795 # Per bank write bursts 77system.physmem.perBankWrBursts::10 67548 # Per bank write bursts 78system.physmem.perBankWrBursts::11 67883 # Per bank write bursts 79system.physmem.perBankWrBursts::12 67328 # Per bank write bursts | 74system.physmem.perBankWrBursts::7 65436 # Per bank write bursts 75system.physmem.perBankWrBursts::8 67310 # Per bank write bursts 76system.physmem.perBankWrBursts::9 67797 # Per bank write bursts 77system.physmem.perBankWrBursts::10 67549 # Per bank write bursts 78system.physmem.perBankWrBursts::11 67882 # Per bank write bursts 79system.physmem.perBankWrBursts::12 67326 # Per bank write bursts |
| 80system.physmem.perBankWrBursts::13 67793 # Per bank write bursts | 80system.physmem.perBankWrBursts::13 67793 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::14 66483 # Per bank write bursts | 81system.physmem.perBankWrBursts::14 66482 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::15 65854 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 82system.physmem.perBankWrBursts::15 65854 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 85system.physmem.totGap 1116876049000 # Total gap between requests | 85system.physmem.totGap 1116865575000 # Total gap between requests |
| 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) | 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 92system.physmem.readPktSize::6 2046592 # Read request sizes (log2) | 92system.physmem.readPktSize::6 2046591 # Read request sizes (log2) |
| 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) | 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 99system.physmem.writePktSize::6 1050124 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 1916546 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 128705 # What read queue length does an incoming req see | 99system.physmem.writePktSize::6 1050123 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 1916631 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 128617 # What read queue length does an incoming req see |
| 102system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 102system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 147system.physmem.wrQLenPdf::15 32789 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 34054 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 56903 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 61212 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 61641 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 61693 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 61593 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 61666 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 61641 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 61698 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 61718 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 61664 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 62178 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 62548 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 62056 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 62535 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 61302 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 61133 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 74 # What write queue length does an incoming req see | 147system.physmem.wrQLenPdf::15 32784 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 34018 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 56910 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 61213 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 61610 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 61708 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 61596 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 61643 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 61643 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 61703 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 61754 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 61670 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 62179 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 62537 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 62061 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 62560 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 61129 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 78 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 166system.physmem.wrQLenPdf::34 6 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 196system.physmem.bytesPerActivate::samples 1910492 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 103.692259 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 81.833601 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 125.494474 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 1485528 77.76% 77.76% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 305524 15.99% 93.75% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 52470 2.75% 96.49% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 20903 1.09% 97.59% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 13406 0.70% 98.29% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 7575 0.40% 98.69% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 5481 0.29% 98.97% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 5100 0.27% 99.24% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 14505 0.76% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 1910492 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 61132 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 33.413630 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 160.636391 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 61087 99.93% 99.93% # Reads before turning the bus around for writes | 196system.physmem.bytesPerActivate::samples 1910448 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 103.693777 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 81.830782 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 125.503425 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 1485607 77.76% 77.76% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 305343 15.98% 93.75% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 52494 2.75% 96.49% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 20883 1.09% 97.59% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 13429 0.70% 98.29% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 7609 0.40% 98.69% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 5497 0.29% 98.97% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 5095 0.27% 99.24% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 14491 0.76% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 1910448 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 61128 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 33.415767 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 160.633753 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 61083 99.93% 99.93% # Reads before turning the bus around for writes |
| 214system.physmem.rdPerTurnAround::1024-2047 20 0.03% 99.96% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes | 214system.physmem.rdPerTurnAround::1024-2047 20 0.03% 99.96% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes 219system.physmem.rdPerTurnAround::10240-11263 1 0.00% 100.00% # Reads before turning the bus around for writes 220system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 221system.physmem.rdPerTurnAround::15360-16383 1 0.00% 100.00% # Reads before turning the bus around for writes 222system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 223system.physmem.rdPerTurnAround::total 61132 # Reads before turning the bus around for writes 224system.physmem.wrPerTurnAround::samples 61132 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::mean 17.177599 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::gmean 17.142637 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::stdev 1.096979 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::16 26963 44.11% 44.11% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::17 1122 1.84% 45.94% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::18 28754 47.04% 92.98% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::19 3885 6.36% 99.33% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::20 352 0.58% 99.91% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::21 46 0.08% 99.98% # Writes before turning the bus around for reads | 223system.physmem.rdPerTurnAround::total 61128 # Reads before turning the bus around for writes 224system.physmem.wrPerTurnAround::samples 61128 # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::mean 17.178707 # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::gmean 17.143614 # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::stdev 1.099153 # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::16 26983 44.14% 44.14% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::17 1095 1.79% 45.93% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::18 28688 46.93% 92.86% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::19 3942 6.45% 99.31% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::20 361 0.59% 99.90% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads |
| 234system.physmem.wrPerTurnAround::22 8 0.01% 100.00% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads | 234system.physmem.wrPerTurnAround::22 8 0.01% 100.00% # Writes before turning the bus around for reads 235system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads 236system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads |
| 237system.physmem.wrPerTurnAround::total 61132 # Writes before turning the bus around for reads 238system.physmem.totQLat 38139021250 # Total ticks spent queuing 239system.physmem.totMemAccLat 76487815000 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 10226345000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 18647.44 # Average queueing delay per DRAM burst | 237system.physmem.wrPerTurnAround::total 61128 # Writes before turning the bus around for reads 238system.physmem.totQLat 38113681000 # Total ticks spent queuing 239system.physmem.totMemAccLat 76462418500 # Total ticks spent from burst creation until serviced by the DRAM 240system.physmem.totBusLat 10226330000 # Total ticks spent in databus transfers 241system.physmem.avgQLat 18635.07 # Average queueing delay per DRAM burst |
| 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 242system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 243system.physmem.avgMemAccLat 37397.44 # Average memory access latency per DRAM burst | 243system.physmem.avgMemAccLat 37385.07 # Average memory access latency per DRAM burst |
| 244system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s | 244system.physmem.avgRdBW 117.20 # Average DRAM read bandwidth in MiByte/s 245system.physmem.avgWrBW 60.17 # Average achieved write bandwidth in MiByte/s 246system.physmem.avgRdBWSys 117.28 # Average system read bandwidth in MiByte/s |
| 247system.physmem.avgWrBWSys 60.17 # Average system write bandwidth in MiByte/s | 247system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s |
| 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 1.39 # Data bus utilization in percentage 250system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing | 248system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 249system.physmem.busUtil 1.39 # Data bus utilization in percentage 250system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads 251system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes 252system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 253system.physmem.avgWrQLen 24.35 # Average write queue length when enqueuing |
| 254system.physmem.readRowHits 773003 # Number of row buffer hits during reads 255system.physmem.writeRowHits 411872 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 37.79 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes 258system.physmem.avgGap 360664.67 # Average gap between requests | 254system.physmem.readRowHits 773150 # Number of row buffer hits during reads 255system.physmem.writeRowHits 411758 # Number of row buffer hits during writes 256system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads 257system.physmem.writeRowHitRate 39.21 # Row buffer hit rate for writes 258system.physmem.avgGap 360661.52 # Average gap between requests |
| 259system.physmem.pageHitRate 38.28 # Row buffer hit rate, read and write combined | 259system.physmem.pageHitRate 38.28 # Row buffer hit rate, read and write combined |
| 260system.physmem_0.actEnergy 7041119400 # Energy for activate commands per rank (pJ) 261system.physmem_0.preEnergy 3841880625 # Energy for precharge commands per rank (pJ) 262system.physmem_0.readEnergy 7718053200 # Energy for read commands per rank (pJ) 263system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ) 264system.physmem_0.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) 265system.physmem_0.actBackEnergy 420554384415 # Energy for active background per rank (pJ) 266system.physmem_0.preBackEnergy 301217964750 # Energy for precharge background per rank (pJ) 267system.physmem_0.totalEnergy 816640712790 # Total energy per rank (pJ) 268system.physmem_0.averagePower 731.183278 # Core power per rank (mW) 269system.physmem_0.memoryStateTime::IDLE 498392390000 # Time in different power states 270system.physmem_0.memoryStateTime::REF 37294920000 # Time in different power states | 260system.physmem_0.actEnergy 7040439000 # Energy for activate commands per rank (pJ) 261system.physmem_0.preEnergy 3841509375 # Energy for precharge commands per rank (pJ) 262system.physmem_0.readEnergy 7717788000 # Energy for read commands per rank (pJ) 263system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ) 264system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) 265system.physmem_0.actBackEnergy 420410239110 # Energy for active background per rank (pJ) 266system.physmem_0.preBackEnergy 301335056250 # Energy for precharge background per rank (pJ) 267system.physmem_0.totalEnergy 816611331495 # Total energy per rank (pJ) 268system.physmem_0.averagePower 731.167175 # Core power per rank (mW) 269system.physmem_0.memoryStateTime::IDLE 498591665750 # Time in different power states 270system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states |
| 271system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 271system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 272system.physmem_0.memoryStateTime::ACT 581188236250 # Time in different power states | 272system.physmem_0.memoryStateTime::ACT 580976292250 # Time in different power states |
| 273system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 273system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 274system.physmem_1.actEnergy 7402200120 # Energy for activate commands per rank (pJ) 275system.physmem_1.preEnergy 4038898875 # Energy for precharge commands per rank (pJ) 276system.physmem_1.readEnergy 8234990400 # Energy for read commands per rank (pJ) 277system.physmem_1.writeEnergy 3486207600 # Energy for write commands per rank (pJ) 278system.physmem_1.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ) 279system.physmem_1.actBackEnergy 429475728015 # Energy for active background per rank (pJ) 280system.physmem_1.preBackEnergy 293392224750 # Energy for precharge background per rank (pJ) 281system.physmem_1.totalEnergy 818979113280 # Total energy per rank (pJ) 282system.physmem_1.averagePower 733.276976 # Core power per rank (mW) 283system.physmem_1.memoryStateTime::IDLE 485326311500 # Time in different power states 284system.physmem_1.memoryStateTime::REF 37294920000 # Time in different power states | 274system.physmem_1.actEnergy 7402532760 # Energy for activate commands per rank (pJ) 275system.physmem_1.preEnergy 4039080375 # Energy for precharge commands per rank (pJ) 276system.physmem_1.readEnergy 8234920200 # Energy for read commands per rank (pJ) 277system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ) 278system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ) 279system.physmem_1.actBackEnergy 429557025690 # Energy for active background per rank (pJ) 280system.physmem_1.preBackEnergy 293311559250 # Energy for precharge background per rank (pJ) 281system.physmem_1.totalEnergy 818979159315 # Total energy per rank (pJ) 282system.physmem_1.averagePower 733.287251 # Core power per rank (mW) 283system.physmem_1.memoryStateTime::IDLE 485194866750 # Time in different power states 284system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states |
| 285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 285system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 286system.physmem_1.memoryStateTime::ACT 594254742500 # Time in different power states | 286system.physmem_1.memoryStateTime::ACT 594372992750 # Time in different power states |
| 287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 287system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 288system.cpu.branchPred.lookups 239639069 # Number of BP lookups 289system.cpu.branchPred.condPredicted 186342280 # Number of conditional branches predicted | 288system.cpu.branchPred.lookups 239639075 # Number of BP lookups 289system.cpu.branchPred.condPredicted 186342287 # Number of conditional branches predicted |
| 290system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect | 290system.cpu.branchPred.condIncorrect 14526140 # Number of conditional branches incorrect |
| 291system.cpu.branchPred.BTBLookups 130646098 # Number of BTB lookups 292system.cpu.branchPred.BTBHits 122079384 # Number of BTB hits | 291system.cpu.branchPred.BTBLookups 130646101 # Number of BTB lookups 292system.cpu.branchPred.BTBHits 122079387 # Number of BTB hits |
| 293system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 294system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage 295system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. 296system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 297system.cpu_clk_domain.clock 500 # Clock period in ticks 298system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst --- 106 unchanged lines hidden (view full) --- 407system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu.itb.read_accesses 0 # DTB read accesses 409system.cpu.itb.write_accesses 0 # DTB write accesses 410system.cpu.itb.inst_accesses 0 # ITB inst accesses 411system.cpu.itb.hits 0 # DTB hits 412system.cpu.itb.misses 0 # DTB misses 413system.cpu.itb.accesses 0 # DTB accesses 414system.cpu.workload.num_syscalls 46 # Number of system calls | 293system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 294system.cpu.branchPred.BTBHitPct 93.442809 # BTB Hit Percentage 295system.cpu.branchPred.usedRAS 15657029 # Number of times the RAS was used to get a target. 296system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 297system.cpu_clk_domain.clock 500 # Clock period in ticks 298system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst --- 106 unchanged lines hidden (view full) --- 407system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu.itb.read_accesses 0 # DTB read accesses 409system.cpu.itb.write_accesses 0 # DTB write accesses 410system.cpu.itb.inst_accesses 0 # ITB inst accesses 411system.cpu.itb.hits 0 # DTB hits 412system.cpu.itb.misses 0 # DTB misses 413system.cpu.itb.accesses 0 # DTB accesses 414system.cpu.workload.num_syscalls 46 # Number of system calls |
| 415system.cpu.numCycles 2233752285 # number of cpu cycles simulated | 415system.cpu.numCycles 2233731339 # number of cpu cycles simulated |
| 416system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 417system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 418system.cpu.committedInsts 1544563088 # Number of instructions committed 419system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed | 416system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 417system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 418system.cpu.committedInsts 1544563088 # Number of instructions committed 419system.cpu.committedOps 1664032481 # Number of ops (including micro ops) committed |
| 420system.cpu.discardedOps 41470092 # Number of ops (including micro ops) which were discarded before commit | 420system.cpu.discardedOps 41470082 # Number of ops (including micro ops) which were discarded before commit |
| 421system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 421system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 422system.cpu.cpi 1.446203 # CPI: cycles per instruction 423system.cpu.ipc 0.691466 # IPC: instructions per cycle 424system.cpu.tickCycles 1834122948 # Number of cycles that the object actually ticked 425system.cpu.idleCycles 399629337 # Total number of cycles that the object has spent stopped | 422system.cpu.cpi 1.446190 # CPI: cycles per instruction 423system.cpu.ipc 0.691472 # IPC: instructions per cycle 424system.cpu.tickCycles 1834124286 # Number of cycles that the object actually ticked 425system.cpu.idleCycles 399607053 # Total number of cycles that the object has spent stopped |
| 426system.cpu.dcache.tags.replacements 9221039 # number of replacements | 426system.cpu.dcache.tags.replacements 9221039 # number of replacements |
| 427system.cpu.dcache.tags.tagsinuse 4085.616333 # Cycle average of tags in use 428system.cpu.dcache.tags.total_refs 624218905 # Total number of references to valid blocks. | 427system.cpu.dcache.tags.tagsinuse 4085.616235 # Cycle average of tags in use 428system.cpu.dcache.tags.total_refs 624218894 # Total number of references to valid blocks. |
| 429system.cpu.dcache.tags.sampled_refs 9225135 # Sample count of references to valid blocks. | 429system.cpu.dcache.tags.sampled_refs 9225135 # Sample count of references to valid blocks. |
| 430system.cpu.dcache.tags.avg_refs 67.665016 # Average number of references to valid blocks. | 430system.cpu.dcache.tags.avg_refs 67.665015 # Average number of references to valid blocks. |
| 431system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. | 431system.cpu.dcache.tags.warmup_cycle 9804990500 # Cycle when the warmup percentage was hit. |
| 432system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616333 # Average occupied blocks per requestor | 432system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616235 # Average occupied blocks per requestor |
| 433system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy 434system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy 435system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 433system.cpu.dcache.tags.occ_percent::cpu.data 0.997465 # Average percentage of cache occupancy 434system.cpu.dcache.tags.occ_percent::total 0.997465 # Average percentage of cache occupancy 435system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 436system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id 437system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id | 436system.cpu.dcache.tags.age_task_id_blocks_1024::0 253 # Occupied blocks per task id 437system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id |
| 438system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id 439system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 440system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 438system.cpu.dcache.tags.age_task_id_blocks_1024::2 2553 # Occupied blocks per task id 439system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 440system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 441system.cpu.dcache.tags.tag_accesses 1276841915 # Number of tag accesses 442system.cpu.dcache.tags.data_accesses 1276841915 # Number of data accesses 443system.cpu.dcache.ReadReq_hits::cpu.data 453887721 # number of ReadReq hits 444system.cpu.dcache.ReadReq_hits::total 453887721 # number of ReadReq hits 445system.cpu.dcache.WriteReq_hits::cpu.data 170331061 # number of WriteReq hits 446system.cpu.dcache.WriteReq_hits::total 170331061 # number of WriteReq hits | 441system.cpu.dcache.tags.tag_accesses 1276841917 # Number of tag accesses 442system.cpu.dcache.tags.data_accesses 1276841917 # Number of data accesses 443system.cpu.dcache.ReadReq_hits::cpu.data 453887722 # number of ReadReq hits 444system.cpu.dcache.ReadReq_hits::total 453887722 # number of ReadReq hits 445system.cpu.dcache.WriteReq_hits::cpu.data 170331049 # number of WriteReq hits 446system.cpu.dcache.WriteReq_hits::total 170331049 # number of WriteReq hits |
| 447system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 448system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 449system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 450system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 451system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 452system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits | 447system.cpu.dcache.SoftPFReq_hits::cpu.data 1 # number of SoftPFReq hits 448system.cpu.dcache.SoftPFReq_hits::total 1 # number of SoftPFReq hits 449system.cpu.dcache.LoadLockedReq_hits::cpu.data 61 # number of LoadLockedReq hits 450system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 451system.cpu.dcache.StoreCondReq_hits::cpu.data 61 # number of StoreCondReq hits 452system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits |
| 453system.cpu.dcache.demand_hits::cpu.data 624218782 # number of demand (read+write) hits 454system.cpu.dcache.demand_hits::total 624218782 # number of demand (read+write) hits 455system.cpu.dcache.overall_hits::cpu.data 624218783 # number of overall hits 456system.cpu.dcache.overall_hits::total 624218783 # number of overall hits | 453system.cpu.dcache.demand_hits::cpu.data 624218771 # number of demand (read+write) hits 454system.cpu.dcache.demand_hits::total 624218771 # number of demand (read+write) hits 455system.cpu.dcache.overall_hits::cpu.data 624218772 # number of overall hits 456system.cpu.dcache.overall_hits::total 624218772 # number of overall hits |
| 457system.cpu.dcache.ReadReq_misses::cpu.data 7334497 # number of ReadReq misses 458system.cpu.dcache.ReadReq_misses::total 7334497 # number of ReadReq misses | 457system.cpu.dcache.ReadReq_misses::cpu.data 7334497 # number of ReadReq misses 458system.cpu.dcache.ReadReq_misses::total 7334497 # number of ReadReq misses |
| 459system.cpu.dcache.WriteReq_misses::cpu.data 2254986 # number of WriteReq misses 460system.cpu.dcache.WriteReq_misses::total 2254986 # number of WriteReq misses | 459system.cpu.dcache.WriteReq_misses::cpu.data 2254998 # number of WriteReq misses 460system.cpu.dcache.WriteReq_misses::total 2254998 # number of WriteReq misses |
| 461system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 462system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses | 461system.cpu.dcache.SoftPFReq_misses::cpu.data 2 # number of SoftPFReq misses 462system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses |
| 463system.cpu.dcache.demand_misses::cpu.data 9589483 # number of demand (read+write) misses 464system.cpu.dcache.demand_misses::total 9589483 # number of demand (read+write) misses 465system.cpu.dcache.overall_misses::cpu.data 9589485 # number of overall misses 466system.cpu.dcache.overall_misses::total 9589485 # number of overall misses 467system.cpu.dcache.ReadReq_miss_latency::cpu.data 190949826000 # number of ReadReq miss cycles 468system.cpu.dcache.ReadReq_miss_latency::total 190949826000 # number of ReadReq miss cycles 469system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060330000 # number of WriteReq miss cycles 470system.cpu.dcache.WriteReq_miss_latency::total 109060330000 # number of WriteReq miss cycles 471system.cpu.dcache.demand_miss_latency::cpu.data 300010156000 # number of demand (read+write) miss cycles 472system.cpu.dcache.demand_miss_latency::total 300010156000 # number of demand (read+write) miss cycles 473system.cpu.dcache.overall_miss_latency::cpu.data 300010156000 # number of overall miss cycles 474system.cpu.dcache.overall_miss_latency::total 300010156000 # number of overall miss cycles 475system.cpu.dcache.ReadReq_accesses::cpu.data 461222218 # number of ReadReq accesses(hits+misses) 476system.cpu.dcache.ReadReq_accesses::total 461222218 # number of ReadReq accesses(hits+misses) | 463system.cpu.dcache.demand_misses::cpu.data 9589495 # number of demand (read+write) misses 464system.cpu.dcache.demand_misses::total 9589495 # number of demand (read+write) misses 465system.cpu.dcache.overall_misses::cpu.data 9589497 # number of overall misses 466system.cpu.dcache.overall_misses::total 9589497 # number of overall misses 467system.cpu.dcache.ReadReq_miss_latency::cpu.data 190935436500 # number of ReadReq miss cycles 468system.cpu.dcache.ReadReq_miss_latency::total 190935436500 # number of ReadReq miss cycles 469system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060065500 # number of WriteReq miss cycles 470system.cpu.dcache.WriteReq_miss_latency::total 109060065500 # number of WriteReq miss cycles 471system.cpu.dcache.demand_miss_latency::cpu.data 299995502000 # number of demand (read+write) miss cycles 472system.cpu.dcache.demand_miss_latency::total 299995502000 # number of demand (read+write) miss cycles 473system.cpu.dcache.overall_miss_latency::cpu.data 299995502000 # number of overall miss cycles 474system.cpu.dcache.overall_miss_latency::total 299995502000 # number of overall miss cycles 475system.cpu.dcache.ReadReq_accesses::cpu.data 461222219 # number of ReadReq accesses(hits+misses) 476system.cpu.dcache.ReadReq_accesses::total 461222219 # number of ReadReq accesses(hits+misses) |
| 477system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 478system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 479system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) 480system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) 481system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) | 477system.cpu.dcache.WriteReq_accesses::cpu.data 172586047 # number of WriteReq accesses(hits+misses) 478system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 479system.cpu.dcache.SoftPFReq_accesses::cpu.data 3 # number of SoftPFReq accesses(hits+misses) 480system.cpu.dcache.SoftPFReq_accesses::total 3 # number of SoftPFReq accesses(hits+misses) 481system.cpu.dcache.LoadLockedReq_accesses::cpu.data 61 # number of LoadLockedReq accesses(hits+misses) 482system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 483system.cpu.dcache.StoreCondReq_accesses::cpu.data 61 # number of StoreCondReq accesses(hits+misses) 484system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) |
| 485system.cpu.dcache.demand_accesses::cpu.data 633808265 # number of demand (read+write) accesses 486system.cpu.dcache.demand_accesses::total 633808265 # number of demand (read+write) accesses 487system.cpu.dcache.overall_accesses::cpu.data 633808268 # number of overall (read+write) accesses 488system.cpu.dcache.overall_accesses::total 633808268 # number of overall (read+write) accesses | 485system.cpu.dcache.demand_accesses::cpu.data 633808266 # number of demand (read+write) accesses 486system.cpu.dcache.demand_accesses::total 633808266 # number of demand (read+write) accesses 487system.cpu.dcache.overall_accesses::cpu.data 633808269 # number of overall (read+write) accesses 488system.cpu.dcache.overall_accesses::total 633808269 # number of overall (read+write) accesses |
| 489system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses 490system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses 491system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses 492system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses 493system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses 494system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses 495system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses 496system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses 497system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses 498system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses | 489system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015902 # miss rate for ReadReq accesses 490system.cpu.dcache.ReadReq_miss_rate::total 0.015902 # miss rate for ReadReq accesses 491system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013066 # miss rate for WriteReq accesses 492system.cpu.dcache.WriteReq_miss_rate::total 0.013066 # miss rate for WriteReq accesses 493system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.666667 # miss rate for SoftPFReq accesses 494system.cpu.dcache.SoftPFReq_miss_rate::total 0.666667 # miss rate for SoftPFReq accesses 495system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses 496system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses 497system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses 498system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses |
| 499system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26034.481438 # average ReadReq miss latency 500system.cpu.dcache.ReadReq_avg_miss_latency::total 26034.481438 # average ReadReq miss latency 501system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48364.082970 # average WriteReq miss latency 502system.cpu.dcache.WriteReq_avg_miss_latency::total 48364.082970 # average WriteReq miss latency 503system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.331649 # average overall miss latency 504system.cpu.dcache.demand_avg_miss_latency::total 31285.331649 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.325124 # average overall miss latency 506system.cpu.dcache.overall_avg_miss_latency::total 31285.325124 # average overall miss latency | 499system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26032.519544 # average ReadReq miss latency 500system.cpu.dcache.ReadReq_avg_miss_latency::total 26032.519544 # average ReadReq miss latency 501system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48363.708305 # average WriteReq miss latency 502system.cpu.dcache.WriteReq_avg_miss_latency::total 48363.708305 # average WriteReq miss latency 503system.cpu.dcache.demand_avg_miss_latency::cpu.data 31283.764369 # average overall miss latency 504system.cpu.dcache.demand_avg_miss_latency::total 31283.764369 # average overall miss latency 505system.cpu.dcache.overall_avg_miss_latency::cpu.data 31283.757845 # average overall miss latency 506system.cpu.dcache.overall_avg_miss_latency::total 31283.757845 # average overall miss latency |
| 507system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 508system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 509system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 510system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 511system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 512system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 513system.cpu.dcache.fast_writes 0 # number of fast writes performed 514system.cpu.dcache.cache_copies 0 # number of cache copies performed 515system.cpu.dcache.writebacks::writebacks 3684564 # number of writebacks 516system.cpu.dcache.writebacks::total 3684564 # number of writebacks 517system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits 518system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits | 507system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 508system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 509system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 510system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 511system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 512system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 513system.cpu.dcache.fast_writes 0 # number of fast writes performed 514system.cpu.dcache.cache_copies 0 # number of cache copies performed 515system.cpu.dcache.writebacks::writebacks 3684564 # number of writebacks 516system.cpu.dcache.writebacks::total 3684564 # number of writebacks 517system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits 518system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits |
| 519system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364134 # number of WriteReq MSHR hits 520system.cpu.dcache.WriteReq_mshr_hits::total 364134 # number of WriteReq MSHR hits 521system.cpu.dcache.demand_mshr_hits::cpu.data 364349 # number of demand (read+write) MSHR hits 522system.cpu.dcache.demand_mshr_hits::total 364349 # number of demand (read+write) MSHR hits 523system.cpu.dcache.overall_mshr_hits::cpu.data 364349 # number of overall MSHR hits 524system.cpu.dcache.overall_mshr_hits::total 364349 # number of overall MSHR hits | 519system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364146 # number of WriteReq MSHR hits 520system.cpu.dcache.WriteReq_mshr_hits::total 364146 # number of WriteReq MSHR hits 521system.cpu.dcache.demand_mshr_hits::cpu.data 364361 # number of demand (read+write) MSHR hits 522system.cpu.dcache.demand_mshr_hits::total 364361 # number of demand (read+write) MSHR hits 523system.cpu.dcache.overall_mshr_hits::cpu.data 364361 # number of overall MSHR hits 524system.cpu.dcache.overall_mshr_hits::total 364361 # number of overall MSHR hits |
| 525system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334282 # number of ReadReq MSHR misses 526system.cpu.dcache.ReadReq_mshr_misses::total 7334282 # number of ReadReq MSHR misses 527system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890852 # number of WriteReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::total 1890852 # number of WriteReq MSHR misses 529system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 530system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 531system.cpu.dcache.demand_mshr_misses::cpu.data 9225134 # number of demand (read+write) MSHR misses 532system.cpu.dcache.demand_mshr_misses::total 9225134 # number of demand (read+write) MSHR misses 533system.cpu.dcache.overall_mshr_misses::cpu.data 9225135 # number of overall MSHR misses 534system.cpu.dcache.overall_mshr_misses::total 9225135 # number of overall MSHR misses | 525system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7334282 # number of ReadReq MSHR misses 526system.cpu.dcache.ReadReq_mshr_misses::total 7334282 # number of ReadReq MSHR misses 527system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890852 # number of WriteReq MSHR misses 528system.cpu.dcache.WriteReq_mshr_misses::total 1890852 # number of WriteReq MSHR misses 529system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 1 # number of SoftPFReq MSHR misses 530system.cpu.dcache.SoftPFReq_mshr_misses::total 1 # number of SoftPFReq MSHR misses 531system.cpu.dcache.demand_mshr_misses::cpu.data 9225134 # number of demand (read+write) MSHR misses 532system.cpu.dcache.demand_mshr_misses::total 9225134 # number of demand (read+write) MSHR misses 533system.cpu.dcache.overall_mshr_misses::cpu.data 9225135 # number of overall MSHR misses 534system.cpu.dcache.overall_mshr_misses::total 9225135 # number of overall MSHR misses |
| 535system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183609818500 # number of ReadReq MSHR miss cycles 536system.cpu.dcache.ReadReq_mshr_miss_latency::total 183609818500 # number of ReadReq MSHR miss cycles 537system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84766639000 # number of WriteReq MSHR miss cycles 538system.cpu.dcache.WriteReq_mshr_miss_latency::total 84766639000 # number of WriteReq MSHR miss cycles | 535system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183595384500 # number of ReadReq MSHR miss cycles 536system.cpu.dcache.ReadReq_mshr_miss_latency::total 183595384500 # number of ReadReq MSHR miss cycles 537system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84757207500 # number of WriteReq MSHR miss cycles 538system.cpu.dcache.WriteReq_mshr_miss_latency::total 84757207500 # number of WriteReq MSHR miss cycles |
| 539system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles 540system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles | 539system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 74000 # number of SoftPFReq MSHR miss cycles 540system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 74000 # number of SoftPFReq MSHR miss cycles |
| 541system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268376457500 # number of demand (read+write) MSHR miss cycles 542system.cpu.dcache.demand_mshr_miss_latency::total 268376457500 # number of demand (read+write) MSHR miss cycles 543system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268376531500 # number of overall MSHR miss cycles 544system.cpu.dcache.overall_mshr_miss_latency::total 268376531500 # number of overall MSHR miss cycles | 541system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268352592000 # number of demand (read+write) MSHR miss cycles 542system.cpu.dcache.demand_mshr_miss_latency::total 268352592000 # number of demand (read+write) MSHR miss cycles 543system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268352666000 # number of overall MSHR miss cycles 544system.cpu.dcache.overall_mshr_miss_latency::total 268352666000 # number of overall MSHR miss cycles |
| 545system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses 546system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses 547system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 548system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 549system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses 550system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses 551system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for demand accesses 552system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses 553system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses 554system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses | 545system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015902 # mshr miss rate for ReadReq accesses 546system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015902 # mshr miss rate for ReadReq accesses 547system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.010956 # mshr miss rate for WriteReq accesses 548system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 549system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses 550system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses 551system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for demand accesses 552system.cpu.dcache.demand_mshr_miss_rate::total 0.014555 # mshr miss rate for demand accesses 553system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014555 # mshr miss rate for overall accesses 554system.cpu.dcache.overall_mshr_miss_rate::total 0.014555 # mshr miss rate for overall accesses |
| 555system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25034.463973 # average ReadReq mshr miss latency 556system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25034.463973 # average ReadReq mshr miss latency 557system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44829.864527 # average WriteReq mshr miss latency 558system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44829.864527 # average WriteReq mshr miss latency | 555system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25032.495955 # average ReadReq mshr miss latency 556system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25032.495955 # average ReadReq mshr miss latency 557system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44824.876564 # average WriteReq mshr miss latency 558system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44824.876564 # average WriteReq mshr miss latency |
| 559system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency 560system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency | 559system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74000 # average SoftPFReq mshr miss latency 560system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74000 # average SoftPFReq mshr miss latency |
| 561system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.876335 # average overall mshr miss latency 562system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.876335 # average overall mshr miss latency 563system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.881203 # average overall mshr miss latency 564system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.881203 # average overall mshr miss latency | 561system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29089.289326 # average overall mshr miss latency 562system.cpu.dcache.demand_avg_mshr_miss_latency::total 29089.289326 # average overall mshr miss latency 563system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29089.294195 # average overall mshr miss latency 564system.cpu.dcache.overall_avg_mshr_miss_latency::total 29089.294195 # average overall mshr miss latency |
| 565system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 566system.cpu.icache.tags.replacements 29 # number of replacements | 565system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 566system.cpu.icache.tags.replacements 29 # number of replacements |
| 567system.cpu.icache.tags.tagsinuse 661.386126 # Cycle average of tags in use 568system.cpu.icache.tags.total_refs 465281345 # Total number of references to valid blocks. | 567system.cpu.icache.tags.tagsinuse 661.385274 # Cycle average of tags in use 568system.cpu.icache.tags.total_refs 465281545 # Total number of references to valid blocks. |
| 569system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. | 569system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. |
| 570system.cpu.icache.tags.avg_refs 567416.274390 # Average number of references to valid blocks. | 570system.cpu.icache.tags.avg_refs 567416.518293 # Average number of references to valid blocks. |
| 571system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 571system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 572system.cpu.icache.tags.occ_blocks::cpu.inst 661.386126 # Average occupied blocks per requestor | 572system.cpu.icache.tags.occ_blocks::cpu.inst 661.385274 # Average occupied blocks per requestor |
| 573system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy 574system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy 575system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id 576system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 577system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 578system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id 579system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id | 573system.cpu.icache.tags.occ_percent::cpu.inst 0.322942 # Average percentage of cache occupancy 574system.cpu.icache.tags.occ_percent::total 0.322942 # Average percentage of cache occupancy 575system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id 576system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 577system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 578system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id 579system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id |
| 580system.cpu.icache.tags.tag_accesses 930565150 # Number of tag accesses 581system.cpu.icache.tags.data_accesses 930565150 # Number of data accesses 582system.cpu.icache.ReadReq_hits::cpu.inst 465281345 # number of ReadReq hits 583system.cpu.icache.ReadReq_hits::total 465281345 # number of ReadReq hits 584system.cpu.icache.demand_hits::cpu.inst 465281345 # number of demand (read+write) hits 585system.cpu.icache.demand_hits::total 465281345 # number of demand (read+write) hits 586system.cpu.icache.overall_hits::cpu.inst 465281345 # number of overall hits 587system.cpu.icache.overall_hits::total 465281345 # number of overall hits | 580system.cpu.icache.tags.tag_accesses 930565550 # Number of tag accesses 581system.cpu.icache.tags.data_accesses 930565550 # Number of data accesses 582system.cpu.icache.ReadReq_hits::cpu.inst 465281545 # number of ReadReq hits 583system.cpu.icache.ReadReq_hits::total 465281545 # number of ReadReq hits 584system.cpu.icache.demand_hits::cpu.inst 465281545 # number of demand (read+write) hits 585system.cpu.icache.demand_hits::total 465281545 # number of demand (read+write) hits 586system.cpu.icache.overall_hits::cpu.inst 465281545 # number of overall hits 587system.cpu.icache.overall_hits::total 465281545 # number of overall hits |
| 588system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses 589system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses 590system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses 591system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses 592system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses 593system.cpu.icache.overall_misses::total 820 # number of overall misses | 588system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses 589system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses 590system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses 591system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses 592system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses 593system.cpu.icache.overall_misses::total 820 # number of overall misses |
| 594system.cpu.icache.ReadReq_miss_latency::cpu.inst 62363500 # number of ReadReq miss cycles 595system.cpu.icache.ReadReq_miss_latency::total 62363500 # number of ReadReq miss cycles 596system.cpu.icache.demand_miss_latency::cpu.inst 62363500 # number of demand (read+write) miss cycles 597system.cpu.icache.demand_miss_latency::total 62363500 # number of demand (read+write) miss cycles 598system.cpu.icache.overall_miss_latency::cpu.inst 62363500 # number of overall miss cycles 599system.cpu.icache.overall_miss_latency::total 62363500 # number of overall miss cycles 600system.cpu.icache.ReadReq_accesses::cpu.inst 465282165 # number of ReadReq accesses(hits+misses) 601system.cpu.icache.ReadReq_accesses::total 465282165 # number of ReadReq accesses(hits+misses) 602system.cpu.icache.demand_accesses::cpu.inst 465282165 # number of demand (read+write) accesses 603system.cpu.icache.demand_accesses::total 465282165 # number of demand (read+write) accesses 604system.cpu.icache.overall_accesses::cpu.inst 465282165 # number of overall (read+write) accesses 605system.cpu.icache.overall_accesses::total 465282165 # number of overall (read+write) accesses | 594system.cpu.icache.ReadReq_miss_latency::cpu.inst 62174000 # number of ReadReq miss cycles 595system.cpu.icache.ReadReq_miss_latency::total 62174000 # number of ReadReq miss cycles 596system.cpu.icache.demand_miss_latency::cpu.inst 62174000 # number of demand (read+write) miss cycles 597system.cpu.icache.demand_miss_latency::total 62174000 # number of demand (read+write) miss cycles 598system.cpu.icache.overall_miss_latency::cpu.inst 62174000 # number of overall miss cycles 599system.cpu.icache.overall_miss_latency::total 62174000 # number of overall miss cycles 600system.cpu.icache.ReadReq_accesses::cpu.inst 465282365 # number of ReadReq accesses(hits+misses) 601system.cpu.icache.ReadReq_accesses::total 465282365 # number of ReadReq accesses(hits+misses) 602system.cpu.icache.demand_accesses::cpu.inst 465282365 # number of demand (read+write) accesses 603system.cpu.icache.demand_accesses::total 465282365 # number of demand (read+write) accesses 604system.cpu.icache.overall_accesses::cpu.inst 465282365 # number of overall (read+write) accesses 605system.cpu.icache.overall_accesses::total 465282365 # number of overall (read+write) accesses |
| 606system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 607system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 608system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 609system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 610system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 611system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses | 606system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 607system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 608system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 609system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 610system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 611system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses |
| 612system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.048780 # average ReadReq miss latency 613system.cpu.icache.ReadReq_avg_miss_latency::total 76053.048780 # average ReadReq miss latency 614system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency 615system.cpu.icache.demand_avg_miss_latency::total 76053.048780 # average overall miss latency 616system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency 617system.cpu.icache.overall_avg_miss_latency::total 76053.048780 # average overall miss latency | 612system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75821.951220 # average ReadReq miss latency 613system.cpu.icache.ReadReq_avg_miss_latency::total 75821.951220 # average ReadReq miss latency 614system.cpu.icache.demand_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency 615system.cpu.icache.demand_avg_miss_latency::total 75821.951220 # average overall miss latency 616system.cpu.icache.overall_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency 617system.cpu.icache.overall_avg_miss_latency::total 75821.951220 # average overall miss latency |
| 618system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 619system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 620system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 621system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 622system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 623system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 624system.cpu.icache.fast_writes 0 # number of fast writes performed 625system.cpu.icache.cache_copies 0 # number of cache copies performed 626system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses 627system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses 628system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses 629system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses 630system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses 631system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses | 618system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 619system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 620system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 621system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 622system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 623system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 624system.cpu.icache.fast_writes 0 # number of fast writes performed 625system.cpu.icache.cache_copies 0 # number of cache copies performed 626system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses 627system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses 628system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses 629system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses 630system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses 631system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses |
| 632system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61543500 # number of ReadReq MSHR miss cycles 633system.cpu.icache.ReadReq_mshr_miss_latency::total 61543500 # number of ReadReq MSHR miss cycles 634system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61543500 # number of demand (read+write) MSHR miss cycles 635system.cpu.icache.demand_mshr_miss_latency::total 61543500 # number of demand (read+write) MSHR miss cycles 636system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61543500 # number of overall MSHR miss cycles 637system.cpu.icache.overall_mshr_miss_latency::total 61543500 # number of overall MSHR miss cycles | 632system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61354000 # number of ReadReq MSHR miss cycles 633system.cpu.icache.ReadReq_mshr_miss_latency::total 61354000 # number of ReadReq MSHR miss cycles 634system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61354000 # number of demand (read+write) MSHR miss cycles 635system.cpu.icache.demand_mshr_miss_latency::total 61354000 # number of demand (read+write) MSHR miss cycles 636system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61354000 # number of overall MSHR miss cycles 637system.cpu.icache.overall_mshr_miss_latency::total 61354000 # number of overall MSHR miss cycles |
| 638system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 640system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 641system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 642system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 643system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses | 638system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 639system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 640system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 641system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 642system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 643system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses |
| 644system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.048780 # average ReadReq mshr miss latency 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.048780 # average ReadReq mshr miss latency 646system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency 648system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency | 644system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74821.951220 # average ReadReq mshr miss latency 645system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74821.951220 # average ReadReq mshr miss latency 646system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency 647system.cpu.icache.demand_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency 648system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency 649system.cpu.icache.overall_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency |
| 650system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 650system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 651system.cpu.l2cache.tags.replacements 2013891 # number of replacements 652system.cpu.l2cache.tags.tagsinuse 31258.308104 # Cycle average of tags in use 653system.cpu.l2cache.tags.total_refs 14509189 # Total number of references to valid blocks. 654system.cpu.l2cache.tags.sampled_refs 2043666 # Sample count of references to valid blocks. 655system.cpu.l2cache.tags.avg_refs 7.099589 # Average number of references to valid blocks. | 651system.cpu.l2cache.tags.replacements 2013890 # number of replacements 652system.cpu.l2cache.tags.tagsinuse 31258.297879 # Cycle average of tags in use 653system.cpu.l2cache.tags.total_refs 14509190 # Total number of references to valid blocks. 654system.cpu.l2cache.tags.sampled_refs 2043665 # Sample count of references to valid blocks. 655system.cpu.l2cache.tags.avg_refs 7.099593 # Average number of references to valid blocks. |
| 656system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. | 656system.cpu.l2cache.tags.warmup_cycle 59769702000 # Cycle when the warmup percentage was hit. |
| 657system.cpu.l2cache.tags.occ_blocks::writebacks 14832.412998 # Average occupied blocks per requestor 658system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588444 # Average occupied blocks per requestor 659system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.306662 # Average occupied blocks per requestor 660system.cpu.l2cache.tags.occ_percent::writebacks 0.452649 # Average percentage of cache occupancy | 657system.cpu.l2cache.tags.occ_blocks::writebacks 14832.420356 # Average occupied blocks per requestor 658system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588666 # Average occupied blocks per requestor 659system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.288857 # Average occupied blocks per requestor 660system.cpu.l2cache.tags.occ_percent::writebacks 0.452650 # Average percentage of cache occupancy |
| 661system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000811 # Average percentage of cache occupancy 662system.cpu.l2cache.tags.occ_percent::cpu.data 0.500467 # Average percentage of cache occupancy 663system.cpu.l2cache.tags.occ_percent::total 0.953928 # Average percentage of cache occupancy 664system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id 665system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 666system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 667system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id 668system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id 669system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15557 # Occupied blocks per task id 670system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id | 661system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000811 # Average percentage of cache occupancy 662system.cpu.l2cache.tags.occ_percent::cpu.data 0.500467 # Average percentage of cache occupancy 663system.cpu.l2cache.tags.occ_percent::total 0.953928 # Average percentage of cache occupancy 664system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id 665system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 666system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 667system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id 668system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id 669system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15557 # Occupied blocks per task id 670system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id |
| 671system.cpu.l2cache.tags.tag_accesses 151497950 # Number of tag accesses 672system.cpu.l2cache.tags.data_accesses 151497950 # Number of data accesses | 671system.cpu.l2cache.tags.tag_accesses 151497949 # Number of tag accesses 672system.cpu.l2cache.tags.data_accesses 151497949 # Number of data accesses |
| 673system.cpu.l2cache.Writeback_hits::writebacks 3684564 # number of Writeback hits 674system.cpu.l2cache.Writeback_hits::total 3684564 # number of Writeback hits | 673system.cpu.l2cache.Writeback_hits::writebacks 3684564 # number of Writeback hits 674system.cpu.l2cache.Writeback_hits::total 3684564 # number of Writeback hits |
| 675system.cpu.l2cache.ReadExReq_hits::cpu.data 1089696 # number of ReadExReq hits 676system.cpu.l2cache.ReadExReq_hits::total 1089696 # number of ReadExReq hits | 675system.cpu.l2cache.ReadExReq_hits::cpu.data 1089697 # number of ReadExReq hits 676system.cpu.l2cache.ReadExReq_hits::total 1089697 # number of ReadExReq hits |
| 677system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 32 # number of ReadCleanReq hits 678system.cpu.l2cache.ReadCleanReq_hits::total 32 # number of ReadCleanReq hits 679system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits 680system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits 681system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits | 677system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 32 # number of ReadCleanReq hits 678system.cpu.l2cache.ReadCleanReq_hits::total 32 # number of ReadCleanReq hits 679system.cpu.l2cache.ReadSharedReq_hits::cpu.data 6089630 # number of ReadSharedReq hits 680system.cpu.l2cache.ReadSharedReq_hits::total 6089630 # number of ReadSharedReq hits 681system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits |
| 682system.cpu.l2cache.demand_hits::cpu.data 7179326 # number of demand (read+write) hits 683system.cpu.l2cache.demand_hits::total 7179358 # number of demand (read+write) hits | 682system.cpu.l2cache.demand_hits::cpu.data 7179327 # number of demand (read+write) hits 683system.cpu.l2cache.demand_hits::total 7179359 # number of demand (read+write) hits |
| 684system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits | 684system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits |
| 685system.cpu.l2cache.overall_hits::cpu.data 7179326 # number of overall hits 686system.cpu.l2cache.overall_hits::total 7179358 # number of overall hits 687system.cpu.l2cache.ReadExReq_misses::cpu.data 801156 # number of ReadExReq misses 688system.cpu.l2cache.ReadExReq_misses::total 801156 # number of ReadExReq misses | 685system.cpu.l2cache.overall_hits::cpu.data 7179327 # number of overall hits 686system.cpu.l2cache.overall_hits::total 7179359 # number of overall hits 687system.cpu.l2cache.ReadExReq_misses::cpu.data 801155 # number of ReadExReq misses 688system.cpu.l2cache.ReadExReq_misses::total 801155 # number of ReadExReq misses |
| 689system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 788 # number of ReadCleanReq misses 690system.cpu.l2cache.ReadCleanReq_misses::total 788 # number of ReadCleanReq misses 691system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244653 # number of ReadSharedReq misses 692system.cpu.l2cache.ReadSharedReq_misses::total 1244653 # number of ReadSharedReq misses 693system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses | 689system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 788 # number of ReadCleanReq misses 690system.cpu.l2cache.ReadCleanReq_misses::total 788 # number of ReadCleanReq misses 691system.cpu.l2cache.ReadSharedReq_misses::cpu.data 1244653 # number of ReadSharedReq misses 692system.cpu.l2cache.ReadSharedReq_misses::total 1244653 # number of ReadSharedReq misses 693system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses |
| 694system.cpu.l2cache.demand_misses::cpu.data 2045809 # number of demand (read+write) misses 695system.cpu.l2cache.demand_misses::total 2046597 # number of demand (read+write) misses | 694system.cpu.l2cache.demand_misses::cpu.data 2045808 # number of demand (read+write) misses 695system.cpu.l2cache.demand_misses::total 2046596 # number of demand (read+write) misses |
| 696system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses | 696system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses |
| 697system.cpu.l2cache.overall_misses::cpu.data 2045809 # number of overall misses 698system.cpu.l2cache.overall_misses::total 2046597 # number of overall misses 699system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70430633500 # number of ReadExReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::total 70430633500 # number of ReadExReq miss cycles 701system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59976000 # number of ReadCleanReq miss cycles 702system.cpu.l2cache.ReadCleanReq_miss_latency::total 59976000 # number of ReadCleanReq miss cycles 703system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108661637000 # number of ReadSharedReq miss cycles 704system.cpu.l2cache.ReadSharedReq_miss_latency::total 108661637000 # number of ReadSharedReq miss cycles 705system.cpu.l2cache.demand_miss_latency::cpu.inst 59976000 # number of demand (read+write) miss cycles 706system.cpu.l2cache.demand_miss_latency::cpu.data 179092270500 # number of demand (read+write) miss cycles 707system.cpu.l2cache.demand_miss_latency::total 179152246500 # number of demand (read+write) miss cycles 708system.cpu.l2cache.overall_miss_latency::cpu.inst 59976000 # number of overall miss cycles 709system.cpu.l2cache.overall_miss_latency::cpu.data 179092270500 # number of overall miss cycles 710system.cpu.l2cache.overall_miss_latency::total 179152246500 # number of overall miss cycles | 697system.cpu.l2cache.overall_misses::cpu.data 2045808 # number of overall misses 698system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses 699system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70421216500 # number of ReadExReq miss cycles 700system.cpu.l2cache.ReadExReq_miss_latency::total 70421216500 # number of ReadExReq miss cycles 701system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59756500 # number of ReadCleanReq miss cycles 702system.cpu.l2cache.ReadCleanReq_miss_latency::total 59756500 # number of ReadCleanReq miss cycles 703system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108645799000 # number of ReadSharedReq miss cycles 704system.cpu.l2cache.ReadSharedReq_miss_latency::total 108645799000 # number of ReadSharedReq miss cycles 705system.cpu.l2cache.demand_miss_latency::cpu.inst 59756500 # number of demand (read+write) miss cycles 706system.cpu.l2cache.demand_miss_latency::cpu.data 179067015500 # number of demand (read+write) miss cycles 707system.cpu.l2cache.demand_miss_latency::total 179126772000 # number of demand (read+write) miss cycles 708system.cpu.l2cache.overall_miss_latency::cpu.inst 59756500 # number of overall miss cycles 709system.cpu.l2cache.overall_miss_latency::cpu.data 179067015500 # number of overall miss cycles 710system.cpu.l2cache.overall_miss_latency::total 179126772000 # number of overall miss cycles |
| 711system.cpu.l2cache.Writeback_accesses::writebacks 3684564 # number of Writeback accesses(hits+misses) 712system.cpu.l2cache.Writeback_accesses::total 3684564 # number of Writeback accesses(hits+misses) 713system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890852 # number of ReadExReq accesses(hits+misses) 714system.cpu.l2cache.ReadExReq_accesses::total 1890852 # number of ReadExReq accesses(hits+misses) 715system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 820 # number of ReadCleanReq accesses(hits+misses) 716system.cpu.l2cache.ReadCleanReq_accesses::total 820 # number of ReadCleanReq accesses(hits+misses) 717system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7334283 # number of ReadSharedReq accesses(hits+misses) 718system.cpu.l2cache.ReadSharedReq_accesses::total 7334283 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 729system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169703 # miss rate for ReadSharedReq accesses 730system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169703 # miss rate for ReadSharedReq accesses 731system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960976 # miss rate for demand accesses 732system.cpu.l2cache.demand_miss_rate::cpu.data 0.221765 # miss rate for demand accesses 733system.cpu.l2cache.demand_miss_rate::total 0.221830 # miss rate for demand accesses 734system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses 735system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses 736system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses | 711system.cpu.l2cache.Writeback_accesses::writebacks 3684564 # number of Writeback accesses(hits+misses) 712system.cpu.l2cache.Writeback_accesses::total 3684564 # number of Writeback accesses(hits+misses) 713system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890852 # number of ReadExReq accesses(hits+misses) 714system.cpu.l2cache.ReadExReq_accesses::total 1890852 # number of ReadExReq accesses(hits+misses) 715system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 820 # number of ReadCleanReq accesses(hits+misses) 716system.cpu.l2cache.ReadCleanReq_accesses::total 820 # number of ReadCleanReq accesses(hits+misses) 717system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 7334283 # number of ReadSharedReq accesses(hits+misses) 718system.cpu.l2cache.ReadSharedReq_accesses::total 7334283 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 729system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.169703 # miss rate for ReadSharedReq accesses 730system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.169703 # miss rate for ReadSharedReq accesses 731system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960976 # miss rate for demand accesses 732system.cpu.l2cache.demand_miss_rate::cpu.data 0.221765 # miss rate for demand accesses 733system.cpu.l2cache.demand_miss_rate::total 0.221830 # miss rate for demand accesses 734system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses 735system.cpu.l2cache.overall_miss_rate::cpu.data 0.221765 # miss rate for overall accesses 736system.cpu.l2cache.overall_miss_rate::total 0.221830 # miss rate for overall accesses |
| 737system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87911.260104 # average ReadExReq miss latency 738system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87911.260104 # average ReadExReq miss latency 739system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76111.675127 # average ReadCleanReq miss latency 740system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76111.675127 # average ReadCleanReq miss latency 741system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87302.755869 # average ReadSharedReq miss latency 742system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87302.755869 # average ReadSharedReq miss latency 743system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency 744system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency 745system.cpu.l2cache.demand_avg_miss_latency::total 87536.650596 # average overall miss latency 746system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency 747system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency 748system.cpu.l2cache.overall_avg_miss_latency::total 87536.650596 # average overall miss latency | 737system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87899.615555 # average ReadExReq miss latency 738system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87899.615555 # average ReadExReq miss latency 739system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75833.121827 # average ReadCleanReq miss latency 740system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75833.121827 # average ReadCleanReq miss latency 741system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87290.031037 # average ReadSharedReq miss latency 742system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87290.031037 # average ReadSharedReq miss latency 743system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency 744system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency 745system.cpu.l2cache.demand_avg_miss_latency::total 87524.246114 # average overall miss latency 746system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency 747system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency 748system.cpu.l2cache.overall_avg_miss_latency::total 87524.246114 # average overall miss latency |
| 749system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 750system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 752system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 753system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 754system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 755system.cpu.l2cache.fast_writes 0 # number of fast writes performed 756system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 749system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 750system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 751system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 752system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 753system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 754system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 755system.cpu.l2cache.fast_writes 0 # number of fast writes performed 756system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 757system.cpu.l2cache.writebacks::writebacks 1050124 # number of writebacks 758system.cpu.l2cache.writebacks::total 1050124 # number of writebacks | 757system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks 758system.cpu.l2cache.writebacks::total 1050123 # number of writebacks |
| 759system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 760system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 761system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits 762system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4 # number of ReadSharedReq MSHR hits 763system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 764system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 765system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 766system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 767system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 768system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 769system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses 770system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses | 759system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 760system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 761system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 4 # number of ReadSharedReq MSHR hits 762system.cpu.l2cache.ReadSharedReq_mshr_hits::total 4 # number of ReadSharedReq MSHR hits 763system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 764system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 765system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 766system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 767system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 768system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 769system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 243 # number of CleanEvict MSHR misses 770system.cpu.l2cache.CleanEvict_mshr_misses::total 243 # number of CleanEvict MSHR misses |
| 771system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801156 # number of ReadExReq MSHR misses 772system.cpu.l2cache.ReadExReq_mshr_misses::total 801156 # number of ReadExReq MSHR misses | 771system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801155 # number of ReadExReq MSHR misses 772system.cpu.l2cache.ReadExReq_mshr_misses::total 801155 # number of ReadExReq MSHR misses |
| 773system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 787 # number of ReadCleanReq MSHR misses 774system.cpu.l2cache.ReadCleanReq_mshr_misses::total 787 # number of ReadCleanReq MSHR misses 775system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses 776system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses 777system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses | 773system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 787 # number of ReadCleanReq MSHR misses 774system.cpu.l2cache.ReadCleanReq_mshr_misses::total 787 # number of ReadCleanReq MSHR misses 775system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 1244649 # number of ReadSharedReq MSHR misses 776system.cpu.l2cache.ReadSharedReq_mshr_misses::total 1244649 # number of ReadSharedReq MSHR misses 777system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses |
| 778system.cpu.l2cache.demand_mshr_misses::cpu.data 2045805 # number of demand (read+write) MSHR misses 779system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses | 778system.cpu.l2cache.demand_mshr_misses::cpu.data 2045804 # number of demand (read+write) MSHR misses 779system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses |
| 780system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses | 780system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses |
| 781system.cpu.l2cache.overall_mshr_misses::cpu.data 2045805 # number of overall MSHR misses 782system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses 783system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62419073500 # number of ReadExReq MSHR miss cycles 784system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62419073500 # number of ReadExReq MSHR miss cycles 785system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52090500 # number of ReadCleanReq MSHR miss cycles 786system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52090500 # number of ReadCleanReq MSHR miss cycles 787system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96214883500 # number of ReadSharedReq MSHR miss cycles 788system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96214883500 # number of ReadSharedReq MSHR miss cycles 789system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52090500 # number of demand (read+write) MSHR miss cycles 790system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158633957000 # number of demand (read+write) MSHR miss cycles 791system.cpu.l2cache.demand_mshr_miss_latency::total 158686047500 # number of demand (read+write) MSHR miss cycles 792system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52090500 # number of overall MSHR miss cycles 793system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158633957000 # number of overall MSHR miss cycles 794system.cpu.l2cache.overall_mshr_miss_latency::total 158686047500 # number of overall MSHR miss cycles | 781system.cpu.l2cache.overall_mshr_misses::cpu.data 2045804 # number of overall MSHR misses 782system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses 783system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62409666500 # number of ReadExReq MSHR miss cycles 784system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62409666500 # number of ReadExReq MSHR miss cycles 785system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51871000 # number of ReadCleanReq MSHR miss cycles 786system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51871000 # number of ReadCleanReq MSHR miss cycles 787system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96199045500 # number of ReadSharedReq MSHR miss cycles 788system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96199045500 # number of ReadSharedReq MSHR miss cycles 789system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51871000 # number of demand (read+write) MSHR miss cycles 790system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158608712000 # number of demand (read+write) MSHR miss cycles 791system.cpu.l2cache.demand_mshr_miss_latency::total 158660583000 # number of demand (read+write) MSHR miss cycles 792system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51871000 # number of overall MSHR miss cycles 793system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158608712000 # number of overall MSHR miss cycles 794system.cpu.l2cache.overall_mshr_miss_latency::total 158660583000 # number of overall MSHR miss cycles |
| 795system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 796system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 797system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423701 # mshr miss rate for ReadExReq accesses 798system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423701 # mshr miss rate for ReadExReq accesses 799system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadCleanReq accesses 800system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.959756 # mshr miss rate for ReadCleanReq accesses 801system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses 802system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses 803system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses 804system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for demand accesses 805system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses 806system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses 807system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for overall accesses 808system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses | 795system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 796system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 797system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423701 # mshr miss rate for ReadExReq accesses 798system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423701 # mshr miss rate for ReadExReq accesses 799system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadCleanReq accesses 800system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.959756 # mshr miss rate for ReadCleanReq accesses 801system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.169703 # mshr miss rate for ReadSharedReq accesses 802system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.169703 # mshr miss rate for ReadSharedReq accesses 803system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses 804system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for demand accesses 805system.cpu.l2cache.demand_mshr_miss_rate::total 0.221830 # mshr miss rate for demand accesses 806system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses 807system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.221764 # mshr miss rate for overall accesses 808system.cpu.l2cache.overall_mshr_miss_rate::total 0.221830 # mshr miss rate for overall accesses |
| 809system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77911.260104 # average ReadExReq mshr miss latency 810system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77911.260104 # average ReadExReq mshr miss latency 811system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66188.691233 # average ReadCleanReq mshr miss latency 812system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66188.691233 # average ReadCleanReq mshr miss latency 813system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77302.824732 # average ReadSharedReq mshr miss latency 814system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77302.824732 # average ReadSharedReq mshr miss latency 815system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency 816system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency 817system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency 818system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency 820system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency | 809system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77899.615555 # average ReadExReq mshr miss latency 810system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77899.615555 # average ReadExReq mshr miss latency 811system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65909.783990 # average ReadCleanReq mshr miss latency 812system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65909.783990 # average ReadCleanReq mshr miss latency 813system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77290.099859 # average ReadSharedReq mshr miss latency 814system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77290.099859 # average ReadSharedReq mshr miss latency 815system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency 816system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency 817system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency 818system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency 820system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency |
| 821system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 821system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 822system.cpu.toL2Bus.snoop_filter.tot_requests 18447023 # Total number of requests made to the snoop filter. 823system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221080 # Number of requests hitting in the snoop filter with a single holder of the requested data. 824system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 825system.cpu.toL2Bus.snoop_filter.tot_snoops 1287 # Total number of snoops made to the snoop filter. 826system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1281 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 827system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 822system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution | 828system.cpu.toL2Bus.trans_dist::ReadResp 7335103 # Transaction distribution |
| 823system.cpu.toL2Bus.trans_dist::Writeback 4734688 # Transaction distribution | 829system.cpu.toL2Bus.trans_dist::Writeback 4734687 # Transaction distribution |
| 824system.cpu.toL2Bus.trans_dist::CleanEvict 6498677 # Transaction distribution 825system.cpu.toL2Bus.trans_dist::ReadExReq 1890852 # Transaction distribution 826system.cpu.toL2Bus.trans_dist::ReadExResp 1890852 # Transaction distribution 827system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution 828system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334283 # Transaction distribution 829system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) 830system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669715 # Packet count per connected master and slave (bytes) 831system.cpu.toL2Bus.pkt_count::total 27671384 # Packet count per connected master and slave (bytes) 832system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) 833system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220736 # Cumulative packet size per connected master and slave (bytes) 834system.cpu.toL2Bus.pkt_size::total 826273216 # Cumulative packet size per connected master and slave (bytes) | 830system.cpu.toL2Bus.trans_dist::CleanEvict 6498677 # Transaction distribution 831system.cpu.toL2Bus.trans_dist::ReadExReq 1890852 # Transaction distribution 832system.cpu.toL2Bus.trans_dist::ReadExResp 1890852 # Transaction distribution 833system.cpu.toL2Bus.trans_dist::ReadCleanReq 820 # Transaction distribution 834system.cpu.toL2Bus.trans_dist::ReadSharedReq 7334283 # Transaction distribution 835system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1669 # Packet count per connected master and slave (bytes) 836system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 27669715 # Packet count per connected master and slave (bytes) 837system.cpu.toL2Bus.pkt_count::total 27671384 # Packet count per connected master and slave (bytes) 838system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) 839system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 826220736 # Cumulative packet size per connected master and slave (bytes) 840system.cpu.toL2Bus.pkt_size::total 826273216 # Cumulative packet size per connected master and slave (bytes) |
| 835system.cpu.toL2Bus.snoops 2013891 # Total snoops (count) 836system.cpu.toL2Bus.snoop_fanout::samples 20460914 # Request fanout histogram 837system.cpu.toL2Bus.snoop_fanout::mean 1.098426 # Request fanout histogram 838system.cpu.toL2Bus.snoop_fanout::stdev 0.297890 # Request fanout histogram | 841system.cpu.toL2Bus.snoops 2013890 # Total snoops (count) 842system.cpu.toL2Bus.snoop_fanout::samples 20460913 # Request fanout histogram 843system.cpu.toL2Bus.snoop_fanout::mean 0.000220 # Request fanout histogram 844system.cpu.toL2Bus.snoop_fanout::stdev 0.014837 # Request fanout histogram |
| 839system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 845system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 840system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 841system.cpu.toL2Bus.snoop_fanout::1 18447023 90.16% 90.16% # Request fanout histogram 842system.cpu.toL2Bus.snoop_fanout::2 2013891 9.84% 100.00% # Request fanout histogram | 846system.cpu.toL2Bus.snoop_fanout::0 20456426 99.98% 99.98% # Request fanout histogram 847system.cpu.toL2Bus.snoop_fanout::1 4481 0.02% 100.00% # Request fanout histogram 848system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram |
| 843system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 849system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 844system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 850system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 845system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 851system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 846system.cpu.toL2Bus.snoop_fanout::total 20460914 # Request fanout histogram | 852system.cpu.toL2Bus.snoop_fanout::total 20460913 # Request fanout histogram |
| 847system.cpu.toL2Bus.reqLayer0.occupancy 12908075500 # Layer occupancy (ticks) 848system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 849system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) 850system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 851system.cpu.toL2Bus.respLayer1.occupancy 13837704496 # Layer occupancy (ticks) 852system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 853system.membus.trans_dist::ReadResp 1245436 # Transaction distribution | 853system.cpu.toL2Bus.reqLayer0.occupancy 12908075500 # Layer occupancy (ticks) 854system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 855system.cpu.toL2Bus.respLayer0.occupancy 1230499 # Layer occupancy (ticks) 856system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 857system.cpu.toL2Bus.respLayer1.occupancy 13837704496 # Layer occupancy (ticks) 858system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 859system.membus.trans_dist::ReadResp 1245436 # Transaction distribution |
| 854system.membus.trans_dist::Writeback 1050124 # Transaction distribution | 860system.membus.trans_dist::Writeback 1050123 # Transaction distribution |
| 855system.membus.trans_dist::CleanEvict 962723 # Transaction distribution | 861system.membus.trans_dist::CleanEvict 962723 # Transaction distribution |
| 856system.membus.trans_dist::ReadExReq 801156 # Transaction distribution 857system.membus.trans_dist::ReadExResp 801156 # Transaction distribution | 862system.membus.trans_dist::ReadExReq 801155 # Transaction distribution 863system.membus.trans_dist::ReadExResp 801155 # Transaction distribution |
| 858system.membus.trans_dist::ReadSharedReq 1245436 # Transaction distribution | 864system.membus.trans_dist::ReadSharedReq 1245436 # Transaction distribution |
| 859system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes) 860system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes) 861system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189824 # Cumulative packet size per connected master and slave (bytes) 862system.membus.pkt_size::total 198189824 # Cumulative packet size per connected master and slave (bytes) | 865system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106028 # Packet count per connected master and slave (bytes) 866system.membus.pkt_count::total 6106028 # Packet count per connected master and slave (bytes) 867system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes) 868system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes) |
| 863system.membus.snoops 0 # Total snoops (count) | 869system.membus.snoops 0 # Total snoops (count) |
| 864system.membus.snoop_fanout::samples 4059439 # Request fanout histogram | 870system.membus.snoop_fanout::samples 4059437 # Request fanout histogram |
| 865system.membus.snoop_fanout::mean 0 # Request fanout histogram 866system.membus.snoop_fanout::stdev 0 # Request fanout histogram 867system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 871system.membus.snoop_fanout::mean 0 # Request fanout histogram 872system.membus.snoop_fanout::stdev 0 # Request fanout histogram 873system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 868system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram | 874system.membus.snoop_fanout::0 4059437 100.00% 100.00% # Request fanout histogram |
| 869system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 870system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 871system.membus.snoop_fanout::min_value 0 # Request fanout histogram 872system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 875system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 876system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 877system.membus.snoop_fanout::min_value 0 # Request fanout histogram 878system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 873system.membus.snoop_fanout::total 4059439 # Request fanout histogram 874system.membus.reqLayer0.occupancy 8663029500 # Layer occupancy (ticks) | 879system.membus.snoop_fanout::total 4059437 # Request fanout histogram 880system.membus.reqLayer0.occupancy 8662977500 # Layer occupancy (ticks) |
| 875system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) | 881system.membus.reqLayer0.utilization 0.8 # Layer utilization (%) |
| 876system.membus.respLayer1.occupancy 11191724000 # Layer occupancy (ticks) | 882system.membus.respLayer1.occupancy 11191643250 # Layer occupancy (ticks) |
| 877system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 878 879---------- End Simulation Statistics ---------- | 883system.membus.respLayer1.utilization 1.0 # Layer utilization (%) 884 885---------- End Simulation Statistics ---------- |