| stats.txt (10585:1c9d5d9417b3) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.108945 # Number of seconds simulated 4sim_ticks 1108944740000 # Number of ticks simulated 5final_tick 1108944740000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.108725 # Number of seconds simulated 4sim_ticks 1108725388000 # Number of ticks simulated 5final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 239014 # Simulator instruction rate (inst/s) 8host_op_rate 257501 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 171603826 # Simulator tick rate (ticks/s) 10host_mem_usage 253696 # Number of bytes of host memory used 11host_seconds 6462.24 # Real time elapsed on the host | 7host_inst_rate 243193 # Simulator instruction rate (inst/s) 8host_op_rate 262004 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 174570169 # Simulator tick rate (ticks/s) 10host_mem_usage 311428 # Number of bytes of host memory used 11host_seconds 6351.17 # Real time elapsed on the host |
| 12sim_insts 1544563087 # Number of instructions simulated 13sim_ops 1664032480 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 1544563087 # Number of instructions simulated 13sim_ops 1664032480 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 131625408 # Number of bytes read from this memory 17system.physmem.bytes_read::total 131625408 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 131558336 # Number of bytes read from this memory 17system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory |
| 18system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory | 18system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory |
| 20system.physmem.bytes_written::writebacks 66989632 # Number of bytes written to this memory 21system.physmem.bytes_written::total 66989632 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 2056647 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2056647 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1046713 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1046713 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 118694289 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 118694289 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 45420 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 45420 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 60408449 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 60408449 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 60408449 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 118694289 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 179102739 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 2056647 # Number of read requests accepted 36system.physmem.writeReqs 1046713 # Number of write requests accepted 37system.physmem.readBursts 2056647 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 1046713 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 131542016 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 83392 # Total number of bytes read from write queue 41system.physmem.bytesWritten 66988032 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 131625408 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 66989632 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 1303 # Number of DRAM read bursts serviced by the write queue | 20system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory 21system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 2055599 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 118657277 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 118657277 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 2055599 # Number of read requests accepted 36system.physmem.writeReqs 1046417 # Number of write requests accepted 37system.physmem.readBursts 2055599 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 1046417 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 131472320 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue 41system.physmem.bytesWritten 66969088 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 131558336 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 66970688 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue |
| 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 47system.physmem.perBankRdBursts::0 128036 # Per bank write bursts 48system.physmem.perBankRdBursts::1 125234 # Per bank write bursts 49system.physmem.perBankRdBursts::2 122300 # Per bank write bursts 50system.physmem.perBankRdBursts::3 124230 # Per bank write bursts 51system.physmem.perBankRdBursts::4 123415 # Per bank write bursts 52system.physmem.perBankRdBursts::5 123345 # Per bank write bursts 53system.physmem.perBankRdBursts::6 123964 # Per bank write bursts 54system.physmem.perBankRdBursts::7 124409 # Per bank write bursts 55system.physmem.perBankRdBursts::8 131872 # Per bank write bursts 56system.physmem.perBankRdBursts::9 134140 # Per bank write bursts 57system.physmem.perBankRdBursts::10 132473 # Per bank write bursts 58system.physmem.perBankRdBursts::11 133756 # Per bank write bursts 59system.physmem.perBankRdBursts::12 133901 # Per bank write bursts 60system.physmem.perBankRdBursts::13 134102 # Per bank write bursts 61system.physmem.perBankRdBursts::14 129958 # Per bank write bursts 62system.physmem.perBankRdBursts::15 130209 # Per bank write bursts 63system.physmem.perBankWrBursts::0 65849 # Per bank write bursts 64system.physmem.perBankWrBursts::1 64131 # Per bank write bursts 65system.physmem.perBankWrBursts::2 62381 # Per bank write bursts 66system.physmem.perBankWrBursts::3 62840 # Per bank write bursts 67system.physmem.perBankWrBursts::4 62871 # Per bank write bursts 68system.physmem.perBankWrBursts::5 62990 # Per bank write bursts 69system.physmem.perBankWrBursts::6 64312 # Per bank write bursts 70system.physmem.perBankWrBursts::7 65310 # Per bank write bursts 71system.physmem.perBankWrBursts::8 67027 # Per bank write bursts 72system.physmem.perBankWrBursts::9 67624 # Per bank write bursts 73system.physmem.perBankWrBursts::10 67292 # Per bank write bursts 74system.physmem.perBankWrBursts::11 67645 # Per bank write bursts 75system.physmem.perBankWrBursts::12 67063 # Per bank write bursts 76system.physmem.perBankWrBursts::13 67560 # Per bank write bursts 77system.physmem.perBankWrBursts::14 66200 # Per bank write bursts 78system.physmem.perBankWrBursts::15 65593 # Per bank write bursts | 47system.physmem.perBankRdBursts::0 127971 # Per bank write bursts 48system.physmem.perBankRdBursts::1 125115 # Per bank write bursts 49system.physmem.perBankRdBursts::2 122192 # Per bank write bursts 50system.physmem.perBankRdBursts::3 124223 # Per bank write bursts 51system.physmem.perBankRdBursts::4 123351 # Per bank write bursts 52system.physmem.perBankRdBursts::5 123340 # Per bank write bursts 53system.physmem.perBankRdBursts::6 123758 # Per bank write bursts 54system.physmem.perBankRdBursts::7 124120 # Per bank write bursts 55system.physmem.perBankRdBursts::8 131994 # Per bank write bursts 56system.physmem.perBankRdBursts::9 134060 # Per bank write bursts 57system.physmem.perBankRdBursts::10 132574 # Per bank write bursts 58system.physmem.perBankRdBursts::11 133683 # Per bank write bursts 59system.physmem.perBankRdBursts::12 133864 # Per bank write bursts 60system.physmem.perBankRdBursts::13 133891 # Per bank write bursts 61system.physmem.perBankRdBursts::14 129793 # Per bank write bursts 62system.physmem.perBankRdBursts::15 130326 # Per bank write bursts 63system.physmem.perBankWrBursts::0 65785 # Per bank write bursts 64system.physmem.perBankWrBursts::1 64106 # Per bank write bursts 65system.physmem.perBankWrBursts::2 62369 # Per bank write bursts 66system.physmem.perBankWrBursts::3 62872 # Per bank write bursts 67system.physmem.perBankWrBursts::4 62855 # Per bank write bursts 68system.physmem.perBankWrBursts::5 62943 # Per bank write bursts 69system.physmem.perBankWrBursts::6 64256 # Per bank write bursts 70system.physmem.perBankWrBursts::7 65177 # Per bank write bursts 71system.physmem.perBankWrBursts::8 67064 # Per bank write bursts 72system.physmem.perBankWrBursts::9 67603 # Per bank write bursts 73system.physmem.perBankWrBursts::10 67361 # Per bank write bursts 74system.physmem.perBankWrBursts::11 67637 # Per bank write bursts 75system.physmem.perBankWrBursts::12 67067 # Per bank write bursts 76system.physmem.perBankWrBursts::13 67487 # Per bank write bursts 77system.physmem.perBankWrBursts::14 66154 # Per bank write bursts 78system.physmem.perBankWrBursts::15 65656 # Per bank write bursts |
| 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 81system.physmem.totGap 1108944651500 # Total gap between requests | 81system.physmem.totGap 1108725299500 # Total gap between requests |
| 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) | 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 88system.physmem.readPktSize::6 2056647 # Read request sizes (log2) | 88system.physmem.readPktSize::6 2055599 # Read request sizes (log2) |
| 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) | 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 95system.physmem.writePktSize::6 1046713 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 1923205 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 132121 # What read queue length does an incoming req see | 95system.physmem.writePktSize::6 1046417 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 1922438 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 131799 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 143system.physmem.wrQLenPdf::15 31987 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 33324 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 57104 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 60908 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 61344 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 61572 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 61490 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 61531 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 61499 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 61550 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 61578 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 61602 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 62038 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 62277 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 61631 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 62828 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 61322 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 61027 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 70 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::15 32284 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 33556 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 57018 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 60831 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 61268 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 61505 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 61466 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 61474 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 61478 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 61526 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 61560 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 61560 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 62022 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 62349 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 61672 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 62578 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 61195 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 60970 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 79 # What write queue length does an incoming req see |
| 162system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see | 162system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see |
| 163system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see | 163system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see |
| 165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see --- 11 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 192system.physmem.bytesPerActivate::samples 1918209 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 103.496643 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 81.775288 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 125.095886 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 1492147 77.79% 77.79% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 306422 15.97% 93.76% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 52965 2.76% 96.52% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 21185 1.10% 97.63% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 13242 0.69% 98.32% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 7471 0.39% 98.71% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 5204 0.27% 98.98% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 3914 0.20% 99.18% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 15659 0.82% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 1918209 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 61025 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 33.632724 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 160.189303 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 60982 99.93% 99.93% # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.96% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes | 192system.physmem.bytesPerActivate::samples 1917383 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 103.495400 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 81.766538 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 125.134212 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 1491936 77.81% 77.81% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 306042 15.96% 93.77% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 52771 2.75% 96.52% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 21239 1.11% 97.63% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 13137 0.69% 98.32% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 7295 0.38% 98.70% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 5316 0.28% 98.98% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 4195 0.22% 99.19% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 15452 0.81% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 1917383 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 60970 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 33.645219 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 157.122880 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 60927 99.93% 99.93% # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::3072-4095 6 0.01% 99.99% # Reads before turning the bus around for writes |
| 213system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes | 213system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes |
| 214system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes | 214system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes | 216system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::total 61025 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 61025 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 17.151790 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 17.116821 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 1.097688 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 27581 45.20% 45.20% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 1180 1.93% 47.13% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 28172 46.16% 93.29% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 3706 6.07% 99.37% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 317 0.52% 99.89% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::21 54 0.09% 99.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::22 9 0.01% 99.99% # Writes before turning the bus around for reads | 218system.physmem.rdPerTurnAround::total 60970 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 60970 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 17.162408 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 17.127431 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 1.097398 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 27276 44.74% 44.74% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 1165 1.91% 46.65% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 28420 46.61% 93.26% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 3653 5.99% 99.25% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 385 0.63% 99.88% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::21 61 0.10% 99.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::22 7 0.01% 100.00% # Writes before turning the bus around for reads |
| 230system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads | 230system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads |
| 231system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads 233system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads 234system.physmem.wrPerTurnAround::total 61025 # Writes before turning the bus around for reads 235system.physmem.totQLat 38537340500 # Total ticks spent queuing 236system.physmem.totMemAccLat 77075040500 # Total ticks spent from burst creation until serviced by the DRAM 237system.physmem.totBusLat 10276720000 # Total ticks spent in databus transfers 238system.physmem.avgQLat 18749.83 # Average queueing delay per DRAM burst | 231system.physmem.wrPerTurnAround::total 60970 # Writes before turning the bus around for reads 232system.physmem.totQLat 38268969000 # Total ticks spent queuing 233system.physmem.totMemAccLat 76786250250 # Total ticks spent from burst creation until serviced by the DRAM 234system.physmem.totBusLat 10271275000 # Total ticks spent in databus transfers 235system.physmem.avgQLat 18629.12 # Average queueing delay per DRAM burst |
| 239system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 236system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 240system.physmem.avgMemAccLat 37499.83 # Average memory access latency per DRAM burst 241system.physmem.avgRdBW 118.62 # Average DRAM read bandwidth in MiByte/s 242system.physmem.avgWrBW 60.41 # Average achieved write bandwidth in MiByte/s 243system.physmem.avgRdBWSys 118.69 # Average system read bandwidth in MiByte/s 244system.physmem.avgWrBWSys 60.41 # Average system write bandwidth in MiByte/s | 237system.physmem.avgMemAccLat 37379.12 # Average memory access latency per DRAM burst 238system.physmem.avgRdBW 118.58 # Average DRAM read bandwidth in MiByte/s 239system.physmem.avgWrBW 60.40 # Average achieved write bandwidth in MiByte/s 240system.physmem.avgRdBWSys 118.66 # Average system read bandwidth in MiByte/s 241system.physmem.avgWrBWSys 60.40 # Average system write bandwidth in MiByte/s |
| 245system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 246system.physmem.busUtil 1.40 # Data bus utilization in percentage 247system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads 248system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes 249system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing | 242system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 243system.physmem.busUtil 1.40 # Data bus utilization in percentage 244system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads 245system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes 246system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing |
| 250system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing 251system.physmem.readRowHits 777039 # Number of row buffer hits during reads 252system.physmem.writeRowHits 406774 # Number of row buffer hits during writes 253system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads 254system.physmem.writeRowHitRate 38.86 # Row buffer hit rate for writes 255system.physmem.avgGap 357336.77 # Average gap between requests | 247system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing 248system.physmem.readRowHits 776845 # Number of row buffer hits during reads 249system.physmem.writeRowHits 406412 # Number of row buffer hits during writes 250system.physmem.readRowHitRate 37.82 # Row buffer hit rate for reads 251system.physmem.writeRowHitRate 38.84 # Row buffer hit rate for writes 252system.physmem.avgGap 357420.88 # Average gap between requests |
| 256system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined | 253system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined |
| 257system.physmem.memoryStateTime::IDLE 313164826000 # Time in different power states 258system.physmem.memoryStateTime::REF 37029980000 # Time in different power states 259system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 260system.physmem.memoryStateTime::ACT 758746776000 # Time in different power states 261system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 262system.physmem.actEnergy::0 7075638360 # Energy for activate commands per rank (pJ) 263system.physmem.actEnergy::1 7426006560 # Energy for activate commands per rank (pJ) 264system.physmem.preEnergy::0 3860715375 # Energy for precharge commands per rank (pJ) 265system.physmem.preEnergy::1 4051888500 # Energy for precharge commands per rank (pJ) 266system.physmem.readEnergy::0 7760165400 # Energy for read commands per rank (pJ) 267system.physmem.readEnergy::1 8271151200 # Energy for read commands per rank (pJ) 268system.physmem.writeEnergy::0 3309232320 # Energy for write commands per rank (pJ) 269system.physmem.writeEnergy::1 3473305920 # Energy for write commands per rank (pJ) 270system.physmem.refreshEnergy::0 72430640880 # Energy for refresh commands per rank (pJ) 271system.physmem.refreshEnergy::1 72430640880 # Energy for refresh commands per rank (pJ) 272system.physmem.actBackEnergy::0 416866648005 # Energy for active background per rank (pJ) 273system.physmem.actBackEnergy::1 425333204280 # Energy for active background per rank (pJ) 274system.physmem.preBackEnergy::0 299692308000 # Energy for precharge background per rank (pJ) 275system.physmem.preBackEnergy::1 292265504250 # Energy for precharge background per rank (pJ) 276system.physmem.totalEnergy::0 810995348340 # Total energy per rank (pJ) 277system.physmem.totalEnergy::1 813251701590 # Total energy per rank (pJ) 278system.physmem.averagePower::0 731.323936 # Core power per rank (mW) 279system.physmem.averagePower::1 733.358627 # Core power per rank (mW) 280system.cpu.branchPred.lookups 240152510 # Number of BP lookups 281system.cpu.branchPred.condPredicted 186756179 # Number of conditional branches predicted 282system.cpu.branchPred.condIncorrect 14598640 # Number of conditional branches incorrect 283system.cpu.branchPred.BTBLookups 131763268 # Number of BTB lookups 284system.cpu.branchPred.BTBHits 122287171 # Number of BTB hits | 254system.physmem_0.actEnergy 7070973840 # Energy for activate commands per rank (pJ) 255system.physmem_0.preEnergy 3858170250 # Energy for precharge commands per rank (pJ) 256system.physmem_0.readEnergy 7753512000 # Energy for read commands per rank (pJ) 257system.physmem_0.writeEnergy 3307152240 # Energy for write commands per rank (pJ) 258system.physmem_0.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) 259system.physmem_0.actBackEnergy 416204777970 # Energy for active background per rank (pJ) 260system.physmem_0.preBackEnergy 300142086750 # Energy for precharge background per rank (pJ) 261system.physmem_0.totalEnergy 810753074250 # Total energy per rank (pJ) 262system.physmem_0.averagePower 731.249224 # Core power per rank (mW) 263system.physmem_0.memoryStateTime::IDLE 496624730250 # Time in different power states 264system.physmem_0.memoryStateTime::REF 37022700000 # Time in different power states 265system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 266system.physmem_0.memoryStateTime::ACT 575075912250 # Time in different power states 267system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 268system.physmem_1.actEnergy 7424434080 # Energy for activate commands per rank (pJ) 269system.physmem_1.preEnergy 4051030500 # Energy for precharge commands per rank (pJ) 270system.physmem_1.readEnergy 8269419600 # Energy for read commands per rank (pJ) 271system.physmem_1.writeEnergy 3473467920 # Energy for write commands per rank (pJ) 272system.physmem_1.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ) 273system.physmem_1.actBackEnergy 425140731810 # Energy for active background per rank (pJ) 274system.physmem_1.preBackEnergy 292303530750 # Energy for precharge background per rank (pJ) 275system.physmem_1.totalEnergy 813079015860 # Total energy per rank (pJ) 276system.physmem_1.averagePower 733.347080 # Core power per rank (mW) 277system.physmem_1.memoryStateTime::IDLE 483537101750 # Time in different power states 278system.physmem_1.memoryStateTime::REF 37022700000 # Time in different power states 279system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 280system.physmem_1.memoryStateTime::ACT 588165429250 # Time in different power states 281system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 282system.cpu.branchPred.lookups 240158127 # Number of BP lookups 283system.cpu.branchPred.condPredicted 186758642 # Number of conditional branches predicted 284system.cpu.branchPred.condIncorrect 14604059 # Number of conditional branches incorrect 285system.cpu.branchPred.BTBLookups 133657061 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 122306338 # Number of BTB hits |
| 285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 286system.cpu.branchPred.BTBHitPct 92.808241 # BTB Hit Percentage 287system.cpu.branchPred.usedRAS 15660181 # Number of times the RAS was used to get a target. | 288system.cpu.branchPred.BTBHitPct 91.507577 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 15659556 # Number of times the RAS was used to get a target. |
| 288system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 289system.cpu_clk_domain.clock 500 # Clock period in ticks | 290system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 291system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 292system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 293system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 294system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 295system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 290system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 291system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 292system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 293system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 294system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 295system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 296system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 297system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 303system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 304system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 305system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 306system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 307system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 308system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 309system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 310system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 300system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 301system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 302system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 303system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 304system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 305system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 306system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 307system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 313system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 314system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 315system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 316system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 317system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 318system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 319system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 320system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 321system.cpu.dtb.walker.walks 0 # Table walker walks requested 322system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 323system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 324system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 325system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 326system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 311system.cpu.dtb.inst_hits 0 # ITB inst hits 312system.cpu.dtb.inst_misses 0 # ITB inst misses 313system.cpu.dtb.read_hits 0 # DTB read hits 314system.cpu.dtb.read_misses 0 # DTB read misses 315system.cpu.dtb.write_hits 0 # DTB write hits 316system.cpu.dtb.write_misses 0 # DTB write misses 317system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 318system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 324system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 325system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 326system.cpu.dtb.read_accesses 0 # DTB read accesses 327system.cpu.dtb.write_accesses 0 # DTB write accesses 328system.cpu.dtb.inst_accesses 0 # ITB inst accesses 329system.cpu.dtb.hits 0 # DTB hits 330system.cpu.dtb.misses 0 # DTB misses 331system.cpu.dtb.accesses 0 # DTB accesses | 329system.cpu.dtb.inst_hits 0 # ITB inst hits 330system.cpu.dtb.inst_misses 0 # ITB inst misses 331system.cpu.dtb.read_hits 0 # DTB read hits 332system.cpu.dtb.read_misses 0 # DTB read misses 333system.cpu.dtb.write_hits 0 # DTB write hits 334system.cpu.dtb.write_misses 0 # DTB write misses 335system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 336system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 342system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 343system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 344system.cpu.dtb.read_accesses 0 # DTB read accesses 345system.cpu.dtb.write_accesses 0 # DTB write accesses 346system.cpu.dtb.inst_accesses 0 # ITB inst accesses 347system.cpu.dtb.hits 0 # DTB hits 348system.cpu.dtb.misses 0 # DTB misses 349system.cpu.dtb.accesses 0 # DTB accesses |
| 350system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 352system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 353system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 354system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 332system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 333system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 334system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 335system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 336system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 337system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 338system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 345system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 346system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 347system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 348system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 349system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 350system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 351system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 352system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 358system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 359system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 360system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 361system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 362system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 363system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 364system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 365system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 371system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 372system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 373system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 374system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 375system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 376system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 377system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 378system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 379system.cpu.itb.walker.walks 0 # Table walker walks requested 380system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 382system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 383system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 384system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 353system.cpu.itb.inst_hits 0 # ITB inst hits 354system.cpu.itb.inst_misses 0 # ITB inst misses 355system.cpu.itb.read_hits 0 # DTB read hits 356system.cpu.itb.read_misses 0 # DTB read misses 357system.cpu.itb.write_hits 0 # DTB write hits 358system.cpu.itb.write_misses 0 # DTB write misses 359system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 360system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 367system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 368system.cpu.itb.read_accesses 0 # DTB read accesses 369system.cpu.itb.write_accesses 0 # DTB write accesses 370system.cpu.itb.inst_accesses 0 # ITB inst accesses 371system.cpu.itb.hits 0 # DTB hits 372system.cpu.itb.misses 0 # DTB misses 373system.cpu.itb.accesses 0 # DTB accesses 374system.cpu.workload.num_syscalls 46 # Number of system calls | 387system.cpu.itb.inst_hits 0 # ITB inst hits 388system.cpu.itb.inst_misses 0 # ITB inst misses 389system.cpu.itb.read_hits 0 # DTB read hits 390system.cpu.itb.read_misses 0 # DTB read misses 391system.cpu.itb.write_hits 0 # DTB write hits 392system.cpu.itb.write_misses 0 # DTB write misses 393system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 394system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 401system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 402system.cpu.itb.read_accesses 0 # DTB read accesses 403system.cpu.itb.write_accesses 0 # DTB write accesses 404system.cpu.itb.inst_accesses 0 # ITB inst accesses 405system.cpu.itb.hits 0 # DTB hits 406system.cpu.itb.misses 0 # DTB misses 407system.cpu.itb.accesses 0 # DTB accesses 408system.cpu.workload.num_syscalls 46 # Number of system calls |
| 375system.cpu.numCycles 2217889480 # number of cpu cycles simulated | 409system.cpu.numCycles 2217450776 # number of cpu cycles simulated |
| 376system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 377system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 378system.cpu.committedInsts 1544563087 # Number of instructions committed 379system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed | 410system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 411system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 412system.cpu.committedInsts 1544563087 # Number of instructions committed 413system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed |
| 380system.cpu.discardedOps 40077128 # Number of ops (including micro ops) which were discarded before commit | 414system.cpu.discardedOps 40093383 # Number of ops (including micro ops) which were discarded before commit |
| 381system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 415system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 382system.cpu.cpi 1.435933 # CPI: cycles per instruction 383system.cpu.ipc 0.696411 # IPC: instructions per cycle 384system.cpu.tickCycles 1838736315 # Number of cycles that the object actually ticked 385system.cpu.idleCycles 379153165 # Total number of cycles that the object has spent stopped 386system.cpu.dcache.tags.replacements 9224311 # number of replacements 387system.cpu.dcache.tags.tagsinuse 4085.608602 # Cycle average of tags in use 388system.cpu.dcache.tags.total_refs 624084220 # Total number of references to valid blocks. 389system.cpu.dcache.tags.sampled_refs 9228407 # Sample count of references to valid blocks. 390system.cpu.dcache.tags.avg_refs 67.626430 # Average number of references to valid blocks. | 416system.cpu.cpi 1.435649 # CPI: cycles per instruction 417system.cpu.ipc 0.696549 # IPC: instructions per cycle 418system.cpu.tickCycles 1838812013 # Number of cycles that the object actually ticked 419system.cpu.idleCycles 378638763 # Total number of cycles that the object has spent stopped 420system.cpu.dcache.tags.replacements 9223724 # number of replacements 421system.cpu.dcache.tags.tagsinuse 4085.606596 # Cycle average of tags in use 422system.cpu.dcache.tags.total_refs 624087400 # Total number of references to valid blocks. 423system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks. 424system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks. |
| 391system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. | 425system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit. |
| 392system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.608602 # Average occupied blocks per requestor | 426system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.606596 # Average occupied blocks per requestor |
| 393system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy 394system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy 395system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 427system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy 428system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy 429system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 396system.cpu.dcache.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id 397system.cpu.dcache.tags.age_task_id_blocks_1024::1 1292 # Occupied blocks per task id 398system.cpu.dcache.tags.age_task_id_blocks_1024::2 2484 # Occupied blocks per task id | 430system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id 431system.cpu.dcache.tags.age_task_id_blocks_1024::1 1296 # Occupied blocks per task id 432system.cpu.dcache.tags.age_task_id_blocks_1024::2 2482 # Occupied blocks per task id |
| 399system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 400system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 433system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 434system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 401system.cpu.dcache.tags.tag_accesses 1276551305 # Number of tag accesses 402system.cpu.dcache.tags.data_accesses 1276551305 # Number of data accesses 403system.cpu.dcache.ReadReq_hits::cpu.inst 453737568 # number of ReadReq hits 404system.cpu.dcache.ReadReq_hits::total 453737568 # number of ReadReq hits 405system.cpu.dcache.WriteReq_hits::cpu.inst 170346530 # number of WriteReq hits 406system.cpu.dcache.WriteReq_hits::total 170346530 # number of WriteReq hits | 435system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses 436system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses 437system.cpu.dcache.ReadReq_hits::cpu.inst 453740634 # number of ReadReq hits 438system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits 439system.cpu.dcache.WriteReq_hits::cpu.inst 170346644 # number of WriteReq hits 440system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits |
| 407system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits 408system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 409system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits 410system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits | 441system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits 442system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 443system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits 444system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits |
| 411system.cpu.dcache.demand_hits::cpu.inst 624084098 # number of demand (read+write) hits 412system.cpu.dcache.demand_hits::total 624084098 # number of demand (read+write) hits 413system.cpu.dcache.overall_hits::cpu.inst 624084098 # number of overall hits 414system.cpu.dcache.overall_hits::total 624084098 # number of overall hits 415system.cpu.dcache.ReadReq_misses::cpu.inst 7337712 # number of ReadReq misses 416system.cpu.dcache.ReadReq_misses::total 7337712 # number of ReadReq misses 417system.cpu.dcache.WriteReq_misses::cpu.inst 2239517 # number of WriteReq misses 418system.cpu.dcache.WriteReq_misses::total 2239517 # number of WriteReq misses 419system.cpu.dcache.demand_misses::cpu.inst 9577229 # number of demand (read+write) misses 420system.cpu.dcache.demand_misses::total 9577229 # number of demand (read+write) misses 421system.cpu.dcache.overall_misses::cpu.inst 9577229 # number of overall misses 422system.cpu.dcache.overall_misses::total 9577229 # number of overall misses 423system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183598363496 # number of ReadReq miss cycles 424system.cpu.dcache.ReadReq_miss_latency::total 183598363496 # number of ReadReq miss cycles 425system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101566510500 # number of WriteReq miss cycles 426system.cpu.dcache.WriteReq_miss_latency::total 101566510500 # number of WriteReq miss cycles 427system.cpu.dcache.demand_miss_latency::cpu.inst 285164873996 # number of demand (read+write) miss cycles 428system.cpu.dcache.demand_miss_latency::total 285164873996 # number of demand (read+write) miss cycles 429system.cpu.dcache.overall_miss_latency::cpu.inst 285164873996 # number of overall miss cycles 430system.cpu.dcache.overall_miss_latency::total 285164873996 # number of overall miss cycles 431system.cpu.dcache.ReadReq_accesses::cpu.inst 461075280 # number of ReadReq accesses(hits+misses) 432system.cpu.dcache.ReadReq_accesses::total 461075280 # number of ReadReq accesses(hits+misses) | 445system.cpu.dcache.demand_hits::cpu.inst 624087278 # number of demand (read+write) hits 446system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits 447system.cpu.dcache.overall_hits::cpu.inst 624087278 # number of overall hits 448system.cpu.dcache.overall_hits::total 624087278 # number of overall hits 449system.cpu.dcache.ReadReq_misses::cpu.inst 7337122 # number of ReadReq misses 450system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses 451system.cpu.dcache.WriteReq_misses::cpu.inst 2239403 # number of WriteReq misses 452system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses 453system.cpu.dcache.demand_misses::cpu.inst 9576525 # number of demand (read+write) misses 454system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses 455system.cpu.dcache.overall_misses::cpu.inst 9576525 # number of overall misses 456system.cpu.dcache.overall_misses::total 9576525 # number of overall misses 457system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183400270746 # number of ReadReq miss cycles 458system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles 459system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101399706750 # number of WriteReq miss cycles 460system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles 461system.cpu.dcache.demand_miss_latency::cpu.inst 284799977496 # number of demand (read+write) miss cycles 462system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles 463system.cpu.dcache.overall_miss_latency::cpu.inst 284799977496 # number of overall miss cycles 464system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles 465system.cpu.dcache.ReadReq_accesses::cpu.inst 461077756 # number of ReadReq accesses(hits+misses) 466system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses) |
| 433system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) 434system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 435system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) 436system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 437system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) 438system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) | 467system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) 468system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 469system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) 470system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 471system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) 472system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) |
| 439system.cpu.dcache.demand_accesses::cpu.inst 633661327 # number of demand (read+write) accesses 440system.cpu.dcache.demand_accesses::total 633661327 # number of demand (read+write) accesses 441system.cpu.dcache.overall_accesses::cpu.inst 633661327 # number of overall (read+write) accesses 442system.cpu.dcache.overall_accesses::total 633661327 # number of overall (read+write) accesses 443system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses 444system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses | 473system.cpu.dcache.demand_accesses::cpu.inst 633663803 # number of demand (read+write) accesses 474system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses 475system.cpu.dcache.overall_accesses::cpu.inst 633663803 # number of overall (read+write) accesses 476system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses 477system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses 478system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses |
| 445system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses 446system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses | 479system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses 480system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses |
| 447system.cpu.dcache.demand_miss_rate::cpu.inst 0.015114 # miss rate for demand accesses 448system.cpu.dcache.demand_miss_rate::total 0.015114 # miss rate for demand accesses 449system.cpu.dcache.overall_miss_rate::cpu.inst 0.015114 # miss rate for overall accesses 450system.cpu.dcache.overall_miss_rate::total 0.015114 # miss rate for overall accesses 451system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25021.200545 # average ReadReq miss latency 452system.cpu.dcache.ReadReq_avg_miss_latency::total 25021.200545 # average ReadReq miss latency 453system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45351.971206 # average WriteReq miss latency 454system.cpu.dcache.WriteReq_avg_miss_latency::total 45351.971206 # average WriteReq miss latency 455system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency 456system.cpu.dcache.demand_avg_miss_latency::total 29775.300768 # average overall miss latency 457system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency 458system.cpu.dcache.overall_avg_miss_latency::total 29775.300768 # average overall miss latency | 481system.cpu.dcache.demand_miss_rate::cpu.inst 0.015113 # miss rate for demand accesses 482system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses 483system.cpu.dcache.overall_miss_rate::cpu.inst 0.015113 # miss rate for overall accesses 484system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses 485system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24996.213876 # average ReadReq miss latency 486system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency 487system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45279.794101 # average WriteReq miss latency 488system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency 489system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency 490system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency 491system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29739.386416 # average overall miss latency 492system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency |
| 459system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 460system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 461system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 462system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 463system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 464system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 465system.cpu.dcache.fast_writes 0 # number of fast writes performed 466system.cpu.dcache.cache_copies 0 # number of cache copies performed | 493system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 494system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 495system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 496system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 497system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 498system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 499system.cpu.dcache.fast_writes 0 # number of fast writes performed 500system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 467system.cpu.dcache.writebacks::writebacks 3700618 # number of writebacks 468system.cpu.dcache.writebacks::total 3700618 # number of writebacks 469system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits 470system.cpu.dcache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits 471system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348609 # number of WriteReq MSHR hits 472system.cpu.dcache.WriteReq_mshr_hits::total 348609 # number of WriteReq MSHR hits 473system.cpu.dcache.demand_mshr_hits::cpu.inst 348822 # number of demand (read+write) MSHR hits 474system.cpu.dcache.demand_mshr_hits::total 348822 # number of demand (read+write) MSHR hits 475system.cpu.dcache.overall_mshr_hits::cpu.inst 348822 # number of overall MSHR hits 476system.cpu.dcache.overall_mshr_hits::total 348822 # number of overall MSHR hits 477system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7337499 # number of ReadReq MSHR misses 478system.cpu.dcache.ReadReq_mshr_misses::total 7337499 # number of ReadReq MSHR misses 479system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890908 # number of WriteReq MSHR misses 480system.cpu.dcache.WriteReq_mshr_misses::total 1890908 # number of WriteReq MSHR misses 481system.cpu.dcache.demand_mshr_misses::cpu.inst 9228407 # number of demand (read+write) MSHR misses 482system.cpu.dcache.demand_mshr_misses::total 9228407 # number of demand (read+write) MSHR misses 483system.cpu.dcache.overall_mshr_misses::cpu.inst 9228407 # number of overall MSHR misses 484system.cpu.dcache.overall_mshr_misses::total 9228407 # number of overall MSHR misses 485system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168505826254 # number of ReadReq MSHR miss cycles 486system.cpu.dcache.ReadReq_mshr_miss_latency::total 168505826254 # number of ReadReq MSHR miss cycles 487system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77457723500 # number of WriteReq MSHR miss cycles 488system.cpu.dcache.WriteReq_mshr_miss_latency::total 77457723500 # number of WriteReq MSHR miss cycles 489system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245963549754 # number of demand (read+write) MSHR miss cycles 490system.cpu.dcache.demand_mshr_miss_latency::total 245963549754 # number of demand (read+write) MSHR miss cycles 491system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245963549754 # number of overall MSHR miss cycles 492system.cpu.dcache.overall_mshr_miss_latency::total 245963549754 # number of overall MSHR miss cycles 493system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015914 # mshr miss rate for ReadReq accesses 494system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015914 # mshr miss rate for ReadReq accesses | 501system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks 502system.cpu.dcache.writebacks::total 3701129 # number of writebacks 503system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 221 # number of ReadReq MSHR hits 504system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits 505system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348484 # number of WriteReq MSHR hits 506system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits 507system.cpu.dcache.demand_mshr_hits::cpu.inst 348705 # number of demand (read+write) MSHR hits 508system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits 509system.cpu.dcache.overall_mshr_hits::cpu.inst 348705 # number of overall MSHR hits 510system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits 511system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336901 # number of ReadReq MSHR misses 512system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses 513system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890919 # number of WriteReq MSHR misses 514system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses 515system.cpu.dcache.demand_mshr_misses::cpu.inst 9227820 # number of demand (read+write) MSHR misses 516system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses 517system.cpu.dcache.overall_mshr_misses::cpu.inst 9227820 # number of overall MSHR misses 518system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses 519system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168309061254 # number of ReadReq MSHR miss cycles 520system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles 521system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77322111500 # number of WriteReq MSHR miss cycles 522system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles 523system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245631172754 # number of demand (read+write) MSHR miss cycles 524system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles 525system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245631172754 # number of overall MSHR miss cycles 526system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles 527system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses 528system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses |
| 495system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses 496system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses | 529system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses 530system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses |
| 497system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for demand accesses 498system.cpu.dcache.demand_mshr_miss_rate::total 0.014564 # mshr miss rate for demand accesses 499system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for overall accesses 500system.cpu.dcache.overall_mshr_miss_rate::total 0.014564 # mshr miss rate for overall accesses 501system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22965.022040 # average ReadReq mshr miss latency 502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22965.022040 # average ReadReq mshr miss latency 503system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40963.242791 # average WriteReq mshr miss latency 504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40963.242791 # average WriteReq mshr miss latency 505system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency 506system.cpu.dcache.demand_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency 507system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency 508system.cpu.dcache.overall_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency | 531system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses 532system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses 533system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses 534system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses 535system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22940.075279 # average ReadReq mshr miss latency 536system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279 # average ReadReq mshr miss latency 537system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40891.286988 # average WriteReq mshr miss latency 538system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988 # average WriteReq mshr miss latency 539system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency 540system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency 541system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26618.548341 # average overall mshr miss latency 542system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency |
| 509system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 510system.cpu.icache.tags.replacements 29 # number of replacements | 543system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 544system.cpu.icache.tags.replacements 29 # number of replacements |
| 511system.cpu.icache.tags.tagsinuse 661.026879 # Cycle average of tags in use 512system.cpu.icache.tags.total_refs 466133968 # Total number of references to valid blocks. | 545system.cpu.icache.tags.tagsinuse 661.153981 # Cycle average of tags in use 546system.cpu.icache.tags.total_refs 466170177 # Total number of references to valid blocks. |
| 513system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. | 547system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. |
| 514system.cpu.icache.tags.avg_refs 568456.058537 # Average number of references to valid blocks. | 548system.cpu.icache.tags.avg_refs 568500.215854 # Average number of references to valid blocks. |
| 515system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 549system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 516system.cpu.icache.tags.occ_blocks::cpu.inst 661.026879 # Average occupied blocks per requestor 517system.cpu.icache.tags.occ_percent::cpu.inst 0.322767 # Average percentage of cache occupancy 518system.cpu.icache.tags.occ_percent::total 0.322767 # Average percentage of cache occupancy | 550system.cpu.icache.tags.occ_blocks::cpu.inst 661.153981 # Average occupied blocks per requestor 551system.cpu.icache.tags.occ_percent::cpu.inst 0.322829 # Average percentage of cache occupancy 552system.cpu.icache.tags.occ_percent::total 0.322829 # Average percentage of cache occupancy |
| 519system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id | 553system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id |
| 520system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id | 554system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id |
| 521system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id | 555system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id |
| 522system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id | 556system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id |
| 523system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id | 557system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id |
| 524system.cpu.icache.tags.tag_accesses 932270396 # Number of tag accesses 525system.cpu.icache.tags.data_accesses 932270396 # Number of data accesses 526system.cpu.icache.ReadReq_hits::cpu.inst 466133968 # number of ReadReq hits 527system.cpu.icache.ReadReq_hits::total 466133968 # number of ReadReq hits 528system.cpu.icache.demand_hits::cpu.inst 466133968 # number of demand (read+write) hits 529system.cpu.icache.demand_hits::total 466133968 # number of demand (read+write) hits 530system.cpu.icache.overall_hits::cpu.inst 466133968 # number of overall hits 531system.cpu.icache.overall_hits::total 466133968 # number of overall hits | 558system.cpu.icache.tags.tag_accesses 932342814 # Number of tag accesses 559system.cpu.icache.tags.data_accesses 932342814 # Number of data accesses 560system.cpu.icache.ReadReq_hits::cpu.inst 466170177 # number of ReadReq hits 561system.cpu.icache.ReadReq_hits::total 466170177 # number of ReadReq hits 562system.cpu.icache.demand_hits::cpu.inst 466170177 # number of demand (read+write) hits 563system.cpu.icache.demand_hits::total 466170177 # number of demand (read+write) hits 564system.cpu.icache.overall_hits::cpu.inst 466170177 # number of overall hits 565system.cpu.icache.overall_hits::total 466170177 # number of overall hits |
| 532system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses 533system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses 534system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses 535system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses 536system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses 537system.cpu.icache.overall_misses::total 820 # number of overall misses | 566system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses 567system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses 568system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses 569system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses 570system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses 571system.cpu.icache.overall_misses::total 820 # number of overall misses |
| 538system.cpu.icache.ReadReq_miss_latency::cpu.inst 58416499 # number of ReadReq miss cycles 539system.cpu.icache.ReadReq_miss_latency::total 58416499 # number of ReadReq miss cycles 540system.cpu.icache.demand_miss_latency::cpu.inst 58416499 # number of demand (read+write) miss cycles 541system.cpu.icache.demand_miss_latency::total 58416499 # number of demand (read+write) miss cycles 542system.cpu.icache.overall_miss_latency::cpu.inst 58416499 # number of overall miss cycles 543system.cpu.icache.overall_miss_latency::total 58416499 # number of overall miss cycles 544system.cpu.icache.ReadReq_accesses::cpu.inst 466134788 # number of ReadReq accesses(hits+misses) 545system.cpu.icache.ReadReq_accesses::total 466134788 # number of ReadReq accesses(hits+misses) 546system.cpu.icache.demand_accesses::cpu.inst 466134788 # number of demand (read+write) accesses 547system.cpu.icache.demand_accesses::total 466134788 # number of demand (read+write) accesses 548system.cpu.icache.overall_accesses::cpu.inst 466134788 # number of overall (read+write) accesses 549system.cpu.icache.overall_accesses::total 466134788 # number of overall (read+write) accesses | 572system.cpu.icache.ReadReq_miss_latency::cpu.inst 58360249 # number of ReadReq miss cycles 573system.cpu.icache.ReadReq_miss_latency::total 58360249 # number of ReadReq miss cycles 574system.cpu.icache.demand_miss_latency::cpu.inst 58360249 # number of demand (read+write) miss cycles 575system.cpu.icache.demand_miss_latency::total 58360249 # number of demand (read+write) miss cycles 576system.cpu.icache.overall_miss_latency::cpu.inst 58360249 # number of overall miss cycles 577system.cpu.icache.overall_miss_latency::total 58360249 # number of overall miss cycles 578system.cpu.icache.ReadReq_accesses::cpu.inst 466170997 # number of ReadReq accesses(hits+misses) 579system.cpu.icache.ReadReq_accesses::total 466170997 # number of ReadReq accesses(hits+misses) 580system.cpu.icache.demand_accesses::cpu.inst 466170997 # number of demand (read+write) accesses 581system.cpu.icache.demand_accesses::total 466170997 # number of demand (read+write) accesses 582system.cpu.icache.overall_accesses::cpu.inst 466170997 # number of overall (read+write) accesses 583system.cpu.icache.overall_accesses::total 466170997 # number of overall (read+write) accesses |
| 550system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 551system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 552system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 553system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 554system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 555system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses | 584system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 585system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 586system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 587system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 588system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 589system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses |
| 556system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71239.632927 # average ReadReq miss latency 557system.cpu.icache.ReadReq_avg_miss_latency::total 71239.632927 # average ReadReq miss latency 558system.cpu.icache.demand_avg_miss_latency::cpu.inst 71239.632927 # average overall miss latency 559system.cpu.icache.demand_avg_miss_latency::total 71239.632927 # average overall miss latency 560system.cpu.icache.overall_avg_miss_latency::cpu.inst 71239.632927 # average overall miss latency 561system.cpu.icache.overall_avg_miss_latency::total 71239.632927 # average overall miss latency | 590system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71171.035366 # average ReadReq miss latency 591system.cpu.icache.ReadReq_avg_miss_latency::total 71171.035366 # average ReadReq miss latency 592system.cpu.icache.demand_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency 593system.cpu.icache.demand_avg_miss_latency::total 71171.035366 # average overall miss latency 594system.cpu.icache.overall_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency 595system.cpu.icache.overall_avg_miss_latency::total 71171.035366 # average overall miss latency |
| 562system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 563system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 564system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 565system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 566system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 567system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 568system.cpu.icache.fast_writes 0 # number of fast writes performed 569system.cpu.icache.cache_copies 0 # number of cache copies performed 570system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses 571system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses 572system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses 573system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses 574system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses 575system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses | 596system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 597system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 598system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 599system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 600system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 601system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 602system.cpu.icache.fast_writes 0 # number of fast writes performed 603system.cpu.icache.cache_copies 0 # number of cache copies performed 604system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses 605system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses 606system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses 607system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses 608system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses 609system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses |
| 576system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56453501 # number of ReadReq MSHR miss cycles 577system.cpu.icache.ReadReq_mshr_miss_latency::total 56453501 # number of ReadReq MSHR miss cycles 578system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56453501 # number of demand (read+write) MSHR miss cycles 579system.cpu.icache.demand_mshr_miss_latency::total 56453501 # number of demand (read+write) MSHR miss cycles 580system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56453501 # number of overall MSHR miss cycles 581system.cpu.icache.overall_mshr_miss_latency::total 56453501 # number of overall MSHR miss cycles | 610system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56400751 # number of ReadReq MSHR miss cycles 611system.cpu.icache.ReadReq_mshr_miss_latency::total 56400751 # number of ReadReq MSHR miss cycles 612system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56400751 # number of demand (read+write) MSHR miss cycles 613system.cpu.icache.demand_mshr_miss_latency::total 56400751 # number of demand (read+write) MSHR miss cycles 614system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56400751 # number of overall MSHR miss cycles 615system.cpu.icache.overall_mshr_miss_latency::total 56400751 # number of overall MSHR miss cycles |
| 582system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 583system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 584system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 585system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 586system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 587system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses | 616system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 617system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 618system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 619system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 620system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 621system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses |
| 588system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68845.732927 # average ReadReq mshr miss latency 589system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68845.732927 # average ReadReq mshr miss latency 590system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68845.732927 # average overall mshr miss latency 591system.cpu.icache.demand_avg_mshr_miss_latency::total 68845.732927 # average overall mshr miss latency 592system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68845.732927 # average overall mshr miss latency 593system.cpu.icache.overall_avg_mshr_miss_latency::total 68845.732927 # average overall mshr miss latency | 622system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68781.403659 # average ReadReq mshr miss latency 623system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68781.403659 # average ReadReq mshr miss latency 624system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency 625system.cpu.icache.demand_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency 626system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency 627system.cpu.icache.overall_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency |
| 594system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 628system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 595system.cpu.l2cache.tags.replacements 2023942 # number of replacements 596system.cpu.l2cache.tags.tagsinuse 31254.337993 # Cycle average of tags in use 597system.cpu.l2cache.tags.total_refs 8984488 # Total number of references to valid blocks. 598system.cpu.l2cache.tags.sampled_refs 2053718 # Sample count of references to valid blocks. 599system.cpu.l2cache.tags.avg_refs 4.374743 # Average number of references to valid blocks. | 629system.cpu.l2cache.tags.replacements 2022895 # number of replacements 630system.cpu.l2cache.tags.tagsinuse 31254.140512 # Cycle average of tags in use 631system.cpu.l2cache.tags.total_refs 8985448 # Total number of references to valid blocks. 632system.cpu.l2cache.tags.sampled_refs 2052670 # Sample count of references to valid blocks. 633system.cpu.l2cache.tags.avg_refs 4.377444 # Average number of references to valid blocks. |
| 600system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit. | 634system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit. |
| 601system.cpu.l2cache.tags.occ_blocks::writebacks 14996.949277 # Average occupied blocks per requestor 602system.cpu.l2cache.tags.occ_blocks::cpu.inst 16257.388715 # Average occupied blocks per requestor 603system.cpu.l2cache.tags.occ_percent::writebacks 0.457671 # Average percentage of cache occupancy 604system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496136 # Average percentage of cache occupancy 605system.cpu.l2cache.tags.occ_percent::total 0.953807 # Average percentage of cache occupancy 606system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id 607system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id | 635system.cpu.l2cache.tags.occ_blocks::writebacks 14999.285776 # Average occupied blocks per requestor 636system.cpu.l2cache.tags.occ_blocks::cpu.inst 16254.854737 # Average occupied blocks per requestor 637system.cpu.l2cache.tags.occ_percent::writebacks 0.457742 # Average percentage of cache occupancy 638system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496059 # Average percentage of cache occupancy 639system.cpu.l2cache.tags.occ_percent::total 0.953801 # Average percentage of cache occupancy 640system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id 641system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id |
| 608system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id | 642system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id |
| 609system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id 610system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id | 643system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id 644system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12850 # Occupied blocks per task id |
| 611system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id | 645system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id |
| 612system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id 613system.cpu.l2cache.tags.tag_accesses 107383386 # Number of tag accesses 614system.cpu.l2cache.tags.data_accesses 107383386 # Number of data accesses 615system.cpu.l2cache.ReadReq_hits::cpu.inst 6081991 # number of ReadReq hits 616system.cpu.l2cache.ReadReq_hits::total 6081991 # number of ReadReq hits 617system.cpu.l2cache.Writeback_hits::writebacks 3700618 # number of Writeback hits 618system.cpu.l2cache.Writeback_hits::total 3700618 # number of Writeback hits 619system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090584 # number of ReadExReq hits 620system.cpu.l2cache.ReadExReq_hits::total 1090584 # number of ReadExReq hits 621system.cpu.l2cache.demand_hits::cpu.inst 7172575 # number of demand (read+write) hits 622system.cpu.l2cache.demand_hits::total 7172575 # number of demand (read+write) hits 623system.cpu.l2cache.overall_hits::cpu.inst 7172575 # number of overall hits 624system.cpu.l2cache.overall_hits::total 7172575 # number of overall hits 625system.cpu.l2cache.ReadReq_misses::cpu.inst 1256328 # number of ReadReq misses 626system.cpu.l2cache.ReadReq_misses::total 1256328 # number of ReadReq misses 627system.cpu.l2cache.ReadExReq_misses::cpu.inst 800324 # number of ReadExReq misses 628system.cpu.l2cache.ReadExReq_misses::total 800324 # number of ReadExReq misses 629system.cpu.l2cache.demand_misses::cpu.inst 2056652 # number of demand (read+write) misses 630system.cpu.l2cache.demand_misses::total 2056652 # number of demand (read+write) misses 631system.cpu.l2cache.overall_misses::cpu.inst 2056652 # number of overall misses 632system.cpu.l2cache.overall_misses::total 2056652 # number of overall misses 633system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100398878250 # number of ReadReq miss cycles 634system.cpu.l2cache.ReadReq_miss_latency::total 100398878250 # number of ReadReq miss cycles 635system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64605165750 # number of ReadExReq miss cycles 636system.cpu.l2cache.ReadExReq_miss_latency::total 64605165750 # number of ReadExReq miss cycles 637system.cpu.l2cache.demand_miss_latency::cpu.inst 165004044000 # number of demand (read+write) miss cycles 638system.cpu.l2cache.demand_miss_latency::total 165004044000 # number of demand (read+write) miss cycles 639system.cpu.l2cache.overall_miss_latency::cpu.inst 165004044000 # number of overall miss cycles 640system.cpu.l2cache.overall_miss_latency::total 165004044000 # number of overall miss cycles 641system.cpu.l2cache.ReadReq_accesses::cpu.inst 7338319 # number of ReadReq accesses(hits+misses) 642system.cpu.l2cache.ReadReq_accesses::total 7338319 # number of ReadReq accesses(hits+misses) 643system.cpu.l2cache.Writeback_accesses::writebacks 3700618 # number of Writeback accesses(hits+misses) 644system.cpu.l2cache.Writeback_accesses::total 3700618 # number of Writeback accesses(hits+misses) 645system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890908 # number of ReadExReq accesses(hits+misses) 646system.cpu.l2cache.ReadExReq_accesses::total 1890908 # number of ReadExReq accesses(hits+misses) 647system.cpu.l2cache.demand_accesses::cpu.inst 9229227 # number of demand (read+write) accesses 648system.cpu.l2cache.demand_accesses::total 9229227 # number of demand (read+write) accesses 649system.cpu.l2cache.overall_accesses::cpu.inst 9229227 # number of overall (read+write) accesses 650system.cpu.l2cache.overall_accesses::total 9229227 # number of overall (read+write) accesses 651system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171201 # miss rate for ReadReq accesses 652system.cpu.l2cache.ReadReq_miss_rate::total 0.171201 # miss rate for ReadReq accesses 653system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423249 # miss rate for ReadExReq accesses 654system.cpu.l2cache.ReadExReq_miss_rate::total 0.423249 # miss rate for ReadExReq accesses 655system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222841 # miss rate for demand accesses 656system.cpu.l2cache.demand_miss_rate::total 0.222841 # miss rate for demand accesses 657system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222841 # miss rate for overall accesses 658system.cpu.l2cache.overall_miss_rate::total 0.222841 # miss rate for overall accesses 659system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79914.543216 # average ReadReq miss latency 660system.cpu.l2cache.ReadReq_avg_miss_latency::total 79914.543216 # average ReadReq miss latency 661system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80723.764063 # average ReadExReq miss latency 662system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80723.764063 # average ReadExReq miss latency 663system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80229.442803 # average overall miss latency 664system.cpu.l2cache.demand_avg_miss_latency::total 80229.442803 # average overall miss latency 665system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80229.442803 # average overall miss latency 666system.cpu.l2cache.overall_avg_miss_latency::total 80229.442803 # average overall miss latency | 646system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id 647system.cpu.l2cache.tags.tag_accesses 107381741 # Number of tag accesses 648system.cpu.l2cache.tags.data_accesses 107381741 # Number of data accesses 649system.cpu.l2cache.ReadReq_hits::cpu.inst 6082213 # number of ReadReq hits 650system.cpu.l2cache.ReadReq_hits::total 6082213 # number of ReadReq hits 651system.cpu.l2cache.Writeback_hits::writebacks 3701129 # number of Writeback hits 652system.cpu.l2cache.Writeback_hits::total 3701129 # number of Writeback hits 653system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090823 # number of ReadExReq hits 654system.cpu.l2cache.ReadExReq_hits::total 1090823 # number of ReadExReq hits 655system.cpu.l2cache.demand_hits::cpu.inst 7173036 # number of demand (read+write) hits 656system.cpu.l2cache.demand_hits::total 7173036 # number of demand (read+write) hits 657system.cpu.l2cache.overall_hits::cpu.inst 7173036 # number of overall hits 658system.cpu.l2cache.overall_hits::total 7173036 # number of overall hits 659system.cpu.l2cache.ReadReq_misses::cpu.inst 1255508 # number of ReadReq misses 660system.cpu.l2cache.ReadReq_misses::total 1255508 # number of ReadReq misses 661system.cpu.l2cache.ReadExReq_misses::cpu.inst 800096 # number of ReadExReq misses 662system.cpu.l2cache.ReadExReq_misses::total 800096 # number of ReadExReq misses 663system.cpu.l2cache.demand_misses::cpu.inst 2055604 # number of demand (read+write) misses 664system.cpu.l2cache.demand_misses::total 2055604 # number of demand (read+write) misses 665system.cpu.l2cache.overall_misses::cpu.inst 2055604 # number of overall misses 666system.cpu.l2cache.overall_misses::total 2055604 # number of overall misses 667system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100200408000 # number of ReadReq miss cycles 668system.cpu.l2cache.ReadReq_miss_latency::total 100200408000 # number of ReadReq miss cycles 669system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64467346000 # number of ReadExReq miss cycles 670system.cpu.l2cache.ReadExReq_miss_latency::total 64467346000 # number of ReadExReq miss cycles 671system.cpu.l2cache.demand_miss_latency::cpu.inst 164667754000 # number of demand (read+write) miss cycles 672system.cpu.l2cache.demand_miss_latency::total 164667754000 # number of demand (read+write) miss cycles 673system.cpu.l2cache.overall_miss_latency::cpu.inst 164667754000 # number of overall miss cycles 674system.cpu.l2cache.overall_miss_latency::total 164667754000 # number of overall miss cycles 675system.cpu.l2cache.ReadReq_accesses::cpu.inst 7337721 # number of ReadReq accesses(hits+misses) 676system.cpu.l2cache.ReadReq_accesses::total 7337721 # number of ReadReq accesses(hits+misses) 677system.cpu.l2cache.Writeback_accesses::writebacks 3701129 # number of Writeback accesses(hits+misses) 678system.cpu.l2cache.Writeback_accesses::total 3701129 # number of Writeback accesses(hits+misses) 679system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890919 # number of ReadExReq accesses(hits+misses) 680system.cpu.l2cache.ReadExReq_accesses::total 1890919 # number of ReadExReq accesses(hits+misses) 681system.cpu.l2cache.demand_accesses::cpu.inst 9228640 # number of demand (read+write) accesses 682system.cpu.l2cache.demand_accesses::total 9228640 # number of demand (read+write) accesses 683system.cpu.l2cache.overall_accesses::cpu.inst 9228640 # number of overall (read+write) accesses 684system.cpu.l2cache.overall_accesses::total 9228640 # number of overall (read+write) accesses 685system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171103 # miss rate for ReadReq accesses 686system.cpu.l2cache.ReadReq_miss_rate::total 0.171103 # miss rate for ReadReq accesses 687system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423125 # miss rate for ReadExReq accesses 688system.cpu.l2cache.ReadExReq_miss_rate::total 0.423125 # miss rate for ReadExReq accesses 689system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses 690system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses 691system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # miss rate for overall accesses 692system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses 693system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79808.657531 # average ReadReq miss latency 694system.cpu.l2cache.ReadReq_avg_miss_latency::total 79808.657531 # average ReadReq miss latency 695system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80574.513558 # average ReadExReq miss latency 696system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80574.513558 # average ReadExReq miss latency 697system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80106.749160 # average overall miss latency 698system.cpu.l2cache.demand_avg_miss_latency::total 80106.749160 # average overall miss latency 699system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80106.749160 # average overall miss latency 700system.cpu.l2cache.overall_avg_miss_latency::total 80106.749160 # average overall miss latency |
| 667system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 668system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 669system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 670system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 671system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 672system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 673system.cpu.l2cache.fast_writes 0 # number of fast writes performed 674system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 701system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 702system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 703system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 704system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 705system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 706system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 707system.cpu.l2cache.fast_writes 0 # number of fast writes performed 708system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 675system.cpu.l2cache.writebacks::writebacks 1046713 # number of writebacks 676system.cpu.l2cache.writebacks::total 1046713 # number of writebacks | 709system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks 710system.cpu.l2cache.writebacks::total 1046417 # number of writebacks |
| 677system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 678system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 679system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 680system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 681system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 682system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits | 711system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 712system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 713system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 714system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 715system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 716system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits |
| 683system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1256323 # number of ReadReq MSHR misses 684system.cpu.l2cache.ReadReq_mshr_misses::total 1256323 # number of ReadReq MSHR misses 685system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800324 # number of ReadExReq MSHR misses 686system.cpu.l2cache.ReadExReq_mshr_misses::total 800324 # number of ReadExReq MSHR misses 687system.cpu.l2cache.demand_mshr_misses::cpu.inst 2056647 # number of demand (read+write) MSHR misses 688system.cpu.l2cache.demand_mshr_misses::total 2056647 # number of demand (read+write) MSHR misses 689system.cpu.l2cache.overall_mshr_misses::cpu.inst 2056647 # number of overall MSHR misses 690system.cpu.l2cache.overall_mshr_misses::total 2056647 # number of overall MSHR misses 691system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84521118250 # number of ReadReq MSHR miss cycles 692system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84521118250 # number of ReadReq MSHR miss cycles 693system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54527231750 # number of ReadExReq MSHR miss cycles 694system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54527231750 # number of ReadExReq MSHR miss cycles 695system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139048350000 # number of demand (read+write) MSHR miss cycles 696system.cpu.l2cache.demand_mshr_miss_latency::total 139048350000 # number of demand (read+write) MSHR miss cycles 697system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139048350000 # number of overall MSHR miss cycles 698system.cpu.l2cache.overall_mshr_miss_latency::total 139048350000 # number of overall MSHR miss cycles 699system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171200 # mshr miss rate for ReadReq accesses 700system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171200 # mshr miss rate for ReadReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423249 # mshr miss rate for ReadExReq accesses 702system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423249 # mshr miss rate for ReadExReq accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::total 0.222841 # mshr miss rate for demand accesses 705system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for overall accesses 706system.cpu.l2cache.overall_mshr_miss_rate::total 0.222841 # mshr miss rate for overall accesses 707system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67276.582734 # average ReadReq mshr miss latency 708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67276.582734 # average ReadReq mshr miss latency 709system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68131.446452 # average ReadExReq mshr miss latency 710system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68131.446452 # average ReadExReq mshr miss latency 711system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency 712system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency 713system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency 714system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency | 717system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255503 # number of ReadReq MSHR misses 718system.cpu.l2cache.ReadReq_mshr_misses::total 1255503 # number of ReadReq MSHR misses 719system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800096 # number of ReadExReq MSHR misses 720system.cpu.l2cache.ReadExReq_mshr_misses::total 800096 # number of ReadExReq MSHR misses 721system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055599 # number of demand (read+write) MSHR misses 722system.cpu.l2cache.demand_mshr_misses::total 2055599 # number of demand (read+write) MSHR misses 723system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055599 # number of overall MSHR misses 724system.cpu.l2cache.overall_mshr_misses::total 2055599 # number of overall MSHR misses 725system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84332667000 # number of ReadReq MSHR miss cycles 726system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84332667000 # number of ReadReq MSHR miss cycles 727system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54391877500 # number of ReadExReq MSHR miss cycles 728system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54391877500 # number of ReadExReq MSHR miss cycles 729system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138724544500 # number of demand (read+write) MSHR miss cycles 730system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles 731system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138724544500 # number of overall MSHR miss cycles 732system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles 733system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171103 # mshr miss rate for ReadReq accesses 734system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses 735system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423125 # mshr miss rate for ReadExReq accesses 736system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses 737system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for demand accesses 738system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses 739system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222741 # mshr miss rate for overall accesses 740system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses 741system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67170.422532 # average ReadReq mshr miss latency 742system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency 743system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67981.689072 # average ReadExReq mshr miss latency 744system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency 745system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency 746system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency 747system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67486.189913 # average overall mshr miss latency 748system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency |
| 715system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 749system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 716system.cpu.toL2Bus.trans_dist::ReadReq 7338319 # Transaction distribution 717system.cpu.toL2Bus.trans_dist::ReadResp 7338319 # Transaction distribution 718system.cpu.toL2Bus.trans_dist::Writeback 3700618 # Transaction distribution 719system.cpu.toL2Bus.trans_dist::ReadExReq 1890908 # Transaction distribution 720system.cpu.toL2Bus.trans_dist::ReadExResp 1890908 # Transaction distribution | 750system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution 751system.cpu.toL2Bus.trans_dist::ReadResp 7337721 # Transaction distribution 752system.cpu.toL2Bus.trans_dist::Writeback 3701129 # Transaction distribution 753system.cpu.toL2Bus.trans_dist::ReadExReq 1890919 # Transaction distribution 754system.cpu.toL2Bus.trans_dist::ReadExResp 1890919 # Transaction distribution |
| 721system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) | 755system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) |
| 722system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22157432 # Packet count per connected master and slave (bytes) 723system.cpu.toL2Bus.pkt_count::total 22159072 # Packet count per connected master and slave (bytes) | 756system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156769 # Packet count per connected master and slave (bytes) 757system.cpu.toL2Bus.pkt_count::total 22158409 # Packet count per connected master and slave (bytes) |
| 724system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) | 758system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) |
| 725system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827457600 # Cumulative packet size per connected master and slave (bytes) 726system.cpu.toL2Bus.pkt_size::total 827510080 # Cumulative packet size per connected master and slave (bytes) | 759system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827452736 # Cumulative packet size per connected master and slave (bytes) 760system.cpu.toL2Bus.pkt_size::total 827505216 # Cumulative packet size per connected master and slave (bytes) |
| 727system.cpu.toL2Bus.snoops 0 # Total snoops (count) | 761system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| 728system.cpu.toL2Bus.snoop_fanout::samples 12929845 # Request fanout histogram | 762system.cpu.toL2Bus.snoop_fanout::samples 12929769 # Request fanout histogram |
| 729system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 730system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 731system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 732system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 733system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 734system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 735system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 736system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram | 763system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 764system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 765system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 766system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 767system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 768system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 769system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 770system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram |
| 737system.cpu.toL2Bus.snoop_fanout::5 12929845 100.00% 100.00% # Request fanout histogram | 771system.cpu.toL2Bus.snoop_fanout::5 12929769 100.00% 100.00% # Request fanout histogram |
| 738system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 739system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 740system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 741system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram | 772system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 773system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 774system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 775system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram |
| 742system.cpu.toL2Bus.snoop_fanout::total 12929845 # Request fanout histogram 743system.cpu.toL2Bus.reqLayer0.occupancy 10165540500 # Layer occupancy (ticks) | 776system.cpu.toL2Bus.snoop_fanout::total 12929769 # Request fanout histogram 777system.cpu.toL2Bus.reqLayer0.occupancy 10166013500 # Layer occupancy (ticks) |
| 744system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) | 778system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) |
| 745system.cpu.toL2Bus.respLayer0.occupancy 1391499 # Layer occupancy (ticks) | 779system.cpu.toL2Bus.respLayer0.occupancy 1389749 # Layer occupancy (ticks) |
| 746system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 780system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 747system.cpu.toL2Bus.respLayer1.occupancy 14187091746 # Layer occupancy (ticks) | 781system.cpu.toL2Bus.respLayer1.occupancy 14186681246 # Layer occupancy (ticks) |
| 748system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) | 782system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) |
| 749system.membus.trans_dist::ReadReq 1256323 # Transaction distribution 750system.membus.trans_dist::ReadResp 1256323 # Transaction distribution 751system.membus.trans_dist::Writeback 1046713 # Transaction distribution 752system.membus.trans_dist::ReadExReq 800324 # Transaction distribution 753system.membus.trans_dist::ReadExResp 800324 # Transaction distribution 754system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5160007 # Packet count per connected master and slave (bytes) 755system.membus.pkt_count::total 5160007 # Packet count per connected master and slave (bytes) 756system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198615040 # Cumulative packet size per connected master and slave (bytes) 757system.membus.pkt_size::total 198615040 # Cumulative packet size per connected master and slave (bytes) | 783system.membus.trans_dist::ReadReq 1255503 # Transaction distribution 784system.membus.trans_dist::ReadResp 1255503 # Transaction distribution 785system.membus.trans_dist::Writeback 1046417 # Transaction distribution 786system.membus.trans_dist::ReadExReq 800096 # Transaction distribution 787system.membus.trans_dist::ReadExResp 800096 # Transaction distribution 788system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157615 # Packet count per connected master and slave (bytes) 789system.membus.pkt_count::total 5157615 # Packet count per connected master and slave (bytes) 790system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198529024 # Cumulative packet size per connected master and slave (bytes) 791system.membus.pkt_size::total 198529024 # Cumulative packet size per connected master and slave (bytes) |
| 758system.membus.snoops 0 # Total snoops (count) | 792system.membus.snoops 0 # Total snoops (count) |
| 759system.membus.snoop_fanout::samples 3103360 # Request fanout histogram | 793system.membus.snoop_fanout::samples 3102016 # Request fanout histogram |
| 760system.membus.snoop_fanout::mean 0 # Request fanout histogram 761system.membus.snoop_fanout::stdev 0 # Request fanout histogram 762system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 794system.membus.snoop_fanout::mean 0 # Request fanout histogram 795system.membus.snoop_fanout::stdev 0 # Request fanout histogram 796system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 763system.membus.snoop_fanout::0 3103360 100.00% 100.00% # Request fanout histogram | 797system.membus.snoop_fanout::0 3102016 100.00% 100.00% # Request fanout histogram |
| 764system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 765system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 766system.membus.snoop_fanout::min_value 0 # Request fanout histogram 767system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 798system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 799system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 800system.membus.snoop_fanout::min_value 0 # Request fanout histogram 801system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 768system.membus.snoop_fanout::total 3103360 # Request fanout histogram 769system.membus.reqLayer0.occupancy 12130659500 # Layer occupancy (ticks) | 802system.membus.snoop_fanout::total 3102016 # Request fanout histogram 803system.membus.reqLayer0.occupancy 12126859000 # Layer occupancy (ticks) |
| 770system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) | 804system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) |
| 771system.membus.respLayer1.occupancy 19439818500 # Layer occupancy (ticks) | 805system.membus.respLayer1.occupancy 19430032500 # Layer occupancy (ticks) |
| 772system.membus.respLayer1.utilization 1.8 # Layer utilization (%) 773 774---------- End Simulation Statistics ---------- | 806system.membus.respLayer1.utilization 1.8 # Layer utilization (%) 807 808---------- End Simulation Statistics ---------- |