| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 1.095875 # Number of seconds simulated 4sim_ticks 1095875470500 # Number of ticks simulated 5final_tick 1095875470500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 1.096187 # Number of seconds simulated 4sim_ticks 1096186990500 # Number of ticks simulated 5final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 232088 # Simulator instruction rate (inst/s) 8host_op_rate 250040 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 164667871 # Simulator tick rate (ticks/s) 10host_mem_usage 318056 # Number of bytes of host memory used 11host_seconds 6655.07 # Real time elapsed on the host | 7host_inst_rate 242878 # Simulator instruction rate (inst/s) 8host_op_rate 261664 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 172372275 # Simulator tick rate (ticks/s) 10host_mem_usage 308000 # Number of bytes of host memory used 11host_seconds 6359.42 # Real time elapsed on the host |
| 12sim_insts 1544563087 # Number of instructions simulated 13sim_ops 1664032480 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 1544563087 # Number of instructions simulated 13sim_ops 1664032480 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 131539072 # Number of bytes read from this memory 17system.physmem.bytes_read::total 131539072 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 131551936 # Number of bytes read from this memory 17system.physmem.bytes_read::total 131551936 # Number of bytes read from this memory |
| 18system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory | 18system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory |
| 20system.physmem.bytes_written::writebacks 66963456 # Number of bytes written to this memory 21system.physmem.bytes_written::total 66963456 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 2055298 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2055298 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1046304 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1046304 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 120031040 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 120031040 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 46020 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 46020 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 61104987 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 61104987 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 61104987 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 120031040 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 181136026 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 2055298 # Number of read requests accepted 36system.physmem.writeReqs 1046304 # Number of write requests accepted 37system.physmem.readBursts 2055298 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 1046304 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 131453056 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue 41system.physmem.bytesWritten 66961856 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 131539072 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 66963456 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue | 20system.physmem.bytes_written::writebacks 66968384 # Number of bytes written to this memory 21system.physmem.bytes_written::total 66968384 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 2055499 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2055499 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1046381 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1046381 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 120008664 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 120008664 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 46007 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 46007 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 61092117 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 61092117 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 61092117 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 120008664 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 181100781 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 2055499 # Number of read requests accepted 36system.physmem.writeReqs 1046381 # Number of write requests accepted 37system.physmem.readBursts 2055499 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 1046381 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 131465088 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 86848 # Total number of bytes read from write queue 41system.physmem.bytesWritten 66966784 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 131551936 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 66968384 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 1357 # Number of DRAM read bursts serviced by the write queue |
| 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 47system.physmem.perBankRdBursts::0 127944 # Per bank write bursts 48system.physmem.perBankRdBursts::1 125151 # Per bank write bursts 49system.physmem.perBankRdBursts::2 122313 # Per bank write bursts 50system.physmem.perBankRdBursts::3 124176 # Per bank write bursts 51system.physmem.perBankRdBursts::4 123203 # Per bank write bursts 52system.physmem.perBankRdBursts::5 123365 # Per bank write bursts 53system.physmem.perBankRdBursts::6 123797 # Per bank write bursts 54system.physmem.perBankRdBursts::7 124247 # Per bank write bursts 55system.physmem.perBankRdBursts::8 131879 # Per bank write bursts 56system.physmem.perBankRdBursts::9 134089 # Per bank write bursts 57system.physmem.perBankRdBursts::10 132451 # Per bank write bursts 58system.physmem.perBankRdBursts::11 133680 # Per bank write bursts 59system.physmem.perBankRdBursts::12 133764 # Per bank write bursts 60system.physmem.perBankRdBursts::13 133810 # Per bank write bursts 61system.physmem.perBankRdBursts::14 129795 # Per bank write bursts 62system.physmem.perBankRdBursts::15 130290 # Per bank write bursts 63system.physmem.perBankWrBursts::0 65788 # Per bank write bursts 64system.physmem.perBankWrBursts::1 64108 # Per bank write bursts 65system.physmem.perBankWrBursts::2 62418 # Per bank write bursts 66system.physmem.perBankWrBursts::3 62855 # Per bank write bursts 67system.physmem.perBankWrBursts::4 62808 # Per bank write bursts 68system.physmem.perBankWrBursts::5 62982 # Per bank write bursts 69system.physmem.perBankWrBursts::6 64271 # Per bank write bursts 70system.physmem.perBankWrBursts::7 65268 # Per bank write bursts 71system.physmem.perBankWrBursts::8 67081 # Per bank write bursts 72system.physmem.perBankWrBursts::9 67609 # Per bank write bursts 73system.physmem.perBankWrBursts::10 67274 # Per bank write bursts 74system.physmem.perBankWrBursts::11 67626 # Per bank write bursts 75system.physmem.perBankWrBursts::12 67000 # Per bank write bursts 76system.physmem.perBankWrBursts::13 67431 # Per bank write bursts 77system.physmem.perBankWrBursts::14 66125 # Per bank write bursts 78system.physmem.perBankWrBursts::15 65635 # Per bank write bursts | 47system.physmem.perBankRdBursts::0 127914 # Per bank write bursts 48system.physmem.perBankRdBursts::1 125107 # Per bank write bursts 49system.physmem.perBankRdBursts::2 122280 # Per bank write bursts 50system.physmem.perBankRdBursts::3 124254 # Per bank write bursts 51system.physmem.perBankRdBursts::4 123262 # Per bank write bursts 52system.physmem.perBankRdBursts::5 123345 # Per bank write bursts 53system.physmem.perBankRdBursts::6 123865 # Per bank write bursts 54system.physmem.perBankRdBursts::7 124190 # Per bank write bursts 55system.physmem.perBankRdBursts::8 131999 # Per bank write bursts 56system.physmem.perBankRdBursts::9 134064 # Per bank write bursts 57system.physmem.perBankRdBursts::10 132428 # Per bank write bursts 58system.physmem.perBankRdBursts::11 133673 # Per bank write bursts 59system.physmem.perBankRdBursts::12 133725 # Per bank write bursts 60system.physmem.perBankRdBursts::13 133862 # Per bank write bursts 61system.physmem.perBankRdBursts::14 129895 # Per bank write bursts 62system.physmem.perBankRdBursts::15 130279 # Per bank write bursts 63system.physmem.perBankWrBursts::0 65789 # Per bank write bursts 64system.physmem.perBankWrBursts::1 64087 # Per bank write bursts 65system.physmem.perBankWrBursts::2 62403 # Per bank write bursts 66system.physmem.perBankWrBursts::3 62885 # Per bank write bursts 67system.physmem.perBankWrBursts::4 62820 # Per bank write bursts 68system.physmem.perBankWrBursts::5 62979 # Per bank write bursts 69system.physmem.perBankWrBursts::6 64285 # Per bank write bursts 70system.physmem.perBankWrBursts::7 65232 # Per bank write bursts 71system.physmem.perBankWrBursts::8 67082 # Per bank write bursts 72system.physmem.perBankWrBursts::9 67588 # Per bank write bursts 73system.physmem.perBankWrBursts::10 67303 # Per bank write bursts 74system.physmem.perBankWrBursts::11 67613 # Per bank write bursts 75system.physmem.perBankWrBursts::12 67020 # Per bank write bursts 76system.physmem.perBankWrBursts::13 67468 # Per bank write bursts 77system.physmem.perBankWrBursts::14 66169 # Per bank write bursts 78system.physmem.perBankWrBursts::15 65633 # Per bank write bursts |
| 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 81system.physmem.totGap 1095875382500 # Total gap between requests | 81system.physmem.totGap 1096186902500 # Total gap between requests |
| 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) | 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 88system.physmem.readPktSize::6 2055298 # Read request sizes (log2) | 88system.physmem.readPktSize::6 2055499 # Read request sizes (log2) |
| 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) | 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 95system.physmem.writePktSize::6 1046304 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 1922424 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 131512 # What read queue length does an incoming req see | 95system.physmem.writePktSize::6 1046381 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 1922421 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 131703 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 143system.physmem.wrQLenPdf::15 33528 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 34841 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 57203 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 60757 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 61403 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 61327 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 61251 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 61258 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 61259 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 61367 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 61289 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 61334 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 62306 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 61683 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 61440 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 62194 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 60945 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 60798 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::15 31796 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 33166 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 57030 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 60853 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 61386 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 61606 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 61543 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 61534 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 61519 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 61592 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 61559 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 61936 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 62305 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 61675 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 62790 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 61332 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 61028 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 81 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see |
| 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 192system.physmem.bytesPerActivate::samples 1911965 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 103.774418 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 81.877172 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 125.825249 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 1485376 77.69% 77.69% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 306998 16.06% 93.75% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 52789 2.76% 96.51% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 21060 1.10% 97.61% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 13283 0.69% 98.30% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 6873 0.36% 98.66% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 5659 0.30% 98.96% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 4134 0.22% 99.17% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 15793 0.83% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 1911965 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 60795 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 33.737117 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 161.571664 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 60754 99.93% 99.93% # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes | 192system.physmem.bytesPerActivate::samples 1916158 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 103.556187 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 81.764224 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 125.552714 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 1491113 77.82% 77.82% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 305811 15.96% 93.78% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 52727 2.75% 96.53% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 21051 1.10% 97.63% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 13077 0.68% 98.31% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 6875 0.36% 98.67% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 5570 0.29% 98.96% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 4107 0.21% 99.17% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 15827 0.83% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 1916158 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 61021 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 33.615247 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 160.737468 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 60978 99.93% 99.93% # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::1024-2047 19 0.03% 99.96% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes |
| 213system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes | 213system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes |
| 214system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes | 214system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes |
| 215system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes | 215system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes | 216system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 217system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes | 217system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::total 60795 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 60795 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 17.209951 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 17.175292 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 1.091996 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 25805 42.45% 42.45% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 1192 1.96% 44.41% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 29551 48.61% 93.01% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 3811 6.27% 99.28% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 363 0.60% 99.88% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::21 60 0.10% 99.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::22 11 0.02% 100.00% # Writes before turning the bus around for reads | 218system.physmem.rdPerTurnAround::total 61021 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 61021 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 17.147474 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 17.112394 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 1.099372 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 27727 45.44% 45.44% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 1223 2.00% 47.44% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 27936 45.78% 93.22% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 3708 6.08% 99.30% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 355 0.58% 99.88% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::21 59 0.10% 99.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::22 10 0.02% 100.00% # Writes before turning the bus around for reads |
| 230system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads | 230system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads |
| 231system.physmem.wrPerTurnAround::total 60795 # Writes before turning the bus around for reads 232system.physmem.totQLat 38124649000 # Total ticks spent queuing 233system.physmem.totMemAccLat 76636286500 # Total ticks spent from burst creation until serviced by the DRAM 234system.physmem.totBusLat 10269770000 # Total ticks spent in databus transfers 235system.physmem.avgQLat 18561.59 # Average queueing delay per DRAM burst | 231system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads 232system.physmem.wrPerTurnAround::total 61021 # Writes before turning the bus around for reads 233system.physmem.totQLat 38533876500 # Total ticks spent queuing 234system.physmem.totMemAccLat 77049039000 # Total ticks spent from burst creation until serviced by the DRAM 235system.physmem.totBusLat 10270710000 # Total ticks spent in databus transfers 236system.physmem.avgQLat 18759.11 # Average queueing delay per DRAM burst |
| 236system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 237system.physmem.avgMemAccLat 37311.59 # Average memory access latency per DRAM burst 238system.physmem.avgRdBW 119.95 # Average DRAM read bandwidth in MiByte/s 239system.physmem.avgWrBW 61.10 # Average achieved write bandwidth in MiByte/s 240system.physmem.avgRdBWSys 120.03 # Average system read bandwidth in MiByte/s 241system.physmem.avgWrBWSys 61.10 # Average system write bandwidth in MiByte/s | 238system.physmem.avgMemAccLat 37509.11 # Average memory access latency per DRAM burst 239system.physmem.avgRdBW 119.93 # Average DRAM read bandwidth in MiByte/s 240system.physmem.avgWrBW 61.09 # Average achieved write bandwidth in MiByte/s 241system.physmem.avgRdBWSys 120.01 # Average system read bandwidth in MiByte/s 242system.physmem.avgWrBWSys 61.09 # Average system write bandwidth in MiByte/s |
| 242system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 243system.physmem.busUtil 1.41 # Data bus utilization in percentage 244system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads 245system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes 246system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing | 243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 244system.physmem.busUtil 1.41 # Data bus utilization in percentage 245system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads 246system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes 247system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing |
| 247system.physmem.avgWrQLen 24.69 # Average write queue length when enqueuing 248system.physmem.readRowHits 779774 # Number of row buffer hits during reads 249system.physmem.writeRowHits 408484 # Number of row buffer hits during writes 250system.physmem.readRowHitRate 37.96 # Row buffer hit rate for reads 251system.physmem.writeRowHitRate 39.04 # Row buffer hit rate for writes 252system.physmem.avgGap 353325.60 # Average gap between requests 253system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined 254system.physmem.memoryStateTime::IDLE 306310282500 # Time in different power states 255system.physmem.memoryStateTime::REF 36593440000 # Time in different power states | 248system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing 249system.physmem.readRowHits 777772 # Number of row buffer hits during reads 250system.physmem.writeRowHits 406558 # Number of row buffer hits during writes 251system.physmem.readRowHitRate 37.86 # Row buffer hit rate for reads 252system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes 253system.physmem.avgGap 353394.36 # Average gap between requests 254system.physmem.pageHitRate 38.20 # Row buffer hit rate, read and write combined 255system.physmem.memoryStateTime::IDLE 306608104500 # Time in different power states 256system.physmem.memoryStateTime::REF 36603840000 # Time in different power states |
| 256system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 257system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 257system.physmem.memoryStateTime::ACT 752968660500 # Time in different power states | 258system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states |
| 258system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 259system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 259system.membus.throughput 181136026 # Throughput (bytes/s) 260system.membus.trans_dist::ReadReq 1255348 # Transaction distribution 261system.membus.trans_dist::ReadResp 1255348 # Transaction distribution 262system.membus.trans_dist::Writeback 1046304 # Transaction distribution 263system.membus.trans_dist::ReadExReq 799950 # Transaction distribution 264system.membus.trans_dist::ReadExResp 799950 # Transaction distribution 265system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5156900 # Packet count per connected master and slave (bytes) 266system.membus.pkt_count::total 5156900 # Packet count per connected master and slave (bytes) 267system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198502528 # Cumulative packet size per connected master and slave (bytes) 268system.membus.tot_pkt_size::total 198502528 # Cumulative packet size per connected master and slave (bytes) 269system.membus.data_through_bus 198502528 # Total data (bytes) 270system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 271system.membus.reqLayer0.occupancy 12227667000 # Layer occupancy (ticks) | 260system.membus.trans_dist::ReadReq 1255486 # Transaction distribution 261system.membus.trans_dist::ReadResp 1255486 # Transaction distribution 262system.membus.trans_dist::Writeback 1046381 # Transaction distribution 263system.membus.trans_dist::ReadExReq 800013 # Transaction distribution 264system.membus.trans_dist::ReadExResp 800013 # Transaction distribution 265system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157379 # Packet count per connected master and slave (bytes) 266system.membus.pkt_count::total 5157379 # Packet count per connected master and slave (bytes) 267system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198520320 # Cumulative packet size per connected master and slave (bytes) 268system.membus.pkt_size::total 198520320 # Cumulative packet size per connected master and slave (bytes) 269system.membus.snoops 0 # Total snoops (count) 270system.membus.snoop_fanout::samples 3101880 # Request fanout histogram 271system.membus.snoop_fanout::mean 0 # Request fanout histogram 272system.membus.snoop_fanout::stdev 0 # Request fanout histogram 273system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 274system.membus.snoop_fanout::0 3101880 100.00% 100.00% # Request fanout histogram 275system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 276system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 277system.membus.snoop_fanout::min_value 0 # Request fanout histogram 278system.membus.snoop_fanout::max_value 0 # Request fanout histogram 279system.membus.snoop_fanout::total 3101880 # Request fanout histogram 280system.membus.reqLayer0.occupancy 12229457500 # Layer occupancy (ticks) |
| 272system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) | 281system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) |
| 273system.membus.respLayer1.occupancy 19360882250 # Layer occupancy (ticks) | 282system.membus.respLayer1.occupancy 19361348500 # Layer occupancy (ticks) |
| 274system.membus.respLayer1.utilization 1.8 # Layer utilization (%) 275system.cpu_clk_domain.clock 500 # Clock period in ticks | 283system.membus.respLayer1.utilization 1.8 # Layer utilization (%) 284system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 276system.cpu.branchPred.lookups 239641872 # Number of BP lookups 277system.cpu.branchPred.condPredicted 186303374 # Number of conditional branches predicted 278system.cpu.branchPred.condIncorrect 14594643 # Number of conditional branches incorrect 279system.cpu.branchPred.BTBLookups 130836287 # Number of BTB lookups 280system.cpu.branchPred.BTBHits 121989290 # Number of BTB hits | 285system.cpu.branchPred.lookups 239650352 # Number of BP lookups 286system.cpu.branchPred.condPredicted 186306880 # Number of conditional branches predicted 287system.cpu.branchPred.condIncorrect 14598405 # Number of conditional branches incorrect 288system.cpu.branchPred.BTBLookups 131764254 # Number of BTB lookups 289system.cpu.branchPred.BTBHits 121991524 # Number of BTB hits |
| 281system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 290system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 282system.cpu.branchPred.BTBHitPct 93.238117 # BTB Hit Percentage 283system.cpu.branchPred.usedRAS 15653729 # Number of times the RAS was used to get a target. | 291system.cpu.branchPred.BTBHitPct 92.583171 # BTB Hit Percentage 292system.cpu.branchPred.usedRAS 15654227 # Number of times the RAS was used to get a target. |
| 284system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 285system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 286system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 287system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 288system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 289system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 290system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 291system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 70 unchanged lines hidden (view full) --- 362system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.itb.read_accesses 0 # DTB read accesses 364system.cpu.itb.write_accesses 0 # DTB write accesses 365system.cpu.itb.inst_accesses 0 # ITB inst accesses 366system.cpu.itb.hits 0 # DTB hits 367system.cpu.itb.misses 0 # DTB misses 368system.cpu.itb.accesses 0 # DTB accesses 369system.cpu.workload.num_syscalls 46 # Number of system calls | 293system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 294system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 295system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 296system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 297system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 298system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 299system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 300system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed --- 70 unchanged lines hidden (view full) --- 371system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 372system.cpu.itb.read_accesses 0 # DTB read accesses 373system.cpu.itb.write_accesses 0 # DTB write accesses 374system.cpu.itb.inst_accesses 0 # ITB inst accesses 375system.cpu.itb.hits 0 # DTB hits 376system.cpu.itb.misses 0 # DTB misses 377system.cpu.itb.accesses 0 # DTB accesses 378system.cpu.workload.num_syscalls 46 # Number of system calls |
| 370system.cpu.numCycles 2191750941 # number of cpu cycles simulated | 379system.cpu.numCycles 2192373981 # number of cpu cycles simulated |
| 371system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 372system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 373system.cpu.committedInsts 1544563087 # Number of instructions committed 374system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed | 380system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 381system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 382system.cpu.committedInsts 1544563087 # Number of instructions committed 383system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed |
| 375system.cpu.discardedOps 42066132 # Number of ops (including micro ops) which were discarded before commit | 384system.cpu.discardedOps 42081657 # Number of ops (including micro ops) which were discarded before commit |
| 376system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 385system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 377system.cpu.cpi 1.419010 # CPI: cycles per instruction 378system.cpu.ipc 0.704717 # IPC: instructions per cycle 379system.cpu.tickCycles 1808188284 # Number of cycles that the object actually ticked 380system.cpu.idleCycles 383562657 # Total number of cycles that the object has spent stopped | 386system.cpu.cpi 1.419414 # CPI: cycles per instruction 387system.cpu.ipc 0.704516 # IPC: instructions per cycle 388system.cpu.tickCycles 1808241834 # Number of cycles that the object actually ticked 389system.cpu.idleCycles 384132147 # Total number of cycles that the object has spent stopped |
| 381system.cpu.icache.tags.replacements 29 # number of replacements | 390system.cpu.icache.tags.replacements 29 # number of replacements |
| 382system.cpu.icache.tags.tagsinuse 661.141376 # Cycle average of tags in use 383system.cpu.icache.tags.total_refs 464847257 # Total number of references to valid blocks. | 391system.cpu.icache.tags.tagsinuse 661.144399 # Cycle average of tags in use 392system.cpu.icache.tags.total_refs 464861353 # Total number of references to valid blocks. |
| 384system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. | 393system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. |
| 385system.cpu.icache.tags.avg_refs 566886.898780 # Average number of references to valid blocks. | 394system.cpu.icache.tags.avg_refs 566904.089024 # Average number of references to valid blocks. |
| 386system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 395system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 387system.cpu.icache.tags.occ_blocks::cpu.inst 661.141376 # Average occupied blocks per requestor 388system.cpu.icache.tags.occ_percent::cpu.inst 0.322823 # Average percentage of cache occupancy 389system.cpu.icache.tags.occ_percent::total 0.322823 # Average percentage of cache occupancy | 396system.cpu.icache.tags.occ_blocks::cpu.inst 661.144399 # Average occupied blocks per requestor 397system.cpu.icache.tags.occ_percent::cpu.inst 0.322824 # Average percentage of cache occupancy 398system.cpu.icache.tags.occ_percent::total 0.322824 # Average percentage of cache occupancy |
| 390system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id 391system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 392system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 393system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id 394system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id | 399system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id 400system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 401system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 402system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id 403system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id |
| 395system.cpu.icache.tags.tag_accesses 929696974 # Number of tag accesses 396system.cpu.icache.tags.data_accesses 929696974 # Number of data accesses 397system.cpu.icache.ReadReq_hits::cpu.inst 464847257 # number of ReadReq hits 398system.cpu.icache.ReadReq_hits::total 464847257 # number of ReadReq hits 399system.cpu.icache.demand_hits::cpu.inst 464847257 # number of demand (read+write) hits 400system.cpu.icache.demand_hits::total 464847257 # number of demand (read+write) hits 401system.cpu.icache.overall_hits::cpu.inst 464847257 # number of overall hits 402system.cpu.icache.overall_hits::total 464847257 # number of overall hits | 404system.cpu.icache.tags.tag_accesses 929725166 # Number of tag accesses 405system.cpu.icache.tags.data_accesses 929725166 # Number of data accesses 406system.cpu.icache.ReadReq_hits::cpu.inst 464861353 # number of ReadReq hits 407system.cpu.icache.ReadReq_hits::total 464861353 # number of ReadReq hits 408system.cpu.icache.demand_hits::cpu.inst 464861353 # number of demand (read+write) hits 409system.cpu.icache.demand_hits::total 464861353 # number of demand (read+write) hits 410system.cpu.icache.overall_hits::cpu.inst 464861353 # number of overall hits 411system.cpu.icache.overall_hits::total 464861353 # number of overall hits |
| 403system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses 404system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses 405system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses 406system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses 407system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses 408system.cpu.icache.overall_misses::total 820 # number of overall misses | 412system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses 413system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses 414system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses 415system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses 416system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses 417system.cpu.icache.overall_misses::total 820 # number of overall misses |
| 409system.cpu.icache.ReadReq_miss_latency::cpu.inst 58324499 # number of ReadReq miss cycles 410system.cpu.icache.ReadReq_miss_latency::total 58324499 # number of ReadReq miss cycles 411system.cpu.icache.demand_miss_latency::cpu.inst 58324499 # number of demand (read+write) miss cycles 412system.cpu.icache.demand_miss_latency::total 58324499 # number of demand (read+write) miss cycles 413system.cpu.icache.overall_miss_latency::cpu.inst 58324499 # number of overall miss cycles 414system.cpu.icache.overall_miss_latency::total 58324499 # number of overall miss cycles 415system.cpu.icache.ReadReq_accesses::cpu.inst 464848077 # number of ReadReq accesses(hits+misses) 416system.cpu.icache.ReadReq_accesses::total 464848077 # number of ReadReq accesses(hits+misses) 417system.cpu.icache.demand_accesses::cpu.inst 464848077 # number of demand (read+write) accesses 418system.cpu.icache.demand_accesses::total 464848077 # number of demand (read+write) accesses 419system.cpu.icache.overall_accesses::cpu.inst 464848077 # number of overall (read+write) accesses 420system.cpu.icache.overall_accesses::total 464848077 # number of overall (read+write) accesses | 418system.cpu.icache.ReadReq_miss_latency::cpu.inst 59141749 # number of ReadReq miss cycles 419system.cpu.icache.ReadReq_miss_latency::total 59141749 # number of ReadReq miss cycles 420system.cpu.icache.demand_miss_latency::cpu.inst 59141749 # number of demand (read+write) miss cycles 421system.cpu.icache.demand_miss_latency::total 59141749 # number of demand (read+write) miss cycles 422system.cpu.icache.overall_miss_latency::cpu.inst 59141749 # number of overall miss cycles 423system.cpu.icache.overall_miss_latency::total 59141749 # number of overall miss cycles 424system.cpu.icache.ReadReq_accesses::cpu.inst 464862173 # number of ReadReq accesses(hits+misses) 425system.cpu.icache.ReadReq_accesses::total 464862173 # number of ReadReq accesses(hits+misses) 426system.cpu.icache.demand_accesses::cpu.inst 464862173 # number of demand (read+write) accesses 427system.cpu.icache.demand_accesses::total 464862173 # number of demand (read+write) accesses 428system.cpu.icache.overall_accesses::cpu.inst 464862173 # number of overall (read+write) accesses 429system.cpu.icache.overall_accesses::total 464862173 # number of overall (read+write) accesses |
| 421system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 422system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 423system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 424system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 425system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 426system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses | 430system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 431system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 432system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 433system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 434system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 435system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses |
| 427system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805 # average ReadReq miss latency 428system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805 # average ReadReq miss latency 429system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency 430system.cpu.icache.demand_avg_miss_latency::total 71127.437805 # average overall miss latency 431system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency 432system.cpu.icache.overall_avg_miss_latency::total 71127.437805 # average overall miss latency | 436system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72124.084146 # average ReadReq miss latency 437system.cpu.icache.ReadReq_avg_miss_latency::total 72124.084146 # average ReadReq miss latency 438system.cpu.icache.demand_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency 439system.cpu.icache.demand_avg_miss_latency::total 72124.084146 # average overall miss latency 440system.cpu.icache.overall_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency 441system.cpu.icache.overall_avg_miss_latency::total 72124.084146 # average overall miss latency |
| 433system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 434system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 435system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 436system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 437system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 438system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 439system.cpu.icache.fast_writes 0 # number of fast writes performed 440system.cpu.icache.cache_copies 0 # number of cache copies performed 441system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses 442system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses 443system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses 444system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses 445system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses 446system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses | 442system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 443system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 444system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 445system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 446system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 447system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 448system.cpu.icache.fast_writes 0 # number of fast writes performed 449system.cpu.icache.cache_copies 0 # number of cache copies performed 450system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses 451system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses 452system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses 453system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses 454system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses 455system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses |
| 447system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56360501 # number of ReadReq MSHR miss cycles 448system.cpu.icache.ReadReq_mshr_miss_latency::total 56360501 # number of ReadReq MSHR miss cycles 449system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56360501 # number of demand (read+write) MSHR miss cycles 450system.cpu.icache.demand_mshr_miss_latency::total 56360501 # number of demand (read+write) MSHR miss cycles 451system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56360501 # number of overall MSHR miss cycles 452system.cpu.icache.overall_mshr_miss_latency::total 56360501 # number of overall MSHR miss cycles | 456system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57178251 # number of ReadReq MSHR miss cycles 457system.cpu.icache.ReadReq_mshr_miss_latency::total 57178251 # number of ReadReq MSHR miss cycles 458system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57178251 # number of demand (read+write) MSHR miss cycles 459system.cpu.icache.demand_mshr_miss_latency::total 57178251 # number of demand (read+write) MSHR miss cycles 460system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57178251 # number of overall MSHR miss cycles 461system.cpu.icache.overall_mshr_miss_latency::total 57178251 # number of overall MSHR miss cycles |
| 453system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 454system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 455system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 456system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 457system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 458system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses | 462system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 463system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 464system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 465system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 466system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 467system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses |
| 459system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68732.318293 # average ReadReq mshr miss latency 460system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68732.318293 # average ReadReq mshr miss latency 461system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency 462system.cpu.icache.demand_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency 463system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency 464system.cpu.icache.overall_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency | 468system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.574390 # average ReadReq mshr miss latency 469system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.574390 # average ReadReq mshr miss latency 470system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency 471system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency 472system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency 473system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency |
| 465system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 474system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 466system.cpu.toL2Bus.throughput 755014954 # Throughput (bytes/s) 467system.cpu.toL2Bus.trans_dist::ReadReq 7336391 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadResp 7336391 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::Writeback 3700895 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::ReadExReq 1890876 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::ReadExResp 1890876 # Transaction distribution | 475system.cpu.toL2Bus.trans_dist::ReadReq 7336783 # Transaction distribution 476system.cpu.toL2Bus.trans_dist::ReadResp 7336783 # Transaction distribution 477system.cpu.toL2Bus.trans_dist::Writeback 3700640 # Transaction distribution 478system.cpu.toL2Bus.trans_dist::ReadExReq 1890869 # Transaction distribution 479system.cpu.toL2Bus.trans_dist::ReadExResp 1890869 # Transaction distribution |
| 472system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) | 480system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) |
| 473system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22153789 # Packet count per connected master and slave (bytes) 474system.cpu.toL2Bus.pkt_count::total 22155429 # Packet count per connected master and slave (bytes) 475system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) 476system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827349888 # Cumulative packet size per connected master and slave (bytes) 477system.cpu.toL2Bus.tot_pkt_size::total 827402368 # Cumulative packet size per connected master and slave (bytes) 478system.cpu.toL2Bus.data_through_bus 827402368 # Total data (bytes) 479system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 480system.cpu.toL2Bus.reqLayer0.occupancy 10164976000 # Layer occupancy (ticks) | 481system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22154304 # Packet count per connected master and slave (bytes) 482system.cpu.toL2Bus.pkt_count::total 22155944 # Packet count per connected master and slave (bytes) 483system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) 484system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827358208 # Cumulative packet size per connected master and slave (bytes) 485system.cpu.toL2Bus.pkt_size::total 827410688 # Cumulative packet size per connected master and slave (bytes) 486system.cpu.toL2Bus.snoops 0 # Total snoops (count) 487system.cpu.toL2Bus.snoop_fanout::samples 12928292 # Request fanout histogram 488system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram 489system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 490system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 491system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 492system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 493system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 494system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 495system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 496system.cpu.toL2Bus.snoop_fanout::5 12928292 100.00% 100.00% # Request fanout histogram 497system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram 498system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 499system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 500system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram 501system.cpu.toL2Bus.snoop_fanout::total 12928292 # Request fanout histogram 502system.cpu.toL2Bus.reqLayer0.occupancy 10164786000 # Layer occupancy (ticks) |
| 481system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) | 503system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) |
| 482system.cpu.toL2Bus.respLayer0.occupancy 1391999 # Layer occupancy (ticks) | 504system.cpu.toL2Bus.respLayer0.occupancy 1391749 # Layer occupancy (ticks) |
| 483system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) | 505system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| 484system.cpu.toL2Bus.respLayer1.occupancy 14185372245 # Layer occupancy (ticks) | 506system.cpu.toL2Bus.respLayer1.occupancy 14185031745 # Layer occupancy (ticks) |
| 485system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) | 507system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) |
| 486system.cpu.l2cache.tags.replacements 2022594 # number of replacements 487system.cpu.l2cache.tags.tagsinuse 31252.258926 # Cycle average of tags in use 488system.cpu.l2cache.tags.total_refs 8984184 # Total number of references to valid blocks. 489system.cpu.l2cache.tags.sampled_refs 2052369 # Sample count of references to valid blocks. 490system.cpu.l2cache.tags.avg_refs 4.377470 # Average number of references to valid blocks. | 508system.cpu.l2cache.tags.replacements 2022796 # number of replacements 509system.cpu.l2cache.tags.tagsinuse 31252.383158 # Cycle average of tags in use 510system.cpu.l2cache.tags.total_refs 8984119 # Total number of references to valid blocks. 511system.cpu.l2cache.tags.sampled_refs 2052571 # Sample count of references to valid blocks. 512system.cpu.l2cache.tags.avg_refs 4.377008 # Average number of references to valid blocks. |
| 491system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit. | 513system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit. |
| 492system.cpu.l2cache.tags.occ_blocks::writebacks 14968.183746 # Average occupied blocks per requestor 493system.cpu.l2cache.tags.occ_blocks::cpu.inst 16284.075180 # Average occupied blocks per requestor 494system.cpu.l2cache.tags.occ_percent::writebacks 0.456793 # Average percentage of cache occupancy 495system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496951 # Average percentage of cache occupancy 496system.cpu.l2cache.tags.occ_percent::total 0.953743 # Average percentage of cache occupancy | 514system.cpu.l2cache.tags.occ_blocks::writebacks 14967.342328 # Average occupied blocks per requestor 515system.cpu.l2cache.tags.occ_blocks::cpu.inst 16285.040830 # Average occupied blocks per requestor 516system.cpu.l2cache.tags.occ_percent::writebacks 0.456767 # Average percentage of cache occupancy 517system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496980 # Average percentage of cache occupancy 518system.cpu.l2cache.tags.occ_percent::total 0.953747 # Average percentage of cache occupancy |
| 497system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id 498system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 499system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 500system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id 501system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id 502system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id 503system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id | 519system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id 520system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 521system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 522system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id 523system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id 524system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id 525system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id |
| 504system.cpu.l2cache.tags.tag_accesses 107368541 # Number of tag accesses 505system.cpu.l2cache.tags.data_accesses 107368541 # Number of data accesses 506system.cpu.l2cache.ReadReq_hits::cpu.inst 6081037 # number of ReadReq hits 507system.cpu.l2cache.ReadReq_hits::total 6081037 # number of ReadReq hits 508system.cpu.l2cache.Writeback_hits::writebacks 3700895 # number of Writeback hits 509system.cpu.l2cache.Writeback_hits::total 3700895 # number of Writeback hits 510system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090926 # number of ReadExReq hits 511system.cpu.l2cache.ReadExReq_hits::total 1090926 # number of ReadExReq hits 512system.cpu.l2cache.demand_hits::cpu.inst 7171963 # number of demand (read+write) hits 513system.cpu.l2cache.demand_hits::total 7171963 # number of demand (read+write) hits 514system.cpu.l2cache.overall_hits::cpu.inst 7171963 # number of overall hits 515system.cpu.l2cache.overall_hits::total 7171963 # number of overall hits 516system.cpu.l2cache.ReadReq_misses::cpu.inst 1255354 # number of ReadReq misses 517system.cpu.l2cache.ReadReq_misses::total 1255354 # number of ReadReq misses 518system.cpu.l2cache.ReadExReq_misses::cpu.inst 799950 # number of ReadExReq misses 519system.cpu.l2cache.ReadExReq_misses::total 799950 # number of ReadExReq misses 520system.cpu.l2cache.demand_misses::cpu.inst 2055304 # number of demand (read+write) misses 521system.cpu.l2cache.demand_misses::total 2055304 # number of demand (read+write) misses 522system.cpu.l2cache.overall_misses::cpu.inst 2055304 # number of overall misses 523system.cpu.l2cache.overall_misses::total 2055304 # number of overall misses 524system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100122250500 # number of ReadReq miss cycles 525system.cpu.l2cache.ReadReq_miss_latency::total 100122250500 # number of ReadReq miss cycles 526system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64358555750 # number of ReadExReq miss cycles 527system.cpu.l2cache.ReadExReq_miss_latency::total 64358555750 # number of ReadExReq miss cycles 528system.cpu.l2cache.demand_miss_latency::cpu.inst 164480806250 # number of demand (read+write) miss cycles 529system.cpu.l2cache.demand_miss_latency::total 164480806250 # number of demand (read+write) miss cycles 530system.cpu.l2cache.overall_miss_latency::cpu.inst 164480806250 # number of overall miss cycles 531system.cpu.l2cache.overall_miss_latency::total 164480806250 # number of overall miss cycles 532system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336391 # number of ReadReq accesses(hits+misses) 533system.cpu.l2cache.ReadReq_accesses::total 7336391 # number of ReadReq accesses(hits+misses) 534system.cpu.l2cache.Writeback_accesses::writebacks 3700895 # number of Writeback accesses(hits+misses) 535system.cpu.l2cache.Writeback_accesses::total 3700895 # number of Writeback accesses(hits+misses) 536system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890876 # number of ReadExReq accesses(hits+misses) 537system.cpu.l2cache.ReadExReq_accesses::total 1890876 # number of ReadExReq accesses(hits+misses) 538system.cpu.l2cache.demand_accesses::cpu.inst 9227267 # number of demand (read+write) accesses 539system.cpu.l2cache.demand_accesses::total 9227267 # number of demand (read+write) accesses 540system.cpu.l2cache.overall_accesses::cpu.inst 9227267 # number of overall (read+write) accesses 541system.cpu.l2cache.overall_accesses::total 9227267 # number of overall (read+write) accesses 542system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171113 # miss rate for ReadReq accesses 543system.cpu.l2cache.ReadReq_miss_rate::total 0.171113 # miss rate for ReadReq accesses 544system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423058 # miss rate for ReadExReq accesses 545system.cpu.l2cache.ReadExReq_miss_rate::total 0.423058 # miss rate for ReadExReq accesses 546system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses 547system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses 548system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # miss rate for overall accesses 549system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses 550system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79756.188693 # average ReadReq miss latency 551system.cpu.l2cache.ReadReq_avg_miss_latency::total 79756.188693 # average ReadReq miss latency 552system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80453.223014 # average ReadExReq miss latency 553system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80453.223014 # average ReadExReq miss latency 554system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80027.483161 # average overall miss latency 555system.cpu.l2cache.demand_avg_miss_latency::total 80027.483161 # average overall miss latency 556system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80027.483161 # average overall miss latency 557system.cpu.l2cache.overall_avg_miss_latency::total 80027.483161 # average overall miss latency | 526system.cpu.l2cache.tags.tag_accesses 107369776 # Number of tag accesses 527system.cpu.l2cache.tags.data_accesses 107369776 # Number of data accesses 528system.cpu.l2cache.ReadReq_hits::cpu.inst 6081291 # number of ReadReq hits 529system.cpu.l2cache.ReadReq_hits::total 6081291 # number of ReadReq hits 530system.cpu.l2cache.Writeback_hits::writebacks 3700640 # number of Writeback hits 531system.cpu.l2cache.Writeback_hits::total 3700640 # number of Writeback hits 532system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090856 # number of ReadExReq hits 533system.cpu.l2cache.ReadExReq_hits::total 1090856 # number of ReadExReq hits 534system.cpu.l2cache.demand_hits::cpu.inst 7172147 # number of demand (read+write) hits 535system.cpu.l2cache.demand_hits::total 7172147 # number of demand (read+write) hits 536system.cpu.l2cache.overall_hits::cpu.inst 7172147 # number of overall hits 537system.cpu.l2cache.overall_hits::total 7172147 # number of overall hits 538system.cpu.l2cache.ReadReq_misses::cpu.inst 1255492 # number of ReadReq misses 539system.cpu.l2cache.ReadReq_misses::total 1255492 # number of ReadReq misses 540system.cpu.l2cache.ReadExReq_misses::cpu.inst 800013 # number of ReadExReq misses 541system.cpu.l2cache.ReadExReq_misses::total 800013 # number of ReadExReq misses 542system.cpu.l2cache.demand_misses::cpu.inst 2055505 # number of demand (read+write) misses 543system.cpu.l2cache.demand_misses::total 2055505 # number of demand (read+write) misses 544system.cpu.l2cache.overall_misses::cpu.inst 2055505 # number of overall misses 545system.cpu.l2cache.overall_misses::total 2055505 # number of overall misses 546system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100333400500 # number of ReadReq miss cycles 547system.cpu.l2cache.ReadReq_miss_latency::total 100333400500 # number of ReadReq miss cycles 548system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64526294750 # number of ReadExReq miss cycles 549system.cpu.l2cache.ReadExReq_miss_latency::total 64526294750 # number of ReadExReq miss cycles 550system.cpu.l2cache.demand_miss_latency::cpu.inst 164859695250 # number of demand (read+write) miss cycles 551system.cpu.l2cache.demand_miss_latency::total 164859695250 # number of demand (read+write) miss cycles 552system.cpu.l2cache.overall_miss_latency::cpu.inst 164859695250 # number of overall miss cycles 553system.cpu.l2cache.overall_miss_latency::total 164859695250 # number of overall miss cycles 554system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336783 # number of ReadReq accesses(hits+misses) 555system.cpu.l2cache.ReadReq_accesses::total 7336783 # number of ReadReq accesses(hits+misses) 556system.cpu.l2cache.Writeback_accesses::writebacks 3700640 # number of Writeback accesses(hits+misses) 557system.cpu.l2cache.Writeback_accesses::total 3700640 # number of Writeback accesses(hits+misses) 558system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890869 # number of ReadExReq accesses(hits+misses) 559system.cpu.l2cache.ReadExReq_accesses::total 1890869 # number of ReadExReq accesses(hits+misses) 560system.cpu.l2cache.demand_accesses::cpu.inst 9227652 # number of demand (read+write) accesses 561system.cpu.l2cache.demand_accesses::total 9227652 # number of demand (read+write) accesses 562system.cpu.l2cache.overall_accesses::cpu.inst 9227652 # number of overall (read+write) accesses 563system.cpu.l2cache.overall_accesses::total 9227652 # number of overall (read+write) accesses 564system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171123 # miss rate for ReadReq accesses 565system.cpu.l2cache.ReadReq_miss_rate::total 0.171123 # miss rate for ReadReq accesses 566system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423093 # miss rate for ReadExReq accesses 567system.cpu.l2cache.ReadExReq_miss_rate::total 0.423093 # miss rate for ReadExReq accesses 568system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222755 # miss rate for demand accesses 569system.cpu.l2cache.demand_miss_rate::total 0.222755 # miss rate for demand accesses 570system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222755 # miss rate for overall accesses 571system.cpu.l2cache.overall_miss_rate::total 0.222755 # miss rate for overall accesses 572system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79915.603206 # average ReadReq miss latency 573system.cpu.l2cache.ReadReq_avg_miss_latency::total 79915.603206 # average ReadReq miss latency 574system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.557768 # average ReadExReq miss latency 575system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.557768 # average ReadExReq miss latency 576system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency 577system.cpu.l2cache.demand_avg_miss_latency::total 80203.986490 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency 579system.cpu.l2cache.overall_avg_miss_latency::total 80203.986490 # average overall miss latency |
| 558system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 559system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 560system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 561system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 562system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 563system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 564system.cpu.l2cache.fast_writes 0 # number of fast writes performed 565system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 580system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 583system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 584system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 585system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 586system.cpu.l2cache.fast_writes 0 # number of fast writes performed 587system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 566system.cpu.l2cache.writebacks::writebacks 1046304 # number of writebacks 567system.cpu.l2cache.writebacks::total 1046304 # number of writebacks | 588system.cpu.l2cache.writebacks::writebacks 1046381 # number of writebacks 589system.cpu.l2cache.writebacks::total 1046381 # number of writebacks |
| 568system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits 569system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 570system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits 571system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 572system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits 573system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits | 590system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits 591system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 592system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits 593system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 594system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits 595system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits |
| 574system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255348 # number of ReadReq MSHR misses 575system.cpu.l2cache.ReadReq_mshr_misses::total 1255348 # number of ReadReq MSHR misses 576system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 799950 # number of ReadExReq MSHR misses 577system.cpu.l2cache.ReadExReq_mshr_misses::total 799950 # number of ReadExReq MSHR misses 578system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055298 # number of demand (read+write) MSHR misses 579system.cpu.l2cache.demand_mshr_misses::total 2055298 # number of demand (read+write) MSHR misses 580system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055298 # number of overall MSHR misses 581system.cpu.l2cache.overall_mshr_misses::total 2055298 # number of overall MSHR misses 582system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84333554000 # number of ReadReq MSHR miss cycles 583system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84333554000 # number of ReadReq MSHR miss cycles 584system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54273221250 # number of ReadExReq MSHR miss cycles 585system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54273221250 # number of ReadExReq MSHR miss cycles 586system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138606775250 # number of demand (read+write) MSHR miss cycles 587system.cpu.l2cache.demand_mshr_miss_latency::total 138606775250 # number of demand (read+write) MSHR miss cycles 588system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138606775250 # number of overall MSHR miss cycles 589system.cpu.l2cache.overall_mshr_miss_latency::total 138606775250 # number of overall MSHR miss cycles 590system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171112 # mshr miss rate for ReadReq accesses 591system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171112 # mshr miss rate for ReadReq accesses 592system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423058 # mshr miss rate for ReadExReq accesses 593system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423058 # mshr miss rate for ReadExReq accesses 594system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for demand accesses 595system.cpu.l2cache.demand_mshr_miss_rate::total 0.222742 # mshr miss rate for demand accesses 596system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for overall accesses 597system.cpu.l2cache.overall_mshr_miss_rate::total 0.222742 # mshr miss rate for overall accesses 598system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67179.422758 # average ReadReq mshr miss latency 599system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67179.422758 # average ReadReq mshr miss latency 600system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67845.766923 # average ReadExReq mshr miss latency 601system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67845.766923 # average ReadExReq mshr miss latency 602system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency 603system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency 604system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency 605system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency | 596system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255486 # number of ReadReq MSHR misses 597system.cpu.l2cache.ReadReq_mshr_misses::total 1255486 # number of ReadReq MSHR misses 598system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800013 # number of ReadExReq MSHR misses 599system.cpu.l2cache.ReadExReq_mshr_misses::total 800013 # number of ReadExReq MSHR misses 600system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055499 # number of demand (read+write) MSHR misses 601system.cpu.l2cache.demand_mshr_misses::total 2055499 # number of demand (read+write) MSHR misses 602system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055499 # number of overall MSHR misses 603system.cpu.l2cache.overall_mshr_misses::total 2055499 # number of overall MSHR misses 604system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84544683250 # number of ReadReq MSHR miss cycles 605system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84544683250 # number of ReadReq MSHR miss cycles 606system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54440940250 # number of ReadExReq MSHR miss cycles 607system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440940250 # number of ReadExReq MSHR miss cycles 608system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138985623500 # number of demand (read+write) MSHR miss cycles 609system.cpu.l2cache.demand_mshr_miss_latency::total 138985623500 # number of demand (read+write) MSHR miss cycles 610system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138985623500 # number of overall MSHR miss cycles 611system.cpu.l2cache.overall_mshr_miss_latency::total 138985623500 # number of overall MSHR miss cycles 612system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171122 # mshr miss rate for ReadReq accesses 613system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171122 # mshr miss rate for ReadReq accesses 614system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423093 # mshr miss rate for ReadExReq accesses 615system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423093 # mshr miss rate for ReadExReq accesses 616system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for demand accesses 617system.cpu.l2cache.demand_mshr_miss_rate::total 0.222754 # mshr miss rate for demand accesses 618system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for overall accesses 619system.cpu.l2cache.overall_mshr_miss_rate::total 0.222754 # mshr miss rate for overall accesses 620system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67340.203913 # average ReadReq mshr miss latency 621system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67340.203913 # average ReadReq mshr miss latency 622system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68050.069499 # average ReadExReq mshr miss latency 623system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68050.069499 # average ReadExReq mshr miss latency 624system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency 625system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency 626system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency 627system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency |
| 606system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 628system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 607system.cpu.dcache.tags.replacements 9222351 # number of replacements 608system.cpu.dcache.tags.tagsinuse 4085.559894 # Cycle average of tags in use 609system.cpu.dcache.tags.total_refs 624001258 # Total number of references to valid blocks. 610system.cpu.dcache.tags.sampled_refs 9226447 # Sample count of references to valid blocks. 611system.cpu.dcache.tags.avg_refs 67.631804 # Average number of references to valid blocks. 612system.cpu.dcache.tags.warmup_cycle 9703664000 # Cycle when the warmup percentage was hit. 613system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.559894 # Average occupied blocks per requestor 614system.cpu.dcache.tags.occ_percent::cpu.inst 0.997451 # Average percentage of cache occupancy 615system.cpu.dcache.tags.occ_percent::total 0.997451 # Average percentage of cache occupancy | 629system.cpu.dcache.tags.replacements 9222736 # number of replacements 630system.cpu.dcache.tags.tagsinuse 4085.561884 # Cycle average of tags in use 631system.cpu.dcache.tags.total_refs 624006676 # Total number of references to valid blocks. 632system.cpu.dcache.tags.sampled_refs 9226832 # Sample count of references to valid blocks. 633system.cpu.dcache.tags.avg_refs 67.629569 # Average number of references to valid blocks. 634system.cpu.dcache.tags.warmup_cycle 9704965000 # Cycle when the warmup percentage was hit. 635system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.561884 # Average occupied blocks per requestor 636system.cpu.dcache.tags.occ_percent::cpu.inst 0.997452 # Average percentage of cache occupancy 637system.cpu.dcache.tags.occ_percent::total 0.997452 # Average percentage of cache occupancy |
| 616system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 638system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 617system.cpu.dcache.tags.age_task_id_blocks_1024::0 283 # Occupied blocks per task id 618system.cpu.dcache.tags.age_task_id_blocks_1024::1 1314 # Occupied blocks per task id 619system.cpu.dcache.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id | 639system.cpu.dcache.tags.age_task_id_blocks_1024::0 280 # Occupied blocks per task id 640system.cpu.dcache.tags.age_task_id_blocks_1024::1 1316 # Occupied blocks per task id 641system.cpu.dcache.tags.age_task_id_blocks_1024::2 2439 # Occupied blocks per task id |
| 620system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 621system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 642system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 643system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 622system.cpu.dcache.tags.tag_accesses 1276381727 # Number of tag accesses 623system.cpu.dcache.tags.data_accesses 1276381727 # Number of data accesses 624system.cpu.dcache.ReadReq_hits::cpu.inst 453655688 # number of ReadReq hits 625system.cpu.dcache.ReadReq_hits::total 453655688 # number of ReadReq hits 626system.cpu.dcache.WriteReq_hits::cpu.inst 170345448 # number of WriteReq hits 627system.cpu.dcache.WriteReq_hits::total 170345448 # number of WriteReq hits | 644system.cpu.dcache.tags.tag_accesses 1276393554 # Number of tag accesses 645system.cpu.dcache.tags.data_accesses 1276393554 # Number of data accesses 646system.cpu.dcache.ReadReq_hits::cpu.inst 453661018 # number of ReadReq hits 647system.cpu.dcache.ReadReq_hits::total 453661018 # number of ReadReq hits 648system.cpu.dcache.WriteReq_hits::cpu.inst 170345536 # number of WriteReq hits 649system.cpu.dcache.WriteReq_hits::total 170345536 # number of WriteReq hits |
| 628system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits 629system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 630system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits 631system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits | 650system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits 651system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 652system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits 653system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits |
| 632system.cpu.dcache.demand_hits::cpu.inst 624001136 # number of demand (read+write) hits 633system.cpu.dcache.demand_hits::total 624001136 # number of demand (read+write) hits 634system.cpu.dcache.overall_hits::cpu.inst 624001136 # number of overall hits 635system.cpu.dcache.overall_hits::total 624001136 # number of overall hits 636system.cpu.dcache.ReadReq_misses::cpu.inst 7335783 # number of ReadReq misses 637system.cpu.dcache.ReadReq_misses::total 7335783 # number of ReadReq misses 638system.cpu.dcache.WriteReq_misses::cpu.inst 2240599 # number of WriteReq misses 639system.cpu.dcache.WriteReq_misses::total 2240599 # number of WriteReq misses 640system.cpu.dcache.demand_misses::cpu.inst 9576382 # number of demand (read+write) misses 641system.cpu.dcache.demand_misses::total 9576382 # number of demand (read+write) misses 642system.cpu.dcache.overall_misses::cpu.inst 9576382 # number of overall misses 643system.cpu.dcache.overall_misses::total 9576382 # number of overall misses 644system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183307188995 # number of ReadReq miss cycles 645system.cpu.dcache.ReadReq_miss_latency::total 183307188995 # number of ReadReq miss cycles 646system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101248592250 # number of WriteReq miss cycles 647system.cpu.dcache.WriteReq_miss_latency::total 101248592250 # number of WriteReq miss cycles 648system.cpu.dcache.demand_miss_latency::cpu.inst 284555781245 # number of demand (read+write) miss cycles 649system.cpu.dcache.demand_miss_latency::total 284555781245 # number of demand (read+write) miss cycles 650system.cpu.dcache.overall_miss_latency::cpu.inst 284555781245 # number of overall miss cycles 651system.cpu.dcache.overall_miss_latency::total 284555781245 # number of overall miss cycles 652system.cpu.dcache.ReadReq_accesses::cpu.inst 460991471 # number of ReadReq accesses(hits+misses) 653system.cpu.dcache.ReadReq_accesses::total 460991471 # number of ReadReq accesses(hits+misses) | 654system.cpu.dcache.demand_hits::cpu.inst 624006554 # number of demand (read+write) hits 655system.cpu.dcache.demand_hits::total 624006554 # number of demand (read+write) hits 656system.cpu.dcache.overall_hits::cpu.inst 624006554 # number of overall hits 657system.cpu.dcache.overall_hits::total 624006554 # number of overall hits 658system.cpu.dcache.ReadReq_misses::cpu.inst 7336174 # number of ReadReq misses 659system.cpu.dcache.ReadReq_misses::total 7336174 # number of ReadReq misses 660system.cpu.dcache.WriteReq_misses::cpu.inst 2240511 # number of WriteReq misses 661system.cpu.dcache.WriteReq_misses::total 2240511 # number of WriteReq misses 662system.cpu.dcache.demand_misses::cpu.inst 9576685 # number of demand (read+write) misses 663system.cpu.dcache.demand_misses::total 9576685 # number of demand (read+write) misses 664system.cpu.dcache.overall_misses::cpu.inst 9576685 # number of overall misses 665system.cpu.dcache.overall_misses::total 9576685 # number of overall misses 666system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183520141245 # number of ReadReq miss cycles 667system.cpu.dcache.ReadReq_miss_latency::total 183520141245 # number of ReadReq miss cycles 668system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101423015250 # number of WriteReq miss cycles 669system.cpu.dcache.WriteReq_miss_latency::total 101423015250 # number of WriteReq miss cycles 670system.cpu.dcache.demand_miss_latency::cpu.inst 284943156495 # number of demand (read+write) miss cycles 671system.cpu.dcache.demand_miss_latency::total 284943156495 # number of demand (read+write) miss cycles 672system.cpu.dcache.overall_miss_latency::cpu.inst 284943156495 # number of overall miss cycles 673system.cpu.dcache.overall_miss_latency::total 284943156495 # number of overall miss cycles 674system.cpu.dcache.ReadReq_accesses::cpu.inst 460997192 # number of ReadReq accesses(hits+misses) 675system.cpu.dcache.ReadReq_accesses::total 460997192 # number of ReadReq accesses(hits+misses) |
| 654system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) 655system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 656system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) 657system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 658system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) 659system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) | 676system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) 677system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 678system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) 679system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 680system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) 681system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) |
| 660system.cpu.dcache.demand_accesses::cpu.inst 633577518 # number of demand (read+write) accesses 661system.cpu.dcache.demand_accesses::total 633577518 # number of demand (read+write) accesses 662system.cpu.dcache.overall_accesses::cpu.inst 633577518 # number of overall (read+write) accesses 663system.cpu.dcache.overall_accesses::total 633577518 # number of overall (read+write) accesses 664system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses 665system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses 666system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012983 # miss rate for WriteReq accesses 667system.cpu.dcache.WriteReq_miss_rate::total 0.012983 # miss rate for WriteReq accesses | 682system.cpu.dcache.demand_accesses::cpu.inst 633583239 # number of demand (read+write) accesses 683system.cpu.dcache.demand_accesses::total 633583239 # number of demand (read+write) accesses 684system.cpu.dcache.overall_accesses::cpu.inst 633583239 # number of overall (read+write) accesses 685system.cpu.dcache.overall_accesses::total 633583239 # number of overall (read+write) accesses 686system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses 687system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses 688system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012982 # miss rate for WriteReq accesses 689system.cpu.dcache.WriteReq_miss_rate::total 0.012982 # miss rate for WriteReq accesses |
| 668system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses 669system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses 670system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses 671system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses | 690system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses 691system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses 692system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses 693system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses |
| 672system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24988.087706 # average ReadReq miss latency 673system.cpu.dcache.ReadReq_avg_miss_latency::total 24988.087706 # average ReadReq miss latency 674system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45188.180594 # average WriteReq miss latency 675system.cpu.dcache.WriteReq_avg_miss_latency::total 45188.180594 # average WriteReq miss latency 676system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency 677system.cpu.dcache.demand_avg_miss_latency::total 29714.330657 # average overall miss latency 678system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency 679system.cpu.dcache.overall_avg_miss_latency::total 29714.330657 # average overall miss latency | 694system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25015.783601 # average ReadReq miss latency 695system.cpu.dcache.ReadReq_avg_miss_latency::total 25015.783601 # average ReadReq miss latency 696system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45267.805090 # average WriteReq miss latency 697system.cpu.dcache.WriteReq_avg_miss_latency::total 45267.805090 # average WriteReq miss latency 698system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency 699system.cpu.dcache.demand_avg_miss_latency::total 29753.840342 # average overall miss latency 700system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency 701system.cpu.dcache.overall_avg_miss_latency::total 29753.840342 # average overall miss latency |
| 680system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 681system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 682system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 683system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 684system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 685system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 686system.cpu.dcache.fast_writes 0 # number of fast writes performed 687system.cpu.dcache.cache_copies 0 # number of cache copies performed | 702system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 703system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 704system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 705system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 706system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 707system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 708system.cpu.dcache.fast_writes 0 # number of fast writes performed 709system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 688system.cpu.dcache.writebacks::writebacks 3700895 # number of writebacks 689system.cpu.dcache.writebacks::total 3700895 # number of writebacks 690system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 212 # number of ReadReq MSHR hits 691system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits 692system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349723 # number of WriteReq MSHR hits 693system.cpu.dcache.WriteReq_mshr_hits::total 349723 # number of WriteReq MSHR hits 694system.cpu.dcache.demand_mshr_hits::cpu.inst 349935 # number of demand (read+write) MSHR hits 695system.cpu.dcache.demand_mshr_hits::total 349935 # number of demand (read+write) MSHR hits 696system.cpu.dcache.overall_mshr_hits::cpu.inst 349935 # number of overall MSHR hits 697system.cpu.dcache.overall_mshr_hits::total 349935 # number of overall MSHR hits 698system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335571 # number of ReadReq MSHR misses 699system.cpu.dcache.ReadReq_mshr_misses::total 7335571 # number of ReadReq MSHR misses 700system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890876 # number of WriteReq MSHR misses 701system.cpu.dcache.WriteReq_mshr_misses::total 1890876 # number of WriteReq MSHR misses 702system.cpu.dcache.demand_mshr_misses::cpu.inst 9226447 # number of demand (read+write) MSHR misses 703system.cpu.dcache.demand_mshr_misses::total 9226447 # number of demand (read+write) MSHR misses 704system.cpu.dcache.overall_mshr_misses::cpu.inst 9226447 # number of overall MSHR misses 705system.cpu.dcache.overall_mshr_misses::total 9226447 # number of overall MSHR misses 706system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168217924005 # number of ReadReq MSHR miss cycles 707system.cpu.dcache.ReadReq_mshr_miss_latency::total 168217924005 # number of ReadReq MSHR miss cycles 708system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77187221250 # number of WriteReq MSHR miss cycles 709system.cpu.dcache.WriteReq_mshr_miss_latency::total 77187221250 # number of WriteReq MSHR miss cycles 710system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245405145255 # number of demand (read+write) MSHR miss cycles 711system.cpu.dcache.demand_mshr_miss_latency::total 245405145255 # number of demand (read+write) MSHR miss cycles 712system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245405145255 # number of overall MSHR miss cycles 713system.cpu.dcache.overall_mshr_miss_latency::total 245405145255 # number of overall MSHR miss cycles | 710system.cpu.dcache.writebacks::writebacks 3700640 # number of writebacks 711system.cpu.dcache.writebacks::total 3700640 # number of writebacks 712system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits 713system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits 714system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349642 # number of WriteReq MSHR hits 715system.cpu.dcache.WriteReq_mshr_hits::total 349642 # number of WriteReq MSHR hits 716system.cpu.dcache.demand_mshr_hits::cpu.inst 349853 # number of demand (read+write) MSHR hits 717system.cpu.dcache.demand_mshr_hits::total 349853 # number of demand (read+write) MSHR hits 718system.cpu.dcache.overall_mshr_hits::cpu.inst 349853 # number of overall MSHR hits 719system.cpu.dcache.overall_mshr_hits::total 349853 # number of overall MSHR hits 720system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335963 # number of ReadReq MSHR misses 721system.cpu.dcache.ReadReq_mshr_misses::total 7335963 # number of ReadReq MSHR misses 722system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890869 # number of WriteReq MSHR misses 723system.cpu.dcache.WriteReq_mshr_misses::total 1890869 # number of WriteReq MSHR misses 724system.cpu.dcache.demand_mshr_misses::cpu.inst 9226832 # number of demand (read+write) MSHR misses 725system.cpu.dcache.demand_mshr_misses::total 9226832 # number of demand (read+write) MSHR misses 726system.cpu.dcache.overall_mshr_misses::cpu.inst 9226832 # number of overall MSHR misses 727system.cpu.dcache.overall_mshr_misses::total 9226832 # number of overall MSHR misses 728system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168431190255 # number of ReadReq MSHR miss cycles 729system.cpu.dcache.ReadReq_mshr_miss_latency::total 168431190255 # number of ReadReq MSHR miss cycles 730system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77354259500 # number of WriteReq MSHR miss cycles 731system.cpu.dcache.WriteReq_mshr_miss_latency::total 77354259500 # number of WriteReq MSHR miss cycles 732system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245785449755 # number of demand (read+write) MSHR miss cycles 733system.cpu.dcache.demand_mshr_miss_latency::total 245785449755 # number of demand (read+write) MSHR miss cycles 734system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245785449755 # number of overall MSHR miss cycles 735system.cpu.dcache.overall_mshr_miss_latency::total 245785449755 # number of overall MSHR miss cycles |
| 714system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses 715system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses 716system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses 717system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses | 736system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses 737system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses 738system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses 739system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses |
| 718system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for demand accesses 719system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses 720system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for overall accesses 721system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses 722system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22931.810490 # average ReadReq mshr miss latency 723system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22931.810490 # average ReadReq mshr miss latency 724system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40820.879450 # average WriteReq mshr miss latency 725system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40820.879450 # average WriteReq mshr miss latency 726system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency 727system.cpu.dcache.demand_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency 728system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency 729system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency | 740system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses 741system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses 742system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses 743system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses 744system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456 # average ReadReq mshr miss latency 745system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456 # average ReadReq mshr miss latency 746system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978 # average WriteReq mshr miss latency 747system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978 # average WriteReq mshr miss latency 748system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency 749system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency 750system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency 751system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency |
| 730system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 731 732---------- End Simulation Statistics ---------- | 752system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 753 754---------- End Simulation Statistics ---------- |