| stats.txt (10260:384d554cea8c) | stats.txt (10352:5f1f92bf76ee) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3final_tick 1134079016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 4host_inst_rate 227824 # Simulator instruction rate (inst/s) 5host_mem_usage 293824 # Number of bytes of host memory used 6host_op_rate 254155 # Simulator op (including micro ops) rate (op/s) 7host_seconds 6779.62 # Real time elapsed on the host 8host_tick_rate 167277674 # Simulator tick rate (ticks/s) | 3sim_seconds 1.095875 # Number of seconds simulated 4sim_ticks 1095875470500 # Number of ticks simulated 5final_tick 1095875470500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 9sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 232088 # Simulator instruction rate (inst/s) 8host_op_rate 250040 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 164667871 # Simulator tick rate (ticks/s) 10host_mem_usage 318056 # Number of bytes of host memory used 11host_seconds 6655.07 # Real time elapsed on the host |
|
| 10sim_insts 1544563087 # Number of instructions simulated | 12sim_insts 1544563087 # Number of instructions simulated |
| 11sim_ops 1723073900 # Number of ops (including micro ops) simulated 12sim_seconds 1.134079 # Number of seconds simulated 13sim_ticks 1134079016500 # Number of ticks simulated | 13sim_ops 1664032480 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts |
| 14system.clk_domain.clock 1000 # Clock period in ticks | 15system.clk_domain.clock 1000 # Clock period in ticks |
| 15system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 16system.cpu.branchPred.BTBHitPct 87.938151 # BTB Hit Percentage 17system.cpu.branchPred.BTBHits 122192107 # Number of BTB hits 18system.cpu.branchPred.BTBLookups 138952327 # Number of BTB lookups 19system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 20system.cpu.branchPred.condIncorrect 14597136 # Number of conditional branches incorrect 21system.cpu.branchPred.condPredicted 197361074 # Number of conditional branches predicted 22system.cpu.branchPred.lookups 250285818 # Number of BP lookups 23system.cpu.branchPred.usedRAS 13226889 # Number of times the RAS was used to get a target. 24system.cpu.committedInsts 1544563087 # Number of instructions committed 25system.cpu.committedOps 1723073900 # Number of ops (including micro ops) committed 26system.cpu.cpi 1.468479 # CPI: cycles per instruction 27system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) 28system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 29system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits 30system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 31system.cpu.dcache.ReadReq_accesses::cpu.inst 485955700 # number of ReadReq accesses(hits+misses) 32system.cpu.dcache.ReadReq_accesses::total 485955700 # number of ReadReq accesses(hits+misses) 33system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24973.063686 # average ReadReq miss latency 34system.cpu.dcache.ReadReq_avg_miss_latency::total 24973.063686 # average ReadReq miss latency 35system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22917.493937 # average ReadReq mshr miss latency 36system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22917.493937 # average ReadReq mshr miss latency 37system.cpu.dcache.ReadReq_hits::cpu.inst 478618690 # number of ReadReq hits 38system.cpu.dcache.ReadReq_hits::total 478618690 # number of ReadReq hits 39system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183227617996 # number of ReadReq miss cycles 40system.cpu.dcache.ReadReq_miss_latency::total 183227617996 # number of ReadReq miss cycles 41system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015098 # miss rate for ReadReq accesses 42system.cpu.dcache.ReadReq_miss_rate::total 0.015098 # miss rate for ReadReq accesses 43system.cpu.dcache.ReadReq_misses::cpu.inst 7337010 # number of ReadReq misses 44system.cpu.dcache.ReadReq_misses::total 7337010 # number of ReadReq misses 45system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 222 # number of ReadReq MSHR hits 46system.cpu.dcache.ReadReq_mshr_hits::total 222 # number of ReadReq MSHR hits 47system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168140794504 # number of ReadReq MSHR miss cycles 48system.cpu.dcache.ReadReq_mshr_miss_latency::total 168140794504 # number of ReadReq MSHR miss cycles 49system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015098 # mshr miss rate for ReadReq accesses 50system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015098 # mshr miss rate for ReadReq accesses 51system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7336788 # number of ReadReq MSHR misses 52system.cpu.dcache.ReadReq_mshr_misses::total 7336788 # number of ReadReq MSHR misses 53system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) 54system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 55system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits 56system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 57system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) 58system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 59system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45215.138055 # average WriteReq miss latency 60system.cpu.dcache.WriteReq_avg_miss_latency::total 45215.138055 # average WriteReq miss latency 61system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40855.687627 # average WriteReq mshr miss latency 62system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40855.687627 # average WriteReq mshr miss latency 63system.cpu.dcache.WriteReq_hits::cpu.inst 170348428 # number of WriteReq hits 64system.cpu.dcache.WriteReq_hits::total 170348428 # number of WriteReq hits 65system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101174252000 # number of WriteReq miss cycles 66system.cpu.dcache.WriteReq_miss_latency::total 101174252000 # number of WriteReq miss cycles 67system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012965 # miss rate for WriteReq accesses 68system.cpu.dcache.WriteReq_miss_rate::total 0.012965 # miss rate for WriteReq accesses 69system.cpu.dcache.WriteReq_misses::cpu.inst 2237619 # number of WriteReq misses 70system.cpu.dcache.WriteReq_misses::total 2237619 # number of WriteReq misses 71system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 346681 # number of WriteReq MSHR hits 72system.cpu.dcache.WriteReq_mshr_hits::total 346681 # number of WriteReq MSHR hits 73system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77255572250 # number of WriteReq MSHR miss cycles 74system.cpu.dcache.WriteReq_mshr_miss_latency::total 77255572250 # number of WriteReq MSHR miss cycles 75system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses 76system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 77system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890938 # number of WriteReq MSHR misses 78system.cpu.dcache.WriteReq_mshr_misses::total 1890938 # number of WriteReq MSHR misses 79system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 80system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 81system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 82system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 83system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 84system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 85system.cpu.dcache.cache_copies 0 # number of cache copies performed 86system.cpu.dcache.demand_accesses::cpu.inst 658541747 # number of demand (read+write) accesses 87system.cpu.dcache.demand_accesses::total 658541747 # number of demand (read+write) accesses 88system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency 89system.cpu.dcache.demand_avg_miss_latency::total 29703.696091 # average overall miss latency 90system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency 91system.cpu.dcache.demand_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency 92system.cpu.dcache.demand_hits::cpu.inst 648967118 # number of demand (read+write) hits 93system.cpu.dcache.demand_hits::total 648967118 # number of demand (read+write) hits 94system.cpu.dcache.demand_miss_latency::cpu.inst 284401869996 # number of demand (read+write) miss cycles 95system.cpu.dcache.demand_miss_latency::total 284401869996 # number of demand (read+write) miss cycles 96system.cpu.dcache.demand_miss_rate::cpu.inst 0.014539 # miss rate for demand accesses 97system.cpu.dcache.demand_miss_rate::total 0.014539 # miss rate for demand accesses 98system.cpu.dcache.demand_misses::cpu.inst 9574629 # number of demand (read+write) misses 99system.cpu.dcache.demand_misses::total 9574629 # number of demand (read+write) misses 100system.cpu.dcache.demand_mshr_hits::cpu.inst 346903 # number of demand (read+write) MSHR hits 101system.cpu.dcache.demand_mshr_hits::total 346903 # number of demand (read+write) MSHR hits 102system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245396366754 # number of demand (read+write) MSHR miss cycles 103system.cpu.dcache.demand_mshr_miss_latency::total 245396366754 # number of demand (read+write) MSHR miss cycles 104system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014012 # mshr miss rate for demand accesses 105system.cpu.dcache.demand_mshr_miss_rate::total 0.014012 # mshr miss rate for demand accesses 106system.cpu.dcache.demand_mshr_misses::cpu.inst 9227726 # number of demand (read+write) MSHR misses 107system.cpu.dcache.demand_mshr_misses::total 9227726 # number of demand (read+write) MSHR misses 108system.cpu.dcache.fast_writes 0 # number of fast writes performed 109system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 110system.cpu.dcache.overall_accesses::cpu.inst 658541747 # number of overall (read+write) accesses 111system.cpu.dcache.overall_accesses::total 658541747 # number of overall (read+write) accesses 112system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29703.696091 # average overall miss latency 113system.cpu.dcache.overall_avg_miss_latency::total 29703.696091 # average overall miss latency 114system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26593.373790 # average overall mshr miss latency 115system.cpu.dcache.overall_avg_mshr_miss_latency::total 26593.373790 # average overall mshr miss latency 116system.cpu.dcache.overall_hits::cpu.inst 648967118 # number of overall hits 117system.cpu.dcache.overall_hits::total 648967118 # number of overall hits 118system.cpu.dcache.overall_miss_latency::cpu.inst 284401869996 # number of overall miss cycles 119system.cpu.dcache.overall_miss_latency::total 284401869996 # number of overall miss cycles 120system.cpu.dcache.overall_miss_rate::cpu.inst 0.014539 # miss rate for overall accesses 121system.cpu.dcache.overall_miss_rate::total 0.014539 # miss rate for overall accesses 122system.cpu.dcache.overall_misses::cpu.inst 9574629 # number of overall misses 123system.cpu.dcache.overall_misses::total 9574629 # number of overall misses 124system.cpu.dcache.overall_mshr_hits::cpu.inst 346903 # number of overall MSHR hits 125system.cpu.dcache.overall_mshr_hits::total 346903 # number of overall MSHR hits 126system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245396366754 # number of overall MSHR miss cycles 127system.cpu.dcache.overall_mshr_miss_latency::total 245396366754 # number of overall MSHR miss cycles 128system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014012 # mshr miss rate for overall accesses 129system.cpu.dcache.overall_mshr_miss_rate::total 0.014012 # mshr miss rate for overall accesses 130system.cpu.dcache.overall_mshr_misses::cpu.inst 9227726 # number of overall MSHR misses 131system.cpu.dcache.overall_mshr_misses::total 9227726 # number of overall MSHR misses 132system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id 133system.cpu.dcache.tags.age_task_id_blocks_1024::1 1280 # Occupied blocks per task id 134system.cpu.dcache.tags.age_task_id_blocks_1024::2 2489 # Occupied blocks per task id 135system.cpu.dcache.tags.age_task_id_blocks_1024::3 70 # Occupied blocks per task id 136system.cpu.dcache.tags.avg_refs 70.327970 # Average number of references to valid blocks. 137system.cpu.dcache.tags.data_accesses 1326311464 # Number of data accesses 138system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.294010 # Average occupied blocks per requestor 139system.cpu.dcache.tags.occ_percent::cpu.inst 0.997386 # Average percentage of cache occupancy 140system.cpu.dcache.tags.occ_percent::total 0.997386 # Average percentage of cache occupancy 141system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 142system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 143system.cpu.dcache.tags.replacements 9223630 # number of replacements 144system.cpu.dcache.tags.sampled_refs 9227726 # Sample count of references to valid blocks. 145system.cpu.dcache.tags.tag_accesses 1326311464 # Number of tag accesses 146system.cpu.dcache.tags.tagsinuse 4085.294010 # Cycle average of tags in use 147system.cpu.dcache.tags.total_refs 648967240 # Total number of references to valid blocks. 148system.cpu.dcache.tags.warmup_cycle 10338720250 # Cycle when the warmup percentage was hit. 149system.cpu.dcache.writebacks::writebacks 3700800 # number of writebacks 150system.cpu.dcache.writebacks::total 3700800 # number of writebacks 151system.cpu.discardedOps 51251418 # Number of ops (including micro ops) which were discarded before commit 152system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 153system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 154system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 155system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 156system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 157system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 158system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 159system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 160system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 161system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 162system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 163system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 164system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 165system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 166system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 167system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 168system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 169system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 170system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 171system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 172system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 173system.cpu.dtb.accesses 0 # DTB accesses 174system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 175system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 176system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 177system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 178system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 179system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 180system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 181system.cpu.dtb.hits 0 # DTB hits 182system.cpu.dtb.inst_accesses 0 # ITB inst accesses 183system.cpu.dtb.inst_hits 0 # ITB inst hits 184system.cpu.dtb.inst_misses 0 # ITB inst misses 185system.cpu.dtb.misses 0 # DTB misses 186system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 187system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 188system.cpu.dtb.read_accesses 0 # DTB read accesses 189system.cpu.dtb.read_hits 0 # DTB read hits 190system.cpu.dtb.read_misses 0 # DTB read misses 191system.cpu.dtb.write_accesses 0 # DTB write accesses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.icache.ReadReq_accesses::cpu.inst 468616075 # number of ReadReq accesses(hits+misses) 195system.cpu.icache.ReadReq_accesses::total 468616075 # number of ReadReq accesses(hits+misses) 196system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71218.824455 # average ReadReq miss latency 197system.cpu.icache.ReadReq_avg_miss_latency::total 71218.824455 # average ReadReq miss latency 198system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68823.548426 # average ReadReq mshr miss latency 199system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68823.548426 # average ReadReq mshr miss latency 200system.cpu.icache.ReadReq_hits::cpu.inst 468615249 # number of ReadReq hits 201system.cpu.icache.ReadReq_hits::total 468615249 # number of ReadReq hits 202system.cpu.icache.ReadReq_miss_latency::cpu.inst 58826749 # number of ReadReq miss cycles 203system.cpu.icache.ReadReq_miss_latency::total 58826749 # number of ReadReq miss cycles 204system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 205system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 206system.cpu.icache.ReadReq_misses::cpu.inst 826 # number of ReadReq misses 207system.cpu.icache.ReadReq_misses::total 826 # number of ReadReq misses 208system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56848251 # number of ReadReq MSHR miss cycles 209system.cpu.icache.ReadReq_mshr_miss_latency::total 56848251 # number of ReadReq MSHR miss cycles 210system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 211system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 212system.cpu.icache.ReadReq_mshr_misses::cpu.inst 826 # number of ReadReq MSHR misses 213system.cpu.icache.ReadReq_mshr_misses::total 826 # number of ReadReq MSHR misses 214system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 215system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 216system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 217system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 218system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 219system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 220system.cpu.icache.cache_copies 0 # number of cache copies performed 221system.cpu.icache.demand_accesses::cpu.inst 468616075 # number of demand (read+write) accesses 222system.cpu.icache.demand_accesses::total 468616075 # number of demand (read+write) accesses 223system.cpu.icache.demand_avg_miss_latency::cpu.inst 71218.824455 # average overall miss latency 224system.cpu.icache.demand_avg_miss_latency::total 71218.824455 # average overall miss latency 225system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68823.548426 # average overall mshr miss latency 226system.cpu.icache.demand_avg_mshr_miss_latency::total 68823.548426 # average overall mshr miss latency 227system.cpu.icache.demand_hits::cpu.inst 468615249 # number of demand (read+write) hits 228system.cpu.icache.demand_hits::total 468615249 # number of demand (read+write) hits 229system.cpu.icache.demand_miss_latency::cpu.inst 58826749 # number of demand (read+write) miss cycles 230system.cpu.icache.demand_miss_latency::total 58826749 # number of demand (read+write) miss cycles 231system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 232system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 233system.cpu.icache.demand_misses::cpu.inst 826 # number of demand (read+write) misses 234system.cpu.icache.demand_misses::total 826 # number of demand (read+write) misses 235system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56848251 # number of demand (read+write) MSHR miss cycles 236system.cpu.icache.demand_mshr_miss_latency::total 56848251 # number of demand (read+write) MSHR miss cycles 237system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 238system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 239system.cpu.icache.demand_mshr_misses::cpu.inst 826 # number of demand (read+write) MSHR misses 240system.cpu.icache.demand_mshr_misses::total 826 # number of demand (read+write) MSHR misses 241system.cpu.icache.fast_writes 0 # number of fast writes performed 242system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 243system.cpu.icache.overall_accesses::cpu.inst 468616075 # number of overall (read+write) accesses 244system.cpu.icache.overall_accesses::total 468616075 # number of overall (read+write) accesses 245system.cpu.icache.overall_avg_miss_latency::cpu.inst 71218.824455 # average overall miss latency 246system.cpu.icache.overall_avg_miss_latency::total 71218.824455 # average overall miss latency 247system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68823.548426 # average overall mshr miss latency 248system.cpu.icache.overall_avg_mshr_miss_latency::total 68823.548426 # average overall mshr miss latency 249system.cpu.icache.overall_hits::cpu.inst 468615249 # number of overall hits 250system.cpu.icache.overall_hits::total 468615249 # number of overall hits 251system.cpu.icache.overall_miss_latency::cpu.inst 58826749 # number of overall miss cycles 252system.cpu.icache.overall_miss_latency::total 58826749 # number of overall miss cycles 253system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 254system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 255system.cpu.icache.overall_misses::cpu.inst 826 # number of overall misses 256system.cpu.icache.overall_misses::total 826 # number of overall misses 257system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56848251 # number of overall MSHR miss cycles 258system.cpu.icache.overall_mshr_miss_latency::total 56848251 # number of overall MSHR miss cycles 259system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 260system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 261system.cpu.icache.overall_mshr_misses::cpu.inst 826 # number of overall MSHR misses 262system.cpu.icache.overall_mshr_misses::total 826 # number of overall MSHR misses 263system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 264system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 265system.cpu.icache.tags.age_task_id_blocks_1024::4 760 # Occupied blocks per task id 266system.cpu.icache.tags.avg_refs 567330.809927 # Average number of references to valid blocks. 267system.cpu.icache.tags.data_accesses 937232976 # Number of data accesses 268system.cpu.icache.tags.occ_blocks::cpu.inst 667.306532 # Average occupied blocks per requestor 269system.cpu.icache.tags.occ_percent::cpu.inst 0.325833 # Average percentage of cache occupancy 270system.cpu.icache.tags.occ_percent::total 0.325833 # Average percentage of cache occupancy 271system.cpu.icache.tags.occ_task_id_blocks::1024 797 # Occupied blocks per task id 272system.cpu.icache.tags.occ_task_id_percent::1024 0.389160 # Percentage of cache occupancy per task id 273system.cpu.icache.tags.replacements 29 # number of replacements 274system.cpu.icache.tags.sampled_refs 826 # Sample count of references to valid blocks. 275system.cpu.icache.tags.tag_accesses 937232976 # Number of tag accesses 276system.cpu.icache.tags.tagsinuse 667.306532 # Cycle average of tags in use 277system.cpu.icache.tags.total_refs 468615249 # Total number of references to valid blocks. 278system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 279system.cpu.idleCycles 378561103 # Total number of cycles that the CPU has spent unscheduled due to idling 280system.cpu.ipc 0.680977 # IPC: instructions per cycle 281system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 282system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 283system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 284system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 285system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 286system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 287system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 288system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 289system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 290system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 291system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 292system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 293system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 294system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 295system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 296system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 297system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 298system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 299system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 300system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 301system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 302system.cpu.itb.accesses 0 # DTB accesses 303system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 304system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 305system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 306system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 307system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 308system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 309system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 310system.cpu.itb.hits 0 # DTB hits 311system.cpu.itb.inst_accesses 0 # ITB inst accesses 312system.cpu.itb.inst_hits 0 # ITB inst hits 313system.cpu.itb.inst_misses 0 # ITB inst misses 314system.cpu.itb.misses 0 # DTB misses 315system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 316system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.itb.read_accesses 0 # DTB read accesses 318system.cpu.itb.read_hits 0 # DTB read hits 319system.cpu.itb.read_misses 0 # DTB read misses 320system.cpu.itb.write_accesses 0 # DTB write accesses 321system.cpu.itb.write_hits 0 # DTB write hits 322system.cpu.itb.write_misses 0 # DTB write misses 323system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890938 # number of ReadExReq accesses(hits+misses) 324system.cpu.l2cache.ReadExReq_accesses::total 1890938 # number of ReadExReq accesses(hits+misses) 325system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80530.523230 # average ReadExReq miss latency 326system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80530.523230 # average ReadExReq miss latency 327system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67904.363586 # average ReadExReq mshr miss latency 328system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67904.363586 # average ReadExReq mshr miss latency 329system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090908 # number of ReadExReq hits 330system.cpu.l2cache.ReadExReq_hits::total 1090908 # number of ReadExReq hits 331system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64426834500 # number of ReadExReq miss cycles 332system.cpu.l2cache.ReadExReq_miss_latency::total 64426834500 # number of ReadExReq miss cycles 333system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423086 # miss rate for ReadExReq accesses 334system.cpu.l2cache.ReadExReq_miss_rate::total 0.423086 # miss rate for ReadExReq accesses 335system.cpu.l2cache.ReadExReq_misses::cpu.inst 800030 # number of ReadExReq misses 336system.cpu.l2cache.ReadExReq_misses::total 800030 # number of ReadExReq misses 337system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54325528000 # number of ReadExReq MSHR miss cycles 338system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54325528000 # number of ReadExReq MSHR miss cycles 339system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423086 # mshr miss rate for ReadExReq accesses 340system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423086 # mshr miss rate for ReadExReq accesses 341system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800030 # number of ReadExReq MSHR misses 342system.cpu.l2cache.ReadExReq_mshr_misses::total 800030 # number of ReadExReq MSHR misses 343system.cpu.l2cache.ReadReq_accesses::cpu.inst 7337614 # number of ReadReq accesses(hits+misses) 344system.cpu.l2cache.ReadReq_accesses::total 7337614 # number of ReadReq accesses(hits+misses) 345system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79650.729800 # average ReadReq miss latency 346system.cpu.l2cache.ReadReq_avg_miss_latency::total 79650.729800 # average ReadReq miss latency 347system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67079.515524 # average ReadReq mshr miss latency 348system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67079.515524 # average ReadReq mshr miss latency 349system.cpu.l2cache.ReadReq_hits::cpu.inst 6081653 # number of ReadReq hits 350system.cpu.l2cache.ReadReq_hits::total 6081653 # number of ReadReq hits 351system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100038210250 # number of ReadReq miss cycles 352system.cpu.l2cache.ReadReq_miss_latency::total 100038210250 # number of ReadReq miss cycles 353system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171167 # miss rate for ReadReq accesses 354system.cpu.l2cache.ReadReq_miss_rate::total 0.171167 # miss rate for ReadReq accesses 355system.cpu.l2cache.ReadReq_misses::cpu.inst 1255961 # number of ReadReq misses 356system.cpu.l2cache.ReadReq_misses::total 1255961 # number of ReadReq misses 357system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits 358system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 359system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84248920000 # number of ReadReq MSHR miss cycles 360system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84248920000 # number of ReadReq MSHR miss cycles 361system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171167 # mshr miss rate for ReadReq accesses 362system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171167 # mshr miss rate for ReadReq accesses 363system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255956 # number of ReadReq MSHR misses 364system.cpu.l2cache.ReadReq_mshr_misses::total 1255956 # number of ReadReq MSHR misses 365system.cpu.l2cache.Writeback_accesses::writebacks 3700800 # number of Writeback accesses(hits+misses) 366system.cpu.l2cache.Writeback_accesses::total 3700800 # number of Writeback accesses(hits+misses) 367system.cpu.l2cache.Writeback_hits::writebacks 3700800 # number of Writeback hits 368system.cpu.l2cache.Writeback_hits::total 3700800 # number of Writeback hits 369system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 370system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 371system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 372system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 373system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.l2cache.cache_copies 0 # number of cache copies performed 376system.cpu.l2cache.demand_accesses::cpu.inst 9228552 # number of demand (read+write) accesses 377system.cpu.l2cache.demand_accesses::total 9228552 # number of demand (read+write) accesses 378system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency 379system.cpu.l2cache.demand_avg_miss_latency::total 79993.076210 # average overall miss latency 380system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency 381system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency 382system.cpu.l2cache.demand_hits::cpu.inst 7172561 # number of demand (read+write) hits 383system.cpu.l2cache.demand_hits::total 7172561 # number of demand (read+write) hits 384system.cpu.l2cache.demand_miss_latency::cpu.inst 164465044750 # number of demand (read+write) miss cycles 385system.cpu.l2cache.demand_miss_latency::total 164465044750 # number of demand (read+write) miss cycles 386system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222786 # miss rate for demand accesses 387system.cpu.l2cache.demand_miss_rate::total 0.222786 # miss rate for demand accesses 388system.cpu.l2cache.demand_misses::cpu.inst 2055991 # number of demand (read+write) misses 389system.cpu.l2cache.demand_misses::total 2055991 # number of demand (read+write) misses 390system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits 391system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 392system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138574448000 # number of demand (read+write) MSHR miss cycles 393system.cpu.l2cache.demand_mshr_miss_latency::total 138574448000 # number of demand (read+write) MSHR miss cycles 394system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for demand accesses 395system.cpu.l2cache.demand_mshr_miss_rate::total 0.222785 # mshr miss rate for demand accesses 396system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055986 # number of demand (read+write) MSHR misses 397system.cpu.l2cache.demand_mshr_misses::total 2055986 # number of demand (read+write) MSHR misses 398system.cpu.l2cache.fast_writes 0 # number of fast writes performed 399system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 400system.cpu.l2cache.overall_accesses::cpu.inst 9228552 # number of overall (read+write) accesses 401system.cpu.l2cache.overall_accesses::total 9228552 # number of overall (read+write) accesses 402system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79993.076210 # average overall miss latency 403system.cpu.l2cache.overall_avg_miss_latency::total 79993.076210 # average overall miss latency 404system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67400.482299 # average overall mshr miss latency 405system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67400.482299 # average overall mshr miss latency 406system.cpu.l2cache.overall_hits::cpu.inst 7172561 # number of overall hits 407system.cpu.l2cache.overall_hits::total 7172561 # number of overall hits 408system.cpu.l2cache.overall_miss_latency::cpu.inst 164465044750 # number of overall miss cycles 409system.cpu.l2cache.overall_miss_latency::total 164465044750 # number of overall miss cycles 410system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222786 # miss rate for overall accesses 411system.cpu.l2cache.overall_miss_rate::total 0.222786 # miss rate for overall accesses 412system.cpu.l2cache.overall_misses::cpu.inst 2055991 # number of overall misses 413system.cpu.l2cache.overall_misses::total 2055991 # number of overall misses 414system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits 415system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 416system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138574448000 # number of overall MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::total 138574448000 # number of overall MSHR miss cycles 418system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222785 # mshr miss rate for overall accesses 419system.cpu.l2cache.overall_mshr_miss_rate::total 0.222785 # mshr miss rate for overall accesses 420system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055986 # number of overall MSHR misses 421system.cpu.l2cache.overall_mshr_misses::total 2055986 # number of overall MSHR misses 422system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 423system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 424system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1208 # Occupied blocks per task id 425system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12891 # Occupied blocks per task id 426system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15554 # Occupied blocks per task id 427system.cpu.l2cache.tags.avg_refs 4.376215 # Average number of references to valid blocks. 428system.cpu.l2cache.tags.data_accesses 107378812 # Number of data accesses 429system.cpu.l2cache.tags.occ_blocks::writebacks 14921.737919 # Average occupied blocks per requestor 430system.cpu.l2cache.tags.occ_blocks::cpu.inst 16303.939645 # Average occupied blocks per requestor 431system.cpu.l2cache.tags.occ_percent::writebacks 0.455375 # Average percentage of cache occupancy 432system.cpu.l2cache.tags.occ_percent::cpu.inst 0.497557 # Average percentage of cache occupancy 433system.cpu.l2cache.tags.occ_percent::total 0.952932 # Average percentage of cache occupancy 434system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id 435system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id 436system.cpu.l2cache.tags.replacements 2023282 # number of replacements 437system.cpu.l2cache.tags.sampled_refs 2053058 # Sample count of references to valid blocks. 438system.cpu.l2cache.tags.tag_accesses 107378812 # Number of tag accesses 439system.cpu.l2cache.tags.tagsinuse 31225.677564 # Cycle average of tags in use 440system.cpu.l2cache.tags.total_refs 8984623 # Total number of references to valid blocks. 441system.cpu.l2cache.tags.warmup_cycle 62285743250 # Cycle when the warmup percentage was hit. 442system.cpu.l2cache.writebacks::writebacks 1046478 # number of writebacks 443system.cpu.l2cache.writebacks::total 1046478 # number of writebacks 444system.cpu.numCycles 2268158033 # number of cpu cycles simulated 445system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 446system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 447system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 448system.cpu.tickCycles 1889596930 # Number of cycles that the CPU actually ticked 449system.cpu.toL2Bus.data_through_bus 827478528 # Total data (bytes) 450system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1652 # Packet count per connected master and slave (bytes) 451system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156252 # Packet count per connected master and slave (bytes) 452system.cpu.toL2Bus.pkt_count::total 22157904 # Packet count per connected master and slave (bytes) 453system.cpu.toL2Bus.reqLayer0.occupancy 10165476000 # Layer occupancy (ticks) 454system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 455system.cpu.toL2Bus.respLayer0.occupancy 1402249 # Layer occupancy (ticks) 456system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 457system.cpu.toL2Bus.respLayer1.occupancy 14183973746 # Layer occupancy (ticks) 458system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 459system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 460system.cpu.toL2Bus.throughput 729648037 # Throughput (bytes/s) 461system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52864 # Cumulative packet size per connected master and slave (bytes) 462system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827425664 # Cumulative packet size per connected master and slave (bytes) 463system.cpu.toL2Bus.tot_pkt_size::total 827478528 # Cumulative packet size per connected master and slave (bytes) 464system.cpu.toL2Bus.trans_dist::ReadReq 7337614 # Transaction distribution 465system.cpu.toL2Bus.trans_dist::ReadResp 7337614 # Transaction distribution 466system.cpu.toL2Bus.trans_dist::Writeback 3700800 # Transaction distribution 467system.cpu.toL2Bus.trans_dist::ReadExReq 1890938 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadExResp 1890938 # Transaction distribution 469system.cpu.workload.num_syscalls 46 # Number of system calls 470system.cpu_clk_domain.clock 500 # Clock period in ticks 471system.membus.data_through_bus 198557696 # Total data (bytes) 472system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158450 # Packet count per connected master and slave (bytes) 473system.membus.pkt_count::total 5158450 # Packet count per connected master and slave (bytes) 474system.membus.reqLayer0.occupancy 12256366000 # Layer occupancy (ticks) 475system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) 476system.membus.respLayer1.occupancy 19378736500 # Layer occupancy (ticks) 477system.membus.respLayer1.utilization 1.7 # Layer utilization (%) 478system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 479system.membus.throughput 175082770 # Throughput (bytes/s) 480system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198557696 # Cumulative packet size per connected master and slave (bytes) 481system.membus.tot_pkt_size::total 198557696 # Cumulative packet size per connected master and slave (bytes) 482system.membus.trans_dist::ReadReq 1255956 # Transaction distribution 483system.membus.trans_dist::ReadResp 1255956 # Transaction distribution 484system.membus.trans_dist::Writeback 1046478 # Transaction distribution 485system.membus.trans_dist::ReadExReq 800030 # Transaction distribution 486system.membus.trans_dist::ReadExResp 800030 # Transaction distribution 487system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 488system.physmem.avgGap 365541.37 # Average gap between requests 489system.physmem.avgMemAccLat 37274.24 # Average memory access latency per DRAM burst 490system.physmem.avgQLat 18524.24 # Average queueing delay per DRAM burst 491system.physmem.avgRdBW 115.95 # Average DRAM read bandwidth in MiByte/s 492system.physmem.avgRdBWSys 116.03 # Average system read bandwidth in MiByte/s 493system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 494system.physmem.avgWrBW 59.05 # Average achieved write bandwidth in MiByte/s 495system.physmem.avgWrBWSys 59.06 # Average system write bandwidth in MiByte/s 496system.physmem.avgWrQLen 24.80 # Average write queue length when enqueuing 497system.physmem.busUtil 1.37 # Data bus utilization in percentage 498system.physmem.busUtilRead 0.91 # Data bus utilization in percentage for reads 499system.physmem.busUtilWrite 0.46 # Data bus utilization in percentage for writes 500system.physmem.bw_inst_read::cpu.inst 44808 # Instruction read bandwidth from this memory (bytes/s) 501system.physmem.bw_inst_read::total 44808 # Instruction read bandwidth from this memory (bytes/s) 502system.physmem.bw_read::cpu.inst 116026399 # Total read bandwidth from this memory (bytes/s) 503system.physmem.bw_read::total 116026399 # Total read bandwidth from this memory (bytes/s) 504system.physmem.bw_total::writebacks 59056372 # Total bandwidth to/from this memory (bytes/s) 505system.physmem.bw_total::cpu.inst 116026399 # Total bandwidth to/from this memory (bytes/s) 506system.physmem.bw_total::total 175082770 # Total bandwidth to/from this memory (bytes/s) 507system.physmem.bw_write::writebacks 59056372 # Write bandwidth from this memory (bytes/s) 508system.physmem.bw_write::total 59056372 # Write bandwidth from this memory (bytes/s) 509system.physmem.bytesPerActivate::samples 1917061 # Bytes accessed per row activation 510system.physmem.bytesPerActivate::mean 103.528140 # Bytes accessed per row activation 511system.physmem.bytesPerActivate::gmean 81.739842 # Bytes accessed per row activation 512system.physmem.bytesPerActivate::stdev 125.452866 # Bytes accessed per row activation 513system.physmem.bytesPerActivate::0-127 1492586 77.86% 77.86% # Bytes accessed per row activation 514system.physmem.bytesPerActivate::128-255 305285 15.92% 93.78% # Bytes accessed per row activation 515system.physmem.bytesPerActivate::256-383 52052 2.72% 96.50% # Bytes accessed per row activation 516system.physmem.bytesPerActivate::384-511 21496 1.12% 97.62% # Bytes accessed per row activation 517system.physmem.bytesPerActivate::512-639 13307 0.69% 98.31% # Bytes accessed per row activation 518system.physmem.bytesPerActivate::640-767 7031 0.37% 98.68% # Bytes accessed per row activation 519system.physmem.bytesPerActivate::768-895 5522 0.29% 98.97% # Bytes accessed per row activation 520system.physmem.bytesPerActivate::896-1023 4121 0.21% 99.18% # Bytes accessed per row activation 521system.physmem.bytesPerActivate::1024-1151 15661 0.82% 100.00% # Bytes accessed per row activation 522system.physmem.bytesPerActivate::total 1917061 # Bytes accessed per row activation 523system.physmem.bytesReadDRAM 131498944 # Total number of bytes read from DRAM 524system.physmem.bytesReadSys 131583104 # Total read bytes from the system interface side 525system.physmem.bytesReadWrQ 84160 # Total number of bytes read from write queue 526system.physmem.bytesWritten 66972672 # Total number of bytes written to DRAM 527system.physmem.bytesWrittenSys 66974592 # Total written bytes from the system interface side 528system.physmem.bytes_inst_read::cpu.inst 50816 # Number of instructions bytes read from this memory 529system.physmem.bytes_inst_read::total 50816 # Number of instructions bytes read from this memory 530system.physmem.bytes_read::cpu.inst 131583104 # Number of bytes read from this memory 531system.physmem.bytes_read::total 131583104 # Number of bytes read from this memory 532system.physmem.bytes_written::writebacks 66974592 # Number of bytes written to this memory 533system.physmem.bytes_written::total 66974592 # Number of bytes written to this memory 534system.physmem.memoryStateTime::IDLE 321867794250 # Time in different power states 535system.physmem.memoryStateTime::REF 37869260000 # Time in different power states 536system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 537system.physmem.memoryStateTime::ACT 774338779750 # Time in different power states 538system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 16system.physmem.bytes_read::cpu.inst 131539072 # Number of bytes read from this memory 17system.physmem.bytes_read::total 131539072 # Number of bytes read from this memory 18system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory 19system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory 20system.physmem.bytes_written::writebacks 66963456 # Number of bytes written to this memory 21system.physmem.bytes_written::total 66963456 # Number of bytes written to this memory 22system.physmem.num_reads::cpu.inst 2055298 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 2055298 # Number of read requests responded to by this memory 24system.physmem.num_writes::writebacks 1046304 # Number of write requests responded to by this memory 25system.physmem.num_writes::total 1046304 # Number of write requests responded to by this memory 26system.physmem.bw_read::cpu.inst 120031040 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 120031040 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 46020 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 46020 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_write::writebacks 61104987 # Write bandwidth from this memory (bytes/s) 31system.physmem.bw_write::total 61104987 # Write bandwidth from this memory (bytes/s) 32system.physmem.bw_total::writebacks 61104987 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 120031040 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::total 181136026 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.readReqs 2055298 # Number of read requests accepted 36system.physmem.writeReqs 1046304 # Number of write requests accepted 37system.physmem.readBursts 2055298 # Number of DRAM read bursts, including those serviced by the write queue 38system.physmem.writeBursts 1046304 # Number of DRAM write bursts, including those merged in the write queue 39system.physmem.bytesReadDRAM 131453056 # Total number of bytes read from DRAM 40system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue 41system.physmem.bytesWritten 66961856 # Total number of bytes written to DRAM 42system.physmem.bytesReadSys 131539072 # Total read bytes from the system interface side 43system.physmem.bytesWrittenSys 66963456 # Total written bytes from the system interface side 44system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue |
| 539system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 540system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 47system.physmem.perBankRdBursts::0 127944 # Per bank write bursts 48system.physmem.perBankRdBursts::1 125151 # Per bank write bursts 49system.physmem.perBankRdBursts::2 122313 # Per bank write bursts 50system.physmem.perBankRdBursts::3 124176 # Per bank write bursts 51system.physmem.perBankRdBursts::4 123203 # Per bank write bursts 52system.physmem.perBankRdBursts::5 123365 # Per bank write bursts 53system.physmem.perBankRdBursts::6 123797 # Per bank write bursts 54system.physmem.perBankRdBursts::7 124247 # Per bank write bursts 55system.physmem.perBankRdBursts::8 131879 # Per bank write bursts 56system.physmem.perBankRdBursts::9 134089 # Per bank write bursts 57system.physmem.perBankRdBursts::10 132451 # Per bank write bursts 58system.physmem.perBankRdBursts::11 133680 # Per bank write bursts 59system.physmem.perBankRdBursts::12 133764 # Per bank write bursts 60system.physmem.perBankRdBursts::13 133810 # Per bank write bursts 61system.physmem.perBankRdBursts::14 129795 # Per bank write bursts 62system.physmem.perBankRdBursts::15 130290 # Per bank write bursts 63system.physmem.perBankWrBursts::0 65788 # Per bank write bursts 64system.physmem.perBankWrBursts::1 64108 # Per bank write bursts 65system.physmem.perBankWrBursts::2 62418 # Per bank write bursts 66system.physmem.perBankWrBursts::3 62855 # Per bank write bursts 67system.physmem.perBankWrBursts::4 62808 # Per bank write bursts 68system.physmem.perBankWrBursts::5 62982 # Per bank write bursts 69system.physmem.perBankWrBursts::6 64271 # Per bank write bursts 70system.physmem.perBankWrBursts::7 65268 # Per bank write bursts 71system.physmem.perBankWrBursts::8 67081 # Per bank write bursts 72system.physmem.perBankWrBursts::9 67609 # Per bank write bursts 73system.physmem.perBankWrBursts::10 67274 # Per bank write bursts 74system.physmem.perBankWrBursts::11 67626 # Per bank write bursts 75system.physmem.perBankWrBursts::12 67000 # Per bank write bursts 76system.physmem.perBankWrBursts::13 67431 # Per bank write bursts 77system.physmem.perBankWrBursts::14 66125 # Per bank write bursts 78system.physmem.perBankWrBursts::15 65635 # Per bank write bursts |
|
| 541system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 542system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 543system.physmem.num_reads::cpu.inst 2055986 # Number of read requests responded to by this memory 544system.physmem.num_reads::total 2055986 # Number of read requests responded to by this memory 545system.physmem.num_writes::writebacks 1046478 # Number of write requests responded to by this memory 546system.physmem.num_writes::total 1046478 # Number of write requests responded to by this memory 547system.physmem.pageHitRate 38.18 # Row buffer hit rate, read and write combined 548system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 549system.physmem.perBankRdBursts::0 127958 # Per bank write bursts 550system.physmem.perBankRdBursts::1 125105 # Per bank write bursts 551system.physmem.perBankRdBursts::2 122165 # Per bank write bursts 552system.physmem.perBankRdBursts::3 124186 # Per bank write bursts 553system.physmem.perBankRdBursts::4 123280 # Per bank write bursts 554system.physmem.perBankRdBursts::5 123449 # Per bank write bursts 555system.physmem.perBankRdBursts::6 123880 # Per bank write bursts 556system.physmem.perBankRdBursts::7 124388 # Per bank write bursts 557system.physmem.perBankRdBursts::8 131994 # Per bank write bursts 558system.physmem.perBankRdBursts::9 133987 # Per bank write bursts 559system.physmem.perBankRdBursts::10 132463 # Per bank write bursts 560system.physmem.perBankRdBursts::11 133769 # Per bank write bursts 561system.physmem.perBankRdBursts::12 133910 # Per bank write bursts 562system.physmem.perBankRdBursts::13 133839 # Per bank write bursts 563system.physmem.perBankRdBursts::14 129945 # Per bank write bursts 564system.physmem.perBankRdBursts::15 130353 # Per bank write bursts 565system.physmem.perBankWrBursts::0 65810 # Per bank write bursts 566system.physmem.perBankWrBursts::1 64091 # Per bank write bursts 567system.physmem.perBankWrBursts::2 62337 # Per bank write bursts 568system.physmem.perBankWrBursts::3 62824 # Per bank write bursts 569system.physmem.perBankWrBursts::4 62831 # Per bank write bursts 570system.physmem.perBankWrBursts::5 62991 # Per bank write bursts 571system.physmem.perBankWrBursts::6 64303 # Per bank write bursts 572system.physmem.perBankWrBursts::7 65302 # Per bank write bursts 573system.physmem.perBankWrBursts::8 67082 # Per bank write bursts 574system.physmem.perBankWrBursts::9 67591 # Per bank write bursts 575system.physmem.perBankWrBursts::10 67285 # Per bank write bursts 576system.physmem.perBankWrBursts::11 67661 # Per bank write bursts 577system.physmem.perBankWrBursts::12 67090 # Per bank write bursts 578system.physmem.perBankWrBursts::13 67416 # Per bank write bursts 579system.physmem.perBankWrBursts::14 66182 # Per bank write bursts 580system.physmem.perBankWrBursts::15 65652 # Per bank write bursts 581system.physmem.rdPerTurnAround::samples 60782 # Reads before turning the bus around for writes 582system.physmem.rdPerTurnAround::mean 33.755668 # Reads before turning the bus around for writes 583system.physmem.rdPerTurnAround::stdev 161.633297 # Reads before turning the bus around for writes 584system.physmem.rdPerTurnAround::0-1023 60741 99.93% 99.93% # Reads before turning the bus around for writes 585system.physmem.rdPerTurnAround::1024-2047 17 0.03% 99.96% # Reads before turning the bus around for writes 586system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes 587system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes 588system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes 589system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes 590system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes 591system.physmem.rdPerTurnAround::13312-14335 2 0.00% 100.00% # Reads before turning the bus around for writes 592system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes 593system.physmem.rdPerTurnAround::total 60782 # Reads before turning the bus around for writes 594system.physmem.rdQLenPdf::0 1924013 # What read queue length does an incoming req see 595system.physmem.rdQLenPdf::1 130641 # What read queue length does an incoming req see 596system.physmem.rdQLenPdf::2 17 # What read queue length does an incoming req see | 81system.physmem.totGap 1095875382500 # Total gap between requests 82system.physmem.readPktSize::0 0 # Read request sizes (log2) 83system.physmem.readPktSize::1 0 # Read request sizes (log2) 84system.physmem.readPktSize::2 0 # Read request sizes (log2) 85system.physmem.readPktSize::3 0 # Read request sizes (log2) 86system.physmem.readPktSize::4 0 # Read request sizes (log2) 87system.physmem.readPktSize::5 0 # Read request sizes (log2) 88system.physmem.readPktSize::6 2055298 # Read request sizes (log2) 89system.physmem.writePktSize::0 0 # Write request sizes (log2) 90system.physmem.writePktSize::1 0 # Write request sizes (log2) 91system.physmem.writePktSize::2 0 # Write request sizes (log2) 92system.physmem.writePktSize::3 0 # Write request sizes (log2) 93system.physmem.writePktSize::4 0 # Write request sizes (log2) 94system.physmem.writePktSize::5 0 # Write request sizes (log2) 95system.physmem.writePktSize::6 1046304 # Write request sizes (log2) 96system.physmem.rdQLenPdf::0 1922424 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::1 131512 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see |
| 597system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 598system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 599system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 600system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 601system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 602system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 603system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 604system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 618system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 619system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 620system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 621system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 622system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 623system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 624system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 625system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see | 99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see --- 13 unchanged lines hidden (view full) --- 120system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| 626system.physmem.readBursts 2055986 # Number of DRAM read bursts, including those serviced by the write queue 627system.physmem.readPktSize::0 0 # Read request sizes (log2) 628system.physmem.readPktSize::1 0 # Read request sizes (log2) 629system.physmem.readPktSize::2 0 # Read request sizes (log2) 630system.physmem.readPktSize::3 0 # Read request sizes (log2) 631system.physmem.readPktSize::4 0 # Read request sizes (log2) 632system.physmem.readPktSize::5 0 # Read request sizes (log2) 633system.physmem.readPktSize::6 2055986 # Read request sizes (log2) 634system.physmem.readReqs 2055986 # Number of read requests accepted 635system.physmem.readRowHitRate 37.77 # Row buffer hit rate for reads 636system.physmem.readRowHits 776076 # Number of row buffer hits during reads 637system.physmem.servicedByWrQ 1315 # Number of DRAM read bursts serviced by the write queue 638system.physmem.totBusLat 10273355000 # Total ticks spent in databus transfers 639system.physmem.totGap 1134078928500 # Total gap between requests 640system.physmem.totMemAccLat 76586290250 # Total ticks spent from burst creation until serviced by the DRAM 641system.physmem.totQLat 38061209000 # Total ticks spent queuing 642system.physmem.wrPerTurnAround::samples 60782 # Writes before turning the bus around for reads 643system.physmem.wrPerTurnAround::mean 17.216413 # Writes before turning the bus around for reads 644system.physmem.wrPerTurnAround::gmean 17.182090 # Writes before turning the bus around for reads 645system.physmem.wrPerTurnAround::stdev 1.086488 # Writes before turning the bus around for reads 646system.physmem.wrPerTurnAround::16 25426 41.83% 41.83% # Writes before turning the bus around for reads 647system.physmem.wrPerTurnAround::17 1488 2.45% 44.28% # Writes before turning the bus around for reads 648system.physmem.wrPerTurnAround::18 29643 48.77% 93.05% # Writes before turning the bus around for reads 649system.physmem.wrPerTurnAround::19 3806 6.26% 99.31% # Writes before turning the bus around for reads 650system.physmem.wrPerTurnAround::20 363 0.60% 99.91% # Writes before turning the bus around for reads 651system.physmem.wrPerTurnAround::21 50 0.08% 99.99% # Writes before turning the bus around for reads 652system.physmem.wrPerTurnAround::22 4 0.01% 100.00% # Writes before turning the bus around for reads 653system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads 654system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads 655system.physmem.wrPerTurnAround::total 60782 # Writes before turning the bus around for reads | |
| 656system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 657system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 658system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 659system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 660system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 661system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 662system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 663system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 664system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 665system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 666system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 667system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 668system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 669system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 670system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 128system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 671system.physmem.wrQLenPdf::15 33627 # What write queue length does an incoming req see 672system.physmem.wrQLenPdf::16 35200 # What write queue length does an incoming req see 673system.physmem.wrQLenPdf::17 57222 # What write queue length does an incoming req see 674system.physmem.wrQLenPdf::18 60715 # What write queue length does an incoming req see 675system.physmem.wrQLenPdf::19 61437 # What write queue length does an incoming req see 676system.physmem.wrQLenPdf::20 61279 # What write queue length does an incoming req see 677system.physmem.wrQLenPdf::21 61254 # What write queue length does an incoming req see 678system.physmem.wrQLenPdf::22 61244 # What write queue length does an incoming req see 679system.physmem.wrQLenPdf::23 61236 # What write queue length does an incoming req see 680system.physmem.wrQLenPdf::24 61317 # What write queue length does an incoming req see 681system.physmem.wrQLenPdf::25 61255 # What write queue length does an incoming req see 682system.physmem.wrQLenPdf::26 61292 # What write queue length does an incoming req see 683system.physmem.wrQLenPdf::27 62303 # What write queue length does an incoming req see 684system.physmem.wrQLenPdf::28 61692 # What write queue length does an incoming req see 685system.physmem.wrQLenPdf::29 61407 # What write queue length does an incoming req see 686system.physmem.wrQLenPdf::30 62182 # What write queue length does an incoming req see 687system.physmem.wrQLenPdf::31 60930 # What write queue length does an incoming req see 688system.physmem.wrQLenPdf::32 60785 # What write queue length does an incoming req see 689system.physmem.wrQLenPdf::33 71 # What write queue length does an incoming req see 690system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see 691system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see 692system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see 693system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 694system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see | 143system.physmem.wrQLenPdf::15 33528 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::16 34841 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::17 57203 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::18 60757 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::19 61403 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::20 61327 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::21 61251 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::22 61258 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::23 61259 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::24 61367 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::25 61289 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::26 61334 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::27 62306 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::28 61683 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::29 61440 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::30 62194 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::31 60945 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::32 60798 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see |
| 695system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 696system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 697system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 698system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 699system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 700system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 701system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 702system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 712system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 713system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 714system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 715system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 716system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 717system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 718system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 719system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see --- 9 unchanged lines hidden (view full) --- 184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 720system.physmem.writeBursts 1046478 # Number of DRAM write bursts, including those merged in the write queue 721system.physmem.writePktSize::0 0 # Write request sizes (log2) 722system.physmem.writePktSize::1 0 # Write request sizes (log2) 723system.physmem.writePktSize::2 0 # Write request sizes (log2) 724system.physmem.writePktSize::3 0 # Write request sizes (log2) 725system.physmem.writePktSize::4 0 # Write request sizes (log2) 726system.physmem.writePktSize::5 0 # Write request sizes (log2) 727system.physmem.writePktSize::6 1046478 # Write request sizes (log2) 728system.physmem.writeReqs 1046478 # Number of write requests accepted 729system.physmem.writeRowHitRate 38.99 # Row buffer hit rate for writes 730system.physmem.writeRowHits 407972 # Number of row buffer hits during writes 731system.voltage_domain.voltage 1 # Voltage in Volts | 192system.physmem.bytesPerActivate::samples 1911965 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::mean 103.774418 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::gmean 81.877172 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::stdev 125.825249 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::0-127 1485376 77.69% 77.69% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::128-255 306998 16.06% 93.75% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::256-383 52789 2.76% 96.51% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::384-511 21060 1.10% 97.61% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::512-639 13283 0.69% 98.30% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::640-767 6873 0.36% 98.66% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::768-895 5659 0.30% 98.96% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::896-1023 4134 0.22% 99.17% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::1024-1151 15793 0.83% 100.00% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::total 1911965 # Bytes accessed per row activation 206system.physmem.rdPerTurnAround::samples 60795 # Reads before turning the bus around for writes 207system.physmem.rdPerTurnAround::mean 33.737117 # Reads before turning the bus around for writes 208system.physmem.rdPerTurnAround::stdev 161.571664 # Reads before turning the bus around for writes 209system.physmem.rdPerTurnAround::0-1023 60754 99.93% 99.93% # Reads before turning the bus around for writes 210system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes 218system.physmem.rdPerTurnAround::total 60795 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 60795 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 17.209951 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 17.175292 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 1.091996 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 25805 42.45% 42.45% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 1192 1.96% 44.41% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 29551 48.61% 93.01% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 3811 6.27% 99.28% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 363 0.60% 99.88% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::21 60 0.10% 99.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::22 11 0.02% 100.00% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::total 60795 # Writes before turning the bus around for reads 232system.physmem.totQLat 38124649000 # Total ticks spent queuing 233system.physmem.totMemAccLat 76636286500 # Total ticks spent from burst creation until serviced by the DRAM 234system.physmem.totBusLat 10269770000 # Total ticks spent in databus transfers 235system.physmem.avgQLat 18561.59 # Average queueing delay per DRAM burst 236system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 237system.physmem.avgMemAccLat 37311.59 # Average memory access latency per DRAM burst 238system.physmem.avgRdBW 119.95 # Average DRAM read bandwidth in MiByte/s 239system.physmem.avgWrBW 61.10 # Average achieved write bandwidth in MiByte/s 240system.physmem.avgRdBWSys 120.03 # Average system read bandwidth in MiByte/s 241system.physmem.avgWrBWSys 61.10 # Average system write bandwidth in MiByte/s 242system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 243system.physmem.busUtil 1.41 # Data bus utilization in percentage 244system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads 245system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes 246system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing 247system.physmem.avgWrQLen 24.69 # Average write queue length when enqueuing 248system.physmem.readRowHits 779774 # Number of row buffer hits during reads 249system.physmem.writeRowHits 408484 # Number of row buffer hits during writes 250system.physmem.readRowHitRate 37.96 # Row buffer hit rate for reads 251system.physmem.writeRowHitRate 39.04 # Row buffer hit rate for writes 252system.physmem.avgGap 353325.60 # Average gap between requests 253system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined 254system.physmem.memoryStateTime::IDLE 306310282500 # Time in different power states 255system.physmem.memoryStateTime::REF 36593440000 # Time in different power states 256system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 257system.physmem.memoryStateTime::ACT 752968660500 # Time in different power states 258system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 259system.membus.throughput 181136026 # Throughput (bytes/s) 260system.membus.trans_dist::ReadReq 1255348 # Transaction distribution 261system.membus.trans_dist::ReadResp 1255348 # Transaction distribution 262system.membus.trans_dist::Writeback 1046304 # Transaction distribution 263system.membus.trans_dist::ReadExReq 799950 # Transaction distribution 264system.membus.trans_dist::ReadExResp 799950 # Transaction distribution 265system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5156900 # Packet count per connected master and slave (bytes) 266system.membus.pkt_count::total 5156900 # Packet count per connected master and slave (bytes) 267system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198502528 # Cumulative packet size per connected master and slave (bytes) 268system.membus.tot_pkt_size::total 198502528 # Cumulative packet size per connected master and slave (bytes) 269system.membus.data_through_bus 198502528 # Total data (bytes) 270system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 271system.membus.reqLayer0.occupancy 12227667000 # Layer occupancy (ticks) 272system.membus.reqLayer0.utilization 1.1 # Layer utilization (%) 273system.membus.respLayer1.occupancy 19360882250 # Layer occupancy (ticks) 274system.membus.respLayer1.utilization 1.8 # Layer utilization (%) 275system.cpu_clk_domain.clock 500 # Clock period in ticks 276system.cpu.branchPred.lookups 239641872 # Number of BP lookups 277system.cpu.branchPred.condPredicted 186303374 # Number of conditional branches predicted 278system.cpu.branchPred.condIncorrect 14594643 # Number of conditional branches incorrect 279system.cpu.branchPred.BTBLookups 130836287 # Number of BTB lookups 280system.cpu.branchPred.BTBHits 121989290 # Number of BTB hits 281system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 282system.cpu.branchPred.BTBHitPct 93.238117 # BTB Hit Percentage 283system.cpu.branchPred.usedRAS 15653729 # Number of times the RAS was used to get a target. 284system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions. 285system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 286system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 287system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 288system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 289system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 290system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 291system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 292system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 293system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 294system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 295system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 296system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 297system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 298system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 299system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 300system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 301system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 302system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 303system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 304system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 305system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 306system.cpu.dtb.inst_hits 0 # ITB inst hits 307system.cpu.dtb.inst_misses 0 # ITB inst misses 308system.cpu.dtb.read_hits 0 # DTB read hits 309system.cpu.dtb.read_misses 0 # DTB read misses 310system.cpu.dtb.write_hits 0 # DTB write hits 311system.cpu.dtb.write_misses 0 # DTB write misses 312system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 313system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 314system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 315system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 316system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 317system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 318system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 319system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 320system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 321system.cpu.dtb.read_accesses 0 # DTB read accesses 322system.cpu.dtb.write_accesses 0 # DTB write accesses 323system.cpu.dtb.inst_accesses 0 # ITB inst accesses 324system.cpu.dtb.hits 0 # DTB hits 325system.cpu.dtb.misses 0 # DTB misses 326system.cpu.dtb.accesses 0 # DTB accesses 327system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 328system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 329system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 330system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 331system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 332system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 333system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 334system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 335system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 336system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 337system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 338system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 339system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 340system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 341system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 342system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 343system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 344system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 345system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 346system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 347system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 348system.cpu.itb.inst_hits 0 # ITB inst hits 349system.cpu.itb.inst_misses 0 # ITB inst misses 350system.cpu.itb.read_hits 0 # DTB read hits 351system.cpu.itb.read_misses 0 # DTB read misses 352system.cpu.itb.write_hits 0 # DTB write hits 353system.cpu.itb.write_misses 0 # DTB write misses 354system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 355system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 356system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 357system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 358system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 359system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 360system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 361system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 362system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.itb.read_accesses 0 # DTB read accesses 364system.cpu.itb.write_accesses 0 # DTB write accesses 365system.cpu.itb.inst_accesses 0 # ITB inst accesses 366system.cpu.itb.hits 0 # DTB hits 367system.cpu.itb.misses 0 # DTB misses 368system.cpu.itb.accesses 0 # DTB accesses 369system.cpu.workload.num_syscalls 46 # Number of system calls 370system.cpu.numCycles 2191750941 # number of cpu cycles simulated 371system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 372system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 373system.cpu.committedInsts 1544563087 # Number of instructions committed 374system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed 375system.cpu.discardedOps 42066132 # Number of ops (including micro ops) which were discarded before commit 376system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 377system.cpu.cpi 1.419010 # CPI: cycles per instruction 378system.cpu.ipc 0.704717 # IPC: instructions per cycle 379system.cpu.tickCycles 1808188284 # Number of cycles that the object actually ticked 380system.cpu.idleCycles 383562657 # Total number of cycles that the object has spent stopped 381system.cpu.icache.tags.replacements 29 # number of replacements 382system.cpu.icache.tags.tagsinuse 661.141376 # Cycle average of tags in use 383system.cpu.icache.tags.total_refs 464847257 # Total number of references to valid blocks. 384system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks. 385system.cpu.icache.tags.avg_refs 566886.898780 # Average number of references to valid blocks. 386system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 387system.cpu.icache.tags.occ_blocks::cpu.inst 661.141376 # Average occupied blocks per requestor 388system.cpu.icache.tags.occ_percent::cpu.inst 0.322823 # Average percentage of cache occupancy 389system.cpu.icache.tags.occ_percent::total 0.322823 # Average percentage of cache occupancy 390system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id 391system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id 392system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id 393system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id 394system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id 395system.cpu.icache.tags.tag_accesses 929696974 # Number of tag accesses 396system.cpu.icache.tags.data_accesses 929696974 # Number of data accesses 397system.cpu.icache.ReadReq_hits::cpu.inst 464847257 # number of ReadReq hits 398system.cpu.icache.ReadReq_hits::total 464847257 # number of ReadReq hits 399system.cpu.icache.demand_hits::cpu.inst 464847257 # number of demand (read+write) hits 400system.cpu.icache.demand_hits::total 464847257 # number of demand (read+write) hits 401system.cpu.icache.overall_hits::cpu.inst 464847257 # number of overall hits 402system.cpu.icache.overall_hits::total 464847257 # number of overall hits 403system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses 404system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses 405system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses 406system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses 407system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses 408system.cpu.icache.overall_misses::total 820 # number of overall misses 409system.cpu.icache.ReadReq_miss_latency::cpu.inst 58324499 # number of ReadReq miss cycles 410system.cpu.icache.ReadReq_miss_latency::total 58324499 # number of ReadReq miss cycles 411system.cpu.icache.demand_miss_latency::cpu.inst 58324499 # number of demand (read+write) miss cycles 412system.cpu.icache.demand_miss_latency::total 58324499 # number of demand (read+write) miss cycles 413system.cpu.icache.overall_miss_latency::cpu.inst 58324499 # number of overall miss cycles 414system.cpu.icache.overall_miss_latency::total 58324499 # number of overall miss cycles 415system.cpu.icache.ReadReq_accesses::cpu.inst 464848077 # number of ReadReq accesses(hits+misses) 416system.cpu.icache.ReadReq_accesses::total 464848077 # number of ReadReq accesses(hits+misses) 417system.cpu.icache.demand_accesses::cpu.inst 464848077 # number of demand (read+write) accesses 418system.cpu.icache.demand_accesses::total 464848077 # number of demand (read+write) accesses 419system.cpu.icache.overall_accesses::cpu.inst 464848077 # number of overall (read+write) accesses 420system.cpu.icache.overall_accesses::total 464848077 # number of overall (read+write) accesses 421system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses 422system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses 423system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses 424system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses 425system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses 426system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses 427system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805 # average ReadReq miss latency 428system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805 # average ReadReq miss latency 429system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency 430system.cpu.icache.demand_avg_miss_latency::total 71127.437805 # average overall miss latency 431system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency 432system.cpu.icache.overall_avg_miss_latency::total 71127.437805 # average overall miss latency 433system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 434system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 435system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 436system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 437system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 438system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 439system.cpu.icache.fast_writes 0 # number of fast writes performed 440system.cpu.icache.cache_copies 0 # number of cache copies performed 441system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses 442system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses 443system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses 444system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses 445system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses 446system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses 447system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56360501 # number of ReadReq MSHR miss cycles 448system.cpu.icache.ReadReq_mshr_miss_latency::total 56360501 # number of ReadReq MSHR miss cycles 449system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56360501 # number of demand (read+write) MSHR miss cycles 450system.cpu.icache.demand_mshr_miss_latency::total 56360501 # number of demand (read+write) MSHR miss cycles 451system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56360501 # number of overall MSHR miss cycles 452system.cpu.icache.overall_mshr_miss_latency::total 56360501 # number of overall MSHR miss cycles 453system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses 454system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses 455system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses 456system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses 457system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses 458system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses 459system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68732.318293 # average ReadReq mshr miss latency 460system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68732.318293 # average ReadReq mshr miss latency 461system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency 462system.cpu.icache.demand_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency 463system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency 464system.cpu.icache.overall_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency 465system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 466system.cpu.toL2Bus.throughput 755014954 # Throughput (bytes/s) 467system.cpu.toL2Bus.trans_dist::ReadReq 7336391 # Transaction distribution 468system.cpu.toL2Bus.trans_dist::ReadResp 7336391 # Transaction distribution 469system.cpu.toL2Bus.trans_dist::Writeback 3700895 # Transaction distribution 470system.cpu.toL2Bus.trans_dist::ReadExReq 1890876 # Transaction distribution 471system.cpu.toL2Bus.trans_dist::ReadExResp 1890876 # Transaction distribution 472system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes) 473system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22153789 # Packet count per connected master and slave (bytes) 474system.cpu.toL2Bus.pkt_count::total 22155429 # Packet count per connected master and slave (bytes) 475system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes) 476system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827349888 # Cumulative packet size per connected master and slave (bytes) 477system.cpu.toL2Bus.tot_pkt_size::total 827402368 # Cumulative packet size per connected master and slave (bytes) 478system.cpu.toL2Bus.data_through_bus 827402368 # Total data (bytes) 479system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 480system.cpu.toL2Bus.reqLayer0.occupancy 10164976000 # Layer occupancy (ticks) 481system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) 482system.cpu.toL2Bus.respLayer0.occupancy 1391999 # Layer occupancy (ticks) 483system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) 484system.cpu.toL2Bus.respLayer1.occupancy 14185372245 # Layer occupancy (ticks) 485system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 486system.cpu.l2cache.tags.replacements 2022594 # number of replacements 487system.cpu.l2cache.tags.tagsinuse 31252.258926 # Cycle average of tags in use 488system.cpu.l2cache.tags.total_refs 8984184 # Total number of references to valid blocks. 489system.cpu.l2cache.tags.sampled_refs 2052369 # Sample count of references to valid blocks. 490system.cpu.l2cache.tags.avg_refs 4.377470 # Average number of references to valid blocks. 491system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit. 492system.cpu.l2cache.tags.occ_blocks::writebacks 14968.183746 # Average occupied blocks per requestor 493system.cpu.l2cache.tags.occ_blocks::cpu.inst 16284.075180 # Average occupied blocks per requestor 494system.cpu.l2cache.tags.occ_percent::writebacks 0.456793 # Average percentage of cache occupancy 495system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496951 # Average percentage of cache occupancy 496system.cpu.l2cache.tags.occ_percent::total 0.953743 # Average percentage of cache occupancy 497system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id 498system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id 499system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id 500system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id 501system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id 502system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id 503system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id 504system.cpu.l2cache.tags.tag_accesses 107368541 # Number of tag accesses 505system.cpu.l2cache.tags.data_accesses 107368541 # Number of data accesses 506system.cpu.l2cache.ReadReq_hits::cpu.inst 6081037 # number of ReadReq hits 507system.cpu.l2cache.ReadReq_hits::total 6081037 # number of ReadReq hits 508system.cpu.l2cache.Writeback_hits::writebacks 3700895 # number of Writeback hits 509system.cpu.l2cache.Writeback_hits::total 3700895 # number of Writeback hits 510system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090926 # number of ReadExReq hits 511system.cpu.l2cache.ReadExReq_hits::total 1090926 # number of ReadExReq hits 512system.cpu.l2cache.demand_hits::cpu.inst 7171963 # number of demand (read+write) hits 513system.cpu.l2cache.demand_hits::total 7171963 # number of demand (read+write) hits 514system.cpu.l2cache.overall_hits::cpu.inst 7171963 # number of overall hits 515system.cpu.l2cache.overall_hits::total 7171963 # number of overall hits 516system.cpu.l2cache.ReadReq_misses::cpu.inst 1255354 # number of ReadReq misses 517system.cpu.l2cache.ReadReq_misses::total 1255354 # number of ReadReq misses 518system.cpu.l2cache.ReadExReq_misses::cpu.inst 799950 # number of ReadExReq misses 519system.cpu.l2cache.ReadExReq_misses::total 799950 # number of ReadExReq misses 520system.cpu.l2cache.demand_misses::cpu.inst 2055304 # number of demand (read+write) misses 521system.cpu.l2cache.demand_misses::total 2055304 # number of demand (read+write) misses 522system.cpu.l2cache.overall_misses::cpu.inst 2055304 # number of overall misses 523system.cpu.l2cache.overall_misses::total 2055304 # number of overall misses 524system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100122250500 # number of ReadReq miss cycles 525system.cpu.l2cache.ReadReq_miss_latency::total 100122250500 # number of ReadReq miss cycles 526system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64358555750 # number of ReadExReq miss cycles 527system.cpu.l2cache.ReadExReq_miss_latency::total 64358555750 # number of ReadExReq miss cycles 528system.cpu.l2cache.demand_miss_latency::cpu.inst 164480806250 # number of demand (read+write) miss cycles 529system.cpu.l2cache.demand_miss_latency::total 164480806250 # number of demand (read+write) miss cycles 530system.cpu.l2cache.overall_miss_latency::cpu.inst 164480806250 # number of overall miss cycles 531system.cpu.l2cache.overall_miss_latency::total 164480806250 # number of overall miss cycles 532system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336391 # number of ReadReq accesses(hits+misses) 533system.cpu.l2cache.ReadReq_accesses::total 7336391 # number of ReadReq accesses(hits+misses) 534system.cpu.l2cache.Writeback_accesses::writebacks 3700895 # number of Writeback accesses(hits+misses) 535system.cpu.l2cache.Writeback_accesses::total 3700895 # number of Writeback accesses(hits+misses) 536system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890876 # number of ReadExReq accesses(hits+misses) 537system.cpu.l2cache.ReadExReq_accesses::total 1890876 # number of ReadExReq accesses(hits+misses) 538system.cpu.l2cache.demand_accesses::cpu.inst 9227267 # number of demand (read+write) accesses 539system.cpu.l2cache.demand_accesses::total 9227267 # number of demand (read+write) accesses 540system.cpu.l2cache.overall_accesses::cpu.inst 9227267 # number of overall (read+write) accesses 541system.cpu.l2cache.overall_accesses::total 9227267 # number of overall (read+write) accesses 542system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171113 # miss rate for ReadReq accesses 543system.cpu.l2cache.ReadReq_miss_rate::total 0.171113 # miss rate for ReadReq accesses 544system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423058 # miss rate for ReadExReq accesses 545system.cpu.l2cache.ReadExReq_miss_rate::total 0.423058 # miss rate for ReadExReq accesses 546system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses 547system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses 548system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # miss rate for overall accesses 549system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses 550system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79756.188693 # average ReadReq miss latency 551system.cpu.l2cache.ReadReq_avg_miss_latency::total 79756.188693 # average ReadReq miss latency 552system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80453.223014 # average ReadExReq miss latency 553system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80453.223014 # average ReadExReq miss latency 554system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80027.483161 # average overall miss latency 555system.cpu.l2cache.demand_avg_miss_latency::total 80027.483161 # average overall miss latency 556system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80027.483161 # average overall miss latency 557system.cpu.l2cache.overall_avg_miss_latency::total 80027.483161 # average overall miss latency 558system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 559system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 560system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 561system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 562system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 563system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 564system.cpu.l2cache.fast_writes 0 # number of fast writes performed 565system.cpu.l2cache.cache_copies 0 # number of cache copies performed 566system.cpu.l2cache.writebacks::writebacks 1046304 # number of writebacks 567system.cpu.l2cache.writebacks::total 1046304 # number of writebacks 568system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits 569system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 570system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits 571system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 572system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits 573system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 574system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255348 # number of ReadReq MSHR misses 575system.cpu.l2cache.ReadReq_mshr_misses::total 1255348 # number of ReadReq MSHR misses 576system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 799950 # number of ReadExReq MSHR misses 577system.cpu.l2cache.ReadExReq_mshr_misses::total 799950 # number of ReadExReq MSHR misses 578system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055298 # number of demand (read+write) MSHR misses 579system.cpu.l2cache.demand_mshr_misses::total 2055298 # number of demand (read+write) MSHR misses 580system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055298 # number of overall MSHR misses 581system.cpu.l2cache.overall_mshr_misses::total 2055298 # number of overall MSHR misses 582system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84333554000 # number of ReadReq MSHR miss cycles 583system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84333554000 # number of ReadReq MSHR miss cycles 584system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54273221250 # number of ReadExReq MSHR miss cycles 585system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54273221250 # number of ReadExReq MSHR miss cycles 586system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138606775250 # number of demand (read+write) MSHR miss cycles 587system.cpu.l2cache.demand_mshr_miss_latency::total 138606775250 # number of demand (read+write) MSHR miss cycles 588system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138606775250 # number of overall MSHR miss cycles 589system.cpu.l2cache.overall_mshr_miss_latency::total 138606775250 # number of overall MSHR miss cycles 590system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171112 # mshr miss rate for ReadReq accesses 591system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171112 # mshr miss rate for ReadReq accesses 592system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423058 # mshr miss rate for ReadExReq accesses 593system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423058 # mshr miss rate for ReadExReq accesses 594system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for demand accesses 595system.cpu.l2cache.demand_mshr_miss_rate::total 0.222742 # mshr miss rate for demand accesses 596system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for overall accesses 597system.cpu.l2cache.overall_mshr_miss_rate::total 0.222742 # mshr miss rate for overall accesses 598system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67179.422758 # average ReadReq mshr miss latency 599system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67179.422758 # average ReadReq mshr miss latency 600system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67845.766923 # average ReadExReq mshr miss latency 601system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67845.766923 # average ReadExReq mshr miss latency 602system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency 603system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency 604system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency 605system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency 606system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 607system.cpu.dcache.tags.replacements 9222351 # number of replacements 608system.cpu.dcache.tags.tagsinuse 4085.559894 # Cycle average of tags in use 609system.cpu.dcache.tags.total_refs 624001258 # Total number of references to valid blocks. 610system.cpu.dcache.tags.sampled_refs 9226447 # Sample count of references to valid blocks. 611system.cpu.dcache.tags.avg_refs 67.631804 # Average number of references to valid blocks. 612system.cpu.dcache.tags.warmup_cycle 9703664000 # Cycle when the warmup percentage was hit. 613system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.559894 # Average occupied blocks per requestor 614system.cpu.dcache.tags.occ_percent::cpu.inst 0.997451 # Average percentage of cache occupancy 615system.cpu.dcache.tags.occ_percent::total 0.997451 # Average percentage of cache occupancy 616system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 617system.cpu.dcache.tags.age_task_id_blocks_1024::0 283 # Occupied blocks per task id 618system.cpu.dcache.tags.age_task_id_blocks_1024::1 1314 # Occupied blocks per task id 619system.cpu.dcache.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id 620system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id 621system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 622system.cpu.dcache.tags.tag_accesses 1276381727 # Number of tag accesses 623system.cpu.dcache.tags.data_accesses 1276381727 # Number of data accesses 624system.cpu.dcache.ReadReq_hits::cpu.inst 453655688 # number of ReadReq hits 625system.cpu.dcache.ReadReq_hits::total 453655688 # number of ReadReq hits 626system.cpu.dcache.WriteReq_hits::cpu.inst 170345448 # number of WriteReq hits 627system.cpu.dcache.WriteReq_hits::total 170345448 # number of WriteReq hits 628system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits 629system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits 630system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits 631system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits 632system.cpu.dcache.demand_hits::cpu.inst 624001136 # number of demand (read+write) hits 633system.cpu.dcache.demand_hits::total 624001136 # number of demand (read+write) hits 634system.cpu.dcache.overall_hits::cpu.inst 624001136 # number of overall hits 635system.cpu.dcache.overall_hits::total 624001136 # number of overall hits 636system.cpu.dcache.ReadReq_misses::cpu.inst 7335783 # number of ReadReq misses 637system.cpu.dcache.ReadReq_misses::total 7335783 # number of ReadReq misses 638system.cpu.dcache.WriteReq_misses::cpu.inst 2240599 # number of WriteReq misses 639system.cpu.dcache.WriteReq_misses::total 2240599 # number of WriteReq misses 640system.cpu.dcache.demand_misses::cpu.inst 9576382 # number of demand (read+write) misses 641system.cpu.dcache.demand_misses::total 9576382 # number of demand (read+write) misses 642system.cpu.dcache.overall_misses::cpu.inst 9576382 # number of overall misses 643system.cpu.dcache.overall_misses::total 9576382 # number of overall misses 644system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183307188995 # number of ReadReq miss cycles 645system.cpu.dcache.ReadReq_miss_latency::total 183307188995 # number of ReadReq miss cycles 646system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101248592250 # number of WriteReq miss cycles 647system.cpu.dcache.WriteReq_miss_latency::total 101248592250 # number of WriteReq miss cycles 648system.cpu.dcache.demand_miss_latency::cpu.inst 284555781245 # number of demand (read+write) miss cycles 649system.cpu.dcache.demand_miss_latency::total 284555781245 # number of demand (read+write) miss cycles 650system.cpu.dcache.overall_miss_latency::cpu.inst 284555781245 # number of overall miss cycles 651system.cpu.dcache.overall_miss_latency::total 284555781245 # number of overall miss cycles 652system.cpu.dcache.ReadReq_accesses::cpu.inst 460991471 # number of ReadReq accesses(hits+misses) 653system.cpu.dcache.ReadReq_accesses::total 460991471 # number of ReadReq accesses(hits+misses) 654system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses) 655system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses) 656system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses) 657system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses) 658system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses) 659system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses) 660system.cpu.dcache.demand_accesses::cpu.inst 633577518 # number of demand (read+write) accesses 661system.cpu.dcache.demand_accesses::total 633577518 # number of demand (read+write) accesses 662system.cpu.dcache.overall_accesses::cpu.inst 633577518 # number of overall (read+write) accesses 663system.cpu.dcache.overall_accesses::total 633577518 # number of overall (read+write) accesses 664system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses 665system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses 666system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012983 # miss rate for WriteReq accesses 667system.cpu.dcache.WriteReq_miss_rate::total 0.012983 # miss rate for WriteReq accesses 668system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses 669system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses 670system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses 671system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses 672system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24988.087706 # average ReadReq miss latency 673system.cpu.dcache.ReadReq_avg_miss_latency::total 24988.087706 # average ReadReq miss latency 674system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45188.180594 # average WriteReq miss latency 675system.cpu.dcache.WriteReq_avg_miss_latency::total 45188.180594 # average WriteReq miss latency 676system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency 677system.cpu.dcache.demand_avg_miss_latency::total 29714.330657 # average overall miss latency 678system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency 679system.cpu.dcache.overall_avg_miss_latency::total 29714.330657 # average overall miss latency 680system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 681system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 682system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 683system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 684system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 685system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 686system.cpu.dcache.fast_writes 0 # number of fast writes performed 687system.cpu.dcache.cache_copies 0 # number of cache copies performed 688system.cpu.dcache.writebacks::writebacks 3700895 # number of writebacks 689system.cpu.dcache.writebacks::total 3700895 # number of writebacks 690system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 212 # number of ReadReq MSHR hits 691system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits 692system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349723 # number of WriteReq MSHR hits 693system.cpu.dcache.WriteReq_mshr_hits::total 349723 # number of WriteReq MSHR hits 694system.cpu.dcache.demand_mshr_hits::cpu.inst 349935 # number of demand (read+write) MSHR hits 695system.cpu.dcache.demand_mshr_hits::total 349935 # number of demand (read+write) MSHR hits 696system.cpu.dcache.overall_mshr_hits::cpu.inst 349935 # number of overall MSHR hits 697system.cpu.dcache.overall_mshr_hits::total 349935 # number of overall MSHR hits 698system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335571 # number of ReadReq MSHR misses 699system.cpu.dcache.ReadReq_mshr_misses::total 7335571 # number of ReadReq MSHR misses 700system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890876 # number of WriteReq MSHR misses 701system.cpu.dcache.WriteReq_mshr_misses::total 1890876 # number of WriteReq MSHR misses 702system.cpu.dcache.demand_mshr_misses::cpu.inst 9226447 # number of demand (read+write) MSHR misses 703system.cpu.dcache.demand_mshr_misses::total 9226447 # number of demand (read+write) MSHR misses 704system.cpu.dcache.overall_mshr_misses::cpu.inst 9226447 # number of overall MSHR misses 705system.cpu.dcache.overall_mshr_misses::total 9226447 # number of overall MSHR misses 706system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168217924005 # number of ReadReq MSHR miss cycles 707system.cpu.dcache.ReadReq_mshr_miss_latency::total 168217924005 # number of ReadReq MSHR miss cycles 708system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77187221250 # number of WriteReq MSHR miss cycles 709system.cpu.dcache.WriteReq_mshr_miss_latency::total 77187221250 # number of WriteReq MSHR miss cycles 710system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245405145255 # number of demand (read+write) MSHR miss cycles 711system.cpu.dcache.demand_mshr_miss_latency::total 245405145255 # number of demand (read+write) MSHR miss cycles 712system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245405145255 # number of overall MSHR miss cycles 713system.cpu.dcache.overall_mshr_miss_latency::total 245405145255 # number of overall MSHR miss cycles 714system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses 715system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses 716system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses 717system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses 718system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for demand accesses 719system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses 720system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for overall accesses 721system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses 722system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22931.810490 # average ReadReq mshr miss latency 723system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22931.810490 # average ReadReq mshr miss latency 724system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40820.879450 # average WriteReq mshr miss latency 725system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40820.879450 # average WriteReq mshr miss latency 726system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency 727system.cpu.dcache.demand_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency 728system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency 729system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency 730system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 732 733---------- End Simulation Statistics ---------- | 731 732---------- End Simulation Statistics ---------- |