3,5c3,5
< sim_seconds 1.150226 # Number of seconds simulated
< sim_ticks 1150225722500 # Number of ticks simulated
< final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.150228 # Number of seconds simulated
> sim_ticks 1150227786500 # Number of ticks simulated
> final_tick 1150227786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 386915 # Simulator instruction rate (inst/s)
< host_op_rate 416843 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 288133243 # Simulator tick rate (ticks/s)
< host_mem_usage 273608 # Number of bytes of host memory used
< host_seconds 3991.99 # Real time elapsed on the host
---
> host_inst_rate 394229 # Simulator instruction rate (inst/s)
> host_op_rate 424722 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 293579950 # Simulator tick rate (ticks/s)
> host_mem_usage 273524 # Number of bytes of host memory used
> host_seconds 3917.94 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
30,31c30,31
< system.physmem.bw_read::cpu.data 114842544 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 114886222 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 114842338 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 114886016 # Total read bandwidth from this memory (bytes/s)
34,36c34,36
< system.physmem.bw_write::writebacks 58988408 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 58988408 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 58988408 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 58988302 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 58988302 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 58988302 # Total bandwidth to/from this memory (bytes/s)
38,39c38,39
< system.physmem.bw_total::cpu.data 114842544 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 173874630 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 114842338 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 173874318 # Total bandwidth to/from this memory (bytes/s)
64c64
< system.physmem.perBankRdBursts::12 134524 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 134523 # Per bank write bursts
67c67
< system.physmem.perBankRdBursts::15 130646 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 130647 # Per bank write bursts
86c86
< system.physmem.totGap 1150225621500 # Total gap between requests
---
> system.physmem.totGap 1150227685500 # Total gap between requests
101,102c101,102
< system.physmem.rdQLenPdf::0 1919491 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 143962 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 1919511 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 143942 # What read queue length does an incoming req see
148,158c148,158
< system.physmem.wrQLenPdf::15 31061 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 32150 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 57332 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 62506 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 62721 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 62815 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 62684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 62639 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 62591 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 62502 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 62571 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 31051 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 32142 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 57333 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 62501 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 62728 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 62816 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 62688 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 62636 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 62501 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 62570 # What write queue length does an incoming req see
160c160
< system.physmem.wrQLenPdf::27 62657 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::27 62659 # What write queue length does an incoming req see
162,165c162,165
< system.physmem.wrQLenPdf::29 62805 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 63052 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 62414 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 62339 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::29 62806 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 63061 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 62416 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 62338 # What write queue length does an incoming req see
197,215c197,215
< system.physmem.bytesPerActivate::samples 1927680 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 103.704050 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 81.827428 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 125.877785 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 1497957 77.71% 77.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 310202 16.09% 93.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 52219 2.71% 96.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 20801 1.08% 97.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 13076 0.68% 98.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 7806 0.40% 98.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 5210 0.27% 98.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5119 0.27% 99.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 15290 0.79% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1927680 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 62182 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 33.137773 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 23.854622 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 150.738788 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 62143 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 1927678 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 103.704158 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 81.827351 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 125.878363 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 1497959 77.71% 77.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 310183 16.09% 93.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 52221 2.71% 96.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 20819 1.08% 97.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 7800 0.40% 98.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5214 0.27% 98.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5117 0.27% 99.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 15291 0.79% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1927678 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 62183 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 33.137240 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 23.854238 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 150.737609 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 62144 99.94% 99.94% # Reads before turning the bus around for writes
225,233c225,233
< system.physmem.rdPerTurnAround::total 62182 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 62182 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.048808 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.017651 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.031288 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 29885 48.06% 48.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 1078 1.73% 49.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 29552 47.53% 97.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 1636 2.63% 99.95% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 62183 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 62183 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.048534 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.017369 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.031425 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 29894 48.07% 48.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 1086 1.75% 49.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 29528 47.49% 97.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 1644 2.64% 99.95% # Writes before turning the bus around for reads
236,238c236,238
< system.physmem.wrPerTurnAround::total 62182 # Writes before turning the bus around for reads
< system.physmem.totQLat 59945214750 # Total ticks spent queuing
< system.physmem.totMemAccLat 98635221000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.wrPerTurnAround::total 62183 # Writes before turning the bus around for reads
> system.physmem.totQLat 59946131250 # Total ticks spent queuing
> system.physmem.totMemAccLat 98636137500 # Total ticks spent from burst creation until serviced by the DRAM
240c240
< system.physmem.avgQLat 29050.73 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 29051.17 # Average queueing delay per DRAM burst
242c242
< system.physmem.avgMemAccLat 47800.73 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 47801.17 # Average memory access latency per DRAM burst
253,254c253,254
< system.physmem.readRowHits 775403 # Number of row buffer hits during reads
< system.physmem.writeRowHits 420503 # Number of row buffer hits during writes
---
> system.physmem.readRowHits 775435 # Number of row buffer hits during reads
> system.physmem.writeRowHits 420473 # Number of row buffer hits during writes
257c257
< system.physmem.avgGap 368081.27 # Average gap between requests
---
> system.physmem.avgGap 368081.93 # Average gap between requests
259,260c259,260
< system.physmem_0.actEnergy 6704024460 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 3563246940 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.actEnergy 6703938780 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 3563201400 # Energy for precharge commands per rank (pJ)
263,279c263,279
< system.physmem_0.refreshEnergy 71584047600.000015 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 47598370410 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 2598119520 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 242886973860 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 71929585440 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 82360762695 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 539073775965 # Total energy per rank (pJ)
< system.physmem_0.averagePower 468.667814 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 1039023905500 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 3501879500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 30346756000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 319059811750 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 187317352250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 77352878250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 532647044750 # Time in different power states
< system.physmem_1.actEnergy 7059682140 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3752298660 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.refreshEnergy 71587735440.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 47610368340 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 2598027360 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 242891748180 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 71936235360 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 82347779655 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 539087705175 # Total energy per rank (pJ)
> system.physmem_0.averagePower 468.679083 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 1039000185750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 3501543500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 30348316000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 319007908000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 187335147250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 77377438000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 532657433750 # Time in different power states
> system.physmem_1.actEnergy 7059753540 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3752336610 # Energy for precharge commands per rank (pJ)
282,299c282,299
< system.physmem_1.refreshEnergy 71064062160.000015 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 47576528010 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 2430223200 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 248601681570 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 68458810560 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 80907988260 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 540316908180 # Total energy per rank (pJ)
< system.physmem_1.averagePower 469.748583 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 1039511813000 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 3059644000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 30118792000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 316054273750 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 178278810500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 77535412750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 545178789500 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 240019882 # Number of BP lookups
< system.cpu.branchPred.condPredicted 186610383 # Number of conditional branches predicted
---
> system.physmem_1.refreshEnergy 71062832880.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 47583848520 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 2430369600 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 248599905450 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 68453747040 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 80907358950 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 540315522360 # Total energy per rank (pJ)
> system.physmem_1.averagePower 469.746535 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 1039499383250 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 3059154750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 30118266000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 316057409750 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 178263690250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 77550921750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 545178344000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 240019900 # Number of BP lookups
> system.cpu.branchPred.condPredicted 186610401 # Number of conditional branches predicted
301,302c301,302
< system.cpu.branchPred.BTBLookups 131646647 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 122324605 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 131646658 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 122324616 # Number of BTB hits
304c304
< system.cpu.branchPred.BTBHitPct 92.918891 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 92.918892 # BTB Hit Percentage
312c312
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
342c342
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
372c372
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
402c402
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
433,434c433,434
< system.cpu.pwrStateResidencyTicks::ON 1150225722500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 2300451445 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 1150227786500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 2300455573 # number of cpu cycles simulated
439c439
< system.cpu.discardedOps 41363683 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 41363694 # Number of ops (including micro ops) which were discarded before commit
441,442c441,442
< system.cpu.cpi 1.489387 # CPI: cycles per instruction
< system.cpu.ipc 0.671417 # IPC: instructions per cycle
---
> system.cpu.cpi 1.489389 # CPI: cycles per instruction
> system.cpu.ipc 0.671416 # IPC: instructions per cycle
482,484c482,484
< system.cpu.tickCycles 1845014986 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 455436459 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 1845015660 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 455439913 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
486,487c486,487
< system.cpu.dcache.tags.tagsinuse 4085.805290 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 624493165 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4085.805308 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 624493167 # Total number of references to valid blocks.
491c491
< system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805290 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805308 # Average occupied blocks per requestor
500,506c500,506
< system.cpu.dcache.tags.tag_accesses 1277391151 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1277391151 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 454163885 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 454163885 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 170329157 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 170329157 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 1277391153 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1277391153 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 454163886 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 454163886 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 170329158 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 170329158 # number of WriteReq hits
513,516c513,516
< system.cpu.dcache.demand_hits::cpu.data 624493042 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 624493042 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 624493043 # number of overall hits
< system.cpu.dcache.overall_hits::total 624493043 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 624493044 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 624493044 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 624493045 # number of overall hits
> system.cpu.dcache.overall_hits::total 624493045 # number of overall hits
519,520c519,520
< system.cpu.dcache.WriteReq_misses::cpu.data 2256890 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2256890 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 2256889 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2256889 # number of WriteReq misses
523,536c523,536
< system.cpu.dcache.demand_misses::cpu.data 9590307 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9590307 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9590309 # number of overall misses
< system.cpu.dcache.overall_misses::total 9590309 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 208195707500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 119902321500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 328098029000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 328098029000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 328098029000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 328098029000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 461497302 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 461497302 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 9590306 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9590306 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9590308 # number of overall misses
> system.cpu.dcache.overall_misses::total 9590308 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 208196327000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 119903341000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 328099668000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 328099668000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 328099668000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 328099668000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 461497303 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 461497303 # number of ReadReq accesses(hits+misses)
545,548c545,548
< system.cpu.dcache.demand_accesses::cpu.data 634083349 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 634083349 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 634083352 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 634083352 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 634083350 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 634083350 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 634083353 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 634083353 # number of overall (read+write) accesses
559,566c559,566
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 34211.420865 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 34211.413730 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 34211.595334 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 34211.588199 # average overall miss latency
577,582c577,582
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366056 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 366056 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 366105 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 366105 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 366105 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 366105 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366055 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 366055 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 366104 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 366104 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 366104 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 366104 # number of overall MSHR hits
593,596c593,596
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92466638500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 92466638500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92467008500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 92467008500 # number of WriteReq MSHR miss cycles
599,602c599,602
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 293324557500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 293324638500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 293325546500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 293325627500 # number of overall MSHR miss cycles
613,616c613,616
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807 # average WriteReq mshr miss latency
619,623c619,623
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
625,626c625,626
< system.cpu.icache.tags.tagsinuse 660.478132 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 466274661 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 660.477823 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 466274758 # Total number of references to valid blocks.
628c628
< system.cpu.icache.tags.avg_refs 567244.113139 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 567244.231144 # Average number of references to valid blocks.
630c630
< system.cpu.icache.tags.occ_blocks::cpu.inst 660.478132 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 660.477823 # Average occupied blocks per requestor
638,646c638,646
< system.cpu.icache.tags.tag_accesses 932551788 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 932551788 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 466274661 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 466274661 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 466274661 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 466274661 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 466274661 # number of overall hits
< system.cpu.icache.overall_hits::total 466274661 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 932551982 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 932551982 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 466274758 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 466274758 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 466274758 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 466274758 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 466274758 # number of overall hits
> system.cpu.icache.overall_hits::total 466274758 # number of overall hits
659,664c659,664
< system.cpu.icache.ReadReq_accesses::cpu.inst 466275483 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 466275483 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 466275483 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 466275483 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 466275483 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 466275483 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 466275580 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 466275580 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 466275580 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 466275580 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 466275580 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 466275580 # number of overall (read+write) accesses
709c709
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
711c711
< system.cpu.l2cache.tags.tagsinuse 31895.835750 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 31895.837315 # Cycle average of tags in use
716,718c716,718
< system.cpu.l2cache.tags.occ_blocks::writebacks 10.372188 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535695 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.927867 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 10.372175 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535649 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.929491 # Average occupied blocks per requestor
732c732
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
761,762c761,762
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282559500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 78282559500 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282928500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 78282928500 # number of ReadExReq miss cycles
765,766c765,766
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125996723500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 125996723500 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125997338000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 125997338000 # number of ReadSharedReq miss cycles
768,769c768,769
< system.cpu.l2cache.demand_miss_latency::cpu.data 204279283000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 204351611000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 204280266500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 204352594500 # number of demand (read+write) miss cycles
771,772c771,772
< system.cpu.l2cache.overall_miss_latency::cpu.data 204279283000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 204351611000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 204280266500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 204352594500 # number of overall miss cycles
801,802c801,802
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96369.213355 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96369.213355 # average ReadExReq miss latency
805,806c805,806
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.786237 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.786237 # average ReadSharedReq miss latency
808,809c808,809
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 98970.973807 # average overall miss latency
811,812c811,812
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 98970.973807 # average overall miss latency
841,842c841,842
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159329500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159329500 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159698500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159698500 # number of ReadExReq MSHR miss cycles
845,846c845,846
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113480200500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113480200500 # number of ReadSharedReq MSHR miss cycles
848,849c848,849
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183639899000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 183704377000 # number of demand (read+write) MSHR miss cycles
851,852c851,852
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183639899000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 183704377000 # number of overall MSHR miss cycles
867,868c867,868
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355 # average ReadExReq mshr miss latency
871,872c871,872
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363 # average ReadSharedReq mshr miss latency
874,875c874,875
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency
877,878c877,878
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency
885c885
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
925c925
< system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
948c948
< system.membus.reqLayer0.occupancy 8804910500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 8804919500 # Layer occupancy (ticks)
950c950
< system.membus.respLayer1.occupancy 11285155750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 11285149250 # Layer occupancy (ticks)
< sim_seconds 1.150226 # Number of seconds simulated
< sim_ticks 1150225722500 # Number of ticks simulated
< final_tick 1150225722500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.150228 # Number of seconds simulated
> sim_ticks 1150227786500 # Number of ticks simulated
> final_tick 1150227786500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 386915 # Simulator instruction rate (inst/s)
< host_op_rate 416843 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 288133243 # Simulator tick rate (ticks/s)
< host_mem_usage 273608 # Number of bytes of host memory used
< host_seconds 3991.99 # Real time elapsed on the host
---
> host_inst_rate 394229 # Simulator instruction rate (inst/s)
> host_op_rate 424722 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 293579950 # Simulator tick rate (ticks/s)
> host_mem_usage 273524 # Number of bytes of host memory used
> host_seconds 3917.94 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
30,31c30,31
< system.physmem.bw_read::cpu.data 114842544 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 114886222 # Total read bandwidth from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.data 114842338 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 114886016 # Total read bandwidth from this memory (bytes/s)
34,36c34,36
< system.physmem.bw_write::writebacks 58988408 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 58988408 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 58988408 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_write::writebacks 58988302 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 58988302 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 58988302 # Total bandwidth to/from this memory (bytes/s)
38,39c38,39
< system.physmem.bw_total::cpu.data 114842544 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 173874630 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_total::cpu.data 114842338 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 173874318 # Total bandwidth to/from this memory (bytes/s)
64c64
< system.physmem.perBankRdBursts::12 134524 # Per bank write bursts
---
> system.physmem.perBankRdBursts::12 134523 # Per bank write bursts
67c67
< system.physmem.perBankRdBursts::15 130646 # Per bank write bursts
---
> system.physmem.perBankRdBursts::15 130647 # Per bank write bursts
86c86
< system.physmem.totGap 1150225621500 # Total gap between requests
---
> system.physmem.totGap 1150227685500 # Total gap between requests
101,102c101,102
< system.physmem.rdQLenPdf::0 1919491 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 143962 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 1919511 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 143942 # What read queue length does an incoming req see
148,158c148,158
< system.physmem.wrQLenPdf::15 31061 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 32150 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 57332 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 62506 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 62721 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 62815 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 62684 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 62639 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 62591 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 62502 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 62571 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 31051 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 32142 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 57333 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 62501 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 62728 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 62816 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 62688 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 62636 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 62593 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 62501 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 62570 # What write queue length does an incoming req see
160c160
< system.physmem.wrQLenPdf::27 62657 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::27 62659 # What write queue length does an incoming req see
162,165c162,165
< system.physmem.wrQLenPdf::29 62805 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 63052 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 62414 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 62339 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::29 62806 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 63061 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 62416 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 62338 # What write queue length does an incoming req see
197,215c197,215
< system.physmem.bytesPerActivate::samples 1927680 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 103.704050 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 81.827428 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 125.877785 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 1497957 77.71% 77.71% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 310202 16.09% 93.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 52219 2.71% 96.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 20801 1.08% 97.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 13076 0.68% 98.27% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 7806 0.40% 98.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 5210 0.27% 98.94% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5119 0.27% 99.21% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 15290 0.79% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1927680 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 62182 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 33.137773 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::gmean 23.854622 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 150.738788 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 62143 99.94% 99.94% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 1927678 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 103.704158 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 81.827351 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 125.878363 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 1497959 77.71% 77.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 310183 16.09% 93.80% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 52221 2.71% 96.51% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 20819 1.08% 97.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 13074 0.68% 98.27% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 7800 0.40% 98.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5214 0.27% 98.94% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5117 0.27% 99.21% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 15291 0.79% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1927678 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 62183 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 33.137240 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::gmean 23.854238 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 150.737609 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 62144 99.94% 99.94% # Reads before turning the bus around for writes
225,233c225,233
< system.physmem.rdPerTurnAround::total 62182 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 62182 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.048808 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.017651 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.031288 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 29885 48.06% 48.06% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 1078 1.73% 49.79% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 29552 47.53% 97.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 1636 2.63% 99.95% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 62183 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 62183 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.048534 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.017369 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.031425 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 29894 48.07% 48.07% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 1086 1.75% 49.82% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 29528 47.49% 97.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 1644 2.64% 99.95% # Writes before turning the bus around for reads
236,238c236,238
< system.physmem.wrPerTurnAround::total 62182 # Writes before turning the bus around for reads
< system.physmem.totQLat 59945214750 # Total ticks spent queuing
< system.physmem.totMemAccLat 98635221000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.wrPerTurnAround::total 62183 # Writes before turning the bus around for reads
> system.physmem.totQLat 59946131250 # Total ticks spent queuing
> system.physmem.totMemAccLat 98636137500 # Total ticks spent from burst creation until serviced by the DRAM
240c240
< system.physmem.avgQLat 29050.73 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 29051.17 # Average queueing delay per DRAM burst
242c242
< system.physmem.avgMemAccLat 47800.73 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 47801.17 # Average memory access latency per DRAM burst
253,254c253,254
< system.physmem.readRowHits 775403 # Number of row buffer hits during reads
< system.physmem.writeRowHits 420503 # Number of row buffer hits during writes
---
> system.physmem.readRowHits 775435 # Number of row buffer hits during reads
> system.physmem.writeRowHits 420473 # Number of row buffer hits during writes
257c257
< system.physmem.avgGap 368081.27 # Average gap between requests
---
> system.physmem.avgGap 368081.93 # Average gap between requests
259,260c259,260
< system.physmem_0.actEnergy 6704024460 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 3563246940 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.actEnergy 6703938780 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 3563201400 # Energy for precharge commands per rank (pJ)
263,279c263,279
< system.physmem_0.refreshEnergy 71584047600.000015 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 47598370410 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 2598119520 # Energy for precharge background per rank (pJ)
< system.physmem_0.actPowerDownEnergy 242886973860 # Energy for active power-down per rank (pJ)
< system.physmem_0.prePowerDownEnergy 71929585440 # Energy for precharge power-down per rank (pJ)
< system.physmem_0.selfRefreshEnergy 82360762695 # Energy for self refresh per rank (pJ)
< system.physmem_0.totalEnergy 539073775965 # Total energy per rank (pJ)
< system.physmem_0.averagePower 468.667814 # Core power per rank (mW)
< system.physmem_0.totalIdleTime 1039023905500 # Total Idle time Per DRAM Rank
< system.physmem_0.memoryStateTime::IDLE 3501879500 # Time in different power states
< system.physmem_0.memoryStateTime::REF 30346756000 # Time in different power states
< system.physmem_0.memoryStateTime::SREF 319059811750 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 187317352250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 77352878250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 532647044750 # Time in different power states
< system.physmem_1.actEnergy 7059682140 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 3752298660 # Energy for precharge commands per rank (pJ)
---
> system.physmem_0.refreshEnergy 71587735440.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 47610368340 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 2598027360 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 242891748180 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 71936235360 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 82347779655 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 539087705175 # Total energy per rank (pJ)
> system.physmem_0.averagePower 468.679083 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 1039000185750 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 3501543500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 30348316000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 319007908000 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 187335147250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 77377438000 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 532657433750 # Time in different power states
> system.physmem_1.actEnergy 7059753540 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 3752336610 # Energy for precharge commands per rank (pJ)
282,299c282,299
< system.physmem_1.refreshEnergy 71064062160.000015 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 47576528010 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 2430223200 # Energy for precharge background per rank (pJ)
< system.physmem_1.actPowerDownEnergy 248601681570 # Energy for active power-down per rank (pJ)
< system.physmem_1.prePowerDownEnergy 68458810560 # Energy for precharge power-down per rank (pJ)
< system.physmem_1.selfRefreshEnergy 80907988260 # Energy for self refresh per rank (pJ)
< system.physmem_1.totalEnergy 540316908180 # Total energy per rank (pJ)
< system.physmem_1.averagePower 469.748583 # Core power per rank (mW)
< system.physmem_1.totalIdleTime 1039511813000 # Total Idle time Per DRAM Rank
< system.physmem_1.memoryStateTime::IDLE 3059644000 # Time in different power states
< system.physmem_1.memoryStateTime::REF 30118792000 # Time in different power states
< system.physmem_1.memoryStateTime::SREF 316054273750 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 178278810500 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 77535412750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 545178789500 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 240019882 # Number of BP lookups
< system.cpu.branchPred.condPredicted 186610383 # Number of conditional branches predicted
---
> system.physmem_1.refreshEnergy 71062832880.000015 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 47583848520 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 2430369600 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 248599905450 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 68453747040 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 80907358950 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 540315522360 # Total energy per rank (pJ)
> system.physmem_1.averagePower 469.746535 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 1039499383250 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 3059154750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 30118266000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 316057409750 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 178263690250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 77550921750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 545178344000 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 240019900 # Number of BP lookups
> system.cpu.branchPred.condPredicted 186610401 # Number of conditional branches predicted
301,302c301,302
< system.cpu.branchPred.BTBLookups 131646647 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 122324605 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 131646658 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 122324616 # Number of BTB hits
304c304
< system.cpu.branchPred.BTBHitPct 92.918891 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 92.918892 # BTB Hit Percentage
312c312
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
342c342
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
372c372
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
402c402
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
433,434c433,434
< system.cpu.pwrStateResidencyTicks::ON 1150225722500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 2300451445 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 1150227786500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 2300455573 # number of cpu cycles simulated
439c439
< system.cpu.discardedOps 41363683 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 41363694 # Number of ops (including micro ops) which were discarded before commit
441,442c441,442
< system.cpu.cpi 1.489387 # CPI: cycles per instruction
< system.cpu.ipc 0.671417 # IPC: instructions per cycle
---
> system.cpu.cpi 1.489389 # CPI: cycles per instruction
> system.cpu.ipc 0.671416 # IPC: instructions per cycle
482,484c482,484
< system.cpu.tickCycles 1845014986 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 455436459 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.tickCycles 1845015660 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 455439913 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
486,487c486,487
< system.cpu.dcache.tags.tagsinuse 4085.805290 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 624493165 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4085.805308 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 624493167 # Total number of references to valid blocks.
491c491
< system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805290 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4085.805308 # Average occupied blocks per requestor
500,506c500,506
< system.cpu.dcache.tags.tag_accesses 1277391151 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1277391151 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 454163885 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 454163885 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 170329157 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 170329157 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 1277391153 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1277391153 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 454163886 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 454163886 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 170329158 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 170329158 # number of WriteReq hits
513,516c513,516
< system.cpu.dcache.demand_hits::cpu.data 624493042 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 624493042 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 624493043 # number of overall hits
< system.cpu.dcache.overall_hits::total 624493043 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 624493044 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 624493044 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 624493045 # number of overall hits
> system.cpu.dcache.overall_hits::total 624493045 # number of overall hits
519,520c519,520
< system.cpu.dcache.WriteReq_misses::cpu.data 2256890 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2256890 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 2256889 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2256889 # number of WriteReq misses
523,536c523,536
< system.cpu.dcache.demand_misses::cpu.data 9590307 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9590307 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9590309 # number of overall misses
< system.cpu.dcache.overall_misses::total 9590309 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 208195707500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 208195707500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 119902321500 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 119902321500 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 328098029000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 328098029000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 328098029000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 328098029000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 461497302 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 461497302 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 9590306 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9590306 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9590308 # number of overall misses
> system.cpu.dcache.overall_misses::total 9590308 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 208196327000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 208196327000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 119903341000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 119903341000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 328099668000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 328099668000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 328099668000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 328099668000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 461497303 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 461497303 # number of ReadReq accesses(hits+misses)
545,548c545,548
< system.cpu.dcache.demand_accesses::cpu.data 634083349 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 634083349 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 634083352 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 634083352 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 634083350 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 634083350 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 634083353 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 634083353 # number of overall (read+write) accesses
559,566c559,566
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28389.999846 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 28389.999846 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.233272 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.233272 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.420865 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 34211.420865 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.413730 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 34211.413730 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28390.084322 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 28390.084322 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53127.708540 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 53127.708540 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 34211.595334 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 34211.595334 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 34211.588199 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 34211.588199 # average overall miss latency
577,582c577,582
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366056 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 366056 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 366105 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 366105 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 366105 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 366105 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 366055 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 366055 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 366104 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 366104 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 366104 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 366104 # number of overall MSHR hits
593,596c593,596
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200857919000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 200857919000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92466638500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 92466638500 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 200858538000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 200858538000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 92467008500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 92467008500 # number of WriteReq MSHR miss cycles
599,602c599,602
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293324557500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 293324557500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293324638500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 293324638500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 293325546500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 293325546500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 293325627500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 293325627500 # number of overall MSHR miss cycles
613,616c613,616
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.586749 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.586749 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.568126 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.568126 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 27389.671158 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 27389.671158 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48902.763807 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48902.763807 # average WriteReq mshr miss latency
619,623c619,623
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.450782 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.450782 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.456116 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.456116 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31799.558000 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 31799.558000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31799.563334 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 31799.563334 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
625,626c625,626
< system.cpu.icache.tags.tagsinuse 660.478132 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 466274661 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 660.477823 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 466274758 # Total number of references to valid blocks.
628c628
< system.cpu.icache.tags.avg_refs 567244.113139 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 567244.231144 # Average number of references to valid blocks.
630c630
< system.cpu.icache.tags.occ_blocks::cpu.inst 660.478132 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 660.477823 # Average occupied blocks per requestor
638,646c638,646
< system.cpu.icache.tags.tag_accesses 932551788 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 932551788 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 466274661 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 466274661 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 466274661 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 466274661 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 466274661 # number of overall hits
< system.cpu.icache.overall_hits::total 466274661 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 932551982 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 932551982 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 466274758 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 466274758 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 466274758 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 466274758 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 466274758 # number of overall hits
> system.cpu.icache.overall_hits::total 466274758 # number of overall hits
659,664c659,664
< system.cpu.icache.ReadReq_accesses::cpu.inst 466275483 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 466275483 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 466275483 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 466275483 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 466275483 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 466275483 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 466275580 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 466275580 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 466275580 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 466275580 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 466275580 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 466275580 # number of overall (read+write) accesses
709c709
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
711c711
< system.cpu.l2cache.tags.tagsinuse 31895.835750 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 31895.837315 # Cycle average of tags in use
716,718c716,718
< system.cpu.l2cache.tags.occ_blocks::writebacks 10.372188 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535695 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.927867 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 10.372175 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 25.535649 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 31859.929491 # Average occupied blocks per requestor
732c732
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
761,762c761,762
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282559500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 78282559500 # number of ReadExReq miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 78282928500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 78282928500 # number of ReadExReq miss cycles
765,766c765,766
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125996723500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 125996723500 # number of ReadSharedReq miss cycles
---
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 125997338000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 125997338000 # number of ReadSharedReq miss cycles
768,769c768,769
< system.cpu.l2cache.demand_miss_latency::cpu.data 204279283000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 204351611000 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.data 204280266500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 204352594500 # number of demand (read+write) miss cycles
771,772c771,772
< system.cpu.l2cache.overall_miss_latency::cpu.data 204279283000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 204351611000 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::cpu.data 204280266500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 204352594500 # number of overall miss cycles
801,802c801,802
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96368.759102 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96368.759102 # average ReadExReq miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96369.213355 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96369.213355 # average ReadExReq miss latency
805,806c805,806
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.295291 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.295291 # average ReadSharedReq miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 100663.786237 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 100663.786237 # average ReadSharedReq miss latency
808,809c808,809
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 98970.497483 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 98970.973807 # average overall miss latency
811,812c811,812
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.096258 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 98970.497483 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 98973.572763 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 98970.973807 # average overall miss latency
841,842c841,842
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159329500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159329500 # number of ReadExReq MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 70159698500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 70159698500 # number of ReadExReq MSHR miss cycles
845,846c845,846
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113479586000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113479586000 # number of ReadSharedReq MSHR miss cycles
---
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 113480200500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 113480200500 # number of ReadSharedReq MSHR miss cycles
848,849c848,849
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183638915500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 183703393500 # number of demand (read+write) MSHR miss cycles
---
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 183639899000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 183704377000 # number of demand (read+write) MSHR miss cycles
851,852c851,852
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183638915500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 183703393500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 183639899000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 183704377000 # number of overall MSHR miss cycles
867,868c867,868
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86368.759102 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86368.759102 # average ReadExReq mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86369.213355 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86369.213355 # average ReadExReq mshr miss latency
871,872c871,872
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.340415 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.340415 # average ReadSharedReq mshr miss latency
---
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 90663.831363 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 90663.831363 # average ReadSharedReq mshr miss latency
874,875c874,875
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency
---
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency
877,878c877,878
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.118709 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.519918 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 88973.595215 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 88970.996243 # average overall mshr miss latency
885c885
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
925c925
< system.membus.pwrStateResidencyTicks::UNDEFINED 1150225722500 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 1150227786500 # Cumulative time (in ticks) in various power states
948c948
< system.membus.reqLayer0.occupancy 8804910500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 8804919500 # Layer occupancy (ticks)
950c950
< system.membus.respLayer1.occupancy 11285155750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 11285149250 # Layer occupancy (ticks)