Cross Reference: /gem5/tests/long/se/60.bzip2/ref/arm/linux/minor-timing/stats.txt

Deleted Added

sdiff udiff text old ( 11103:38f6188421e0 ) new ( 11138:a611a23c8cc2 )

full compact

3,5c3,5
< sim_seconds 1.116876 # Number of seconds simulated
< sim_ticks 1116876142500 # Number of ticks simulated
< final_tick 1116876142500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.116866 # Number of seconds simulated
> sim_ticks 1116865669500 # Number of ticks simulated
> final_tick 1116865669500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 161785 # Simulator instruction rate (inst/s)
< host_op_rate 174299 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 116987267 # Simulator tick rate (ticks/s)
< host_mem_usage 309392 # Number of bytes of host memory used
< host_seconds 9546.99 # Real time elapsed on the host
---
> host_inst_rate 226280 # Simulator instruction rate (inst/s)
> host_op_rate 243783 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 163622006 # Simulator tick rate (ticks/s)
> host_mem_usage 317884 # Number of bytes of host memory used
> host_seconds 6825.89 # Real time elapsed on the host
17,18c17,18
< system.physmem.bytes_read::cpu.data 130931520 # Number of bytes read from this memory
< system.physmem.bytes_read::total 130981888 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.data 130931456 # Number of bytes read from this memory
> system.physmem.bytes_read::total 130981824 # Number of bytes read from this memory
21,22c21,22
< system.physmem.bytes_written::writebacks 67207936 # Number of bytes written to this memory
< system.physmem.bytes_written::total 67207936 # Number of bytes written to this memory
---
> system.physmem.bytes_written::writebacks 67207872 # Number of bytes written to this memory
> system.physmem.bytes_written::total 67207872 # Number of bytes written to this memory
24,48c24,48
< system.physmem.num_reads::cpu.data 2045805 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 2046592 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1050124 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1050124 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 45097 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 117230116 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 117275213 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 45097 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 45097 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 60174923 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 60174923 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 60174923 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 45097 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 117230116 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 177450137 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 2046592 # Number of read requests accepted
< system.physmem.writeReqs 1050124 # Number of write requests accepted
< system.physmem.readBursts 2046592 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1050124 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 130897216 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 84672 # Total number of bytes read from write queue
< system.physmem.bytesWritten 67206464 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 130981888 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 67207936 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 1323 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.num_reads::cpu.data 2045804 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 2046591 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1050123 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1050123 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 45098 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 117231158 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 117276256 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 45098 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 45098 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 60175430 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 60175430 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 60175430 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 45098 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 117231158 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 177451686 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 2046591 # Number of read requests accepted
> system.physmem.writeReqs 1050123 # Number of write requests accepted
> system.physmem.readBursts 2046591 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1050123 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 130897024 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 84800 # Total number of bytes read from write queue
> system.physmem.bytesWritten 67206400 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 130981824 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 67207872 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 1325 # Number of DRAM read bursts serviced by the write queue
51,53c51,53
< system.physmem.perBankRdBursts::0 127284 # Per bank write bursts
< system.physmem.perBankRdBursts::1 124662 # Per bank write bursts
< system.physmem.perBankRdBursts::2 121597 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 127282 # Per bank write bursts
> system.physmem.perBankRdBursts::1 124660 # Per bank write bursts
> system.physmem.perBankRdBursts::2 121599 # Per bank write bursts
55c55
< system.physmem.perBankRdBursts::4 122617 # Per bank write bursts
---
> system.physmem.perBankRdBursts::4 122616 # Per bank write bursts
58c58
< system.physmem.perBankRdBursts::7 123759 # Per bank write bursts
---
> system.physmem.perBankRdBursts::7 123764 # Per bank write bursts
60,66c60,66
< system.physmem.perBankRdBursts::9 133511 # Per bank write bursts
< system.physmem.perBankRdBursts::10 132080 # Per bank write bursts
< system.physmem.perBankRdBursts::11 133309 # Per bank write bursts
< system.physmem.perBankRdBursts::12 133252 # Per bank write bursts
< system.physmem.perBankRdBursts::13 133368 # Per bank write bursts
< system.physmem.perBankRdBursts::14 129308 # Per bank write bursts
< system.physmem.perBankRdBursts::15 129546 # Per bank write bursts
---
> system.physmem.perBankRdBursts::9 133514 # Per bank write bursts
> system.physmem.perBankRdBursts::10 132084 # Per bank write bursts
> system.physmem.perBankRdBursts::11 133304 # Per bank write bursts
> system.physmem.perBankRdBursts::12 133248 # Per bank write bursts
> system.physmem.perBankRdBursts::13 133365 # Per bank write bursts
> system.physmem.perBankRdBursts::14 129309 # Per bank write bursts
> system.physmem.perBankRdBursts::15 129545 # Per bank write bursts
74,79c74,79
< system.physmem.perBankWrBursts::7 65435 # Per bank write bursts
< system.physmem.perBankWrBursts::8 67311 # Per bank write bursts
< system.physmem.perBankWrBursts::9 67795 # Per bank write bursts
< system.physmem.perBankWrBursts::10 67548 # Per bank write bursts
< system.physmem.perBankWrBursts::11 67883 # Per bank write bursts
< system.physmem.perBankWrBursts::12 67328 # Per bank write bursts
---
> system.physmem.perBankWrBursts::7 65436 # Per bank write bursts
> system.physmem.perBankWrBursts::8 67310 # Per bank write bursts
> system.physmem.perBankWrBursts::9 67797 # Per bank write bursts
> system.physmem.perBankWrBursts::10 67549 # Per bank write bursts
> system.physmem.perBankWrBursts::11 67882 # Per bank write bursts
> system.physmem.perBankWrBursts::12 67326 # Per bank write bursts
81c81
< system.physmem.perBankWrBursts::14 66483 # Per bank write bursts
---
> system.physmem.perBankWrBursts::14 66482 # Per bank write bursts
85c85
< system.physmem.totGap 1116876049000 # Total gap between requests
---
> system.physmem.totGap 1116865575000 # Total gap between requests
92c92
< system.physmem.readPktSize::6 2046592 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 2046591 # Read request sizes (log2)
99,101c99,101
< system.physmem.writePktSize::6 1050124 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1916546 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 128705 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1050123 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1916631 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 128617 # What read queue length does an incoming req see
147,165c147,165
< system.physmem.wrQLenPdf::15 32789 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 34054 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 56903 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 61212 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 61641 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 61693 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 61593 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 61666 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 61641 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 61698 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 61718 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 61664 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 62178 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 62548 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 62056 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 62535 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 61302 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 61133 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 74 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 32784 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 34018 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 56910 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 61213 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 61610 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 61708 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 61596 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 61643 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 61643 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 61703 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 61754 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 61670 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 62179 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 62537 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 62061 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 62560 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 61301 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 61129 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 78 # What write queue length does an incoming req see
196,213c196,213
< system.physmem.bytesPerActivate::samples 1910492 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 103.692259 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 81.833601 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 125.494474 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 1485528 77.76% 77.76% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 305524 15.99% 93.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 52470 2.75% 96.49% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 20903 1.09% 97.59% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 13406 0.70% 98.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 7575 0.40% 98.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 5481 0.29% 98.97% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5100 0.27% 99.24% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 14505 0.76% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1910492 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 61132 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 33.413630 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 160.636391 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 61087 99.93% 99.93% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 1910448 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 103.693777 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 81.830782 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 125.503425 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 1485607 77.76% 77.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 305343 15.98% 93.75% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 52494 2.75% 96.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 20883 1.09% 97.59% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 13429 0.70% 98.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 7609 0.40% 98.69% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5497 0.29% 98.97% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5095 0.27% 99.24% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 14491 0.76% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1910448 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 61128 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 33.415767 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 160.633753 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 61083 99.93% 99.93% # Reads before turning the bus around for writes
223,233c223,233
< system.physmem.rdPerTurnAround::total 61132 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 61132 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.177599 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.142637 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.096979 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 26963 44.11% 44.11% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 1122 1.84% 45.94% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 28754 47.04% 92.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 3885 6.36% 99.33% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 352 0.58% 99.91% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 46 0.08% 99.98% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 61128 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 61128 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.178707 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.143614 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.099153 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 26983 44.14% 44.14% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 1095 1.79% 45.93% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 28688 46.93% 92.86% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 3942 6.45% 99.31% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 361 0.59% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads
237,241c237,241
< system.physmem.wrPerTurnAround::total 61132 # Writes before turning the bus around for reads
< system.physmem.totQLat 38139021250 # Total ticks spent queuing
< system.physmem.totMemAccLat 76487815000 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 10226345000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 18647.44 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::total 61128 # Writes before turning the bus around for reads
> system.physmem.totQLat 38113681000 # Total ticks spent queuing
> system.physmem.totMemAccLat 76462418500 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 10226330000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 18635.07 # Average queueing delay per DRAM burst
243c243
< system.physmem.avgMemAccLat 37397.44 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 37385.07 # Average memory access latency per DRAM burst
247c247
< system.physmem.avgWrBWSys 60.17 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgWrBWSys 60.18 # Average system write bandwidth in MiByte/s
254,258c254,258
< system.physmem.readRowHits 773003 # Number of row buffer hits during reads
< system.physmem.writeRowHits 411872 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 37.79 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 39.22 # Row buffer hit rate for writes
< system.physmem.avgGap 360664.67 # Average gap between requests
---
> system.physmem.readRowHits 773150 # Number of row buffer hits during reads
> system.physmem.writeRowHits 411758 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 37.80 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 39.21 # Row buffer hit rate for writes
> system.physmem.avgGap 360661.52 # Average gap between requests
260,270c260,270
< system.physmem_0.actEnergy 7041119400 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 3841880625 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 7718053200 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3318446880 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 420554384415 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 301217964750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 816640712790 # Total energy per rank (pJ)
< system.physmem_0.averagePower 731.183278 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 498392390000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 37294920000 # Time in different power states
---
> system.physmem_0.actEnergy 7040439000 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 3841509375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 7717788000 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 3318453360 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 420410239110 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 301335056250 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 816611331495 # Total energy per rank (pJ)
> system.physmem_0.averagePower 731.167175 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 498591665750 # Time in different power states
> system.physmem_0.memoryStateTime::REF 37294400000 # Time in different power states
272c272
< system.physmem_0.memoryStateTime::ACT 581188236250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 580976292250 # Time in different power states
274,284c274,284
< system.physmem_1.actEnergy 7402200120 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 4038898875 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 8234990400 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3486207600 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 72948863520 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 429475728015 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 293392224750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 818979113280 # Total energy per rank (pJ)
< system.physmem_1.averagePower 733.276976 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 485326311500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 37294920000 # Time in different power states
---
> system.physmem_1.actEnergy 7402532760 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 4039080375 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 8234920200 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3486194640 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 72947846400 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 429557025690 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 293311559250 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 818979159315 # Total energy per rank (pJ)
> system.physmem_1.averagePower 733.287251 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 485194866750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 37294400000 # Time in different power states
286c286
< system.physmem_1.memoryStateTime::ACT 594254742500 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 594372992750 # Time in different power states
288,289c288,289
< system.cpu.branchPred.lookups 239639069 # Number of BP lookups
< system.cpu.branchPred.condPredicted 186342280 # Number of conditional branches predicted
---
> system.cpu.branchPred.lookups 239639075 # Number of BP lookups
> system.cpu.branchPred.condPredicted 186342287 # Number of conditional branches predicted
291,292c291,292
< system.cpu.branchPred.BTBLookups 130646098 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 122079384 # Number of BTB hits
---
> system.cpu.branchPred.BTBLookups 130646101 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 122079387 # Number of BTB hits
415c415
< system.cpu.numCycles 2233752285 # number of cpu cycles simulated
---
> system.cpu.numCycles 2233731339 # number of cpu cycles simulated
420c420
< system.cpu.discardedOps 41470092 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 41470082 # Number of ops (including micro ops) which were discarded before commit
422,425c422,425
< system.cpu.cpi 1.446203 # CPI: cycles per instruction
< system.cpu.ipc 0.691466 # IPC: instructions per cycle
< system.cpu.tickCycles 1834122948 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 399629337 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.446190 # CPI: cycles per instruction
> system.cpu.ipc 0.691472 # IPC: instructions per cycle
> system.cpu.tickCycles 1834124286 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 399607053 # Total number of cycles that the object has spent stopped
427,428c427,428
< system.cpu.dcache.tags.tagsinuse 4085.616333 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 624218905 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 4085.616235 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 624218894 # Total number of references to valid blocks.
430c430
< system.cpu.dcache.tags.avg_refs 67.665016 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 67.665015 # Average number of references to valid blocks.
432c432
< system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616333 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 4085.616235 # Average occupied blocks per requestor
436,437c436,437
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 245 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1237 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 253 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1229 # Occupied blocks per task id
441,446c441,446
< system.cpu.dcache.tags.tag_accesses 1276841915 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1276841915 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 453887721 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 453887721 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 170331061 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 170331061 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 1276841917 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1276841917 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 453887722 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 453887722 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 170331049 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 170331049 # number of WriteReq hits
453,456c453,456
< system.cpu.dcache.demand_hits::cpu.data 624218782 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 624218782 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 624218783 # number of overall hits
< system.cpu.dcache.overall_hits::total 624218783 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 624218771 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 624218771 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 624218772 # number of overall hits
> system.cpu.dcache.overall_hits::total 624218772 # number of overall hits
459,460c459,460
< system.cpu.dcache.WriteReq_misses::cpu.data 2254986 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2254986 # number of WriteReq misses
---
> system.cpu.dcache.WriteReq_misses::cpu.data 2254998 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2254998 # number of WriteReq misses
463,476c463,476
< system.cpu.dcache.demand_misses::cpu.data 9589483 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9589483 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9589485 # number of overall misses
< system.cpu.dcache.overall_misses::total 9589485 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 190949826000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 190949826000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060330000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 109060330000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 300010156000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 300010156000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 300010156000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 300010156000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 461222218 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 461222218 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 9589495 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9589495 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9589497 # number of overall misses
> system.cpu.dcache.overall_misses::total 9589497 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 190935436500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 190935436500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 109060065500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 109060065500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 299995502000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 299995502000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 299995502000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 299995502000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 461222219 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 461222219 # number of ReadReq accesses(hits+misses)
485,488c485,488
< system.cpu.dcache.demand_accesses::cpu.data 633808265 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 633808265 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 633808268 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 633808268 # number of overall (read+write) accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 633808266 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 633808266 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 633808269 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 633808269 # number of overall (read+write) accesses
499,506c499,506
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26034.481438 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 26034.481438 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48364.082970 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 48364.082970 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 31285.331649 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 31285.331649 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 31285.325124 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31285.325124 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26032.519544 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 26032.519544 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48363.708305 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 48363.708305 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 31283.764369 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 31283.764369 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 31283.757845 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 31283.757845 # average overall miss latency
519,524c519,524
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364134 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 364134 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 364349 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 364349 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 364349 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 364349 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 364146 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 364146 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 364361 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 364361 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 364361 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 364361 # number of overall MSHR hits
535,538c535,538
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183609818500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 183609818500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84766639000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 84766639000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 183595384500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 183595384500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 84757207500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 84757207500 # number of WriteReq MSHR miss cycles
541,544c541,544
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268376457500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 268376457500 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268376531500 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 268376531500 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 268352592000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 268352592000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 268352666000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 268352666000 # number of overall MSHR miss cycles
555,558c555,558
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25034.463973 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25034.463973 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44829.864527 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44829.864527 # average WriteReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 25032.495955 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25032.495955 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44824.876564 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44824.876564 # average WriteReq mshr miss latency
561,564c561,564
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29091.876335 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 29091.876335 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29091.881203 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 29091.881203 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29089.289326 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 29089.289326 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29089.294195 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 29089.294195 # average overall mshr miss latency
567,568c567,568
< system.cpu.icache.tags.tagsinuse 661.386126 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 465281345 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 661.385274 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 465281545 # Total number of references to valid blocks.
570c570
< system.cpu.icache.tags.avg_refs 567416.274390 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 567416.518293 # Average number of references to valid blocks.
572c572
< system.cpu.icache.tags.occ_blocks::cpu.inst 661.386126 # Average occupied blocks per requestor
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 661.385274 # Average occupied blocks per requestor
580,587c580,587
< system.cpu.icache.tags.tag_accesses 930565150 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 930565150 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 465281345 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 465281345 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 465281345 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 465281345 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 465281345 # number of overall hits
< system.cpu.icache.overall_hits::total 465281345 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 930565550 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 930565550 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 465281545 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 465281545 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 465281545 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 465281545 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 465281545 # number of overall hits
> system.cpu.icache.overall_hits::total 465281545 # number of overall hits
594,605c594,605
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 62363500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 62363500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 62363500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 62363500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 62363500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 62363500 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 465282165 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 465282165 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 465282165 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 465282165 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 465282165 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 465282165 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 62174000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 62174000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 62174000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 62174000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 62174000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 62174000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 465282365 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 465282365 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 465282365 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 465282365 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 465282365 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 465282365 # number of overall (read+write) accesses
612,617c612,617
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76053.048780 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 76053.048780 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 76053.048780 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 76053.048780 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 76053.048780 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75821.951220 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 75821.951220 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 75821.951220 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 75821.951220 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 75821.951220 # average overall miss latency
632,637c632,637
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61543500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 61543500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61543500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 61543500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61543500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 61543500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61354000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 61354000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61354000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 61354000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61354000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 61354000 # number of overall MSHR miss cycles
644,649c644,649
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75053.048780 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75053.048780 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75053.048780 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 75053.048780 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74821.951220 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74821.951220 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74821.951220 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 74821.951220 # average overall mshr miss latency
651,655c651,655
< system.cpu.l2cache.tags.replacements 2013891 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 31258.308104 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 14509189 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2043666 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 7.099589 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 2013890 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 31258.297879 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 14509190 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2043665 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 7.099593 # Average number of references to valid blocks.
657,660c657,660
< system.cpu.l2cache.tags.occ_blocks::writebacks 14832.412998 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588444 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.306662 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.452649 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 14832.420356 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.588666 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 16399.288857 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.452650 # Average percentage of cache occupancy
671,672c671,672
< system.cpu.l2cache.tags.tag_accesses 151497950 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 151497950 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 151497949 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 151497949 # Number of data accesses
675,676c675,676
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1089696 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1089696 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1089697 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1089697 # number of ReadExReq hits
682,683c682,683
< system.cpu.l2cache.demand_hits::cpu.data 7179326 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 7179358 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 7179327 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 7179359 # number of demand (read+write) hits
685,688c685,688
< system.cpu.l2cache.overall_hits::cpu.data 7179326 # number of overall hits
< system.cpu.l2cache.overall_hits::total 7179358 # number of overall hits
< system.cpu.l2cache.ReadExReq_misses::cpu.data 801156 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 801156 # number of ReadExReq misses
---
> system.cpu.l2cache.overall_hits::cpu.data 7179327 # number of overall hits
> system.cpu.l2cache.overall_hits::total 7179359 # number of overall hits
> system.cpu.l2cache.ReadExReq_misses::cpu.data 801155 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 801155 # number of ReadExReq misses
694,695c694,695
< system.cpu.l2cache.demand_misses::cpu.data 2045809 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 2046597 # number of demand (read+write) misses
---
> system.cpu.l2cache.demand_misses::cpu.data 2045808 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 2046596 # number of demand (read+write) misses
697,710c697,710
< system.cpu.l2cache.overall_misses::cpu.data 2045809 # number of overall misses
< system.cpu.l2cache.overall_misses::total 2046597 # number of overall misses
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70430633500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 70430633500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59976000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 59976000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108661637000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 108661637000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 59976000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 179092270500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 179152246500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 59976000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 179092270500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 179152246500 # number of overall miss cycles
---
> system.cpu.l2cache.overall_misses::cpu.data 2045808 # number of overall misses
> system.cpu.l2cache.overall_misses::total 2046596 # number of overall misses
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70421216500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 70421216500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 59756500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 59756500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 108645799000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 108645799000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 59756500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 179067015500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 179126772000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 59756500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 179067015500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 179126772000 # number of overall miss cycles
737,748c737,748
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87911.260104 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87911.260104 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 76111.675127 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 76111.675127 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87302.755869 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87302.755869 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 87536.650596 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76111.675127 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87541.051242 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 87536.650596 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 87899.615555 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 87899.615555 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75833.121827 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75833.121827 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 87290.031037 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 87290.031037 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 87524.246114 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75833.121827 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87528.749277 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 87524.246114 # average overall miss latency
757,758c757,758
< system.cpu.l2cache.writebacks::writebacks 1050124 # number of writebacks
< system.cpu.l2cache.writebacks::total 1050124 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 1050123 # number of writebacks
> system.cpu.l2cache.writebacks::total 1050123 # number of writebacks
771,772c771,772
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801156 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 801156 # number of ReadExReq MSHR misses
---
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 801155 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 801155 # number of ReadExReq MSHR misses
778,779c778,779
< system.cpu.l2cache.demand_mshr_misses::cpu.data 2045805 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 2046592 # number of demand (read+write) MSHR misses
---
> system.cpu.l2cache.demand_mshr_misses::cpu.data 2045804 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 2046591 # number of demand (read+write) MSHR misses
781,794c781,794
< system.cpu.l2cache.overall_mshr_misses::cpu.data 2045805 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 2046592 # number of overall MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62419073500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62419073500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 52090500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 52090500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96214883500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96214883500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 52090500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158633957000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 158686047500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 52090500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158633957000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 158686047500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_misses::cpu.data 2045804 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 2046591 # number of overall MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 62409666500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 62409666500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 51871000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 51871000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 96199045500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 96199045500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51871000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 158608712000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 158660583000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51871000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 158608712000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 158660583000 # number of overall MSHR miss cycles
809,820c809,820
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77911.260104 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77911.260104 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 66188.691233 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 66188.691233 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77302.824732 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77302.824732 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66188.691233 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77541.093604 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77536.728131 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77899.615555 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 77899.615555 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 65909.783990 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 65909.783990 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77290.099859 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77290.099859 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 65909.783990 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 77528.791614 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 77524.323619 # average overall mshr miss latency
821a822,827
> system.cpu.toL2Bus.snoop_filter.tot_requests 18447023 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 9221080 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1594 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 1287 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 1281 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 6 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
823c829
< system.cpu.toL2Bus.trans_dist::Writeback 4734688 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::Writeback 4734687 # Transaction distribution
835,838c841,844
< system.cpu.toL2Bus.snoops 2013891 # Total snoops (count)
< system.cpu.toL2Bus.snoop_fanout::samples 20460914 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 1.098426 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0.297890 # Request fanout histogram
---
> system.cpu.toL2Bus.snoops 2013890 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 20460913 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 0.000220 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.014837 # Request fanout histogram
840,842c846,848
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 18447023 90.16% 90.16% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::2 2013891 9.84% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 20456426 99.98% 99.98% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 4481 0.02% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 6 0.00% 100.00% # Request fanout histogram
844c850
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
846c852
< system.cpu.toL2Bus.snoop_fanout::total 20460914 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::total 20460913 # Request fanout histogram
854c860
< system.membus.trans_dist::Writeback 1050124 # Transaction distribution
---
> system.membus.trans_dist::Writeback 1050123 # Transaction distribution
856,857c862,863
< system.membus.trans_dist::ReadExReq 801156 # Transaction distribution
< system.membus.trans_dist::ReadExResp 801156 # Transaction distribution
---
> system.membus.trans_dist::ReadExReq 801155 # Transaction distribution
> system.membus.trans_dist::ReadExResp 801155 # Transaction distribution
859,862c865,868
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106031 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 6106031 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189824 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 198189824 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 6106028 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 6106028 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198189696 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 198189696 # Cumulative packet size per connected master and slave (bytes)
864c870
< system.membus.snoop_fanout::samples 4059439 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 4059437 # Request fanout histogram
868c874
< system.membus.snoop_fanout::0 4059439 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 4059437 100.00% 100.00% # Request fanout histogram
873,874c879,880
< system.membus.snoop_fanout::total 4059439 # Request fanout histogram
< system.membus.reqLayer0.occupancy 8663029500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 4059437 # Request fanout histogram
> system.membus.reqLayer0.occupancy 8662977500 # Layer occupancy (ticks)
876c882
< system.membus.respLayer1.occupancy 11191724000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 11191643250 # Layer occupancy (ticks)