3,5c3,5
< sim_seconds 1.121265 # Number of seconds simulated
< sim_ticks 1121265462500 # Number of ticks simulated
< final_tick 1121265462500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.119236 # Number of seconds simulated
> sim_ticks 1119236001500 # Number of ticks simulated
> final_tick 1119236001500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 238084 # Simulator instruction rate (inst/s)
< host_op_rate 256500 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 172835636 # Simulator tick rate (ticks/s)
< host_mem_usage 314372 # Number of bytes of host memory used
< host_seconds 6487.47 # Real time elapsed on the host
---
> host_inst_rate 240571 # Simulator instruction rate (inst/s)
> host_op_rate 259178 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 174324523 # Simulator tick rate (ticks/s)
> host_mem_usage 314620 # Number of bytes of host memory used
> host_seconds 6420.42 # Real time elapsed on the host
16,48c16,48
< system.physmem.bytes_read::cpu.inst 50816 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 131531264 # Number of bytes read from this memory
< system.physmem.bytes_read::total 131582080 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 50816 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 50816 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 66976320 # Number of bytes written to this memory
< system.physmem.bytes_written::total 66976320 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 794 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 2055176 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 2055970 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1046505 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1046505 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 45320 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 117306087 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 117351407 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 45320 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 45320 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 59732795 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 59732795 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 59732795 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 45320 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 117306087 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 177084202 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 2055970 # Number of read requests accepted
< system.physmem.writeReqs 1046505 # Number of write requests accepted
< system.physmem.readBursts 2055970 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1046505 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 131497344 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 84736 # Total number of bytes read from write queue
< system.physmem.bytesWritten 66974720 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 131582080 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 66976320 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 1324 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bytes_read::cpu.inst 50432 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 131457472 # Number of bytes read from this memory
> system.physmem.bytes_read::total 131507904 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 66959680 # Number of bytes written to this memory
> system.physmem.bytes_written::total 66959680 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 788 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 2054023 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 2054811 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1046245 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1046245 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 45059 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 117452862 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 117497922 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 45059 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 45059 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 59826239 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 59826239 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 59826239 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 45059 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 117452862 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 177324160 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 2054811 # Number of read requests accepted
> system.physmem.writeReqs 1046245 # Number of write requests accepted
> system.physmem.readBursts 2054811 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1046245 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 131422592 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 85312 # Total number of bytes read from write queue
> system.physmem.bytesWritten 66958080 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 131507904 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 66959680 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 1333 # Number of DRAM read bursts serviced by the write queue
51,82c51,82
< system.physmem.perBankRdBursts::0 128088 # Per bank write bursts
< system.physmem.perBankRdBursts::1 125235 # Per bank write bursts
< system.physmem.perBankRdBursts::2 122283 # Per bank write bursts
< system.physmem.perBankRdBursts::3 124122 # Per bank write bursts
< system.physmem.perBankRdBursts::4 123237 # Per bank write bursts
< system.physmem.perBankRdBursts::5 123404 # Per bank write bursts
< system.physmem.perBankRdBursts::6 123754 # Per bank write bursts
< system.physmem.perBankRdBursts::7 124260 # Per bank write bursts
< system.physmem.perBankRdBursts::8 132002 # Per bank write bursts
< system.physmem.perBankRdBursts::9 134077 # Per bank write bursts
< system.physmem.perBankRdBursts::10 132455 # Per bank write bursts
< system.physmem.perBankRdBursts::11 133729 # Per bank write bursts
< system.physmem.perBankRdBursts::12 133726 # Per bank write bursts
< system.physmem.perBankRdBursts::13 133924 # Per bank write bursts
< system.physmem.perBankRdBursts::14 129890 # Per bank write bursts
< system.physmem.perBankRdBursts::15 130460 # Per bank write bursts
< system.physmem.perBankWrBursts::0 65849 # Per bank write bursts
< system.physmem.perBankWrBursts::1 64148 # Per bank write bursts
< system.physmem.perBankWrBursts::2 62390 # Per bank write bursts
< system.physmem.perBankWrBursts::3 62849 # Per bank write bursts
< system.physmem.perBankWrBursts::4 62818 # Per bank write bursts
< system.physmem.perBankWrBursts::5 62997 # Per bank write bursts
< system.physmem.perBankWrBursts::6 64238 # Per bank write bursts
< system.physmem.perBankWrBursts::7 65252 # Per bank write bursts
< system.physmem.perBankWrBursts::8 67098 # Per bank write bursts
< system.physmem.perBankWrBursts::9 67598 # Per bank write bursts
< system.physmem.perBankWrBursts::10 67270 # Per bank write bursts
< system.physmem.perBankWrBursts::11 67670 # Per bank write bursts
< system.physmem.perBankWrBursts::12 67009 # Per bank write bursts
< system.physmem.perBankWrBursts::13 67470 # Per bank write bursts
< system.physmem.perBankWrBursts::14 66159 # Per bank write bursts
< system.physmem.perBankWrBursts::15 65665 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 127863 # Per bank write bursts
> system.physmem.perBankRdBursts::1 125217 # Per bank write bursts
> system.physmem.perBankRdBursts::2 122173 # Per bank write bursts
> system.physmem.perBankRdBursts::3 124176 # Per bank write bursts
> system.physmem.perBankRdBursts::4 123271 # Per bank write bursts
> system.physmem.perBankRdBursts::5 123280 # Per bank write bursts
> system.physmem.perBankRdBursts::6 123668 # Per bank write bursts
> system.physmem.perBankRdBursts::7 124134 # Per bank write bursts
> system.physmem.perBankRdBursts::8 131770 # Per bank write bursts
> system.physmem.perBankRdBursts::9 134069 # Per bank write bursts
> system.physmem.perBankRdBursts::10 132400 # Per bank write bursts
> system.physmem.perBankRdBursts::11 133571 # Per bank write bursts
> system.physmem.perBankRdBursts::12 133882 # Per bank write bursts
> system.physmem.perBankRdBursts::13 133894 # Per bank write bursts
> system.physmem.perBankRdBursts::14 129882 # Per bank write bursts
> system.physmem.perBankRdBursts::15 130228 # Per bank write bursts
> system.physmem.perBankWrBursts::0 65769 # Per bank write bursts
> system.physmem.perBankWrBursts::1 64155 # Per bank write bursts
> system.physmem.perBankWrBursts::2 62373 # Per bank write bursts
> system.physmem.perBankWrBursts::3 62858 # Per bank write bursts
> system.physmem.perBankWrBursts::4 62829 # Per bank write bursts
> system.physmem.perBankWrBursts::5 62965 # Per bank write bursts
> system.physmem.perBankWrBursts::6 64230 # Per bank write bursts
> system.physmem.perBankWrBursts::7 65234 # Per bank write bursts
> system.physmem.perBankWrBursts::8 67002 # Per bank write bursts
> system.physmem.perBankWrBursts::9 67576 # Per bank write bursts
> system.physmem.perBankWrBursts::10 67286 # Per bank write bursts
> system.physmem.perBankWrBursts::11 67640 # Per bank write bursts
> system.physmem.perBankWrBursts::12 67022 # Per bank write bursts
> system.physmem.perBankWrBursts::13 67467 # Per bank write bursts
> system.physmem.perBankWrBursts::14 66208 # Per bank write bursts
> system.physmem.perBankWrBursts::15 65606 # Per bank write bursts
85c85
< system.physmem.totGap 1121265368000 # Total gap between requests
---
> system.physmem.totGap 1119235907000 # Total gap between requests
92c92
< system.physmem.readPktSize::6 2055970 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 2054811 # Read request sizes (log2)
99,102c99,102
< system.physmem.writePktSize::6 1046505 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1926795 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 127832 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1046245 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1925781 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 127679 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
147,163c147,163
< system.physmem.wrQLenPdf::15 32223 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 33685 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 56905 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 60965 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 61436 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 61459 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 61451 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 61451 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 61467 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 61525 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 61499 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 61509 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 62354 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 61776 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 61856 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 62659 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 61196 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 32244 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 33494 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 56963 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 61003 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 61383 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 61457 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 61389 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 61438 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 61514 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 61512 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 61526 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 61507 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 62283 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 61797 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 61801 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 62618 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 61214 # What write queue length does an incoming req see
165,169c165,169
< system.physmem.wrQLenPdf::33 93 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::33 97 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 2 # What write queue length does an incoming req see
196,215c196,215
< system.physmem.bytesPerActivate::samples 1920747 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 103.329698 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 81.701744 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 124.647307 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 1495902 77.88% 77.88% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 305625 15.91% 93.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 52698 2.74% 96.54% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 21305 1.11% 97.65% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 13173 0.69% 98.33% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 7131 0.37% 98.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 5450 0.28% 98.99% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 5094 0.27% 99.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 14369 0.75% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1920747 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 60965 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 33.654375 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 161.846066 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 60925 99.93% 99.93% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-2047 15 0.02% 99.96% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 1918760 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 103.389572 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 81.724365 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 124.748032 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 1494097 77.87% 77.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 305195 15.91% 93.77% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 52958 2.76% 96.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 21140 1.10% 97.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 13031 0.68% 98.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 7420 0.39% 98.70% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5500 0.29% 98.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5087 0.27% 99.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 14332 0.75% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1918760 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 60963 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 33.636353 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 160.963797 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 60925 99.94% 99.94% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.96% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2048-3071 11 0.02% 99.98% # Reads before turning the bus around for writes
220c220
< system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
222,234c222,235
< system.physmem.rdPerTurnAround::total 60965 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 60965 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.165259 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.130353 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.096188 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 27136 44.51% 44.51% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 1324 2.17% 46.68% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 28285 46.40% 93.08% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 3807 6.24% 99.32% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 355 0.58% 99.90% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 47 0.08% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 1 0.00% 100.00% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 60963 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 60963 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.161557 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.126473 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.099462 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 27343 44.85% 44.85% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 1128 1.85% 46.70% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 28298 46.42% 93.12% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 3779 6.20% 99.32% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 354 0.58% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 49 0.08% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 6 0.01% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 2 0.00% 99.99% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::24 1 0.00% 100.00% # Writes before turning the bus around for reads
236,240c237,243
< system.physmem.wrPerTurnAround::total 60965 # Writes before turning the bus around for reads
< system.physmem.totQLat 38466601000 # Total ticks spent queuing
< system.physmem.totMemAccLat 76991213500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 10273230000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 18721.77 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 60963 # Writes before turning the bus around for reads
> system.physmem.totQLat 38392697500 # Total ticks spent queuing
> system.physmem.totMemAccLat 76895410000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 10267390000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 18696.43 # Average queueing delay per DRAM burst
242,246c245,249
< system.physmem.avgMemAccLat 37471.77 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 117.28 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 59.73 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 117.35 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 59.73 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 37446.43 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 117.42 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 59.82 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 117.50 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 59.83 # Average system write bandwidth in MiByte/s
252,269c255,272
< system.physmem.avgWrQLen 24.95 # Average write queue length when enqueuing
< system.physmem.readRowHits 774547 # Number of row buffer hits during reads
< system.physmem.writeRowHits 405822 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 37.70 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 38.78 # Row buffer hit rate for writes
< system.physmem.avgGap 361409.96 # Average gap between requests
< system.physmem.pageHitRate 38.06 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 7084922040 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 3865780875 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 7755875400 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3308305680 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 73235182800 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 422966689965 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 301732094250 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 819948851010 # Total energy per rank (pJ)
< system.physmem_0.averagePower 731.275041 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 499232206000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 37441300000 # Time in different power states
---
> system.physmem.avgWrQLen 25.22 # Average write queue length when enqueuing
> system.physmem.readRowHits 774740 # Number of row buffer hits during reads
> system.physmem.writeRowHits 406194 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 37.73 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 38.82 # Row buffer hit rate for writes
> system.physmem.avgGap 360920.90 # Average gap between requests
> system.physmem.pageHitRate 38.10 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 7079751000 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 3862959375 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 7751413800 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 3307476240 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 73102957200 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 422173404720 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 301213311750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 818491274085 # Total energy per rank (pJ)
> system.physmem_0.averagePower 731.295434 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 498371051250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 37373700000 # Time in different power states
271c274
< system.physmem_0.memoryStateTime::ACT 584588629000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 583490028750 # Time in different power states
273,283c276,286
< system.physmem_1.actEnergy 7435910160 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 4057292250 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 8269996800 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3472884720 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 73235182800 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 431711081055 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 294061575750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 822243923535 # Total energy per rank (pJ)
< system.physmem_1.averagePower 733.321912 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 486423236500 # Time in different power states
< system.physmem_1.memoryStateTime::REF 37441300000 # Time in different power states
---
> system.physmem_1.actEnergy 7426074600 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 4051925625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 8265605400 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3472029360 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 73102957200 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 430406880300 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 293990964750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 820716437235 # Total energy per rank (pJ)
> system.physmem_1.averagePower 733.283545 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 486308465000 # Time in different power states
> system.physmem_1.memoryStateTime::REF 37373700000 # Time in different power states
285c288
< system.physmem_1.memoryStateTime::ACT 597397500000 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 595553667000 # Time in different power states
287,291c290,294
< system.cpu.branchPred.lookups 240144458 # Number of BP lookups
< system.cpu.branchPred.condPredicted 186748856 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 14594265 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 132793559 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 122289853 # Number of BTB hits
---
> system.cpu.branchPred.lookups 239764270 # Number of BP lookups
> system.cpu.branchPred.condPredicted 186476421 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 14595676 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 130796554 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 122091083 # Number of BTB hits
293,294c296,297
< system.cpu.branchPred.BTBHitPct 92.090199 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 15658823 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 93.344266 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 15654091 # Number of times the RAS was used to get a target.
414c417
< system.cpu.numCycles 2242530925 # number of cpu cycles simulated
---
> system.cpu.numCycles 2238472003 # number of cpu cycles simulated
419c422
< system.cpu.discardedOps 40067412 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 41626992 # Number of ops (including micro ops) which were discarded before commit
421,433c424,436
< system.cpu.cpi 1.451887 # CPI: cycles per instruction
< system.cpu.ipc 0.688759 # IPC: instructions per cycle
< system.cpu.tickCycles 1838970368 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 403560557 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 9223420 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4085.640559 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 624065637 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 9227516 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 67.630946 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 9814734000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4085.640559 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy
---
> system.cpu.cpi 1.449259 # CPI: cycles per instruction
> system.cpu.ipc 0.690008 # IPC: instructions per cycle
> system.cpu.tickCycles 1834950604 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 403521399 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 9221835 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4085.627405 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 624240644 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 9225931 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 67.661534 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 9809256250 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4085.627405 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.997468 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.997468 # Average percentage of cache occupancy
435,436c438,439
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 252 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1219 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 244 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1227 # Occupied blocks per task id
440,445c443,448
< system.cpu.dcache.tags.tag_accesses 1276541490 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1276541490 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 453733959 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 453733959 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 170331555 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 170331555 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 1276887063 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1276887063 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 453909121 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 453909121 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 170331400 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 170331400 # number of WriteReq hits
452,459c455,462
< system.cpu.dcache.demand_hits::cpu.data 624065514 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 624065514 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 624065515 # number of overall hits
< system.cpu.dcache.overall_hits::total 624065515 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 7336856 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 7336856 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 2254492 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2254492 # number of WriteReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 624240521 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 624240521 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 624240522 # number of overall hits
> system.cpu.dcache.overall_hits::total 624240522 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 7335273 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 7335273 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 2254647 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2254647 # number of WriteReq misses
462,475c465,478
< system.cpu.dcache.demand_misses::cpu.data 9591348 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9591348 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9591350 # number of overall misses
< system.cpu.dcache.overall_misses::total 9591350 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 192473949996 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 192473949996 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 109728776250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 109728776250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 302202726246 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 302202726246 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 302202726246 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 302202726246 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 461070815 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 461070815 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_misses::cpu.data 9589920 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9589920 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9589922 # number of overall misses
> system.cpu.dcache.overall_misses::total 9589922 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 192354012246 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 192354012246 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 109627439500 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 109627439500 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 301981451746 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 301981451746 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 301981451746 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 301981451746 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 461244394 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 461244394 # number of ReadReq accesses(hits+misses)
484,491c487,494
< system.cpu.dcache.demand_accesses::cpu.data 633656862 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 633656862 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 633656865 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 633656865 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 633830441 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 633830441 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 633830444 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 633830444 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015903 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.015903 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013064 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.013064 # miss rate for WriteReq accesses
494,505c497,508
< system.cpu.dcache.demand_miss_rate::cpu.data 0.015137 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.015137 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.015137 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.015137 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26233.845941 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 26233.845941 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48671.175702 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 48671.175702 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 31507.847098 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 31507.847098 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 31507.840528 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 31507.840528 # average overall miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.015130 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.015130 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.015130 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.015130 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26223.156554 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 26223.156554 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48622.883981 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 48622.883981 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 31489.465162 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 31489.465162 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 31489.458595 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 31489.458595 # average overall miss latency
514,527c517,530
< system.cpu.dcache.writebacks::writebacks 3700612 # number of writebacks
< system.cpu.dcache.writebacks::total 3700612 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 212 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363621 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 363621 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 363833 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 363833 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 363833 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 363833 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336644 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 7336644 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890871 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1890871 # number of WriteReq MSHR misses
---
> system.cpu.dcache.writebacks::writebacks 3700642 # number of writebacks
> system.cpu.dcache.writebacks::total 3700642 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 215 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 215 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363775 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 363775 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 363990 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 363990 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 363990 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 363990 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7335058 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 7335058 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890872 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1890872 # number of WriteReq MSHR misses
530,537c533,540
< system.cpu.dcache.demand_mshr_misses::cpu.data 9227515 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 9227515 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 9227516 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9227516 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181052332504 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 181052332504 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83984263000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 83984263000 # number of WriteReq MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_misses::cpu.data 9225930 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 9225930 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9225931 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9225931 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 180934230004 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 180934230004 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83925664500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 83925664500 # number of WriteReq MSHR miss cycles
540,545c543,548
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 265036595504 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 265036595504 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 265036669254 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 265036669254 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264859894504 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 264859894504 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264859968254 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 264859968254 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015903 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015903 # mshr miss rate for ReadReq accesses
550,557c553,560
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24677.813521 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24677.813521 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44415.649190 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44415.649190 # average WriteReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.014556 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014556 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.014556 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24667.048305 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24667.048305 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44384.635502 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44384.635502 # average WriteReq mshr miss latency
560,563c563,566
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28722.423697 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 28722.423697 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28722.428577 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 28722.428577 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28708.205515 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28708.205515 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28708.210397 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 28708.210397 # average overall mshr miss latency
565,569c568,572
< system.cpu.icache.tags.replacements 35 # number of replacements
< system.cpu.icache.tags.tagsinuse 662.614734 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 466141021 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 828 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 562972.247585 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 29 # number of replacements
> system.cpu.icache.tags.tagsinuse 662.446494 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 465464024 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 821 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 566947.654080 # Average number of references to valid blocks.
571,574c574,577
< system.cpu.icache.tags.occ_blocks::cpu.inst 662.614734 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.323542 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.323542 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_task_id_blocks::1024 793 # Occupied blocks per task id
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 662.446494 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.323460 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.323460 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_task_id_blocks::1024 792 # Occupied blocks per task id
576,604c579,607
< system.cpu.icache.tags.age_task_id_blocks_1024::2 7 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id
< system.cpu.icache.tags.occ_task_id_percent::1024 0.387207 # Percentage of cache occupancy per task id
< system.cpu.icache.tags.tag_accesses 932284526 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 932284526 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 466141021 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 466141021 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 466141021 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 466141021 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 466141021 # number of overall hits
< system.cpu.icache.overall_hits::total 466141021 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 828 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 828 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 828 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 828 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 828 # number of overall misses
< system.cpu.icache.overall_misses::total 828 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 63773749 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 63773749 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 63773749 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 63773749 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 63773749 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 63773749 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 466141849 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 466141849 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 466141849 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 466141849 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 466141849 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 466141849 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 755 # Occupied blocks per task id
> system.cpu.icache.tags.occ_task_id_percent::1024 0.386719 # Percentage of cache occupancy per task id
> system.cpu.icache.tags.tag_accesses 930930511 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 930930511 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 465464024 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 465464024 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 465464024 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 465464024 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 465464024 # number of overall hits
> system.cpu.icache.overall_hits::total 465464024 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 821 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 821 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 821 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 821 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 821 # number of overall misses
> system.cpu.icache.overall_misses::total 821 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 63001249 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 63001249 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 63001249 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 63001249 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 63001249 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 63001249 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 465464845 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 465464845 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 465464845 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 465464845 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 465464845 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 465464845 # number of overall (read+write) accesses
611,616c614,619
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77021.435990 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 77021.435990 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 77021.435990 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 77021.435990 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 77021.435990 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 77021.435990 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 76737.209501 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 76737.209501 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 76737.209501 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 76737.209501 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 76737.209501 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 76737.209501 # average overall miss latency
625,636c628,639
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 828 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 828 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 828 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 828 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 828 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 828 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62196251 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 62196251 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62196251 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 62196251 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62196251 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 62196251 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 821 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 821 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 821 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 821 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 821 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 821 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61437251 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 61437251 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61437251 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 61437251 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61437251 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 61437251 # number of overall MSHR miss cycles
643,648c646,651
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75116.245169 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75116.245169 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75116.245169 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 75116.245169 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75116.245169 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 75116.245169 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 74832.218027 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 74832.218027 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 74832.218027 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 74832.218027 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 74832.218027 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 74832.218027 # average overall mshr miss latency
650,662c653,665
< system.cpu.l2cache.tags.replacements 2023265 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 31261.991003 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 8984313 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2053040 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.376102 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 59841737750 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 14971.940870 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.910061 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 16263.140072 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.456907 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000821 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.496312 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.954040 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.replacements 2022107 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 31260.648625 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 8983908 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2051882 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.378375 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 59777107750 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 14976.284316 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.749735 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 16257.614575 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.457040 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000816 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.496143 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.953999 # Average percentage of cache occupancy
666c669
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1244 # Occupied blocks per task id
668c671
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15554 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15557 # Occupied blocks per task id
670,741c673,744
< system.cpu.l2cache.tags.tag_accesses 107375559 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 107375559 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 33 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::cpu.data 6081577 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 6081610 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 3700612 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 3700612 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1090759 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1090759 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 33 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::cpu.data 7172336 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 7172369 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 33 # number of overall hits
< system.cpu.l2cache.overall_hits::cpu.data 7172336 # number of overall hits
< system.cpu.l2cache.overall_hits::total 7172369 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 1255068 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 1255863 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 800112 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 800112 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 795 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 2055180 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 2055975 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 795 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 2055180 # number of overall misses
< system.cpu.l2cache.overall_misses::total 2055975 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 61020250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109853349250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 109914369500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70575135000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 70575135000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 61020250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 180428484250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 180489504500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 61020250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 180428484250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 180489504500 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 828 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 7336645 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 7337473 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 3700612 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 3700612 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890871 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 1890871 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 828 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 9227516 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 9228344 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 828 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 9227516 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 9228344 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960145 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171068 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.171157 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423145 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.423145 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960145 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.222723 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.222789 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960145 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.222723 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.222789 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76755.031447 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87527.806661 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 87520.987162 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88206.569830 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88206.569830 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76755.031447 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87792.059211 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 87787.791437 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76755.031447 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87792.059211 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 87787.791437 # average overall miss latency
---
> system.cpu.l2cache.tags.tag_accesses 107361906 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 107361906 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 32 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::cpu.data 6080985 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 6081017 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 3700642 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 3700642 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1090919 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1090919 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 32 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::cpu.data 7171904 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 7171936 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 32 # number of overall hits
> system.cpu.l2cache.overall_hits::cpu.data 7171904 # number of overall hits
> system.cpu.l2cache.overall_hits::total 7171936 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 789 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 1254074 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 1254863 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 799953 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 799953 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 789 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 2054027 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 2054816 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 789 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 2054027 # number of overall misses
> system.cpu.l2cache.overall_misses::total 2054816 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60278250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109743015750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 109803294000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70520146000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 70520146000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 60278250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 180263161750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 180323440000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 60278250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 180263161750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 180323440000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 821 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 7335059 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 7335880 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 3700642 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 3700642 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890872 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 1890872 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 821 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 9225931 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 9226752 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 821 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 9225931 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 9226752 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961023 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.170970 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.171058 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423060 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.423060 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961023 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.222636 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.222702 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961023 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.222636 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.222702 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76398.288973 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87509.202607 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 87502.216577 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88155.361627 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88155.361627 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76398.288973 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87760.853071 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 87756.490119 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76398.288973 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87760.853071 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 87756.490119 # average overall miss latency
750,751c753,754
< system.cpu.l2cache.writebacks::writebacks 1046505 # number of writebacks
< system.cpu.l2cache.writebacks::total 1046505 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 1046245 # number of writebacks
> system.cpu.l2cache.writebacks::total 1046245 # number of writebacks
761,804c764,807
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 794 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1255064 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 1255858 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800112 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 800112 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 794 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 2055176 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 2055970 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 794 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 2055176 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 2055970 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51069250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93985038750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94036108000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60466755500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60466755500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51069250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154451794250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 154502863500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51069250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154451794250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 154502863500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958937 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171068 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171157 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423145 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423145 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958937 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222723 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.222789 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958937 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222723 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.222789 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64318.954660 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74884.658272 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74877.978243 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75572.864174 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75572.864174 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64318.954660 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75152.587540 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75148.403673 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64318.954660 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75152.587540 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75148.403673 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 788 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254070 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 1254858 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 799953 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 799953 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 788 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 2054023 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 2054811 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 788 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 2054023 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 2054811 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 50399250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93887019000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 93937418250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60414024000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60414024000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50399250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154301043000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 154351442250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50399250 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154301043000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 154351442250 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.170969 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171058 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423060 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423060 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222636 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.222701 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959805 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222636 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.222701 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 63958.439086 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74865.851986 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74859.002572 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75521.966916 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75521.966916 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 63958.439086 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75121.380335 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75117.099456 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 63958.439086 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75121.380335 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75117.099456 # average overall mshr miss latency
806,816c809,819
< system.cpu.toL2Bus.trans_dist::ReadReq 7337473 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 7337473 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 3700612 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 1890871 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 1890871 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1656 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22155644 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 22157300 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52992 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827400192 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 827453184 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadReq 7335880 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 7335880 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 3700642 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 1890872 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 1890872 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1642 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22152504 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 22154146 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52544 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827300672 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 827353216 # Cumulative packet size per connected master and slave (bytes)
818c821
< system.cpu.toL2Bus.snoop_fanout::samples 12928956 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 12927394 # Request fanout histogram
823c826
< system.cpu.toL2Bus.snoop_fanout::1 12928956 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::1 12927394 100.00% 100.00% # Request fanout histogram
828,829c831,832
< system.cpu.toL2Bus.snoop_fanout::total 12928956 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 10165090000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::total 12927394 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 10164339000 # Layer occupancy (ticks)
831c834
< system.cpu.toL2Bus.respLayer0.occupancy 1409749 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1397749 # Layer occupancy (ticks)
833c836
< system.cpu.toL2Bus.respLayer1.occupancy 14190252246 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 14187903746 # Layer occupancy (ticks)
835,843c838,846
< system.membus.trans_dist::ReadReq 1255858 # Transaction distribution
< system.membus.trans_dist::ReadResp 1255858 # Transaction distribution
< system.membus.trans_dist::Writeback 1046505 # Transaction distribution
< system.membus.trans_dist::ReadExReq 800112 # Transaction distribution
< system.membus.trans_dist::ReadExResp 800112 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158445 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5158445 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198558400 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 198558400 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadReq 1254858 # Transaction distribution
> system.membus.trans_dist::ReadResp 1254858 # Transaction distribution
> system.membus.trans_dist::Writeback 1046245 # Transaction distribution
> system.membus.trans_dist::ReadExReq 799953 # Transaction distribution
> system.membus.trans_dist::ReadExResp 799953 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5155867 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5155867 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198467584 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 198467584 # Cumulative packet size per connected master and slave (bytes)
845c848
< system.membus.snoop_fanout::samples 3102475 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 3101056 # Request fanout histogram
849c852
< system.membus.snoop_fanout::0 3102475 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 3101056 100.00% 100.00% # Request fanout histogram
854,855c857,858
< system.membus.snoop_fanout::total 3102475 # Request fanout histogram
< system.membus.reqLayer0.occupancy 7945005500 # Layer occupancy (ticks)
---
> system.membus.snoop_fanout::total 3101056 # Request fanout histogram
> system.membus.reqLayer0.occupancy 7929911000 # Layer occupancy (ticks)
857c860
< system.membus.respLayer1.occupancy 11244435500 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 11237799750 # Layer occupancy (ticks)