3,5c3,5
< sim_seconds 1.108725 # Number of seconds simulated
< sim_ticks 1108725388000 # Number of ticks simulated
< final_tick 1108725388000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.121241 # Number of seconds simulated
> sim_ticks 1121241432500 # Number of ticks simulated
> final_tick 1121241432500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 160331 # Simulator instruction rate (inst/s)
< host_op_rate 172733 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 115089854 # Simulator tick rate (ticks/s)
< host_mem_usage 301444 # Number of bytes of host memory used
< host_seconds 9633.56 # Real time elapsed on the host
---
> host_inst_rate 243175 # Simulator instruction rate (inst/s)
> host_op_rate 261985 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 176527853 # Simulator tick rate (ticks/s)
> host_mem_usage 312356 # Number of bytes of host memory used
> host_seconds 6351.64 # Real time elapsed on the host
16,48c16,48
< system.physmem.bytes_read::cpu.inst 50368 # Number of bytes read from this memory
< system.physmem.bytes_read::cpu.data 131507968 # Number of bytes read from this memory
< system.physmem.bytes_read::total 131558336 # Number of bytes read from this memory
< system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory
< system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory
< system.physmem.bytes_written::writebacks 66970688 # Number of bytes written to this memory
< system.physmem.bytes_written::total 66970688 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 787 # Number of read requests responded to by this memory
< system.physmem.num_reads::cpu.data 2054812 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 2055599 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1046417 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1046417 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 45429 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 118611849 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 118657277 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 45429 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 45429 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 60403314 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 60403314 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 60403314 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 45429 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 118611849 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 179060592 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 2055599 # Number of read requests accepted
< system.physmem.writeReqs 1046417 # Number of write requests accepted
< system.physmem.readBursts 2055599 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1046417 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 131472320 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue
< system.physmem.bytesWritten 66969088 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 131558336 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 66970688 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bytes_read::cpu.inst 50560 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 131525952 # Number of bytes read from this memory
> system.physmem.bytes_read::total 131576512 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 50560 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 50560 # Number of instructions bytes read from this memory
> system.physmem.bytes_written::writebacks 66977984 # Number of bytes written to this memory
> system.physmem.bytes_written::total 66977984 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 790 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 2055093 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 2055883 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1046531 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1046531 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 45093 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 117303864 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 117348956 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 45093 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 45093 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 59735559 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 59735559 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 59735559 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 45093 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 117303864 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 177084516 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 2055883 # Number of read requests accepted
> system.physmem.writeReqs 1046531 # Number of write requests accepted
> system.physmem.readBursts 2055883 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1046531 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 131490688 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 85824 # Total number of bytes read from write queue
> system.physmem.bytesWritten 66976384 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 131576512 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 66977984 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 1341 # Number of DRAM read bursts serviced by the write queue
51,82c51,82
< system.physmem.perBankRdBursts::0 127971 # Per bank write bursts
< system.physmem.perBankRdBursts::1 125115 # Per bank write bursts
< system.physmem.perBankRdBursts::2 122192 # Per bank write bursts
< system.physmem.perBankRdBursts::3 124223 # Per bank write bursts
< system.physmem.perBankRdBursts::4 123351 # Per bank write bursts
< system.physmem.perBankRdBursts::5 123340 # Per bank write bursts
< system.physmem.perBankRdBursts::6 123758 # Per bank write bursts
< system.physmem.perBankRdBursts::7 124120 # Per bank write bursts
< system.physmem.perBankRdBursts::8 131994 # Per bank write bursts
< system.physmem.perBankRdBursts::9 134060 # Per bank write bursts
< system.physmem.perBankRdBursts::10 132574 # Per bank write bursts
< system.physmem.perBankRdBursts::11 133683 # Per bank write bursts
< system.physmem.perBankRdBursts::12 133864 # Per bank write bursts
< system.physmem.perBankRdBursts::13 133891 # Per bank write bursts
< system.physmem.perBankRdBursts::14 129793 # Per bank write bursts
< system.physmem.perBankRdBursts::15 130326 # Per bank write bursts
< system.physmem.perBankWrBursts::0 65785 # Per bank write bursts
< system.physmem.perBankWrBursts::1 64106 # Per bank write bursts
< system.physmem.perBankWrBursts::2 62369 # Per bank write bursts
< system.physmem.perBankWrBursts::3 62872 # Per bank write bursts
< system.physmem.perBankWrBursts::4 62855 # Per bank write bursts
< system.physmem.perBankWrBursts::5 62943 # Per bank write bursts
< system.physmem.perBankWrBursts::6 64256 # Per bank write bursts
< system.physmem.perBankWrBursts::7 65177 # Per bank write bursts
< system.physmem.perBankWrBursts::8 67064 # Per bank write bursts
< system.physmem.perBankWrBursts::9 67603 # Per bank write bursts
< system.physmem.perBankWrBursts::10 67361 # Per bank write bursts
< system.physmem.perBankWrBursts::11 67637 # Per bank write bursts
< system.physmem.perBankWrBursts::12 67067 # Per bank write bursts
< system.physmem.perBankWrBursts::13 67487 # Per bank write bursts
< system.physmem.perBankWrBursts::14 66154 # Per bank write bursts
< system.physmem.perBankWrBursts::15 65656 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 127988 # Per bank write bursts
> system.physmem.perBankRdBursts::1 125250 # Per bank write bursts
> system.physmem.perBankRdBursts::2 122092 # Per bank write bursts
> system.physmem.perBankRdBursts::3 124158 # Per bank write bursts
> system.physmem.perBankRdBursts::4 123330 # Per bank write bursts
> system.physmem.perBankRdBursts::5 123315 # Per bank write bursts
> system.physmem.perBankRdBursts::6 123951 # Per bank write bursts
> system.physmem.perBankRdBursts::7 124319 # Per bank write bursts
> system.physmem.perBankRdBursts::8 132052 # Per bank write bursts
> system.physmem.perBankRdBursts::9 134015 # Per bank write bursts
> system.physmem.perBankRdBursts::10 132327 # Per bank write bursts
> system.physmem.perBankRdBursts::11 133706 # Per bank write bursts
> system.physmem.perBankRdBursts::12 133817 # Per bank write bursts
> system.physmem.perBankRdBursts::13 133969 # Per bank write bursts
> system.physmem.perBankRdBursts::14 129938 # Per bank write bursts
> system.physmem.perBankRdBursts::15 130315 # Per bank write bursts
> system.physmem.perBankWrBursts::0 65788 # Per bank write bursts
> system.physmem.perBankWrBursts::1 64148 # Per bank write bursts
> system.physmem.perBankWrBursts::2 62323 # Per bank write bursts
> system.physmem.perBankWrBursts::3 62858 # Per bank write bursts
> system.physmem.perBankWrBursts::4 62842 # Per bank write bursts
> system.physmem.perBankWrBursts::5 62926 # Per bank write bursts
> system.physmem.perBankWrBursts::6 64344 # Per bank write bursts
> system.physmem.perBankWrBursts::7 65270 # Per bank write bursts
> system.physmem.perBankWrBursts::8 67114 # Per bank write bursts
> system.physmem.perBankWrBursts::9 67597 # Per bank write bursts
> system.physmem.perBankWrBursts::10 67253 # Per bank write bursts
> system.physmem.perBankWrBursts::11 67655 # Per bank write bursts
> system.physmem.perBankWrBursts::12 67032 # Per bank write bursts
> system.physmem.perBankWrBursts::13 67505 # Per bank write bursts
> system.physmem.perBankWrBursts::14 66189 # Per bank write bursts
> system.physmem.perBankWrBursts::15 65662 # Per bank write bursts
85c85
< system.physmem.totGap 1108725299500 # Total gap between requests
---
> system.physmem.totGap 1121241338000 # Total gap between requests
92c92
< system.physmem.readPktSize::6 2055599 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 2055883 # Read request sizes (log2)
99,102c99,102
< system.physmem.writePktSize::6 1046417 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1922438 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 131799 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1046531 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1926751 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 127772 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see
147,167c147,167
< system.physmem.wrQLenPdf::15 32284 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 33556 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 57018 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 60831 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 61268 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 61505 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 61466 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 61474 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 61478 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 61526 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 61560 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 61560 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 62022 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 62349 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 61672 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 62578 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 61195 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 60970 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 79 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 32090 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 33564 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 56918 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 60994 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 61458 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 61482 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 61483 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 61490 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 61494 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 61503 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 61511 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 61551 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 62299 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 61830 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 61881 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 62640 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 61233 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 60987 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 91 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 15 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
196,213c196,213
< system.physmem.bytesPerActivate::samples 1917383 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 103.495400 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 81.766538 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 125.134212 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 1491936 77.81% 77.81% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 306042 15.96% 93.77% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 52771 2.75% 96.52% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 21239 1.11% 97.63% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 13137 0.69% 98.32% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 7295 0.38% 98.70% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 5316 0.28% 98.98% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 4195 0.22% 99.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 15452 0.81% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1917383 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 60970 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 33.645219 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 157.122880 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 60927 99.93% 99.93% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 1919691 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 103.383938 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 81.729389 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 124.654868 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 1494811 77.87% 77.87% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 305161 15.90% 93.76% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 53151 2.77% 96.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 21323 1.11% 97.64% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 13050 0.68% 98.32% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 7398 0.39% 98.71% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5428 0.28% 98.99% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 5020 0.26% 99.25% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 14349 0.75% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1919691 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 60985 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 33.641650 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 160.664141 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 60945 99.93% 99.93% # Reads before turning the bus around for writes
215c215
< system.physmem.rdPerTurnAround::2048-3071 12 0.02% 99.98% # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes
218,219c218,219
< system.physmem.rdPerTurnAround::9216-10239 2 0.00% 100.00% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
222,239c222,240
< system.physmem.rdPerTurnAround::total 60970 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 60970 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.162408 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.127431 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.097398 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 27276 44.74% 44.74% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 1165 1.91% 46.65% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 28420 46.61% 93.26% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 3653 5.99% 99.25% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 385 0.63% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 61 0.10% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 7 0.01% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::total 60970 # Writes before turning the bus around for reads
< system.physmem.totQLat 38268969000 # Total ticks spent queuing
< system.physmem.totMemAccLat 76786250250 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 10271275000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 18629.12 # Average queueing delay per DRAM burst
---
> system.physmem.rdPerTurnAround::total 60985 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 60985 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.160056 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.125150 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.096252 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 27287 44.74% 44.74% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 1323 2.17% 46.91% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 28176 46.20% 93.11% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 3806 6.24% 99.36% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 330 0.54% 99.90% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 51 0.08% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 9 0.01% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::26 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 60985 # Writes before turning the bus around for reads
> system.physmem.totQLat 38434565750 # Total ticks spent queuing
> system.physmem.totMemAccLat 76957228250 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 10272710000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 18707.12 # Average queueing delay per DRAM burst
241,245c242,246
< system.physmem.avgMemAccLat 37379.12 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 118.58 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 60.40 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 118.66 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 60.40 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 37457.12 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 117.27 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 59.73 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 117.35 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 59.74 # Average system write bandwidth in MiByte/s
247,248c248,249
< system.physmem.busUtil 1.40 # Data bus utilization in percentage
< system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 1.38 # Data bus utilization in percentage
> system.physmem.busUtilRead 0.92 # Data bus utilization in percentage for reads
251,268c252,269
< system.physmem.avgWrQLen 24.62 # Average write queue length when enqueuing
< system.physmem.readRowHits 776845 # Number of row buffer hits during reads
< system.physmem.writeRowHits 406412 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 37.82 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 38.84 # Row buffer hit rate for writes
< system.physmem.avgGap 357420.88 # Average gap between requests
< system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 7070973840 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 3858170250 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 7753512000 # Energy for read commands per rank (pJ)
< system.physmem_0.writeEnergy 3307152240 # Energy for write commands per rank (pJ)
< system.physmem_0.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 416204777970 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 300142086750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 810753074250 # Total energy per rank (pJ)
< system.physmem_0.averagePower 731.249224 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 496624730250 # Time in different power states
< system.physmem_0.memoryStateTime::REF 37022700000 # Time in different power states
---
> system.physmem.avgWrQLen 25.03 # Average write queue length when enqueuing
> system.physmem.readRowHits 774810 # Number of row buffer hits during reads
> system.physmem.writeRowHits 406537 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 37.71 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes
> system.physmem.avgGap 361409.32 # Average gap between requests
> system.physmem.pageHitRate 38.09 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 7080832080 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 3863549250 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 7756031400 # Energy for read commands per rank (pJ)
> system.physmem_0.writeEnergy 3308033520 # Energy for write commands per rank (pJ)
> system.physmem_0.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 422818284195 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 301848259500 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 819908647065 # Total energy per rank (pJ)
> system.physmem_0.averagePower 731.254419 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 499427924250 # Time in different power states
> system.physmem_0.memoryStateTime::REF 37440520000 # Time in different power states
270c271
< system.physmem_0.memoryStateTime::ACT 575075912250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 584369735750 # Time in different power states
272,282c273,283
< system.physmem_1.actEnergy 7424434080 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 4051030500 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 8269419600 # Energy for read commands per rank (pJ)
< system.physmem_1.writeEnergy 3473467920 # Energy for write commands per rank (pJ)
< system.physmem_1.refreshEnergy 72416401200 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 425140731810 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 292303530750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 813079015860 # Total energy per rank (pJ)
< system.physmem_1.averagePower 733.347080 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 483537101750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 37022700000 # Time in different power states
---
> system.physmem_1.actEnergy 7432016760 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 4055167875 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 8269029600 # Energy for read commands per rank (pJ)
> system.physmem_1.writeEnergy 3473325360 # Energy for write commands per rank (pJ)
> system.physmem_1.refreshEnergy 73233657120 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 431345081205 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 294368613000 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 822176890920 # Total energy per rank (pJ)
> system.physmem_1.averagePower 733.277404 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 486933261750 # Time in different power states
> system.physmem_1.memoryStateTime::REF 37440520000 # Time in different power states
284c285
< system.physmem_1.memoryStateTime::ACT 588165429250 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 596864300250 # Time in different power states
286,290c287,291
< system.cpu.branchPred.lookups 240158127 # Number of BP lookups
< system.cpu.branchPred.condPredicted 186758642 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 14604059 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 133657061 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 122306338 # Number of BTB hits
---
> system.cpu.branchPred.lookups 240141363 # Number of BP lookups
> system.cpu.branchPred.condPredicted 186745178 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 14595264 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 132286201 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 122283419 # Number of BTB hits
292,293c293,294
< system.cpu.branchPred.BTBHitPct 91.507577 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 15659556 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 92.438530 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 15659523 # Number of times the RAS was used to get a target.
413c414
< system.cpu.numCycles 2217450776 # number of cpu cycles simulated
---
> system.cpu.numCycles 2242482865 # number of cpu cycles simulated
418c419
< system.cpu.discardedOps 40093383 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 40063389 # Number of ops (including micro ops) which were discarded before commit
420,432c421,433
< system.cpu.cpi 1.435649 # CPI: cycles per instruction
< system.cpu.ipc 0.696549 # IPC: instructions per cycle
< system.cpu.tickCycles 1838812013 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 378638763 # Total number of cycles that the object has spent stopped
< system.cpu.dcache.tags.replacements 9223724 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4085.606596 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 624087400 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 9227820 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 67.631076 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 4085.606596 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.997463 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy
---
> system.cpu.cpi 1.451856 # CPI: cycles per instruction
> system.cpu.ipc 0.688774 # IPC: instructions per cycle
> system.cpu.tickCycles 1838984641 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 403498224 # Total number of cycles that the object has spent stopped
> system.cpu.dcache.tags.replacements 9223361 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4085.642530 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 624067003 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 9227457 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 67.631527 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 9813070000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 4085.642530 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.997471 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.997471 # Average percentage of cache occupancy
434,436c435,437
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 257 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1296 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2482 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 255 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1217 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2563 # Occupied blocks per task id
439,444c440,445
< system.cpu.dcache.tags.tag_accesses 1276555670 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1276555670 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 453740634 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 453740634 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 170346644 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 170346644 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 1276544027 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1276544027 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 453735354 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 453735354 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 170331527 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 170331527 # number of WriteReq hits
449,470c450,471
< system.cpu.dcache.demand_hits::cpu.data 624087278 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 624087278 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 624087278 # number of overall hits
< system.cpu.dcache.overall_hits::total 624087278 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 7337122 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 7337122 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 2239403 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2239403 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 9576525 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9576525 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 9576525 # number of overall misses
< system.cpu.dcache.overall_misses::total 9576525 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 183400270746 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 183400270746 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 101399706750 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 101399706750 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 284799977496 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 284799977496 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 284799977496 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 284799977496 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 461077756 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 461077756 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.data 624066881 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 624066881 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 624066881 # number of overall hits
> system.cpu.dcache.overall_hits::total 624066881 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 7336762 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 7336762 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 2254520 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2254520 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 9591282 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9591282 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 9591282 # number of overall misses
> system.cpu.dcache.overall_misses::total 9591282 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 192442349996 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 192442349996 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 109711138250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 109711138250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 302153488246 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 302153488246 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 302153488246 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 302153488246 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 461072116 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 461072116 # number of ReadReq accesses(hits+misses)
477,496c478,497
< system.cpu.dcache.demand_accesses::cpu.data 633663803 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 633663803 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 633663803 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 633663803 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015913 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.012976 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.015113 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.015113 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.015113 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.015113 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24996.213876 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 24996.213876 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45279.794101 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 45279.794101 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29739.386416 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 29739.386416 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 29739.386416 # average overall miss latency
---
> system.cpu.dcache.demand_accesses::cpu.data 633658163 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 633658163 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 633658163 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 633658163 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.015912 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.015912 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.013063 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.013063 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.015136 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.015136 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.015136 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.015136 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 26229.874977 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 26229.874977 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48662.747835 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 48662.747835 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 31502.930291 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 31502.930291 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 31502.930291 # average overall miss latency
505,532c506,533
< system.cpu.dcache.writebacks::writebacks 3701129 # number of writebacks
< system.cpu.dcache.writebacks::total 3701129 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 221 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 221 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 348484 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 348484 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 348705 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 348705 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 348705 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 348705 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336901 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 7336901 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890919 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1890919 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 9227820 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 9227820 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 9227820 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9227820 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 168309061254 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 168309061254 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 77322111500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 77322111500 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 245631172754 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 245631172754 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 245631172754 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 245631172754 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015913 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.writebacks::writebacks 3701040 # number of writebacks
> system.cpu.dcache.writebacks::total 3701040 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 208 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 208 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 363617 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 363617 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 363825 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 363825 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 363825 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 363825 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7336554 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 7336554 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1890903 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1890903 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 9227457 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 9227457 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 9227457 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9227457 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 181020888504 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 181020888504 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 83976849000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 83976849000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 264997737504 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 264997737504 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 264997737504 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 264997737504 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.015912 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015912 # mshr miss rate for ReadReq accesses
535,546c536,547
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014563 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22940.075279 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22940.075279 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40891.286988 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40891.286988 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26618.548341 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26618.548341 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.014562 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 24673.830317 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 24673.830317 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44410.976660 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44410.976660 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28718.393107 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 28718.393107 # average overall mshr miss latency
548,552c549,553
< system.cpu.icache.tags.replacements 29 # number of replacements
< system.cpu.icache.tags.tagsinuse 661.153981 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 466170177 # Total number of references to valid blocks.
< system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks.
< system.cpu.icache.tags.avg_refs 568500.215854 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.replacements 32 # number of replacements
> system.cpu.icache.tags.tagsinuse 661.433391 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 466139352 # Total number of references to valid blocks.
> system.cpu.icache.tags.sampled_refs 823 # Sample count of references to valid blocks.
> system.cpu.icache.tags.avg_refs 566390.464156 # Average number of references to valid blocks.
554,556c555,557
< system.cpu.icache.tags.occ_blocks::cpu.inst 661.153981 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.322829 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.322829 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 661.433391 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.322966 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.322966 # Average percentage of cache occupancy
559,560c560,561
< system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::2 6 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id
562,587c563,588
< system.cpu.icache.tags.tag_accesses 932342814 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 932342814 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 466170177 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 466170177 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 466170177 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 466170177 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 466170177 # number of overall hits
< system.cpu.icache.overall_hits::total 466170177 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses
< system.cpu.icache.overall_misses::total 820 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 58360249 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 58360249 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 58360249 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 58360249 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 58360249 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 58360249 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 466170997 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 466170997 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 466170997 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 466170997 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 466170997 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 466170997 # number of overall (read+write) accesses
---
> system.cpu.icache.tags.tag_accesses 932281173 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 932281173 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 466139352 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 466139352 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 466139352 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 466139352 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 466139352 # number of overall hits
> system.cpu.icache.overall_hits::total 466139352 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 823 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 823 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 823 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 823 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 823 # number of overall misses
> system.cpu.icache.overall_misses::total 823 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 63715999 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 63715999 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 63715999 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 63715999 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 63715999 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 63715999 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 466140175 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 466140175 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 466140175 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 466140175 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 466140175 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 466140175 # number of overall (read+write) accesses
594,599c595,600
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71171.035366 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 71171.035366 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 71171.035366 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 71171.035366 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 71171.035366 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77419.196841 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 77419.196841 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 77419.196841 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 77419.196841 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 77419.196841 # average overall miss latency
608,619c609,620
< system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses
< system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses
< system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses
< system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
< system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
< system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56400751 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 56400751 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56400751 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 56400751 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56400751 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 56400751 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_misses::cpu.inst 823 # number of ReadReq MSHR misses
> system.cpu.icache.ReadReq_mshr_misses::total 823 # number of ReadReq MSHR misses
> system.cpu.icache.demand_mshr_misses::cpu.inst 823 # number of demand (read+write) MSHR misses
> system.cpu.icache.demand_mshr_misses::total 823 # number of demand (read+write) MSHR misses
> system.cpu.icache.overall_mshr_misses::cpu.inst 823 # number of overall MSHR misses
> system.cpu.icache.overall_mshr_misses::total 823 # number of overall MSHR misses
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 62148501 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 62148501 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 62148501 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 62148501 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 62148501 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 62148501 # number of overall MSHR miss cycles
626,631c627,632
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68781.403659 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68781.403659 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68781.403659 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 68781.403659 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75514.582017 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75514.582017 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75514.582017 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 75514.582017 # average overall mshr miss latency
633,645c634,646
< system.cpu.l2cache.tags.replacements 2022895 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 31254.140512 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 8985448 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2052670 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.377444 # Average number of references to valid blocks.
< system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit.
< system.cpu.l2cache.tags.occ_blocks::writebacks 14999.285776 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.862616 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 16227.992121 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.457742 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000820 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.495239 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.953801 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.replacements 2023178 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 31261.935104 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 8984732 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2052953 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.376492 # Average number of references to valid blocks.
> system.cpu.l2cache.tags.warmup_cycle 59841737750 # Cycle when the warmup percentage was hit.
> system.cpu.l2cache.tags.occ_blocks::writebacks 14973.678994 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 26.751537 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 16261.504573 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.456960 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.000816 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.496262 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.954039 # Average percentage of cache occupancy
649,651c650,652
< system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1247 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12850 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1246 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12852 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15555 # Occupied blocks per task id
653,654c654,655
< system.cpu.l2cache.tags.tag_accesses 107381741 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 107381741 # Number of data accesses
---
> system.cpu.l2cache.tags.tag_accesses 107378416 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 107378416 # Number of data accesses
656,661c657,662
< system.cpu.l2cache.ReadReq_hits::cpu.data 6082181 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 6082213 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 3701129 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 3701129 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.data 1090823 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1090823 # number of ReadExReq hits
---
> system.cpu.l2cache.ReadReq_hits::cpu.data 6081604 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 6081636 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 3701040 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 3701040 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.data 1090756 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1090756 # number of ReadExReq hits
663,664c664,665
< system.cpu.l2cache.demand_hits::cpu.data 7173004 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 7173036 # number of demand (read+write) hits
---
> system.cpu.l2cache.demand_hits::cpu.data 7172360 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 7172392 # number of demand (read+write) hits
666,724c667,725
< system.cpu.l2cache.overall_hits::cpu.data 7173004 # number of overall hits
< system.cpu.l2cache.overall_hits::total 7173036 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 788 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::cpu.data 1254720 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 1255508 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.data 800096 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 800096 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 788 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::cpu.data 2054816 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 2055604 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 788 # number of overall misses
< system.cpu.l2cache.overall_misses::cpu.data 2054816 # number of overall misses
< system.cpu.l2cache.overall_misses::total 2055604 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 55257250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 100145150750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 100200408000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 64467346000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 64467346000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 55257250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 164612496750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 164667754000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 55257250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 164612496750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 164667754000 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 820 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::cpu.data 7336901 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 7337721 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 3701129 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 3701129 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890919 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 1890919 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 820 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::cpu.data 9227820 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 9228640 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 820 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.data 9227820 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 9228640 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960976 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171015 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.171103 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423125 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.423125 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960976 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::cpu.data 0.222676 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960976 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::cpu.data 0.222676 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70123.413706 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79814.740141 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 79808.657531 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80574.513558 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80574.513558 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70123.413706 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80110.577662 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 80106.749160 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70123.413706 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80110.577662 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 80106.749160 # average overall miss latency
---
> system.cpu.l2cache.overall_hits::cpu.data 7172360 # number of overall hits
> system.cpu.l2cache.overall_hits::total 7172392 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 791 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::cpu.data 1254950 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 1255741 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.data 800147 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 800147 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 791 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::cpu.data 2055097 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 2055888 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 791 # number of overall misses
> system.cpu.l2cache.overall_misses::cpu.data 2055097 # number of overall misses
> system.cpu.l2cache.overall_misses::total 2055888 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60988000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 109821544000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 109882532000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 70568051000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 70568051000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 60988000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 180389595000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 180450583000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 60988000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 180389595000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 180450583000 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 823 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::cpu.data 7336554 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 7337377 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 3701040 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 3701040 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.data 1890903 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 1890903 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 823 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::cpu.data 9227457 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 9228280 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 823 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.data 9227457 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 9228280 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.961118 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.171054 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.171143 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.423156 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.423156 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.961118 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::cpu.data 0.222715 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.222781 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.961118 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::cpu.data 0.222715 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.222781 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 77102.402023 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 87510.692856 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 87504.136601 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88193.858129 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88193.858129 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 87772.574673 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77102.402023 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 87776.681587 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 87772.574673 # average overall miss latency
733,734c734,735
< system.cpu.l2cache.writebacks::writebacks 1046417 # number of writebacks
< system.cpu.l2cache.writebacks::total 1046417 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 1046531 # number of writebacks
> system.cpu.l2cache.writebacks::total 1046531 # number of writebacks
744,787c745,788
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 787 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254716 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 1255503 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800096 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 800096 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 787 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.data 2054812 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 2055599 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 787 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.data 2054812 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 2055599 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 45360250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 84287306750 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84332667000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 54391877500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54391877500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 45360250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 138679184250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 138724544500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 45360250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 138679184250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 138724544500 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171014 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171103 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423125 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423125 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.222741 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959756 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222676 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.222741 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57636.912325 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67176.402270 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67170.422532 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67981.689072 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67981.689072 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57636.912325 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67489.962220 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67486.189913 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 790 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1254946 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 1255736 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 800147 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 800147 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 790 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.data 2055093 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 2055883 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 790 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.data 2055093 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 2055883 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 51087500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 93955002000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94006089500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 60459125500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 60459125500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 51087500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 154414127500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 154465215000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 51087500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 154414127500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 154465215000 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.171054 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171142 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.423156 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423156 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.222781 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959903 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.222715 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.222781 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64667.721519 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 74867.764828 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 74861.347847 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 75560.022721 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 75560.022721 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64667.721519 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 75137.294273 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 75133.271203 # average overall mshr miss latency
789,799c790,800
< system.cpu.toL2Bus.trans_dist::ReadReq 7337721 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 7337721 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 3701129 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 1890919 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 1890919 # Transaction distribution
< system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22156769 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 22158409 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827452736 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_size::total 827505216 # Cumulative packet size per connected master and slave (bytes)
---
> system.cpu.toL2Bus.trans_dist::ReadReq 7337377 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 7337377 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 3701040 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 1890903 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 1890903 # Transaction distribution
> system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1646 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22155954 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 22157600 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52672 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827423808 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 827476480 # Cumulative packet size per connected master and slave (bytes)
801,802c802,803
< system.cpu.toL2Bus.snoop_fanout::samples 12929769 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::samples 12929320 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
808,811c809,810
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 12929769 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 12929320 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
813,816c812,815
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::total 12929769 # Request fanout histogram
< system.cpu.toL2Bus.reqLayer0.occupancy 10166013500 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 12929320 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 10165700000 # Layer occupancy (ticks)
818c817
< system.cpu.toL2Bus.respLayer0.occupancy 1389749 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1400999 # Layer occupancy (ticks)
820c819
< system.cpu.toL2Bus.respLayer1.occupancy 14186681246 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 14190167496 # Layer occupancy (ticks)
822,830c821,829
< system.membus.trans_dist::ReadReq 1255503 # Transaction distribution
< system.membus.trans_dist::ReadResp 1255503 # Transaction distribution
< system.membus.trans_dist::Writeback 1046417 # Transaction distribution
< system.membus.trans_dist::ReadExReq 800096 # Transaction distribution
< system.membus.trans_dist::ReadExResp 800096 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157615 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5157615 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198529024 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 198529024 # Cumulative packet size per connected master and slave (bytes)
---
> system.membus.trans_dist::ReadReq 1255736 # Transaction distribution
> system.membus.trans_dist::ReadResp 1255736 # Transaction distribution
> system.membus.trans_dist::Writeback 1046531 # Transaction distribution
> system.membus.trans_dist::ReadExReq 800147 # Transaction distribution
> system.membus.trans_dist::ReadExResp 800147 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5158297 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5158297 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198554496 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 198554496 # Cumulative packet size per connected master and slave (bytes)
832c831
< system.membus.snoop_fanout::samples 3102016 # Request fanout histogram
---
> system.membus.snoop_fanout::samples 3102414 # Request fanout histogram
836c835
< system.membus.snoop_fanout::0 3102016 100.00% 100.00% # Request fanout histogram
---
> system.membus.snoop_fanout::0 3102414 100.00% 100.00% # Request fanout histogram
841,845c840,844
< system.membus.snoop_fanout::total 3102016 # Request fanout histogram
< system.membus.reqLayer0.occupancy 12126859000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.1 # Layer utilization (%)
< system.membus.respLayer1.occupancy 19430032500 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
---
> system.membus.snoop_fanout::total 3102414 # Request fanout histogram
> system.membus.reqLayer0.occupancy 7944829000 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 0.7 # Layer utilization (%)
> system.membus.respLayer1.occupancy 11243795500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 1.0 # Layer utilization (%)