3,5c3,5
< sim_seconds 1.095875 # Number of seconds simulated
< sim_ticks 1095875470500 # Number of ticks simulated
< final_tick 1095875470500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 1.096187 # Number of seconds simulated
> sim_ticks 1096186990500 # Number of ticks simulated
> final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 232088 # Simulator instruction rate (inst/s)
< host_op_rate 250040 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 164667871 # Simulator tick rate (ticks/s)
< host_mem_usage 318056 # Number of bytes of host memory used
< host_seconds 6655.07 # Real time elapsed on the host
---
> host_inst_rate 242878 # Simulator instruction rate (inst/s)
> host_op_rate 261664 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 172372275 # Simulator tick rate (ticks/s)
> host_mem_usage 308000 # Number of bytes of host memory used
> host_seconds 6359.42 # Real time elapsed on the host
16,17c16,17
< system.physmem.bytes_read::cpu.inst 131539072 # Number of bytes read from this memory
< system.physmem.bytes_read::total 131539072 # Number of bytes read from this memory
---
> system.physmem.bytes_read::cpu.inst 131551936 # Number of bytes read from this memory
> system.physmem.bytes_read::total 131551936 # Number of bytes read from this memory
20,44c20,44
< system.physmem.bytes_written::writebacks 66963456 # Number of bytes written to this memory
< system.physmem.bytes_written::total 66963456 # Number of bytes written to this memory
< system.physmem.num_reads::cpu.inst 2055298 # Number of read requests responded to by this memory
< system.physmem.num_reads::total 2055298 # Number of read requests responded to by this memory
< system.physmem.num_writes::writebacks 1046304 # Number of write requests responded to by this memory
< system.physmem.num_writes::total 1046304 # Number of write requests responded to by this memory
< system.physmem.bw_read::cpu.inst 120031040 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 120031040 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 46020 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 46020 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_write::writebacks 61104987 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_write::total 61104987 # Write bandwidth from this memory (bytes/s)
< system.physmem.bw_total::writebacks 61104987 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 120031040 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 181136026 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.readReqs 2055298 # Number of read requests accepted
< system.physmem.writeReqs 1046304 # Number of write requests accepted
< system.physmem.readBursts 2055298 # Number of DRAM read bursts, including those serviced by the write queue
< system.physmem.writeBursts 1046304 # Number of DRAM write bursts, including those merged in the write queue
< system.physmem.bytesReadDRAM 131453056 # Total number of bytes read from DRAM
< system.physmem.bytesReadWrQ 86016 # Total number of bytes read from write queue
< system.physmem.bytesWritten 66961856 # Total number of bytes written to DRAM
< system.physmem.bytesReadSys 131539072 # Total read bytes from the system interface side
< system.physmem.bytesWrittenSys 66963456 # Total written bytes from the system interface side
< system.physmem.servicedByWrQ 1344 # Number of DRAM read bursts serviced by the write queue
---
> system.physmem.bytes_written::writebacks 66968384 # Number of bytes written to this memory
> system.physmem.bytes_written::total 66968384 # Number of bytes written to this memory
> system.physmem.num_reads::cpu.inst 2055499 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 2055499 # Number of read requests responded to by this memory
> system.physmem.num_writes::writebacks 1046381 # Number of write requests responded to by this memory
> system.physmem.num_writes::total 1046381 # Number of write requests responded to by this memory
> system.physmem.bw_read::cpu.inst 120008664 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 120008664 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 46007 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 46007 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_write::writebacks 61092117 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_write::total 61092117 # Write bandwidth from this memory (bytes/s)
> system.physmem.bw_total::writebacks 61092117 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 120008664 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 181100781 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.readReqs 2055499 # Number of read requests accepted
> system.physmem.writeReqs 1046381 # Number of write requests accepted
> system.physmem.readBursts 2055499 # Number of DRAM read bursts, including those serviced by the write queue
> system.physmem.writeBursts 1046381 # Number of DRAM write bursts, including those merged in the write queue
> system.physmem.bytesReadDRAM 131465088 # Total number of bytes read from DRAM
> system.physmem.bytesReadWrQ 86848 # Total number of bytes read from write queue
> system.physmem.bytesWritten 66966784 # Total number of bytes written to DRAM
> system.physmem.bytesReadSys 131551936 # Total read bytes from the system interface side
> system.physmem.bytesWrittenSys 66968384 # Total written bytes from the system interface side
> system.physmem.servicedByWrQ 1357 # Number of DRAM read bursts serviced by the write queue
47,78c47,78
< system.physmem.perBankRdBursts::0 127944 # Per bank write bursts
< system.physmem.perBankRdBursts::1 125151 # Per bank write bursts
< system.physmem.perBankRdBursts::2 122313 # Per bank write bursts
< system.physmem.perBankRdBursts::3 124176 # Per bank write bursts
< system.physmem.perBankRdBursts::4 123203 # Per bank write bursts
< system.physmem.perBankRdBursts::5 123365 # Per bank write bursts
< system.physmem.perBankRdBursts::6 123797 # Per bank write bursts
< system.physmem.perBankRdBursts::7 124247 # Per bank write bursts
< system.physmem.perBankRdBursts::8 131879 # Per bank write bursts
< system.physmem.perBankRdBursts::9 134089 # Per bank write bursts
< system.physmem.perBankRdBursts::10 132451 # Per bank write bursts
< system.physmem.perBankRdBursts::11 133680 # Per bank write bursts
< system.physmem.perBankRdBursts::12 133764 # Per bank write bursts
< system.physmem.perBankRdBursts::13 133810 # Per bank write bursts
< system.physmem.perBankRdBursts::14 129795 # Per bank write bursts
< system.physmem.perBankRdBursts::15 130290 # Per bank write bursts
< system.physmem.perBankWrBursts::0 65788 # Per bank write bursts
< system.physmem.perBankWrBursts::1 64108 # Per bank write bursts
< system.physmem.perBankWrBursts::2 62418 # Per bank write bursts
< system.physmem.perBankWrBursts::3 62855 # Per bank write bursts
< system.physmem.perBankWrBursts::4 62808 # Per bank write bursts
< system.physmem.perBankWrBursts::5 62982 # Per bank write bursts
< system.physmem.perBankWrBursts::6 64271 # Per bank write bursts
< system.physmem.perBankWrBursts::7 65268 # Per bank write bursts
< system.physmem.perBankWrBursts::8 67081 # Per bank write bursts
< system.physmem.perBankWrBursts::9 67609 # Per bank write bursts
< system.physmem.perBankWrBursts::10 67274 # Per bank write bursts
< system.physmem.perBankWrBursts::11 67626 # Per bank write bursts
< system.physmem.perBankWrBursts::12 67000 # Per bank write bursts
< system.physmem.perBankWrBursts::13 67431 # Per bank write bursts
< system.physmem.perBankWrBursts::14 66125 # Per bank write bursts
< system.physmem.perBankWrBursts::15 65635 # Per bank write bursts
---
> system.physmem.perBankRdBursts::0 127914 # Per bank write bursts
> system.physmem.perBankRdBursts::1 125107 # Per bank write bursts
> system.physmem.perBankRdBursts::2 122280 # Per bank write bursts
> system.physmem.perBankRdBursts::3 124254 # Per bank write bursts
> system.physmem.perBankRdBursts::4 123262 # Per bank write bursts
> system.physmem.perBankRdBursts::5 123345 # Per bank write bursts
> system.physmem.perBankRdBursts::6 123865 # Per bank write bursts
> system.physmem.perBankRdBursts::7 124190 # Per bank write bursts
> system.physmem.perBankRdBursts::8 131999 # Per bank write bursts
> system.physmem.perBankRdBursts::9 134064 # Per bank write bursts
> system.physmem.perBankRdBursts::10 132428 # Per bank write bursts
> system.physmem.perBankRdBursts::11 133673 # Per bank write bursts
> system.physmem.perBankRdBursts::12 133725 # Per bank write bursts
> system.physmem.perBankRdBursts::13 133862 # Per bank write bursts
> system.physmem.perBankRdBursts::14 129895 # Per bank write bursts
> system.physmem.perBankRdBursts::15 130279 # Per bank write bursts
> system.physmem.perBankWrBursts::0 65789 # Per bank write bursts
> system.physmem.perBankWrBursts::1 64087 # Per bank write bursts
> system.physmem.perBankWrBursts::2 62403 # Per bank write bursts
> system.physmem.perBankWrBursts::3 62885 # Per bank write bursts
> system.physmem.perBankWrBursts::4 62820 # Per bank write bursts
> system.physmem.perBankWrBursts::5 62979 # Per bank write bursts
> system.physmem.perBankWrBursts::6 64285 # Per bank write bursts
> system.physmem.perBankWrBursts::7 65232 # Per bank write bursts
> system.physmem.perBankWrBursts::8 67082 # Per bank write bursts
> system.physmem.perBankWrBursts::9 67588 # Per bank write bursts
> system.physmem.perBankWrBursts::10 67303 # Per bank write bursts
> system.physmem.perBankWrBursts::11 67613 # Per bank write bursts
> system.physmem.perBankWrBursts::12 67020 # Per bank write bursts
> system.physmem.perBankWrBursts::13 67468 # Per bank write bursts
> system.physmem.perBankWrBursts::14 66169 # Per bank write bursts
> system.physmem.perBankWrBursts::15 65633 # Per bank write bursts
81c81
< system.physmem.totGap 1095875382500 # Total gap between requests
---
> system.physmem.totGap 1096186902500 # Total gap between requests
88c88
< system.physmem.readPktSize::6 2055298 # Read request sizes (log2)
---
> system.physmem.readPktSize::6 2055499 # Read request sizes (log2)
95,97c95,97
< system.physmem.writePktSize::6 1046304 # Write request sizes (log2)
< system.physmem.rdQLenPdf::0 1922424 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 131512 # What read queue length does an incoming req see
---
> system.physmem.writePktSize::6 1046381 # Write request sizes (log2)
> system.physmem.rdQLenPdf::0 1922421 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 131703 # What read queue length does an incoming req see
143,166c143,166
< system.physmem.wrQLenPdf::15 33528 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::16 34841 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::17 57203 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::18 60757 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::19 61403 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::20 61327 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::21 61251 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::22 61258 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::23 61259 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::24 61367 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::25 61289 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::26 61334 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::27 62306 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::28 61683 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::29 61440 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::30 62194 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::31 60945 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::32 60798 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::34 13 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::35 3 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
< system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
---
> system.physmem.wrQLenPdf::15 31796 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::16 33166 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::17 57030 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::18 60853 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::19 61386 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::20 61606 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::21 61543 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::22 61534 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::23 61519 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::24 61592 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::25 61559 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::27 61936 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::28 62305 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::29 61675 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::30 62790 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::31 61332 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::32 61028 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::33 81 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
> system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
192,212c192,212
< system.physmem.bytesPerActivate::samples 1911965 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 103.774418 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 81.877172 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 125.825249 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 1485376 77.69% 77.69% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 306998 16.06% 93.75% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 52789 2.76% 96.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 21060 1.10% 97.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 13283 0.69% 98.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 6873 0.36% 98.66% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 5659 0.30% 98.96% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::896-1023 4134 0.22% 99.17% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 15793 0.83% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 1911965 # Bytes accessed per row activation
< system.physmem.rdPerTurnAround::samples 60795 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::mean 33.737117 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::stdev 161.571664 # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::0-1023 60754 99.93% 99.93% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::1024-2047 14 0.02% 99.96% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::2048-3071 14 0.02% 99.98% # Reads before turning the bus around for writes
< system.physmem.rdPerTurnAround::3072-4095 5 0.01% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.bytesPerActivate::samples 1916158 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 103.556187 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 81.764224 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 125.552714 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 1491113 77.82% 77.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 305811 15.96% 93.78% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 52727 2.75% 96.53% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 21051 1.10% 97.63% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 13077 0.68% 98.31% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 6875 0.36% 98.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 5570 0.29% 98.96% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 4107 0.21% 99.17% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 15827 0.83% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 1916158 # Bytes accessed per row activation
> system.physmem.rdPerTurnAround::samples 61021 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::mean 33.615247 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::stdev 160.737468 # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::0-1023 60978 99.93% 99.93% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::1024-2047 19 0.03% 99.96% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes
> system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes
214c214
< system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
216c216
< system.physmem.rdPerTurnAround::14336-15359 1 0.00% 100.00% # Reads before turning the bus around for writes
---
> system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
218,229c218,229
< system.physmem.rdPerTurnAround::total 60795 # Reads before turning the bus around for writes
< system.physmem.wrPerTurnAround::samples 60795 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::mean 17.209951 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::gmean 17.175292 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::stdev 1.091996 # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::16 25805 42.45% 42.45% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::17 1192 1.96% 44.41% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::18 29551 48.61% 93.01% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::19 3811 6.27% 99.28% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::20 363 0.60% 99.88% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::21 60 0.10% 99.98% # Writes before turning the bus around for reads
< system.physmem.wrPerTurnAround::22 11 0.02% 100.00% # Writes before turning the bus around for reads
---
> system.physmem.rdPerTurnAround::total 61021 # Reads before turning the bus around for writes
> system.physmem.wrPerTurnAround::samples 61021 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::mean 17.147474 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::gmean 17.112394 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::stdev 1.099372 # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::16 27727 45.44% 45.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::17 1223 2.00% 47.44% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::18 27936 45.78% 93.22% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::19 3708 6.08% 99.30% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::20 355 0.58% 99.88% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::21 59 0.10% 99.98% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::22 10 0.02% 100.00% # Writes before turning the bus around for reads
231,235c231,236
< system.physmem.wrPerTurnAround::total 60795 # Writes before turning the bus around for reads
< system.physmem.totQLat 38124649000 # Total ticks spent queuing
< system.physmem.totMemAccLat 76636286500 # Total ticks spent from burst creation until serviced by the DRAM
< system.physmem.totBusLat 10269770000 # Total ticks spent in databus transfers
< system.physmem.avgQLat 18561.59 # Average queueing delay per DRAM burst
---
> system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
> system.physmem.wrPerTurnAround::total 61021 # Writes before turning the bus around for reads
> system.physmem.totQLat 38533876500 # Total ticks spent queuing
> system.physmem.totMemAccLat 77049039000 # Total ticks spent from burst creation until serviced by the DRAM
> system.physmem.totBusLat 10270710000 # Total ticks spent in databus transfers
> system.physmem.avgQLat 18759.11 # Average queueing delay per DRAM burst
237,241c238,242
< system.physmem.avgMemAccLat 37311.59 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 119.95 # Average DRAM read bandwidth in MiByte/s
< system.physmem.avgWrBW 61.10 # Average achieved write bandwidth in MiByte/s
< system.physmem.avgRdBWSys 120.03 # Average system read bandwidth in MiByte/s
< system.physmem.avgWrBWSys 61.10 # Average system write bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 37509.11 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 119.93 # Average DRAM read bandwidth in MiByte/s
> system.physmem.avgWrBW 61.09 # Average achieved write bandwidth in MiByte/s
> system.physmem.avgRdBWSys 120.01 # Average system read bandwidth in MiByte/s
> system.physmem.avgWrBWSys 61.09 # Average system write bandwidth in MiByte/s
247,255c248,256
< system.physmem.avgWrQLen 24.69 # Average write queue length when enqueuing
< system.physmem.readRowHits 779774 # Number of row buffer hits during reads
< system.physmem.writeRowHits 408484 # Number of row buffer hits during writes
< system.physmem.readRowHitRate 37.96 # Row buffer hit rate for reads
< system.physmem.writeRowHitRate 39.04 # Row buffer hit rate for writes
< system.physmem.avgGap 353325.60 # Average gap between requests
< system.physmem.pageHitRate 38.33 # Row buffer hit rate, read and write combined
< system.physmem.memoryStateTime::IDLE 306310282500 # Time in different power states
< system.physmem.memoryStateTime::REF 36593440000 # Time in different power states
---
> system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing
> system.physmem.readRowHits 777772 # Number of row buffer hits during reads
> system.physmem.writeRowHits 406558 # Number of row buffer hits during writes
> system.physmem.readRowHitRate 37.86 # Row buffer hit rate for reads
> system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes
> system.physmem.avgGap 353394.36 # Average gap between requests
> system.physmem.pageHitRate 38.20 # Row buffer hit rate, read and write combined
> system.physmem.memoryStateTime::IDLE 306608104500 # Time in different power states
> system.physmem.memoryStateTime::REF 36603840000 # Time in different power states
257c258
< system.physmem.memoryStateTime::ACT 752968660500 # Time in different power states
---
> system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states
259,271c260,280
< system.membus.throughput 181136026 # Throughput (bytes/s)
< system.membus.trans_dist::ReadReq 1255348 # Transaction distribution
< system.membus.trans_dist::ReadResp 1255348 # Transaction distribution
< system.membus.trans_dist::Writeback 1046304 # Transaction distribution
< system.membus.trans_dist::ReadExReq 799950 # Transaction distribution
< system.membus.trans_dist::ReadExResp 799950 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5156900 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 5156900 # Packet count per connected master and slave (bytes)
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198502528 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 198502528 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 198502528 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.membus.reqLayer0.occupancy 12227667000 # Layer occupancy (ticks)
---
> system.membus.trans_dist::ReadReq 1255486 # Transaction distribution
> system.membus.trans_dist::ReadResp 1255486 # Transaction distribution
> system.membus.trans_dist::Writeback 1046381 # Transaction distribution
> system.membus.trans_dist::ReadExReq 800013 # Transaction distribution
> system.membus.trans_dist::ReadExResp 800013 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157379 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 5157379 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198520320 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 198520320 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 3101880 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 3101880 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 3101880 # Request fanout histogram
> system.membus.reqLayer0.occupancy 12229457500 # Layer occupancy (ticks)
273c282
< system.membus.respLayer1.occupancy 19360882250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 19361348500 # Layer occupancy (ticks)
276,280c285,289
< system.cpu.branchPred.lookups 239641872 # Number of BP lookups
< system.cpu.branchPred.condPredicted 186303374 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 14594643 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 130836287 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 121989290 # Number of BTB hits
---
> system.cpu.branchPred.lookups 239650352 # Number of BP lookups
> system.cpu.branchPred.condPredicted 186306880 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 14598405 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 131764254 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 121991524 # Number of BTB hits
282,283c291,292
< system.cpu.branchPred.BTBHitPct 93.238117 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 15653729 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 92.583171 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 15654227 # Number of times the RAS was used to get a target.
370c379
< system.cpu.numCycles 2191750941 # number of cpu cycles simulated
---
> system.cpu.numCycles 2192373981 # number of cpu cycles simulated
375c384
< system.cpu.discardedOps 42066132 # Number of ops (including micro ops) which were discarded before commit
---
> system.cpu.discardedOps 42081657 # Number of ops (including micro ops) which were discarded before commit
377,380c386,389
< system.cpu.cpi 1.419010 # CPI: cycles per instruction
< system.cpu.ipc 0.704717 # IPC: instructions per cycle
< system.cpu.tickCycles 1808188284 # Number of cycles that the object actually ticked
< system.cpu.idleCycles 383562657 # Total number of cycles that the object has spent stopped
---
> system.cpu.cpi 1.419414 # CPI: cycles per instruction
> system.cpu.ipc 0.704516 # IPC: instructions per cycle
> system.cpu.tickCycles 1808241834 # Number of cycles that the object actually ticked
> system.cpu.idleCycles 384132147 # Total number of cycles that the object has spent stopped
382,383c391,392
< system.cpu.icache.tags.tagsinuse 661.141376 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 464847257 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 661.144399 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 464861353 # Total number of references to valid blocks.
385c394
< system.cpu.icache.tags.avg_refs 566886.898780 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 566904.089024 # Average number of references to valid blocks.
387,389c396,398
< system.cpu.icache.tags.occ_blocks::cpu.inst 661.141376 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.322823 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.322823 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 661.144399 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.322824 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.322824 # Average percentage of cache occupancy
395,402c404,411
< system.cpu.icache.tags.tag_accesses 929696974 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 929696974 # Number of data accesses
< system.cpu.icache.ReadReq_hits::cpu.inst 464847257 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 464847257 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 464847257 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 464847257 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 464847257 # number of overall hits
< system.cpu.icache.overall_hits::total 464847257 # number of overall hits
---
> system.cpu.icache.tags.tag_accesses 929725166 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 929725166 # Number of data accesses
> system.cpu.icache.ReadReq_hits::cpu.inst 464861353 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 464861353 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 464861353 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 464861353 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 464861353 # number of overall hits
> system.cpu.icache.overall_hits::total 464861353 # number of overall hits
409,420c418,429
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 58324499 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 58324499 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 58324499 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 58324499 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 58324499 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 58324499 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 464848077 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 464848077 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 464848077 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 464848077 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 464848077 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 464848077 # number of overall (read+write) accesses
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 59141749 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 59141749 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 59141749 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 59141749 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 59141749 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 59141749 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 464862173 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 464862173 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 464862173 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 464862173 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 464862173 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 464862173 # number of overall (read+write) accesses
427,432c436,441
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71127.437805 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 71127.437805 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 71127.437805 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 71127.437805 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 71127.437805 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72124.084146 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 72124.084146 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 72124.084146 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 72124.084146 # average overall miss latency
447,452c456,461
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 56360501 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 56360501 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56360501 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 56360501 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56360501 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 56360501 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57178251 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 57178251 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57178251 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 57178251 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57178251 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 57178251 # number of overall MSHR miss cycles
459,464c468,473
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68732.318293 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68732.318293 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68732.318293 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 68732.318293 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.574390 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.574390 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency
466,471c475,479
< system.cpu.toL2Bus.throughput 755014954 # Throughput (bytes/s)
< system.cpu.toL2Bus.trans_dist::ReadReq 7336391 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadResp 7336391 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::Writeback 3700895 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExReq 1890876 # Transaction distribution
< system.cpu.toL2Bus.trans_dist::ReadExResp 1890876 # Transaction distribution
---
> system.cpu.toL2Bus.trans_dist::ReadReq 7336783 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadResp 7336783 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::Writeback 3700640 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExReq 1890869 # Transaction distribution
> system.cpu.toL2Bus.trans_dist::ReadExResp 1890869 # Transaction distribution
473,480c481,502
< system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22153789 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.pkt_count::total 22155429 # Packet count per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827349888 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 827402368 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 827402368 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
< system.cpu.toL2Bus.reqLayer0.occupancy 10164976000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22154304 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_count::total 22155944 # Packet count per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827358208 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 827410688 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 12928292 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::5 12928292 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 12928292 # Request fanout histogram
> system.cpu.toL2Bus.reqLayer0.occupancy 10164786000 # Layer occupancy (ticks)
482c504
< system.cpu.toL2Bus.respLayer0.occupancy 1391999 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 1391749 # Layer occupancy (ticks)
484c506
< system.cpu.toL2Bus.respLayer1.occupancy 14185372245 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 14185031745 # Layer occupancy (ticks)
486,490c508,512
< system.cpu.l2cache.tags.replacements 2022594 # number of replacements
< system.cpu.l2cache.tags.tagsinuse 31252.258926 # Cycle average of tags in use
< system.cpu.l2cache.tags.total_refs 8984184 # Total number of references to valid blocks.
< system.cpu.l2cache.tags.sampled_refs 2052369 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 4.377470 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.replacements 2022796 # number of replacements
> system.cpu.l2cache.tags.tagsinuse 31252.383158 # Cycle average of tags in use
> system.cpu.l2cache.tags.total_refs 8984119 # Total number of references to valid blocks.
> system.cpu.l2cache.tags.sampled_refs 2052571 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 4.377008 # Average number of references to valid blocks.
492,496c514,518
< system.cpu.l2cache.tags.occ_blocks::writebacks 14968.183746 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 16284.075180 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.456793 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496951 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.953743 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 14967.342328 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 16285.040830 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.456767 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496980 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.953747 # Average percentage of cache occupancy
504,557c526,579
< system.cpu.l2cache.tags.tag_accesses 107368541 # Number of tag accesses
< system.cpu.l2cache.tags.data_accesses 107368541 # Number of data accesses
< system.cpu.l2cache.ReadReq_hits::cpu.inst 6081037 # number of ReadReq hits
< system.cpu.l2cache.ReadReq_hits::total 6081037 # number of ReadReq hits
< system.cpu.l2cache.Writeback_hits::writebacks 3700895 # number of Writeback hits
< system.cpu.l2cache.Writeback_hits::total 3700895 # number of Writeback hits
< system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090926 # number of ReadExReq hits
< system.cpu.l2cache.ReadExReq_hits::total 1090926 # number of ReadExReq hits
< system.cpu.l2cache.demand_hits::cpu.inst 7171963 # number of demand (read+write) hits
< system.cpu.l2cache.demand_hits::total 7171963 # number of demand (read+write) hits
< system.cpu.l2cache.overall_hits::cpu.inst 7171963 # number of overall hits
< system.cpu.l2cache.overall_hits::total 7171963 # number of overall hits
< system.cpu.l2cache.ReadReq_misses::cpu.inst 1255354 # number of ReadReq misses
< system.cpu.l2cache.ReadReq_misses::total 1255354 # number of ReadReq misses
< system.cpu.l2cache.ReadExReq_misses::cpu.inst 799950 # number of ReadExReq misses
< system.cpu.l2cache.ReadExReq_misses::total 799950 # number of ReadExReq misses
< system.cpu.l2cache.demand_misses::cpu.inst 2055304 # number of demand (read+write) misses
< system.cpu.l2cache.demand_misses::total 2055304 # number of demand (read+write) misses
< system.cpu.l2cache.overall_misses::cpu.inst 2055304 # number of overall misses
< system.cpu.l2cache.overall_misses::total 2055304 # number of overall misses
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100122250500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 100122250500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64358555750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 64358555750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 164480806250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 164480806250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 164480806250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 164480806250 # number of overall miss cycles
< system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336391 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.ReadReq_accesses::total 7336391 # number of ReadReq accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::writebacks 3700895 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.Writeback_accesses::total 3700895 # number of Writeback accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890876 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.ReadExReq_accesses::total 1890876 # number of ReadExReq accesses(hits+misses)
< system.cpu.l2cache.demand_accesses::cpu.inst 9227267 # number of demand (read+write) accesses
< system.cpu.l2cache.demand_accesses::total 9227267 # number of demand (read+write) accesses
< system.cpu.l2cache.overall_accesses::cpu.inst 9227267 # number of overall (read+write) accesses
< system.cpu.l2cache.overall_accesses::total 9227267 # number of overall (read+write) accesses
< system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171113 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_miss_rate::total 0.171113 # miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423058 # miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_miss_rate::total 0.423058 # miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222742 # miss rate for demand accesses
< system.cpu.l2cache.demand_miss_rate::total 0.222742 # miss rate for demand accesses
< system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222742 # miss rate for overall accesses
< system.cpu.l2cache.overall_miss_rate::total 0.222742 # miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79756.188693 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 79756.188693 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80453.223014 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80453.223014 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80027.483161 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 80027.483161 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80027.483161 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 80027.483161 # average overall miss latency
---
> system.cpu.l2cache.tags.tag_accesses 107369776 # Number of tag accesses
> system.cpu.l2cache.tags.data_accesses 107369776 # Number of data accesses
> system.cpu.l2cache.ReadReq_hits::cpu.inst 6081291 # number of ReadReq hits
> system.cpu.l2cache.ReadReq_hits::total 6081291 # number of ReadReq hits
> system.cpu.l2cache.Writeback_hits::writebacks 3700640 # number of Writeback hits
> system.cpu.l2cache.Writeback_hits::total 3700640 # number of Writeback hits
> system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090856 # number of ReadExReq hits
> system.cpu.l2cache.ReadExReq_hits::total 1090856 # number of ReadExReq hits
> system.cpu.l2cache.demand_hits::cpu.inst 7172147 # number of demand (read+write) hits
> system.cpu.l2cache.demand_hits::total 7172147 # number of demand (read+write) hits
> system.cpu.l2cache.overall_hits::cpu.inst 7172147 # number of overall hits
> system.cpu.l2cache.overall_hits::total 7172147 # number of overall hits
> system.cpu.l2cache.ReadReq_misses::cpu.inst 1255492 # number of ReadReq misses
> system.cpu.l2cache.ReadReq_misses::total 1255492 # number of ReadReq misses
> system.cpu.l2cache.ReadExReq_misses::cpu.inst 800013 # number of ReadExReq misses
> system.cpu.l2cache.ReadExReq_misses::total 800013 # number of ReadExReq misses
> system.cpu.l2cache.demand_misses::cpu.inst 2055505 # number of demand (read+write) misses
> system.cpu.l2cache.demand_misses::total 2055505 # number of demand (read+write) misses
> system.cpu.l2cache.overall_misses::cpu.inst 2055505 # number of overall misses
> system.cpu.l2cache.overall_misses::total 2055505 # number of overall misses
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100333400500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 100333400500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64526294750 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 64526294750 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 164859695250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 164859695250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 164859695250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 164859695250 # number of overall miss cycles
> system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336783 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.ReadReq_accesses::total 7336783 # number of ReadReq accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::writebacks 3700640 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.Writeback_accesses::total 3700640 # number of Writeback accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890869 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.ReadExReq_accesses::total 1890869 # number of ReadExReq accesses(hits+misses)
> system.cpu.l2cache.demand_accesses::cpu.inst 9227652 # number of demand (read+write) accesses
> system.cpu.l2cache.demand_accesses::total 9227652 # number of demand (read+write) accesses
> system.cpu.l2cache.overall_accesses::cpu.inst 9227652 # number of overall (read+write) accesses
> system.cpu.l2cache.overall_accesses::total 9227652 # number of overall (read+write) accesses
> system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171123 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_miss_rate::total 0.171123 # miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423093 # miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_miss_rate::total 0.423093 # miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222755 # miss rate for demand accesses
> system.cpu.l2cache.demand_miss_rate::total 0.222755 # miss rate for demand accesses
> system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222755 # miss rate for overall accesses
> system.cpu.l2cache.overall_miss_rate::total 0.222755 # miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79915.603206 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 79915.603206 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.557768 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.557768 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 80203.986490 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 80203.986490 # average overall miss latency
566,567c588,589
< system.cpu.l2cache.writebacks::writebacks 1046304 # number of writebacks
< system.cpu.l2cache.writebacks::total 1046304 # number of writebacks
---
> system.cpu.l2cache.writebacks::writebacks 1046381 # number of writebacks
> system.cpu.l2cache.writebacks::total 1046381 # number of writebacks
574,605c596,627
< system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255348 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadReq_mshr_misses::total 1255348 # number of ReadReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 799950 # number of ReadExReq MSHR misses
< system.cpu.l2cache.ReadExReq_mshr_misses::total 799950 # number of ReadExReq MSHR misses
< system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055298 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.demand_mshr_misses::total 2055298 # number of demand (read+write) MSHR misses
< system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055298 # number of overall MSHR misses
< system.cpu.l2cache.overall_mshr_misses::total 2055298 # number of overall MSHR misses
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84333554000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84333554000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54273221250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54273221250 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138606775250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 138606775250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138606775250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 138606775250 # number of overall MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171112 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171112 # mshr miss rate for ReadReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423058 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423058 # mshr miss rate for ReadExReq accesses
< system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for demand accesses
< system.cpu.l2cache.demand_mshr_miss_rate::total 0.222742 # mshr miss rate for demand accesses
< system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222742 # mshr miss rate for overall accesses
< system.cpu.l2cache.overall_mshr_miss_rate::total 0.222742 # mshr miss rate for overall accesses
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67179.422758 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67179.422758 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 67845.766923 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67845.766923 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67438.772991 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67438.772991 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255486 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadReq_mshr_misses::total 1255486 # number of ReadReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800013 # number of ReadExReq MSHR misses
> system.cpu.l2cache.ReadExReq_mshr_misses::total 800013 # number of ReadExReq MSHR misses
> system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055499 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.demand_mshr_misses::total 2055499 # number of demand (read+write) MSHR misses
> system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055499 # number of overall MSHR misses
> system.cpu.l2cache.overall_mshr_misses::total 2055499 # number of overall MSHR misses
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84544683250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84544683250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54440940250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440940250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138985623500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 138985623500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138985623500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 138985623500 # number of overall MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171122 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171122 # mshr miss rate for ReadReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423093 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423093 # mshr miss rate for ReadExReq accesses
> system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for demand accesses
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.222754 # mshr miss rate for demand accesses
> system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for overall accesses
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.222754 # mshr miss rate for overall accesses
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67340.203913 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67340.203913 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68050.069499 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68050.069499 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency
607,615c629,637
< system.cpu.dcache.tags.replacements 9222351 # number of replacements
< system.cpu.dcache.tags.tagsinuse 4085.559894 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 624001258 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 9226447 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 67.631804 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 9703664000 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.559894 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.inst 0.997451 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.997451 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.replacements 9222736 # number of replacements
> system.cpu.dcache.tags.tagsinuse 4085.561884 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 624006676 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 9226832 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 67.629569 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 9704965000 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.561884 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.inst 0.997452 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.997452 # Average percentage of cache occupancy
617,619c639,641
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 283 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 1314 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::2 2438 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 280 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 1316 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::2 2439 # Occupied blocks per task id
622,627c644,649
< system.cpu.dcache.tags.tag_accesses 1276381727 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 1276381727 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.inst 453655688 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 453655688 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.inst 170345448 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 170345448 # number of WriteReq hits
---
> system.cpu.dcache.tags.tag_accesses 1276393554 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 1276393554 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.inst 453661018 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 453661018 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.inst 170345536 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 170345536 # number of WriteReq hits
632,653c654,675
< system.cpu.dcache.demand_hits::cpu.inst 624001136 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 624001136 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.inst 624001136 # number of overall hits
< system.cpu.dcache.overall_hits::total 624001136 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.inst 7335783 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 7335783 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.inst 2240599 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 2240599 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.inst 9576382 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 9576382 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.inst 9576382 # number of overall misses
< system.cpu.dcache.overall_misses::total 9576382 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183307188995 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 183307188995 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101248592250 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 101248592250 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.inst 284555781245 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 284555781245 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.inst 284555781245 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 284555781245 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.inst 460991471 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 460991471 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_hits::cpu.inst 624006554 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 624006554 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.inst 624006554 # number of overall hits
> system.cpu.dcache.overall_hits::total 624006554 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.inst 7336174 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 7336174 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.inst 2240511 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 2240511 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.inst 9576685 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 9576685 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.inst 9576685 # number of overall misses
> system.cpu.dcache.overall_misses::total 9576685 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183520141245 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 183520141245 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101423015250 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 101423015250 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.inst 284943156495 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 284943156495 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.inst 284943156495 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 284943156495 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.inst 460997192 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 460997192 # number of ReadReq accesses(hits+misses)
660,667c682,689
< system.cpu.dcache.demand_accesses::cpu.inst 633577518 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 633577518 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.inst 633577518 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 633577518 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015913 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.015913 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012983 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.012983 # miss rate for WriteReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.inst 633583239 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 633583239 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.inst 633583239 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 633583239 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012982 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.012982 # miss rate for WriteReq accesses
672,679c694,701
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 24988.087706 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 24988.087706 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45188.180594 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 45188.180594 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 29714.330657 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29714.330657 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 29714.330657 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25015.783601 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 25015.783601 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45267.805090 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 45267.805090 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 29753.840342 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 29753.840342 # average overall miss latency
688,713c710,735
< system.cpu.dcache.writebacks::writebacks 3700895 # number of writebacks
< system.cpu.dcache.writebacks::total 3700895 # number of writebacks
< system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 212 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 212 # number of ReadReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349723 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 349723 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.inst 349935 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 349935 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.inst 349935 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 349935 # number of overall MSHR hits
< system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335571 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 7335571 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890876 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 1890876 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.inst 9226447 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 9226447 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.inst 9226447 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 9226447 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168217924005 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 168217924005 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77187221250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 77187221250 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245405145255 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 245405145255 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245405145255 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 245405145255 # number of overall MSHR miss cycles
---
> system.cpu.dcache.writebacks::writebacks 3700640 # number of writebacks
> system.cpu.dcache.writebacks::total 3700640 # number of writebacks
> system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349642 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 349642 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.inst 349853 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 349853 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.inst 349853 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 349853 # number of overall MSHR hits
> system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335963 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 7335963 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890869 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 1890869 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.inst 9226832 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 9226832 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.inst 9226832 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 9226832 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168431190255 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 168431190255 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77354259500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 77354259500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245785449755 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 245785449755 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245785449755 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 245785449755 # number of overall MSHR miss cycles
718,729c740,751
< system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.014562 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014562 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.014562 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22931.810490 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22931.810490 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40820.879450 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40820.879450 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26598.011700 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 26598.011700 # average overall mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency