1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.096187 # Number of seconds simulated
4sim_ticks 1096186990500 # Number of ticks simulated
5final_tick 1096186990500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 245276 # Simulator instruction rate (inst/s)
8host_op_rate 264248 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 174074375 # Simulator tick rate (ticks/s)
10host_mem_usage 310916 # Number of bytes of host memory used
11host_seconds 6297.23 # Real time elapsed on the host
12sim_insts 1544563087 # Number of instructions simulated
13sim_ops 1664032480 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 131551936 # Number of bytes read from this memory
17system.physmem.bytes_read::total 131551936 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 50432 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 50432 # Number of instructions bytes read from this memory
20system.physmem.bytes_written::writebacks 66968384 # Number of bytes written to this memory
21system.physmem.bytes_written::total 66968384 # Number of bytes written to this memory
22system.physmem.num_reads::cpu.inst 2055499 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 2055499 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 1046381 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 1046381 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 120008664 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 120008664 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 46007 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 46007 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_write::writebacks 61092117 # Write bandwidth from this memory (bytes/s)
31system.physmem.bw_write::total 61092117 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_total::writebacks 61092117 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.bw_total::cpu.inst 120008664 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::total 181100781 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.readReqs 2055499 # Number of read requests accepted
36system.physmem.writeReqs 1046381 # Number of write requests accepted
37system.physmem.readBursts 2055499 # Number of DRAM read bursts, including those serviced by the write queue
38system.physmem.writeBursts 1046381 # Number of DRAM write bursts, including those merged in the write queue
39system.physmem.bytesReadDRAM 131465088 # Total number of bytes read from DRAM
40system.physmem.bytesReadWrQ 86848 # Total number of bytes read from write queue
41system.physmem.bytesWritten 66966784 # Total number of bytes written to DRAM
42system.physmem.bytesReadSys 131551936 # Total read bytes from the system interface side
43system.physmem.bytesWrittenSys 66968384 # Total written bytes from the system interface side
44system.physmem.servicedByWrQ 1357 # Number of DRAM read bursts serviced by the write queue
45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
47system.physmem.perBankRdBursts::0 127914 # Per bank write bursts
48system.physmem.perBankRdBursts::1 125107 # Per bank write bursts
49system.physmem.perBankRdBursts::2 122280 # Per bank write bursts
50system.physmem.perBankRdBursts::3 124254 # Per bank write bursts
51system.physmem.perBankRdBursts::4 123262 # Per bank write bursts
52system.physmem.perBankRdBursts::5 123345 # Per bank write bursts
53system.physmem.perBankRdBursts::6 123865 # Per bank write bursts
54system.physmem.perBankRdBursts::7 124190 # Per bank write bursts
55system.physmem.perBankRdBursts::8 131999 # Per bank write bursts
56system.physmem.perBankRdBursts::9 134064 # Per bank write bursts
57system.physmem.perBankRdBursts::10 132428 # Per bank write bursts
58system.physmem.perBankRdBursts::11 133673 # Per bank write bursts
59system.physmem.perBankRdBursts::12 133725 # Per bank write bursts
60system.physmem.perBankRdBursts::13 133862 # Per bank write bursts
61system.physmem.perBankRdBursts::14 129895 # Per bank write bursts
62system.physmem.perBankRdBursts::15 130279 # Per bank write bursts
63system.physmem.perBankWrBursts::0 65789 # Per bank write bursts
64system.physmem.perBankWrBursts::1 64087 # Per bank write bursts
65system.physmem.perBankWrBursts::2 62403 # Per bank write bursts
66system.physmem.perBankWrBursts::3 62885 # Per bank write bursts
67system.physmem.perBankWrBursts::4 62820 # Per bank write bursts
68system.physmem.perBankWrBursts::5 62979 # Per bank write bursts
69system.physmem.perBankWrBursts::6 64285 # Per bank write bursts
70system.physmem.perBankWrBursts::7 65232 # Per bank write bursts
71system.physmem.perBankWrBursts::8 67082 # Per bank write bursts
72system.physmem.perBankWrBursts::9 67588 # Per bank write bursts
73system.physmem.perBankWrBursts::10 67303 # Per bank write bursts
74system.physmem.perBankWrBursts::11 67613 # Per bank write bursts
75system.physmem.perBankWrBursts::12 67020 # Per bank write bursts
76system.physmem.perBankWrBursts::13 67468 # Per bank write bursts
77system.physmem.perBankWrBursts::14 66169 # Per bank write bursts
78system.physmem.perBankWrBursts::15 65633 # Per bank write bursts
79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
81system.physmem.totGap 1096186902500 # Total gap between requests
82system.physmem.readPktSize::0 0 # Read request sizes (log2)
83system.physmem.readPktSize::1 0 # Read request sizes (log2)
84system.physmem.readPktSize::2 0 # Read request sizes (log2)
85system.physmem.readPktSize::3 0 # Read request sizes (log2)
86system.physmem.readPktSize::4 0 # Read request sizes (log2)
87system.physmem.readPktSize::5 0 # Read request sizes (log2)
88system.physmem.readPktSize::6 2055499 # Read request sizes (log2)
89system.physmem.writePktSize::0 0 # Write request sizes (log2)
90system.physmem.writePktSize::1 0 # Write request sizes (log2)
91system.physmem.writePktSize::2 0 # Write request sizes (log2)
92system.physmem.writePktSize::3 0 # Write request sizes (log2)
93system.physmem.writePktSize::4 0 # Write request sizes (log2)
94system.physmem.writePktSize::5 0 # Write request sizes (log2)
95system.physmem.writePktSize::6 1046381 # Write request sizes (log2)
96system.physmem.rdQLenPdf::0 1922421 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::1 131703 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see

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135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::15 31796 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 33166 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::17 57030 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::18 60853 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::19 61386 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::20 61606 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::21 61543 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::22 61534 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::23 61519 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::24 61592 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 61559 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 61622 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 61936 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 62305 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 61675 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 62790 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 61332 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::32 61028 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::33 81 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::34 8 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::35 2 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see

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184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
192system.physmem.bytesPerActivate::samples 1916158 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::mean 103.556187 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::gmean 81.764224 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::stdev 125.552714 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::0-127 1491113 77.82% 77.82% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::128-255 305811 15.96% 93.78% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::256-383 52727 2.75% 96.53% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::384-511 21051 1.10% 97.63% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::512-639 13077 0.68% 98.31% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::640-767 6875 0.36% 98.67% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::768-895 5570 0.29% 98.96% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::896-1023 4107 0.21% 99.17% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1024-1151 15827 0.83% 100.00% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::total 1916158 # Bytes accessed per row activation
206system.physmem.rdPerTurnAround::samples 61021 # Reads before turning the bus around for writes
207system.physmem.rdPerTurnAround::mean 33.615247 # Reads before turning the bus around for writes
208system.physmem.rdPerTurnAround::stdev 160.737468 # Reads before turning the bus around for writes
209system.physmem.rdPerTurnAround::0-1023 60978 99.93% 99.93% # Reads before turning the bus around for writes
210system.physmem.rdPerTurnAround::1024-2047 19 0.03% 99.96% # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::2048-3071 9 0.01% 99.98% # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::10240-11263 1 0.00% 99.99% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::total 61021 # Reads before turning the bus around for writes
219system.physmem.wrPerTurnAround::samples 61021 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::mean 17.147474 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::gmean 17.112394 # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::stdev 1.099372 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::16 27727 45.44% 45.44% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::17 1223 2.00% 47.44% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::18 27936 45.78% 93.22% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::19 3708 6.08% 99.30% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::20 355 0.58% 99.88% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::21 59 0.10% 99.98% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::22 10 0.02% 100.00% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::23 2 0.00% 100.00% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::28 1 0.00% 100.00% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::total 61021 # Writes before turning the bus around for reads
233system.physmem.totQLat 38533876500 # Total ticks spent queuing
234system.physmem.totMemAccLat 77049039000 # Total ticks spent from burst creation until serviced by the DRAM
235system.physmem.totBusLat 10270710000 # Total ticks spent in databus transfers
236system.physmem.avgQLat 18759.11 # Average queueing delay per DRAM burst
237system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
238system.physmem.avgMemAccLat 37509.11 # Average memory access latency per DRAM burst
239system.physmem.avgRdBW 119.93 # Average DRAM read bandwidth in MiByte/s
240system.physmem.avgWrBW 61.09 # Average achieved write bandwidth in MiByte/s
241system.physmem.avgRdBWSys 120.01 # Average system read bandwidth in MiByte/s
242system.physmem.avgWrBWSys 61.09 # Average system write bandwidth in MiByte/s
243system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
244system.physmem.busUtil 1.41 # Data bus utilization in percentage
245system.physmem.busUtilRead 0.94 # Data bus utilization in percentage for reads
246system.physmem.busUtilWrite 0.48 # Data bus utilization in percentage for writes
247system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
248system.physmem.avgWrQLen 24.88 # Average write queue length when enqueuing
249system.physmem.readRowHits 777772 # Number of row buffer hits during reads
250system.physmem.writeRowHits 406558 # Number of row buffer hits during writes
251system.physmem.readRowHitRate 37.86 # Row buffer hit rate for reads
252system.physmem.writeRowHitRate 38.85 # Row buffer hit rate for writes
253system.physmem.avgGap 353394.36 # Average gap between requests
254system.physmem.pageHitRate 38.20 # Row buffer hit rate, read and write combined
255system.physmem.memoryStateTime::IDLE 306608104500 # Time in different power states
256system.physmem.memoryStateTime::REF 36603840000 # Time in different power states
257system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
258system.physmem.memoryStateTime::ACT 752971887000 # Time in different power states
259system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
260system.physmem.actEnergy::0 7068978000 # Energy for activate commands per rank (pJ)
261system.physmem.actEnergy::1 7417161360 # Energy for activate commands per rank (pJ)
262system.physmem.preEnergy::0 3857081250 # Energy for precharge commands per rank (pJ)
263system.physmem.preEnergy::1 4047062250 # Energy for precharge commands per rank (pJ)
264system.physmem.readEnergy::0 7754580600 # Energy for read commands per rank (pJ)
265system.physmem.readEnergy::1 8267360400 # Energy for read commands per rank (pJ)
266system.physmem.writeEnergy::0 3307910400 # Energy for write commands per rank (pJ)
267system.physmem.writeEnergy::1 3472476480 # Energy for write commands per rank (pJ)
268system.physmem.refreshEnergy::0 71597111040 # Energy for refresh commands per rank (pJ)
269system.physmem.refreshEnergy::1 71597111040 # Energy for refresh commands per rank (pJ)
270system.physmem.actBackEnergy::0 413628192720 # Energy for active background per rank (pJ)
271system.physmem.actBackEnergy::1 422690389875 # Energy for active background per rank (pJ)
272system.physmem.preBackEnergy::0 294876051750 # Energy for precharge background per rank (pJ)
273system.physmem.preBackEnergy::1 286926756000 # Energy for precharge background per rank (pJ)
274system.physmem.totalEnergy::0 802089905760 # Total energy per rank (pJ)
275system.physmem.totalEnergy::1 804418317405 # Total energy per rank (pJ)
276system.physmem.averagePower::0 731.713906 # Core power per rank (mW)
277system.physmem.averagePower::1 733.838021 # Core power per rank (mW)
278system.membus.trans_dist::ReadReq 1255486 # Transaction distribution
279system.membus.trans_dist::ReadResp 1255486 # Transaction distribution
280system.membus.trans_dist::Writeback 1046381 # Transaction distribution
281system.membus.trans_dist::ReadExReq 800013 # Transaction distribution
282system.membus.trans_dist::ReadExResp 800013 # Transaction distribution
283system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5157379 # Packet count per connected master and slave (bytes)
284system.membus.pkt_count::total 5157379 # Packet count per connected master and slave (bytes)
285system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198520320 # Cumulative packet size per connected master and slave (bytes)
286system.membus.pkt_size::total 198520320 # Cumulative packet size per connected master and slave (bytes)
287system.membus.snoops 0 # Total snoops (count)
288system.membus.snoop_fanout::samples 3101880 # Request fanout histogram
289system.membus.snoop_fanout::mean 0 # Request fanout histogram
290system.membus.snoop_fanout::stdev 0 # Request fanout histogram
291system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
292system.membus.snoop_fanout::0 3101880 100.00% 100.00% # Request fanout histogram
293system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
294system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
295system.membus.snoop_fanout::min_value 0 # Request fanout histogram
296system.membus.snoop_fanout::max_value 0 # Request fanout histogram
297system.membus.snoop_fanout::total 3101880 # Request fanout histogram
298system.membus.reqLayer0.occupancy 12229457500 # Layer occupancy (ticks)
299system.membus.reqLayer0.utilization 1.1 # Layer utilization (%)
300system.membus.respLayer1.occupancy 19361348500 # Layer occupancy (ticks)
301system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
302system.cpu_clk_domain.clock 500 # Clock period in ticks
303system.cpu.branchPred.lookups 239650352 # Number of BP lookups
304system.cpu.branchPred.condPredicted 186306880 # Number of conditional branches predicted
305system.cpu.branchPred.condIncorrect 14598405 # Number of conditional branches incorrect
306system.cpu.branchPred.BTBLookups 131764254 # Number of BTB lookups
307system.cpu.branchPred.BTBHits 121991524 # Number of BTB hits
308system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
309system.cpu.branchPred.BTBHitPct 92.583171 # BTB Hit Percentage
310system.cpu.branchPred.usedRAS 15654227 # Number of times the RAS was used to get a target.
311system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
312system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
313system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
314system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
315system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
316system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
317system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
318system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
319system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

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389system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
390system.cpu.itb.read_accesses 0 # DTB read accesses
391system.cpu.itb.write_accesses 0 # DTB write accesses
392system.cpu.itb.inst_accesses 0 # ITB inst accesses
393system.cpu.itb.hits 0 # DTB hits
394system.cpu.itb.misses 0 # DTB misses
395system.cpu.itb.accesses 0 # DTB accesses
396system.cpu.workload.num_syscalls 46 # Number of system calls
397system.cpu.numCycles 2192373981 # number of cpu cycles simulated
398system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
399system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
400system.cpu.committedInsts 1544563087 # Number of instructions committed
401system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed
402system.cpu.discardedOps 42081657 # Number of ops (including micro ops) which were discarded before commit
403system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
404system.cpu.cpi 1.419414 # CPI: cycles per instruction
405system.cpu.ipc 0.704516 # IPC: instructions per cycle
406system.cpu.tickCycles 1808241834 # Number of cycles that the object actually ticked
407system.cpu.idleCycles 384132147 # Total number of cycles that the object has spent stopped
408system.cpu.icache.tags.replacements 29 # number of replacements
409system.cpu.icache.tags.tagsinuse 661.144399 # Cycle average of tags in use
410system.cpu.icache.tags.total_refs 464861353 # Total number of references to valid blocks.
411system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks.
412system.cpu.icache.tags.avg_refs 566904.089024 # Average number of references to valid blocks.
413system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
414system.cpu.icache.tags.occ_blocks::cpu.inst 661.144399 # Average occupied blocks per requestor
415system.cpu.icache.tags.occ_percent::cpu.inst 0.322824 # Average percentage of cache occupancy
416system.cpu.icache.tags.occ_percent::total 0.322824 # Average percentage of cache occupancy
417system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id
418system.cpu.icache.tags.age_task_id_blocks_1024::0 32 # Occupied blocks per task id
419system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
420system.cpu.icache.tags.age_task_id_blocks_1024::4 754 # Occupied blocks per task id
421system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id
422system.cpu.icache.tags.tag_accesses 929725166 # Number of tag accesses
423system.cpu.icache.tags.data_accesses 929725166 # Number of data accesses
424system.cpu.icache.ReadReq_hits::cpu.inst 464861353 # number of ReadReq hits
425system.cpu.icache.ReadReq_hits::total 464861353 # number of ReadReq hits
426system.cpu.icache.demand_hits::cpu.inst 464861353 # number of demand (read+write) hits
427system.cpu.icache.demand_hits::total 464861353 # number of demand (read+write) hits
428system.cpu.icache.overall_hits::cpu.inst 464861353 # number of overall hits
429system.cpu.icache.overall_hits::total 464861353 # number of overall hits
430system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses
431system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses
432system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses
433system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses
434system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses
435system.cpu.icache.overall_misses::total 820 # number of overall misses
436system.cpu.icache.ReadReq_miss_latency::cpu.inst 59141749 # number of ReadReq miss cycles
437system.cpu.icache.ReadReq_miss_latency::total 59141749 # number of ReadReq miss cycles
438system.cpu.icache.demand_miss_latency::cpu.inst 59141749 # number of demand (read+write) miss cycles
439system.cpu.icache.demand_miss_latency::total 59141749 # number of demand (read+write) miss cycles
440system.cpu.icache.overall_miss_latency::cpu.inst 59141749 # number of overall miss cycles
441system.cpu.icache.overall_miss_latency::total 59141749 # number of overall miss cycles
442system.cpu.icache.ReadReq_accesses::cpu.inst 464862173 # number of ReadReq accesses(hits+misses)
443system.cpu.icache.ReadReq_accesses::total 464862173 # number of ReadReq accesses(hits+misses)
444system.cpu.icache.demand_accesses::cpu.inst 464862173 # number of demand (read+write) accesses
445system.cpu.icache.demand_accesses::total 464862173 # number of demand (read+write) accesses
446system.cpu.icache.overall_accesses::cpu.inst 464862173 # number of overall (read+write) accesses
447system.cpu.icache.overall_accesses::total 464862173 # number of overall (read+write) accesses
448system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000002 # miss rate for ReadReq accesses
449system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
450system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
451system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
452system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
453system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
454system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72124.084146 # average ReadReq miss latency
455system.cpu.icache.ReadReq_avg_miss_latency::total 72124.084146 # average ReadReq miss latency
456system.cpu.icache.demand_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency
457system.cpu.icache.demand_avg_miss_latency::total 72124.084146 # average overall miss latency
458system.cpu.icache.overall_avg_miss_latency::cpu.inst 72124.084146 # average overall miss latency
459system.cpu.icache.overall_avg_miss_latency::total 72124.084146 # average overall miss latency
460system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
461system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
462system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
463system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
464system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
465system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
466system.cpu.icache.fast_writes 0 # number of fast writes performed
467system.cpu.icache.cache_copies 0 # number of cache copies performed
468system.cpu.icache.ReadReq_mshr_misses::cpu.inst 820 # number of ReadReq MSHR misses
469system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses
470system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses
471system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
472system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
473system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
474system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 57178251 # number of ReadReq MSHR miss cycles
475system.cpu.icache.ReadReq_mshr_miss_latency::total 57178251 # number of ReadReq MSHR miss cycles
476system.cpu.icache.demand_mshr_miss_latency::cpu.inst 57178251 # number of demand (read+write) MSHR miss cycles
477system.cpu.icache.demand_mshr_miss_latency::total 57178251 # number of demand (read+write) MSHR miss cycles
478system.cpu.icache.overall_mshr_miss_latency::cpu.inst 57178251 # number of overall MSHR miss cycles
479system.cpu.icache.overall_mshr_miss_latency::total 57178251 # number of overall MSHR miss cycles
480system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
481system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000002 # mshr miss rate for ReadReq accesses
482system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
483system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
484system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
485system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
486system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69729.574390 # average ReadReq mshr miss latency
487system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69729.574390 # average ReadReq mshr miss latency
488system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency
489system.cpu.icache.demand_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency
490system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69729.574390 # average overall mshr miss latency
491system.cpu.icache.overall_avg_mshr_miss_latency::total 69729.574390 # average overall mshr miss latency
492system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
493system.cpu.toL2Bus.trans_dist::ReadReq 7336783 # Transaction distribution
494system.cpu.toL2Bus.trans_dist::ReadResp 7336783 # Transaction distribution
495system.cpu.toL2Bus.trans_dist::Writeback 3700640 # Transaction distribution
496system.cpu.toL2Bus.trans_dist::ReadExReq 1890869 # Transaction distribution
497system.cpu.toL2Bus.trans_dist::ReadExResp 1890869 # Transaction distribution
498system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes)
499system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22154304 # Packet count per connected master and slave (bytes)
500system.cpu.toL2Bus.pkt_count::total 22155944 # Packet count per connected master and slave (bytes)
501system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes)
502system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827358208 # Cumulative packet size per connected master and slave (bytes)
503system.cpu.toL2Bus.pkt_size::total 827410688 # Cumulative packet size per connected master and slave (bytes)
504system.cpu.toL2Bus.snoops 0 # Total snoops (count)
505system.cpu.toL2Bus.snoop_fanout::samples 12928292 # Request fanout histogram
506system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
507system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
508system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
509system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
510system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
511system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
512system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
513system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
514system.cpu.toL2Bus.snoop_fanout::5 12928292 100.00% 100.00% # Request fanout histogram
515system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
516system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
517system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
518system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
519system.cpu.toL2Bus.snoop_fanout::total 12928292 # Request fanout histogram
520system.cpu.toL2Bus.reqLayer0.occupancy 10164786000 # Layer occupancy (ticks)
521system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
522system.cpu.toL2Bus.respLayer0.occupancy 1391749 # Layer occupancy (ticks)
523system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
524system.cpu.toL2Bus.respLayer1.occupancy 14185031745 # Layer occupancy (ticks)
525system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
526system.cpu.l2cache.tags.replacements 2022796 # number of replacements
527system.cpu.l2cache.tags.tagsinuse 31252.383158 # Cycle average of tags in use
528system.cpu.l2cache.tags.total_refs 8984119 # Total number of references to valid blocks.
529system.cpu.l2cache.tags.sampled_refs 2052571 # Sample count of references to valid blocks.
530system.cpu.l2cache.tags.avg_refs 4.377008 # Average number of references to valid blocks.
531system.cpu.l2cache.tags.warmup_cycle 58953869250 # Cycle when the warmup percentage was hit.
532system.cpu.l2cache.tags.occ_blocks::writebacks 14967.342328 # Average occupied blocks per requestor
533system.cpu.l2cache.tags.occ_blocks::cpu.inst 16285.040830 # Average occupied blocks per requestor
534system.cpu.l2cache.tags.occ_percent::writebacks 0.456767 # Average percentage of cache occupancy
535system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496980 # Average percentage of cache occupancy
536system.cpu.l2cache.tags.occ_percent::total 0.953747 # Average percentage of cache occupancy
537system.cpu.l2cache.tags.occ_task_id_blocks::1024 29775 # Occupied blocks per task id
538system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id
539system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
540system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id
541system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
542system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id
543system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908661 # Percentage of cache occupancy per task id
544system.cpu.l2cache.tags.tag_accesses 107369776 # Number of tag accesses
545system.cpu.l2cache.tags.data_accesses 107369776 # Number of data accesses
546system.cpu.l2cache.ReadReq_hits::cpu.inst 6081291 # number of ReadReq hits
547system.cpu.l2cache.ReadReq_hits::total 6081291 # number of ReadReq hits
548system.cpu.l2cache.Writeback_hits::writebacks 3700640 # number of Writeback hits
549system.cpu.l2cache.Writeback_hits::total 3700640 # number of Writeback hits
550system.cpu.l2cache.ReadExReq_hits::cpu.inst 1090856 # number of ReadExReq hits
551system.cpu.l2cache.ReadExReq_hits::total 1090856 # number of ReadExReq hits
552system.cpu.l2cache.demand_hits::cpu.inst 7172147 # number of demand (read+write) hits
553system.cpu.l2cache.demand_hits::total 7172147 # number of demand (read+write) hits
554system.cpu.l2cache.overall_hits::cpu.inst 7172147 # number of overall hits
555system.cpu.l2cache.overall_hits::total 7172147 # number of overall hits
556system.cpu.l2cache.ReadReq_misses::cpu.inst 1255492 # number of ReadReq misses
557system.cpu.l2cache.ReadReq_misses::total 1255492 # number of ReadReq misses
558system.cpu.l2cache.ReadExReq_misses::cpu.inst 800013 # number of ReadExReq misses
559system.cpu.l2cache.ReadExReq_misses::total 800013 # number of ReadExReq misses
560system.cpu.l2cache.demand_misses::cpu.inst 2055505 # number of demand (read+write) misses
561system.cpu.l2cache.demand_misses::total 2055505 # number of demand (read+write) misses
562system.cpu.l2cache.overall_misses::cpu.inst 2055505 # number of overall misses
563system.cpu.l2cache.overall_misses::total 2055505 # number of overall misses
564system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100333400500 # number of ReadReq miss cycles
565system.cpu.l2cache.ReadReq_miss_latency::total 100333400500 # number of ReadReq miss cycles
566system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst 64526294750 # number of ReadExReq miss cycles
567system.cpu.l2cache.ReadExReq_miss_latency::total 64526294750 # number of ReadExReq miss cycles
568system.cpu.l2cache.demand_miss_latency::cpu.inst 164859695250 # number of demand (read+write) miss cycles
569system.cpu.l2cache.demand_miss_latency::total 164859695250 # number of demand (read+write) miss cycles
570system.cpu.l2cache.overall_miss_latency::cpu.inst 164859695250 # number of overall miss cycles
571system.cpu.l2cache.overall_miss_latency::total 164859695250 # number of overall miss cycles
572system.cpu.l2cache.ReadReq_accesses::cpu.inst 7336783 # number of ReadReq accesses(hits+misses)
573system.cpu.l2cache.ReadReq_accesses::total 7336783 # number of ReadReq accesses(hits+misses)
574system.cpu.l2cache.Writeback_accesses::writebacks 3700640 # number of Writeback accesses(hits+misses)
575system.cpu.l2cache.Writeback_accesses::total 3700640 # number of Writeback accesses(hits+misses)
576system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890869 # number of ReadExReq accesses(hits+misses)
577system.cpu.l2cache.ReadExReq_accesses::total 1890869 # number of ReadExReq accesses(hits+misses)
578system.cpu.l2cache.demand_accesses::cpu.inst 9227652 # number of demand (read+write) accesses
579system.cpu.l2cache.demand_accesses::total 9227652 # number of demand (read+write) accesses
580system.cpu.l2cache.overall_accesses::cpu.inst 9227652 # number of overall (read+write) accesses
581system.cpu.l2cache.overall_accesses::total 9227652 # number of overall (read+write) accesses
582system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171123 # miss rate for ReadReq accesses
583system.cpu.l2cache.ReadReq_miss_rate::total 0.171123 # miss rate for ReadReq accesses
584system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423093 # miss rate for ReadExReq accesses
585system.cpu.l2cache.ReadExReq_miss_rate::total 0.423093 # miss rate for ReadExReq accesses
586system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222755 # miss rate for demand accesses
587system.cpu.l2cache.demand_miss_rate::total 0.222755 # miss rate for demand accesses
588system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222755 # miss rate for overall accesses
589system.cpu.l2cache.overall_miss_rate::total 0.222755 # miss rate for overall accesses
590system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79915.603206 # average ReadReq miss latency
591system.cpu.l2cache.ReadReq_avg_miss_latency::total 79915.603206 # average ReadReq miss latency
592system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80656.557768 # average ReadExReq miss latency
593system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80656.557768 # average ReadExReq miss latency
594system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency
595system.cpu.l2cache.demand_avg_miss_latency::total 80203.986490 # average overall miss latency
596system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80203.986490 # average overall miss latency
597system.cpu.l2cache.overall_avg_miss_latency::total 80203.986490 # average overall miss latency
598system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
599system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
600system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
601system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
602system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
603system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
604system.cpu.l2cache.fast_writes 0 # number of fast writes performed
605system.cpu.l2cache.cache_copies 0 # number of cache copies performed
606system.cpu.l2cache.writebacks::writebacks 1046381 # number of writebacks
607system.cpu.l2cache.writebacks::total 1046381 # number of writebacks
608system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 6 # number of ReadReq MSHR hits
609system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits
610system.cpu.l2cache.demand_mshr_hits::cpu.inst 6 # number of demand (read+write) MSHR hits
611system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits
612system.cpu.l2cache.overall_mshr_hits::cpu.inst 6 # number of overall MSHR hits
613system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits
614system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1255486 # number of ReadReq MSHR misses
615system.cpu.l2cache.ReadReq_mshr_misses::total 1255486 # number of ReadReq MSHR misses
616system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800013 # number of ReadExReq MSHR misses
617system.cpu.l2cache.ReadExReq_mshr_misses::total 800013 # number of ReadExReq MSHR misses
618system.cpu.l2cache.demand_mshr_misses::cpu.inst 2055499 # number of demand (read+write) MSHR misses
619system.cpu.l2cache.demand_mshr_misses::total 2055499 # number of demand (read+write) MSHR misses
620system.cpu.l2cache.overall_mshr_misses::cpu.inst 2055499 # number of overall MSHR misses
621system.cpu.l2cache.overall_mshr_misses::total 2055499 # number of overall MSHR misses
622system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84544683250 # number of ReadReq MSHR miss cycles
623system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84544683250 # number of ReadReq MSHR miss cycles
624system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54440940250 # number of ReadExReq MSHR miss cycles
625system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54440940250 # number of ReadExReq MSHR miss cycles
626system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 138985623500 # number of demand (read+write) MSHR miss cycles
627system.cpu.l2cache.demand_mshr_miss_latency::total 138985623500 # number of demand (read+write) MSHR miss cycles
628system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 138985623500 # number of overall MSHR miss cycles
629system.cpu.l2cache.overall_mshr_miss_latency::total 138985623500 # number of overall MSHR miss cycles
630system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171122 # mshr miss rate for ReadReq accesses
631system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171122 # mshr miss rate for ReadReq accesses
632system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423093 # mshr miss rate for ReadExReq accesses
633system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423093 # mshr miss rate for ReadExReq accesses
634system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for demand accesses
635system.cpu.l2cache.demand_mshr_miss_rate::total 0.222754 # mshr miss rate for demand accesses
636system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222754 # mshr miss rate for overall accesses
637system.cpu.l2cache.overall_mshr_miss_rate::total 0.222754 # mshr miss rate for overall accesses
638system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67340.203913 # average ReadReq mshr miss latency
639system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67340.203913 # average ReadReq mshr miss latency
640system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68050.069499 # average ReadExReq mshr miss latency
641system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68050.069499 # average ReadExReq mshr miss latency
642system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency
643system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency
644system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67616.488016 # average overall mshr miss latency
645system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67616.488016 # average overall mshr miss latency
646system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
647system.cpu.dcache.tags.replacements 9222736 # number of replacements
648system.cpu.dcache.tags.tagsinuse 4085.561884 # Cycle average of tags in use
649system.cpu.dcache.tags.total_refs 624006676 # Total number of references to valid blocks.
650system.cpu.dcache.tags.sampled_refs 9226832 # Sample count of references to valid blocks.
651system.cpu.dcache.tags.avg_refs 67.629569 # Average number of references to valid blocks.
652system.cpu.dcache.tags.warmup_cycle 9704965000 # Cycle when the warmup percentage was hit.
653system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.561884 # Average occupied blocks per requestor
654system.cpu.dcache.tags.occ_percent::cpu.inst 0.997452 # Average percentage of cache occupancy
655system.cpu.dcache.tags.occ_percent::total 0.997452 # Average percentage of cache occupancy
656system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
657system.cpu.dcache.tags.age_task_id_blocks_1024::0 280 # Occupied blocks per task id
658system.cpu.dcache.tags.age_task_id_blocks_1024::1 1316 # Occupied blocks per task id
659system.cpu.dcache.tags.age_task_id_blocks_1024::2 2439 # Occupied blocks per task id
660system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
661system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
662system.cpu.dcache.tags.tag_accesses 1276393554 # Number of tag accesses
663system.cpu.dcache.tags.data_accesses 1276393554 # Number of data accesses
664system.cpu.dcache.ReadReq_hits::cpu.inst 453661018 # number of ReadReq hits
665system.cpu.dcache.ReadReq_hits::total 453661018 # number of ReadReq hits
666system.cpu.dcache.WriteReq_hits::cpu.inst 170345536 # number of WriteReq hits
667system.cpu.dcache.WriteReq_hits::total 170345536 # number of WriteReq hits
668system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits
669system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
670system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits
671system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
672system.cpu.dcache.demand_hits::cpu.inst 624006554 # number of demand (read+write) hits
673system.cpu.dcache.demand_hits::total 624006554 # number of demand (read+write) hits
674system.cpu.dcache.overall_hits::cpu.inst 624006554 # number of overall hits
675system.cpu.dcache.overall_hits::total 624006554 # number of overall hits
676system.cpu.dcache.ReadReq_misses::cpu.inst 7336174 # number of ReadReq misses
677system.cpu.dcache.ReadReq_misses::total 7336174 # number of ReadReq misses
678system.cpu.dcache.WriteReq_misses::cpu.inst 2240511 # number of WriteReq misses
679system.cpu.dcache.WriteReq_misses::total 2240511 # number of WriteReq misses
680system.cpu.dcache.demand_misses::cpu.inst 9576685 # number of demand (read+write) misses
681system.cpu.dcache.demand_misses::total 9576685 # number of demand (read+write) misses
682system.cpu.dcache.overall_misses::cpu.inst 9576685 # number of overall misses
683system.cpu.dcache.overall_misses::total 9576685 # number of overall misses
684system.cpu.dcache.ReadReq_miss_latency::cpu.inst 183520141245 # number of ReadReq miss cycles
685system.cpu.dcache.ReadReq_miss_latency::total 183520141245 # number of ReadReq miss cycles
686system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101423015250 # number of WriteReq miss cycles
687system.cpu.dcache.WriteReq_miss_latency::total 101423015250 # number of WriteReq miss cycles
688system.cpu.dcache.demand_miss_latency::cpu.inst 284943156495 # number of demand (read+write) miss cycles
689system.cpu.dcache.demand_miss_latency::total 284943156495 # number of demand (read+write) miss cycles
690system.cpu.dcache.overall_miss_latency::cpu.inst 284943156495 # number of overall miss cycles
691system.cpu.dcache.overall_miss_latency::total 284943156495 # number of overall miss cycles
692system.cpu.dcache.ReadReq_accesses::cpu.inst 460997192 # number of ReadReq accesses(hits+misses)
693system.cpu.dcache.ReadReq_accesses::total 460997192 # number of ReadReq accesses(hits+misses)
694system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses)
695system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
696system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses)
697system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
698system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses)
699system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
700system.cpu.dcache.demand_accesses::cpu.inst 633583239 # number of demand (read+write) accesses
701system.cpu.dcache.demand_accesses::total 633583239 # number of demand (read+write) accesses
702system.cpu.dcache.overall_accesses::cpu.inst 633583239 # number of overall (read+write) accesses
703system.cpu.dcache.overall_accesses::total 633583239 # number of overall (read+write) accesses
704system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.015914 # miss rate for ReadReq accesses
705system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses
706system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012982 # miss rate for WriteReq accesses
707system.cpu.dcache.WriteReq_miss_rate::total 0.012982 # miss rate for WriteReq accesses
708system.cpu.dcache.demand_miss_rate::cpu.inst 0.015115 # miss rate for demand accesses
709system.cpu.dcache.demand_miss_rate::total 0.015115 # miss rate for demand accesses
710system.cpu.dcache.overall_miss_rate::cpu.inst 0.015115 # miss rate for overall accesses
711system.cpu.dcache.overall_miss_rate::total 0.015115 # miss rate for overall accesses
712system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25015.783601 # average ReadReq miss latency
713system.cpu.dcache.ReadReq_avg_miss_latency::total 25015.783601 # average ReadReq miss latency
714system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45267.805090 # average WriteReq miss latency
715system.cpu.dcache.WriteReq_avg_miss_latency::total 45267.805090 # average WriteReq miss latency
716system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency
717system.cpu.dcache.demand_avg_miss_latency::total 29753.840342 # average overall miss latency
718system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29753.840342 # average overall miss latency
719system.cpu.dcache.overall_avg_miss_latency::total 29753.840342 # average overall miss latency
720system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
721system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
722system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
723system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
724system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
725system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
726system.cpu.dcache.fast_writes 0 # number of fast writes performed
727system.cpu.dcache.cache_copies 0 # number of cache copies performed
728system.cpu.dcache.writebacks::writebacks 3700640 # number of writebacks
729system.cpu.dcache.writebacks::total 3700640 # number of writebacks
730system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 211 # number of ReadReq MSHR hits
731system.cpu.dcache.ReadReq_mshr_hits::total 211 # number of ReadReq MSHR hits
732system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 349642 # number of WriteReq MSHR hits
733system.cpu.dcache.WriteReq_mshr_hits::total 349642 # number of WriteReq MSHR hits
734system.cpu.dcache.demand_mshr_hits::cpu.inst 349853 # number of demand (read+write) MSHR hits
735system.cpu.dcache.demand_mshr_hits::total 349853 # number of demand (read+write) MSHR hits
736system.cpu.dcache.overall_mshr_hits::cpu.inst 349853 # number of overall MSHR hits
737system.cpu.dcache.overall_mshr_hits::total 349853 # number of overall MSHR hits
738system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7335963 # number of ReadReq MSHR misses
739system.cpu.dcache.ReadReq_mshr_misses::total 7335963 # number of ReadReq MSHR misses
740system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890869 # number of WriteReq MSHR misses
741system.cpu.dcache.WriteReq_mshr_misses::total 1890869 # number of WriteReq MSHR misses
742system.cpu.dcache.demand_mshr_misses::cpu.inst 9226832 # number of demand (read+write) MSHR misses
743system.cpu.dcache.demand_mshr_misses::total 9226832 # number of demand (read+write) MSHR misses
744system.cpu.dcache.overall_mshr_misses::cpu.inst 9226832 # number of overall MSHR misses
745system.cpu.dcache.overall_mshr_misses::total 9226832 # number of overall MSHR misses
746system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168431190255 # number of ReadReq MSHR miss cycles
747system.cpu.dcache.ReadReq_mshr_miss_latency::total 168431190255 # number of ReadReq MSHR miss cycles
748system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77354259500 # number of WriteReq MSHR miss cycles
749system.cpu.dcache.WriteReq_mshr_miss_latency::total 77354259500 # number of WriteReq MSHR miss cycles
750system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245785449755 # number of demand (read+write) MSHR miss cycles
751system.cpu.dcache.demand_mshr_miss_latency::total 245785449755 # number of demand (read+write) MSHR miss cycles
752system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245785449755 # number of overall MSHR miss cycles
753system.cpu.dcache.overall_mshr_miss_latency::total 245785449755 # number of overall MSHR miss cycles
754system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015913 # mshr miss rate for ReadReq accesses
755system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015913 # mshr miss rate for ReadReq accesses
756system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses
757system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
758system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for demand accesses
759system.cpu.dcache.demand_mshr_miss_rate::total 0.014563 # mshr miss rate for demand accesses
760system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014563 # mshr miss rate for overall accesses
761system.cpu.dcache.overall_mshr_miss_rate::total 0.014563 # mshr miss rate for overall accesses
762system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22959.656456 # average ReadReq mshr miss latency
763system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22959.656456 # average ReadReq mshr miss latency
764system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40909.369978 # average WriteReq mshr miss latency
765system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40909.369978 # average WriteReq mshr miss latency
766system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency
767system.cpu.dcache.demand_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency
768system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26638.119103 # average overall mshr miss latency
769system.cpu.dcache.overall_avg_mshr_miss_latency::total 26638.119103 # average overall mshr miss latency
770system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
771
772---------- End Simulation Statistics ----------