1
2---------- Begin Simulation Statistics ----------
3sim_seconds 1.108945 # Number of seconds simulated
4sim_ticks 1108944740000 # Number of ticks simulated
5final_tick 1108944740000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 239014 # Simulator instruction rate (inst/s)
8host_op_rate 257501 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 171603826 # Simulator tick rate (ticks/s)
10host_mem_usage 253696 # Number of bytes of host memory used
11host_seconds 6462.24 # Real time elapsed on the host
12sim_insts 1544563087 # Number of instructions simulated
13sim_ops 1664032480 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 131625408 # Number of bytes read from this memory
17system.physmem.bytes_read::total 131625408 # Number of bytes read from this memory
18system.physmem.bytes_inst_read::cpu.inst 50368 # Number of instructions bytes read from this memory
19system.physmem.bytes_inst_read::total 50368 # Number of instructions bytes read from this memory
20system.physmem.bytes_written::writebacks 66989632 # Number of bytes written to this memory
21system.physmem.bytes_written::total 66989632 # Number of bytes written to this memory
22system.physmem.num_reads::cpu.inst 2056647 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 2056647 # Number of read requests responded to by this memory
24system.physmem.num_writes::writebacks 1046713 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 1046713 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 118694289 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 118694289 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 45420 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 45420 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_write::writebacks 60408449 # Write bandwidth from this memory (bytes/s)
31system.physmem.bw_write::total 60408449 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_total::writebacks 60408449 # Total bandwidth to/from this memory (bytes/s)
33system.physmem.bw_total::cpu.inst 118694289 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::total 179102739 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.readReqs 2056647 # Number of read requests accepted
36system.physmem.writeReqs 1046713 # Number of write requests accepted
37system.physmem.readBursts 2056647 # Number of DRAM read bursts, including those serviced by the write queue
38system.physmem.writeBursts 1046713 # Number of DRAM write bursts, including those merged in the write queue
39system.physmem.bytesReadDRAM 131542016 # Total number of bytes read from DRAM
40system.physmem.bytesReadWrQ 83392 # Total number of bytes read from write queue
41system.physmem.bytesWritten 66988032 # Total number of bytes written to DRAM
42system.physmem.bytesReadSys 131625408 # Total read bytes from the system interface side
43system.physmem.bytesWrittenSys 66989632 # Total written bytes from the system interface side
44system.physmem.servicedByWrQ 1303 # Number of DRAM read bursts serviced by the write queue
45system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
46system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
47system.physmem.perBankRdBursts::0 128036 # Per bank write bursts
48system.physmem.perBankRdBursts::1 125234 # Per bank write bursts
49system.physmem.perBankRdBursts::2 122300 # Per bank write bursts
50system.physmem.perBankRdBursts::3 124230 # Per bank write bursts
51system.physmem.perBankRdBursts::4 123415 # Per bank write bursts
52system.physmem.perBankRdBursts::5 123345 # Per bank write bursts
53system.physmem.perBankRdBursts::6 123964 # Per bank write bursts
54system.physmem.perBankRdBursts::7 124409 # Per bank write bursts
55system.physmem.perBankRdBursts::8 131872 # Per bank write bursts
56system.physmem.perBankRdBursts::9 134140 # Per bank write bursts
57system.physmem.perBankRdBursts::10 132473 # Per bank write bursts
58system.physmem.perBankRdBursts::11 133756 # Per bank write bursts
59system.physmem.perBankRdBursts::12 133901 # Per bank write bursts
60system.physmem.perBankRdBursts::13 134102 # Per bank write bursts
61system.physmem.perBankRdBursts::14 129958 # Per bank write bursts
62system.physmem.perBankRdBursts::15 130209 # Per bank write bursts
63system.physmem.perBankWrBursts::0 65849 # Per bank write bursts
64system.physmem.perBankWrBursts::1 64131 # Per bank write bursts
65system.physmem.perBankWrBursts::2 62381 # Per bank write bursts
66system.physmem.perBankWrBursts::3 62840 # Per bank write bursts
67system.physmem.perBankWrBursts::4 62871 # Per bank write bursts
68system.physmem.perBankWrBursts::5 62990 # Per bank write bursts
69system.physmem.perBankWrBursts::6 64312 # Per bank write bursts
70system.physmem.perBankWrBursts::7 65310 # Per bank write bursts
71system.physmem.perBankWrBursts::8 67027 # Per bank write bursts
72system.physmem.perBankWrBursts::9 67624 # Per bank write bursts
73system.physmem.perBankWrBursts::10 67292 # Per bank write bursts
74system.physmem.perBankWrBursts::11 67645 # Per bank write bursts
75system.physmem.perBankWrBursts::12 67063 # Per bank write bursts
76system.physmem.perBankWrBursts::13 67560 # Per bank write bursts
77system.physmem.perBankWrBursts::14 66200 # Per bank write bursts
78system.physmem.perBankWrBursts::15 65593 # Per bank write bursts
79system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
80system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
81system.physmem.totGap 1108944651500 # Total gap between requests
82system.physmem.readPktSize::0 0 # Read request sizes (log2)
83system.physmem.readPktSize::1 0 # Read request sizes (log2)
84system.physmem.readPktSize::2 0 # Read request sizes (log2)
85system.physmem.readPktSize::3 0 # Read request sizes (log2)
86system.physmem.readPktSize::4 0 # Read request sizes (log2)
87system.physmem.readPktSize::5 0 # Read request sizes (log2)
88system.physmem.readPktSize::6 2056647 # Read request sizes (log2)
89system.physmem.writePktSize::0 0 # Write request sizes (log2)
90system.physmem.writePktSize::1 0 # Write request sizes (log2)
91system.physmem.writePktSize::2 0 # Write request sizes (log2)
92system.physmem.writePktSize::3 0 # Write request sizes (log2)
93system.physmem.writePktSize::4 0 # Write request sizes (log2)
94system.physmem.writePktSize::5 0 # Write request sizes (log2)
95system.physmem.writePktSize::6 1046713 # Write request sizes (log2)
96system.physmem.rdQLenPdf::0 1923205 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::1 132121 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::2 18 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see

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135system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::15 31987 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::16 33324 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::17 57104 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::18 60908 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::19 61344 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::20 61572 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::21 61490 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::22 61531 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::23 61499 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::24 61550 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::25 61578 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::26 61602 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::27 62038 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::28 62277 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::29 61631 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::30 62828 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::31 61322 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::32 61027 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::33 70 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::34 11 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::35 4 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see

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184system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
192system.physmem.bytesPerActivate::samples 1918209 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::mean 103.496643 # Bytes accessed per row activation
194system.physmem.bytesPerActivate::gmean 81.775288 # Bytes accessed per row activation
195system.physmem.bytesPerActivate::stdev 125.095886 # Bytes accessed per row activation
196system.physmem.bytesPerActivate::0-127 1492147 77.79% 77.79% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::128-255 306422 15.97% 93.76% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::256-383 52965 2.76% 96.52% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::384-511 21185 1.10% 97.63% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::512-639 13242 0.69% 98.32% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::640-767 7471 0.39% 98.71% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::768-895 5204 0.27% 98.98% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::896-1023 3914 0.20% 99.18% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::1024-1151 15659 0.82% 100.00% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::total 1918209 # Bytes accessed per row activation
206system.physmem.rdPerTurnAround::samples 61025 # Reads before turning the bus around for writes
207system.physmem.rdPerTurnAround::mean 33.632724 # Reads before turning the bus around for writes
208system.physmem.rdPerTurnAround::stdev 160.189303 # Reads before turning the bus around for writes
209system.physmem.rdPerTurnAround::0-1023 60982 99.93% 99.93% # Reads before turning the bus around for writes
210system.physmem.rdPerTurnAround::1024-2047 18 0.03% 99.96% # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::2048-3071 10 0.02% 99.98% # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::3072-4095 7 0.01% 99.99% # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::4096-5119 3 0.00% 99.99% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::12288-13311 2 0.00% 100.00% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::13312-14335 1 0.00% 100.00% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::22528-23551 1 0.00% 100.00% # Reads before turning the bus around for writes
218system.physmem.rdPerTurnAround::total 61025 # Reads before turning the bus around for writes
219system.physmem.wrPerTurnAround::samples 61025 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::mean 17.151790 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::gmean 17.116821 # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::stdev 1.097688 # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::16 27581 45.20% 45.20% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::17 1180 1.93% 47.13% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::18 28172 46.16% 93.29% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::19 3706 6.07% 99.37% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::20 317 0.52% 99.89% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::21 54 0.09% 99.98% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::22 9 0.01% 99.99% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::23 3 0.00% 100.00% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::25 1 0.00% 100.00% # Writes before turning the bus around for reads
232system.physmem.wrPerTurnAround::27 1 0.00% 100.00% # Writes before turning the bus around for reads
233system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads
234system.physmem.wrPerTurnAround::total 61025 # Writes before turning the bus around for reads
235system.physmem.totQLat 38537340500 # Total ticks spent queuing
236system.physmem.totMemAccLat 77075040500 # Total ticks spent from burst creation until serviced by the DRAM
237system.physmem.totBusLat 10276720000 # Total ticks spent in databus transfers
238system.physmem.avgQLat 18749.83 # Average queueing delay per DRAM burst
239system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
240system.physmem.avgMemAccLat 37499.83 # Average memory access latency per DRAM burst
241system.physmem.avgRdBW 118.62 # Average DRAM read bandwidth in MiByte/s
242system.physmem.avgWrBW 60.41 # Average achieved write bandwidth in MiByte/s
243system.physmem.avgRdBWSys 118.69 # Average system read bandwidth in MiByte/s
244system.physmem.avgWrBWSys 60.41 # Average system write bandwidth in MiByte/s
245system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
246system.physmem.busUtil 1.40 # Data bus utilization in percentage
247system.physmem.busUtilRead 0.93 # Data bus utilization in percentage for reads
248system.physmem.busUtilWrite 0.47 # Data bus utilization in percentage for writes
249system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing
250system.physmem.avgWrQLen 25.09 # Average write queue length when enqueuing
251system.physmem.readRowHits 777039 # Number of row buffer hits during reads
252system.physmem.writeRowHits 406774 # Number of row buffer hits during writes
253system.physmem.readRowHitRate 37.81 # Row buffer hit rate for reads
254system.physmem.writeRowHitRate 38.86 # Row buffer hit rate for writes
255system.physmem.avgGap 357336.77 # Average gap between requests
256system.physmem.pageHitRate 38.16 # Row buffer hit rate, read and write combined
257system.physmem.memoryStateTime::IDLE 313164826000 # Time in different power states
258system.physmem.memoryStateTime::REF 37029980000 # Time in different power states
259system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
260system.physmem.memoryStateTime::ACT 758746776000 # Time in different power states
261system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
262system.physmem.actEnergy::0 7075638360 # Energy for activate commands per rank (pJ)
263system.physmem.actEnergy::1 7426006560 # Energy for activate commands per rank (pJ)
264system.physmem.preEnergy::0 3860715375 # Energy for precharge commands per rank (pJ)
265system.physmem.preEnergy::1 4051888500 # Energy for precharge commands per rank (pJ)
266system.physmem.readEnergy::0 7760165400 # Energy for read commands per rank (pJ)
267system.physmem.readEnergy::1 8271151200 # Energy for read commands per rank (pJ)
268system.physmem.writeEnergy::0 3309232320 # Energy for write commands per rank (pJ)
269system.physmem.writeEnergy::1 3473305920 # Energy for write commands per rank (pJ)
270system.physmem.refreshEnergy::0 72430640880 # Energy for refresh commands per rank (pJ)
271system.physmem.refreshEnergy::1 72430640880 # Energy for refresh commands per rank (pJ)
272system.physmem.actBackEnergy::0 416866648005 # Energy for active background per rank (pJ)
273system.physmem.actBackEnergy::1 425333204280 # Energy for active background per rank (pJ)
274system.physmem.preBackEnergy::0 299692308000 # Energy for precharge background per rank (pJ)
275system.physmem.preBackEnergy::1 292265504250 # Energy for precharge background per rank (pJ)
276system.physmem.totalEnergy::0 810995348340 # Total energy per rank (pJ)
277system.physmem.totalEnergy::1 813251701590 # Total energy per rank (pJ)
278system.physmem.averagePower::0 731.323936 # Core power per rank (mW)
279system.physmem.averagePower::1 733.358627 # Core power per rank (mW)
280system.cpu.branchPred.lookups 240152510 # Number of BP lookups
281system.cpu.branchPred.condPredicted 186756179 # Number of conditional branches predicted
282system.cpu.branchPred.condIncorrect 14598640 # Number of conditional branches incorrect
283system.cpu.branchPred.BTBLookups 131763268 # Number of BTB lookups
284system.cpu.branchPred.BTBHits 122287171 # Number of BTB hits
285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
286system.cpu.branchPred.BTBHitPct 92.808241 # BTB Hit Percentage
287system.cpu.branchPred.usedRAS 15660181 # Number of times the RAS was used to get a target.
288system.cpu.branchPred.RASInCorrect 15 # Number of incorrect RAS predictions.
289system.cpu_clk_domain.clock 500 # Clock period in ticks
290system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
291system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
292system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
293system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
294system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
295system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
296system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
297system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA

--- 69 unchanged lines hidden (view full) ---

367system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
368system.cpu.itb.read_accesses 0 # DTB read accesses
369system.cpu.itb.write_accesses 0 # DTB write accesses
370system.cpu.itb.inst_accesses 0 # ITB inst accesses
371system.cpu.itb.hits 0 # DTB hits
372system.cpu.itb.misses 0 # DTB misses
373system.cpu.itb.accesses 0 # DTB accesses
374system.cpu.workload.num_syscalls 46 # Number of system calls
375system.cpu.numCycles 2217889480 # number of cpu cycles simulated
376system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
377system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
378system.cpu.committedInsts 1544563087 # Number of instructions committed
379system.cpu.committedOps 1664032480 # Number of ops (including micro ops) committed
380system.cpu.discardedOps 40077128 # Number of ops (including micro ops) which were discarded before commit
381system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
382system.cpu.cpi 1.435933 # CPI: cycles per instruction
383system.cpu.ipc 0.696411 # IPC: instructions per cycle
384system.cpu.tickCycles 1838736315 # Number of cycles that the object actually ticked
385system.cpu.idleCycles 379153165 # Total number of cycles that the object has spent stopped
386system.cpu.dcache.tags.replacements 9224311 # number of replacements
387system.cpu.dcache.tags.tagsinuse 4085.608602 # Cycle average of tags in use
388system.cpu.dcache.tags.total_refs 624084220 # Total number of references to valid blocks.
389system.cpu.dcache.tags.sampled_refs 9228407 # Sample count of references to valid blocks.
390system.cpu.dcache.tags.avg_refs 67.626430 # Average number of references to valid blocks.
391system.cpu.dcache.tags.warmup_cycle 9776044000 # Cycle when the warmup percentage was hit.
392system.cpu.dcache.tags.occ_blocks::cpu.inst 4085.608602 # Average occupied blocks per requestor
393system.cpu.dcache.tags.occ_percent::cpu.inst 0.997463 # Average percentage of cache occupancy
394system.cpu.dcache.tags.occ_percent::total 0.997463 # Average percentage of cache occupancy
395system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
396system.cpu.dcache.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id
397system.cpu.dcache.tags.age_task_id_blocks_1024::1 1292 # Occupied blocks per task id
398system.cpu.dcache.tags.age_task_id_blocks_1024::2 2484 # Occupied blocks per task id
399system.cpu.dcache.tags.age_task_id_blocks_1024::3 61 # Occupied blocks per task id
400system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
401system.cpu.dcache.tags.tag_accesses 1276551305 # Number of tag accesses
402system.cpu.dcache.tags.data_accesses 1276551305 # Number of data accesses
403system.cpu.dcache.ReadReq_hits::cpu.inst 453737568 # number of ReadReq hits
404system.cpu.dcache.ReadReq_hits::total 453737568 # number of ReadReq hits
405system.cpu.dcache.WriteReq_hits::cpu.inst 170346530 # number of WriteReq hits
406system.cpu.dcache.WriteReq_hits::total 170346530 # number of WriteReq hits
407system.cpu.dcache.LoadLockedReq_hits::cpu.inst 61 # number of LoadLockedReq hits
408system.cpu.dcache.LoadLockedReq_hits::total 61 # number of LoadLockedReq hits
409system.cpu.dcache.StoreCondReq_hits::cpu.inst 61 # number of StoreCondReq hits
410system.cpu.dcache.StoreCondReq_hits::total 61 # number of StoreCondReq hits
411system.cpu.dcache.demand_hits::cpu.inst 624084098 # number of demand (read+write) hits
412system.cpu.dcache.demand_hits::total 624084098 # number of demand (read+write) hits
413system.cpu.dcache.overall_hits::cpu.inst 624084098 # number of overall hits
414system.cpu.dcache.overall_hits::total 624084098 # number of overall hits
415system.cpu.dcache.ReadReq_misses::cpu.inst 7337712 # number of ReadReq misses
416system.cpu.dcache.ReadReq_misses::total 7337712 # number of ReadReq misses
417system.cpu.dcache.WriteReq_misses::cpu.inst 2239517 # number of WriteReq misses
418system.cpu.dcache.WriteReq_misses::total 2239517 # number of WriteReq misses
419system.cpu.dcache.demand_misses::cpu.inst 9577229 # number of demand (read+write) misses
420system.cpu.dcache.demand_misses::total 9577229 # number of demand (read+write) misses
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422system.cpu.dcache.overall_misses::total 9577229 # number of overall misses
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424system.cpu.dcache.ReadReq_miss_latency::total 183598363496 # number of ReadReq miss cycles
425system.cpu.dcache.WriteReq_miss_latency::cpu.inst 101566510500 # number of WriteReq miss cycles
426system.cpu.dcache.WriteReq_miss_latency::total 101566510500 # number of WriteReq miss cycles
427system.cpu.dcache.demand_miss_latency::cpu.inst 285164873996 # number of demand (read+write) miss cycles
428system.cpu.dcache.demand_miss_latency::total 285164873996 # number of demand (read+write) miss cycles
429system.cpu.dcache.overall_miss_latency::cpu.inst 285164873996 # number of overall miss cycles
430system.cpu.dcache.overall_miss_latency::total 285164873996 # number of overall miss cycles
431system.cpu.dcache.ReadReq_accesses::cpu.inst 461075280 # number of ReadReq accesses(hits+misses)
432system.cpu.dcache.ReadReq_accesses::total 461075280 # number of ReadReq accesses(hits+misses)
433system.cpu.dcache.WriteReq_accesses::cpu.inst 172586047 # number of WriteReq accesses(hits+misses)
434system.cpu.dcache.WriteReq_accesses::total 172586047 # number of WriteReq accesses(hits+misses)
435system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 61 # number of LoadLockedReq accesses(hits+misses)
436system.cpu.dcache.LoadLockedReq_accesses::total 61 # number of LoadLockedReq accesses(hits+misses)
437system.cpu.dcache.StoreCondReq_accesses::cpu.inst 61 # number of StoreCondReq accesses(hits+misses)
438system.cpu.dcache.StoreCondReq_accesses::total 61 # number of StoreCondReq accesses(hits+misses)
439system.cpu.dcache.demand_accesses::cpu.inst 633661327 # number of demand (read+write) accesses
440system.cpu.dcache.demand_accesses::total 633661327 # number of demand (read+write) accesses
441system.cpu.dcache.overall_accesses::cpu.inst 633661327 # number of overall (read+write) accesses
442system.cpu.dcache.overall_accesses::total 633661327 # number of overall (read+write) accesses
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444system.cpu.dcache.ReadReq_miss_rate::total 0.015914 # miss rate for ReadReq accesses
445system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.012976 # miss rate for WriteReq accesses
446system.cpu.dcache.WriteReq_miss_rate::total 0.012976 # miss rate for WriteReq accesses
447system.cpu.dcache.demand_miss_rate::cpu.inst 0.015114 # miss rate for demand accesses
448system.cpu.dcache.demand_miss_rate::total 0.015114 # miss rate for demand accesses
449system.cpu.dcache.overall_miss_rate::cpu.inst 0.015114 # miss rate for overall accesses
450system.cpu.dcache.overall_miss_rate::total 0.015114 # miss rate for overall accesses
451system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 25021.200545 # average ReadReq miss latency
452system.cpu.dcache.ReadReq_avg_miss_latency::total 25021.200545 # average ReadReq miss latency
453system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 45351.971206 # average WriteReq miss latency
454system.cpu.dcache.WriteReq_avg_miss_latency::total 45351.971206 # average WriteReq miss latency
455system.cpu.dcache.demand_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency
456system.cpu.dcache.demand_avg_miss_latency::total 29775.300768 # average overall miss latency
457system.cpu.dcache.overall_avg_miss_latency::cpu.inst 29775.300768 # average overall miss latency
458system.cpu.dcache.overall_avg_miss_latency::total 29775.300768 # average overall miss latency
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460system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
461system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
462system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
463system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
464system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
465system.cpu.dcache.fast_writes 0 # number of fast writes performed
466system.cpu.dcache.cache_copies 0 # number of cache copies performed
467system.cpu.dcache.writebacks::writebacks 3700618 # number of writebacks
468system.cpu.dcache.writebacks::total 3700618 # number of writebacks
469system.cpu.dcache.ReadReq_mshr_hits::cpu.inst 213 # number of ReadReq MSHR hits
470system.cpu.dcache.ReadReq_mshr_hits::total 213 # number of ReadReq MSHR hits
471system.cpu.dcache.WriteReq_mshr_hits::cpu.inst 348609 # number of WriteReq MSHR hits
472system.cpu.dcache.WriteReq_mshr_hits::total 348609 # number of WriteReq MSHR hits
473system.cpu.dcache.demand_mshr_hits::cpu.inst 348822 # number of demand (read+write) MSHR hits
474system.cpu.dcache.demand_mshr_hits::total 348822 # number of demand (read+write) MSHR hits
475system.cpu.dcache.overall_mshr_hits::cpu.inst 348822 # number of overall MSHR hits
476system.cpu.dcache.overall_mshr_hits::total 348822 # number of overall MSHR hits
477system.cpu.dcache.ReadReq_mshr_misses::cpu.inst 7337499 # number of ReadReq MSHR misses
478system.cpu.dcache.ReadReq_mshr_misses::total 7337499 # number of ReadReq MSHR misses
479system.cpu.dcache.WriteReq_mshr_misses::cpu.inst 1890908 # number of WriteReq MSHR misses
480system.cpu.dcache.WriteReq_mshr_misses::total 1890908 # number of WriteReq MSHR misses
481system.cpu.dcache.demand_mshr_misses::cpu.inst 9228407 # number of demand (read+write) MSHR misses
482system.cpu.dcache.demand_mshr_misses::total 9228407 # number of demand (read+write) MSHR misses
483system.cpu.dcache.overall_mshr_misses::cpu.inst 9228407 # number of overall MSHR misses
484system.cpu.dcache.overall_mshr_misses::total 9228407 # number of overall MSHR misses
485system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst 168505826254 # number of ReadReq MSHR miss cycles
486system.cpu.dcache.ReadReq_mshr_miss_latency::total 168505826254 # number of ReadReq MSHR miss cycles
487system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 77457723500 # number of WriteReq MSHR miss cycles
488system.cpu.dcache.WriteReq_mshr_miss_latency::total 77457723500 # number of WriteReq MSHR miss cycles
489system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 245963549754 # number of demand (read+write) MSHR miss cycles
490system.cpu.dcache.demand_mshr_miss_latency::total 245963549754 # number of demand (read+write) MSHR miss cycles
491system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 245963549754 # number of overall MSHR miss cycles
492system.cpu.dcache.overall_mshr_miss_latency::total 245963549754 # number of overall MSHR miss cycles
493system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.015914 # mshr miss rate for ReadReq accesses
494system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.015914 # mshr miss rate for ReadReq accesses
495system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.010956 # mshr miss rate for WriteReq accesses
496system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.010956 # mshr miss rate for WriteReq accesses
497system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for demand accesses
498system.cpu.dcache.demand_mshr_miss_rate::total 0.014564 # mshr miss rate for demand accesses
499system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.014564 # mshr miss rate for overall accesses
500system.cpu.dcache.overall_mshr_miss_rate::total 0.014564 # mshr miss rate for overall accesses
501system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 22965.022040 # average ReadReq mshr miss latency
502system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22965.022040 # average ReadReq mshr miss latency
503system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 40963.242791 # average WriteReq mshr miss latency
504system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40963.242791 # average WriteReq mshr miss latency
505system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency
506system.cpu.dcache.demand_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency
507system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 26652.871915 # average overall mshr miss latency
508system.cpu.dcache.overall_avg_mshr_miss_latency::total 26652.871915 # average overall mshr miss latency
509system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
510system.cpu.icache.tags.replacements 29 # number of replacements
511system.cpu.icache.tags.tagsinuse 661.026879 # Cycle average of tags in use
512system.cpu.icache.tags.total_refs 466133968 # Total number of references to valid blocks.
513system.cpu.icache.tags.sampled_refs 820 # Sample count of references to valid blocks.
514system.cpu.icache.tags.avg_refs 568456.058537 # Average number of references to valid blocks.
515system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
516system.cpu.icache.tags.occ_blocks::cpu.inst 661.026879 # Average occupied blocks per requestor
517system.cpu.icache.tags.occ_percent::cpu.inst 0.322767 # Average percentage of cache occupancy
518system.cpu.icache.tags.occ_percent::total 0.322767 # Average percentage of cache occupancy
519system.cpu.icache.tags.occ_task_id_blocks::1024 791 # Occupied blocks per task id
520system.cpu.icache.tags.age_task_id_blocks_1024::0 33 # Occupied blocks per task id
521system.cpu.icache.tags.age_task_id_blocks_1024::2 5 # Occupied blocks per task id
522system.cpu.icache.tags.age_task_id_blocks_1024::4 753 # Occupied blocks per task id
523system.cpu.icache.tags.occ_task_id_percent::1024 0.386230 # Percentage of cache occupancy per task id
524system.cpu.icache.tags.tag_accesses 932270396 # Number of tag accesses
525system.cpu.icache.tags.data_accesses 932270396 # Number of data accesses
526system.cpu.icache.ReadReq_hits::cpu.inst 466133968 # number of ReadReq hits
527system.cpu.icache.ReadReq_hits::total 466133968 # number of ReadReq hits
528system.cpu.icache.demand_hits::cpu.inst 466133968 # number of demand (read+write) hits
529system.cpu.icache.demand_hits::total 466133968 # number of demand (read+write) hits
530system.cpu.icache.overall_hits::cpu.inst 466133968 # number of overall hits
531system.cpu.icache.overall_hits::total 466133968 # number of overall hits
532system.cpu.icache.ReadReq_misses::cpu.inst 820 # number of ReadReq misses
533system.cpu.icache.ReadReq_misses::total 820 # number of ReadReq misses
534system.cpu.icache.demand_misses::cpu.inst 820 # number of demand (read+write) misses
535system.cpu.icache.demand_misses::total 820 # number of demand (read+write) misses
536system.cpu.icache.overall_misses::cpu.inst 820 # number of overall misses
537system.cpu.icache.overall_misses::total 820 # number of overall misses
538system.cpu.icache.ReadReq_miss_latency::cpu.inst 58416499 # number of ReadReq miss cycles
539system.cpu.icache.ReadReq_miss_latency::total 58416499 # number of ReadReq miss cycles
540system.cpu.icache.demand_miss_latency::cpu.inst 58416499 # number of demand (read+write) miss cycles
541system.cpu.icache.demand_miss_latency::total 58416499 # number of demand (read+write) miss cycles
542system.cpu.icache.overall_miss_latency::cpu.inst 58416499 # number of overall miss cycles
543system.cpu.icache.overall_miss_latency::total 58416499 # number of overall miss cycles
544system.cpu.icache.ReadReq_accesses::cpu.inst 466134788 # number of ReadReq accesses(hits+misses)
545system.cpu.icache.ReadReq_accesses::total 466134788 # number of ReadReq accesses(hits+misses)
546system.cpu.icache.demand_accesses::cpu.inst 466134788 # number of demand (read+write) accesses
547system.cpu.icache.demand_accesses::total 466134788 # number of demand (read+write) accesses
548system.cpu.icache.overall_accesses::cpu.inst 466134788 # number of overall (read+write) accesses
549system.cpu.icache.overall_accesses::total 466134788 # number of overall (read+write) accesses
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551system.cpu.icache.ReadReq_miss_rate::total 0.000002 # miss rate for ReadReq accesses
552system.cpu.icache.demand_miss_rate::cpu.inst 0.000002 # miss rate for demand accesses
553system.cpu.icache.demand_miss_rate::total 0.000002 # miss rate for demand accesses
554system.cpu.icache.overall_miss_rate::cpu.inst 0.000002 # miss rate for overall accesses
555system.cpu.icache.overall_miss_rate::total 0.000002 # miss rate for overall accesses
556system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71239.632927 # average ReadReq miss latency
557system.cpu.icache.ReadReq_avg_miss_latency::total 71239.632927 # average ReadReq miss latency
558system.cpu.icache.demand_avg_miss_latency::cpu.inst 71239.632927 # average overall miss latency
559system.cpu.icache.demand_avg_miss_latency::total 71239.632927 # average overall miss latency
560system.cpu.icache.overall_avg_miss_latency::cpu.inst 71239.632927 # average overall miss latency
561system.cpu.icache.overall_avg_miss_latency::total 71239.632927 # average overall miss latency
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563system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
564system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
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567system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
568system.cpu.icache.fast_writes 0 # number of fast writes performed
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571system.cpu.icache.ReadReq_mshr_misses::total 820 # number of ReadReq MSHR misses
572system.cpu.icache.demand_mshr_misses::cpu.inst 820 # number of demand (read+write) MSHR misses
573system.cpu.icache.demand_mshr_misses::total 820 # number of demand (read+write) MSHR misses
574system.cpu.icache.overall_mshr_misses::cpu.inst 820 # number of overall MSHR misses
575system.cpu.icache.overall_mshr_misses::total 820 # number of overall MSHR misses
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577system.cpu.icache.ReadReq_mshr_miss_latency::total 56453501 # number of ReadReq MSHR miss cycles
578system.cpu.icache.demand_mshr_miss_latency::cpu.inst 56453501 # number of demand (read+write) MSHR miss cycles
579system.cpu.icache.demand_mshr_miss_latency::total 56453501 # number of demand (read+write) MSHR miss cycles
580system.cpu.icache.overall_mshr_miss_latency::cpu.inst 56453501 # number of overall MSHR miss cycles
581system.cpu.icache.overall_mshr_miss_latency::total 56453501 # number of overall MSHR miss cycles
582system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for ReadReq accesses
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584system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for demand accesses
585system.cpu.icache.demand_mshr_miss_rate::total 0.000002 # mshr miss rate for demand accesses
586system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000002 # mshr miss rate for overall accesses
587system.cpu.icache.overall_mshr_miss_rate::total 0.000002 # mshr miss rate for overall accesses
588system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68845.732927 # average ReadReq mshr miss latency
589system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68845.732927 # average ReadReq mshr miss latency
590system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68845.732927 # average overall mshr miss latency
591system.cpu.icache.demand_avg_mshr_miss_latency::total 68845.732927 # average overall mshr miss latency
592system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68845.732927 # average overall mshr miss latency
593system.cpu.icache.overall_avg_mshr_miss_latency::total 68845.732927 # average overall mshr miss latency
594system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
595system.cpu.l2cache.tags.replacements 2023942 # number of replacements
596system.cpu.l2cache.tags.tagsinuse 31254.337993 # Cycle average of tags in use
597system.cpu.l2cache.tags.total_refs 8984488 # Total number of references to valid blocks.
598system.cpu.l2cache.tags.sampled_refs 2053718 # Sample count of references to valid blocks.
599system.cpu.l2cache.tags.avg_refs 4.374743 # Average number of references to valid blocks.
600system.cpu.l2cache.tags.warmup_cycle 59502848750 # Cycle when the warmup percentage was hit.
601system.cpu.l2cache.tags.occ_blocks::writebacks 14996.949277 # Average occupied blocks per requestor
602system.cpu.l2cache.tags.occ_blocks::cpu.inst 16257.388715 # Average occupied blocks per requestor
603system.cpu.l2cache.tags.occ_percent::writebacks 0.457671 # Average percentage of cache occupancy
604system.cpu.l2cache.tags.occ_percent::cpu.inst 0.496136 # Average percentage of cache occupancy
605system.cpu.l2cache.tags.occ_percent::total 0.953807 # Average percentage of cache occupancy
606system.cpu.l2cache.tags.occ_task_id_blocks::1024 29776 # Occupied blocks per task id
607system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id
608system.cpu.l2cache.tags.age_task_id_blocks_1024::1 31 # Occupied blocks per task id
609system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1248 # Occupied blocks per task id
610system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12849 # Occupied blocks per task id
611system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15556 # Occupied blocks per task id
612system.cpu.l2cache.tags.occ_task_id_percent::1024 0.908691 # Percentage of cache occupancy per task id
613system.cpu.l2cache.tags.tag_accesses 107383386 # Number of tag accesses
614system.cpu.l2cache.tags.data_accesses 107383386 # Number of data accesses
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616system.cpu.l2cache.ReadReq_hits::total 6081991 # number of ReadReq hits
617system.cpu.l2cache.Writeback_hits::writebacks 3700618 # number of Writeback hits
618system.cpu.l2cache.Writeback_hits::total 3700618 # number of Writeback hits
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620system.cpu.l2cache.ReadExReq_hits::total 1090584 # number of ReadExReq hits
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622system.cpu.l2cache.demand_hits::total 7172575 # number of demand (read+write) hits
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624system.cpu.l2cache.overall_hits::total 7172575 # number of overall hits
625system.cpu.l2cache.ReadReq_misses::cpu.inst 1256328 # number of ReadReq misses
626system.cpu.l2cache.ReadReq_misses::total 1256328 # number of ReadReq misses
627system.cpu.l2cache.ReadExReq_misses::cpu.inst 800324 # number of ReadExReq misses
628system.cpu.l2cache.ReadExReq_misses::total 800324 # number of ReadExReq misses
629system.cpu.l2cache.demand_misses::cpu.inst 2056652 # number of demand (read+write) misses
630system.cpu.l2cache.demand_misses::total 2056652 # number of demand (read+write) misses
631system.cpu.l2cache.overall_misses::cpu.inst 2056652 # number of overall misses
632system.cpu.l2cache.overall_misses::total 2056652 # number of overall misses
633system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 100398878250 # number of ReadReq miss cycles
634system.cpu.l2cache.ReadReq_miss_latency::total 100398878250 # number of ReadReq miss cycles
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636system.cpu.l2cache.ReadExReq_miss_latency::total 64605165750 # number of ReadExReq miss cycles
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638system.cpu.l2cache.demand_miss_latency::total 165004044000 # number of demand (read+write) miss cycles
639system.cpu.l2cache.overall_miss_latency::cpu.inst 165004044000 # number of overall miss cycles
640system.cpu.l2cache.overall_miss_latency::total 165004044000 # number of overall miss cycles
641system.cpu.l2cache.ReadReq_accesses::cpu.inst 7338319 # number of ReadReq accesses(hits+misses)
642system.cpu.l2cache.ReadReq_accesses::total 7338319 # number of ReadReq accesses(hits+misses)
643system.cpu.l2cache.Writeback_accesses::writebacks 3700618 # number of Writeback accesses(hits+misses)
644system.cpu.l2cache.Writeback_accesses::total 3700618 # number of Writeback accesses(hits+misses)
645system.cpu.l2cache.ReadExReq_accesses::cpu.inst 1890908 # number of ReadExReq accesses(hits+misses)
646system.cpu.l2cache.ReadExReq_accesses::total 1890908 # number of ReadExReq accesses(hits+misses)
647system.cpu.l2cache.demand_accesses::cpu.inst 9229227 # number of demand (read+write) accesses
648system.cpu.l2cache.demand_accesses::total 9229227 # number of demand (read+write) accesses
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650system.cpu.l2cache.overall_accesses::total 9229227 # number of overall (read+write) accesses
651system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.171201 # miss rate for ReadReq accesses
652system.cpu.l2cache.ReadReq_miss_rate::total 0.171201 # miss rate for ReadReq accesses
653system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst 0.423249 # miss rate for ReadExReq accesses
654system.cpu.l2cache.ReadExReq_miss_rate::total 0.423249 # miss rate for ReadExReq accesses
655system.cpu.l2cache.demand_miss_rate::cpu.inst 0.222841 # miss rate for demand accesses
656system.cpu.l2cache.demand_miss_rate::total 0.222841 # miss rate for demand accesses
657system.cpu.l2cache.overall_miss_rate::cpu.inst 0.222841 # miss rate for overall accesses
658system.cpu.l2cache.overall_miss_rate::total 0.222841 # miss rate for overall accesses
659system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79914.543216 # average ReadReq miss latency
660system.cpu.l2cache.ReadReq_avg_miss_latency::total 79914.543216 # average ReadReq miss latency
661system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 80723.764063 # average ReadExReq miss latency
662system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80723.764063 # average ReadExReq miss latency
663system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 80229.442803 # average overall miss latency
664system.cpu.l2cache.demand_avg_miss_latency::total 80229.442803 # average overall miss latency
665system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 80229.442803 # average overall miss latency
666system.cpu.l2cache.overall_avg_miss_latency::total 80229.442803 # average overall miss latency
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669system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
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671system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
672system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
673system.cpu.l2cache.fast_writes 0 # number of fast writes performed
674system.cpu.l2cache.cache_copies 0 # number of cache copies performed
675system.cpu.l2cache.writebacks::writebacks 1046713 # number of writebacks
676system.cpu.l2cache.writebacks::total 1046713 # number of writebacks
677system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 5 # number of ReadReq MSHR hits
678system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
679system.cpu.l2cache.demand_mshr_hits::cpu.inst 5 # number of demand (read+write) MSHR hits
680system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
681system.cpu.l2cache.overall_mshr_hits::cpu.inst 5 # number of overall MSHR hits
682system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
683system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1256323 # number of ReadReq MSHR misses
684system.cpu.l2cache.ReadReq_mshr_misses::total 1256323 # number of ReadReq MSHR misses
685system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst 800324 # number of ReadExReq MSHR misses
686system.cpu.l2cache.ReadExReq_mshr_misses::total 800324 # number of ReadExReq MSHR misses
687system.cpu.l2cache.demand_mshr_misses::cpu.inst 2056647 # number of demand (read+write) MSHR misses
688system.cpu.l2cache.demand_mshr_misses::total 2056647 # number of demand (read+write) MSHR misses
689system.cpu.l2cache.overall_mshr_misses::cpu.inst 2056647 # number of overall MSHR misses
690system.cpu.l2cache.overall_mshr_misses::total 2056647 # number of overall MSHR misses
691system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 84521118250 # number of ReadReq MSHR miss cycles
692system.cpu.l2cache.ReadReq_mshr_miss_latency::total 84521118250 # number of ReadReq MSHR miss cycles
693system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst 54527231750 # number of ReadExReq MSHR miss cycles
694system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 54527231750 # number of ReadExReq MSHR miss cycles
695system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 139048350000 # number of demand (read+write) MSHR miss cycles
696system.cpu.l2cache.demand_mshr_miss_latency::total 139048350000 # number of demand (read+write) MSHR miss cycles
697system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 139048350000 # number of overall MSHR miss cycles
698system.cpu.l2cache.overall_mshr_miss_latency::total 139048350000 # number of overall MSHR miss cycles
699system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.171200 # mshr miss rate for ReadReq accesses
700system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.171200 # mshr miss rate for ReadReq accesses
701system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.423249 # mshr miss rate for ReadExReq accesses
702system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.423249 # mshr miss rate for ReadExReq accesses
703system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for demand accesses
704system.cpu.l2cache.demand_mshr_miss_rate::total 0.222841 # mshr miss rate for demand accesses
705system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.222841 # mshr miss rate for overall accesses
706system.cpu.l2cache.overall_mshr_miss_rate::total 0.222841 # mshr miss rate for overall accesses
707system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67276.582734 # average ReadReq mshr miss latency
708system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67276.582734 # average ReadReq mshr miss latency
709system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 68131.446452 # average ReadExReq mshr miss latency
710system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68131.446452 # average ReadExReq mshr miss latency
711system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency
712system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency
713system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67609.244562 # average overall mshr miss latency
714system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67609.244562 # average overall mshr miss latency
715system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
716system.cpu.toL2Bus.trans_dist::ReadReq 7338319 # Transaction distribution
717system.cpu.toL2Bus.trans_dist::ReadResp 7338319 # Transaction distribution
718system.cpu.toL2Bus.trans_dist::Writeback 3700618 # Transaction distribution
719system.cpu.toL2Bus.trans_dist::ReadExReq 1890908 # Transaction distribution
720system.cpu.toL2Bus.trans_dist::ReadExResp 1890908 # Transaction distribution
721system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1640 # Packet count per connected master and slave (bytes)
722system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 22157432 # Packet count per connected master and slave (bytes)
723system.cpu.toL2Bus.pkt_count::total 22159072 # Packet count per connected master and slave (bytes)
724system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 52480 # Cumulative packet size per connected master and slave (bytes)
725system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 827457600 # Cumulative packet size per connected master and slave (bytes)
726system.cpu.toL2Bus.pkt_size::total 827510080 # Cumulative packet size per connected master and slave (bytes)
727system.cpu.toL2Bus.snoops 0 # Total snoops (count)
728system.cpu.toL2Bus.snoop_fanout::samples 12929845 # Request fanout histogram
729system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
730system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
731system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
732system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
733system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
734system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
735system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
736system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
737system.cpu.toL2Bus.snoop_fanout::5 12929845 100.00% 100.00% # Request fanout histogram
738system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
739system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
740system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
741system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
742system.cpu.toL2Bus.snoop_fanout::total 12929845 # Request fanout histogram
743system.cpu.toL2Bus.reqLayer0.occupancy 10165540500 # Layer occupancy (ticks)
744system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
745system.cpu.toL2Bus.respLayer0.occupancy 1391499 # Layer occupancy (ticks)
746system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
747system.cpu.toL2Bus.respLayer1.occupancy 14187091746 # Layer occupancy (ticks)
748system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%)
749system.membus.trans_dist::ReadReq 1256323 # Transaction distribution
750system.membus.trans_dist::ReadResp 1256323 # Transaction distribution
751system.membus.trans_dist::Writeback 1046713 # Transaction distribution
752system.membus.trans_dist::ReadExReq 800324 # Transaction distribution
753system.membus.trans_dist::ReadExResp 800324 # Transaction distribution
754system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 5160007 # Packet count per connected master and slave (bytes)
755system.membus.pkt_count::total 5160007 # Packet count per connected master and slave (bytes)
756system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 198615040 # Cumulative packet size per connected master and slave (bytes)
757system.membus.pkt_size::total 198615040 # Cumulative packet size per connected master and slave (bytes)
758system.membus.snoops 0 # Total snoops (count)
759system.membus.snoop_fanout::samples 3103360 # Request fanout histogram
760system.membus.snoop_fanout::mean 0 # Request fanout histogram
761system.membus.snoop_fanout::stdev 0 # Request fanout histogram
762system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
763system.membus.snoop_fanout::0 3103360 100.00% 100.00% # Request fanout histogram
764system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
765system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
766system.membus.snoop_fanout::min_value 0 # Request fanout histogram
767system.membus.snoop_fanout::max_value 0 # Request fanout histogram
768system.membus.snoop_fanout::total 3103360 # Request fanout histogram
769system.membus.reqLayer0.occupancy 12130659500 # Layer occupancy (ticks)
770system.membus.reqLayer0.utilization 1.1 # Layer utilization (%)
771system.membus.respLayer1.occupancy 19439818500 # Layer occupancy (ticks)
772system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
773
774---------- End Simulation Statistics ----------