| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.058750 # Number of seconds simulated 4sim_ticks 58750410500 # Number of ticks simulated 5final_tick 58750410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.060131 # Number of seconds simulated 4sim_ticks 60130734500 # Number of ticks simulated 5final_tick 60130734500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 179920 # Simulator instruction rate (inst/s) 8host_op_rate 230092 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 149057017 # Simulator tick rate (ticks/s) 10host_mem_usage 281832 # Number of bytes of host memory used 11host_seconds 394.15 # Real time elapsed on the host | 7host_inst_rate 142105 # Simulator instruction rate (inst/s) 8host_op_rate 181732 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 120494644 # Simulator tick rate (ticks/s) 10host_mem_usage 279144 # Number of bytes of host memory used 11host_seconds 499.03 # Real time elapsed on the host |
| 12sim_insts 70915150 # Number of instructions simulated 13sim_ops 90690106 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 70915150 # Number of instructions simulated 13sim_ops 90690106 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory |
| 29system.physmem.bw_read::cpu.inst 4873770 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 135124571 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 139998341 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 4873770 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 4873770 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 94285775 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 94285775 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 94285775 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 4873770 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 135124571 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 234284116 # Total bandwidth to/from this memory (bytes/s) | 29system.physmem.bw_read::cpu.inst 4761891 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 132022735 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 136784626 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 4761891 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 4761891 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 92121409 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 92121409 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 92121409 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 4761891 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 132022735 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 228906035 # Total bandwidth to/from this memory (bytes/s) |
| 40system.physmem.readReqs 128515 # Number of read requests accepted 41system.physmem.writeReqs 86552 # Number of write requests accepted 42system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue | 40system.physmem.readReqs 128515 # Number of read requests accepted 41system.physmem.writeReqs 86552 # Number of write requests accepted 42system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue |
| 44system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue 46system.physmem.bytesWritten 5537600 # Total number of bytes written to DRAM | 44system.physmem.bytesReadDRAM 8224640 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue 46system.physmem.bytesWritten 5537472 # Total number of bytes written to DRAM |
| 47system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side | 47system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side |
| 49system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue | 49system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue |
| 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 52system.physmem.perBankRdBursts::0 8086 # Per bank write bursts 53system.physmem.perBankRdBursts::1 8335 # Per bank write bursts 54system.physmem.perBankRdBursts::2 8257 # Per bank write bursts 55system.physmem.perBankRdBursts::3 8155 # Per bank write bursts 56system.physmem.perBankRdBursts::4 8301 # Per bank write bursts 57system.physmem.perBankRdBursts::5 8413 # Per bank write bursts 58system.physmem.perBankRdBursts::6 8070 # Per bank write bursts 59system.physmem.perBankRdBursts::7 7917 # Per bank write bursts | 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 52system.physmem.perBankRdBursts::0 8086 # Per bank write bursts 53system.physmem.perBankRdBursts::1 8335 # Per bank write bursts 54system.physmem.perBankRdBursts::2 8257 # Per bank write bursts 55system.physmem.perBankRdBursts::3 8155 # Per bank write bursts 56system.physmem.perBankRdBursts::4 8301 # Per bank write bursts 57system.physmem.perBankRdBursts::5 8413 # Per bank write bursts 58system.physmem.perBankRdBursts::6 8070 # Per bank write bursts 59system.physmem.perBankRdBursts::7 7917 # Per bank write bursts |
| 60system.physmem.perBankRdBursts::8 8053 # Per bank write bursts 61system.physmem.perBankRdBursts::9 7612 # Per bank write bursts | 60system.physmem.perBankRdBursts::8 8054 # Per bank write bursts 61system.physmem.perBankRdBursts::9 7613 # Per bank write bursts |
| 62system.physmem.perBankRdBursts::10 7771 # Per bank write bursts 63system.physmem.perBankRdBursts::11 7825 # Per bank write bursts 64system.physmem.perBankRdBursts::12 7888 # Per bank write bursts 65system.physmem.perBankRdBursts::13 7870 # Per bank write bursts 66system.physmem.perBankRdBursts::14 7981 # Per bank write bursts 67system.physmem.perBankRdBursts::15 7974 # Per bank write bursts | 62system.physmem.perBankRdBursts::10 7771 # Per bank write bursts 63system.physmem.perBankRdBursts::11 7825 # Per bank write bursts 64system.physmem.perBankRdBursts::12 7888 # Per bank write bursts 65system.physmem.perBankRdBursts::13 7870 # Per bank write bursts 66system.physmem.perBankRdBursts::14 7981 # Per bank write bursts 67system.physmem.perBankRdBursts::15 7974 # Per bank write bursts |
| 68system.physmem.perBankWrBursts::0 5399 # Per bank write bursts | 68system.physmem.perBankWrBursts::0 5400 # Per bank write bursts |
| 69system.physmem.perBankWrBursts::1 5549 # Per bank write bursts | 69system.physmem.perBankWrBursts::1 5549 # Per bank write bursts |
| 70system.physmem.perBankWrBursts::2 5476 # Per bank write bursts 71system.physmem.perBankWrBursts::3 5348 # Per bank write bursts | 70system.physmem.perBankWrBursts::2 5475 # Per bank write bursts 71system.physmem.perBankWrBursts::3 5349 # Per bank write bursts |
| 72system.physmem.perBankWrBursts::4 5387 # Per bank write bursts | 72system.physmem.perBankWrBursts::4 5387 # Per bank write bursts |
| 73system.physmem.perBankWrBursts::5 5588 # Per bank write bursts | 73system.physmem.perBankWrBursts::5 5586 # Per bank write bursts |
| 74system.physmem.perBankWrBursts::6 5325 # Per bank write bursts 75system.physmem.perBankWrBursts::7 5260 # Per bank write bursts 76system.physmem.perBankWrBursts::8 5187 # Per bank write bursts | 74system.physmem.perBankWrBursts::6 5325 # Per bank write bursts 75system.physmem.perBankWrBursts::7 5260 # Per bank write bursts 76system.physmem.perBankWrBursts::8 5187 # Per bank write bursts |
| 77system.physmem.perBankWrBursts::9 5136 # Per bank write bursts | 77system.physmem.perBankWrBursts::9 5135 # Per bank write bursts |
| 78system.physmem.perBankWrBursts::10 5306 # Per bank write bursts 79system.physmem.perBankWrBursts::11 5279 # Per bank write bursts 80system.physmem.perBankWrBursts::12 5541 # Per bank write bursts 81system.physmem.perBankWrBursts::13 5597 # Per bank write bursts 82system.physmem.perBankWrBursts::14 5706 # Per bank write bursts 83system.physmem.perBankWrBursts::15 5441 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 78system.physmem.perBankWrBursts::10 5306 # Per bank write bursts 79system.physmem.perBankWrBursts::11 5279 # Per bank write bursts 80system.physmem.perBankWrBursts::12 5541 # Per bank write bursts 81system.physmem.perBankWrBursts::13 5597 # Per bank write bursts 82system.physmem.perBankWrBursts::14 5706 # Per bank write bursts 83system.physmem.perBankWrBursts::15 5441 # Per bank write bursts 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 86system.physmem.totGap 58750379000 # Total gap between requests | 86system.physmem.totGap 60130703000 # Total gap between requests |
| 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 128515 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 86552 # Write request sizes (log2) | 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) 93system.physmem.readPktSize::6 128515 # Read request sizes (log2) 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) 100system.physmem.writePktSize::6 86552 # Write request sizes (log2) |
| 101system.physmem.rdQLenPdf::0 116239 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 12249 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::0 116093 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 12374 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 26 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::15 470 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 477 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 5340 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 5346 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 5349 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 5348 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 5355 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 5356 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 5371 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 5382 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 5490 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 5388 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 5469 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 5417 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 5499 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 5347 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::15 442 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 447 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 4746 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 5341 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 5353 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 5353 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 5356 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 5357 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 5353 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 5356 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 5371 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 5373 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 5375 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 5413 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 5459 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 5434 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 5406 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 5596 # What write queue length does an incoming req see |
| 166system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see | 166system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see |
| 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see | 167system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 197system.physmem.bytesPerActivate::samples 32968 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 417.384130 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 256.722785 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 362.908382 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 8749 26.54% 26.54% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 6430 19.50% 46.04% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 3309 10.04% 56.08% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 2430 7.37% 63.45% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 2267 6.88% 70.33% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 1599 4.85% 75.18% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 1281 3.89% 79.06% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 1267 3.84% 82.90% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 5636 17.10% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 32968 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 5346 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 24.036289 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 17.665302 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 347.416280 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 5344 99.96% 99.96% # Reads before turning the bus around for writes | 197system.physmem.bytesPerActivate::samples 32872 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 418.606960 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 258.790126 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 361.910519 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 8567 26.06% 26.06% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 6423 19.54% 45.60% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 3392 10.32% 55.92% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 2472 7.52% 63.44% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 2230 6.78% 70.22% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 1616 4.92% 75.14% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 1339 4.07% 79.21% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 1211 3.68% 82.90% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 5622 17.10% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 32872 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 5350 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 24.018131 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 17.666671 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 347.276238 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 5348 99.96% 99.96% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes | 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::total 5346 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 5346 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.184998 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.174634 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.600598 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 4870 91.10% 91.10% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 4 0.07% 91.17% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 438 8.19% 99.36% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 27 0.51% 99.87% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 7 0.13% 100.00% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::total 5346 # Writes before turning the bus around for reads 229system.physmem.totQLat 1552277750 # Total ticks spent queuing 230system.physmem.totMemAccLat 3961802750 # Total ticks spent from burst creation until serviced by the DRAM 231system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers 232system.physmem.avgQLat 12079.23 # Average queueing delay per DRAM burst | 218system.physmem.rdPerTurnAround::total 5350 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 5350 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.172523 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.162775 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.583592 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 4904 91.66% 91.66% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 3 0.06% 91.72% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 417 7.79% 99.51% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 22 0.41% 99.93% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 3 0.06% 99.98% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::24 1 0.02% 100.00% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::total 5350 # Writes before turning the bus around for reads 230system.physmem.totQLat 3048956750 # Total ticks spent queuing 231system.physmem.totMemAccLat 5458519250 # Total ticks spent from burst creation until serviced by the DRAM 232system.physmem.totBusLat 642550000 # Total ticks spent in databus transfers 233system.physmem.avgQLat 23725.44 # Average queueing delay per DRAM burst |
| 233system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 234system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 234system.physmem.avgMemAccLat 30829.23 # Average memory access latency per DRAM burst 235system.physmem.avgRdBW 139.99 # Average DRAM read bandwidth in MiByte/s 236system.physmem.avgWrBW 94.26 # Average achieved write bandwidth in MiByte/s 237system.physmem.avgRdBWSys 140.00 # Average system read bandwidth in MiByte/s 238system.physmem.avgWrBWSys 94.29 # Average system write bandwidth in MiByte/s | 235system.physmem.avgMemAccLat 42475.44 # Average memory access latency per DRAM burst 236system.physmem.avgRdBW 136.78 # Average DRAM read bandwidth in MiByte/s 237system.physmem.avgWrBW 92.09 # Average achieved write bandwidth in MiByte/s 238system.physmem.avgRdBWSys 136.78 # Average system read bandwidth in MiByte/s 239system.physmem.avgWrBWSys 92.12 # Average system write bandwidth in MiByte/s |
| 239system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 240system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 240system.physmem.busUtil 1.83 # Data bus utilization in percentage 241system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads 242system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes | 241system.physmem.busUtil 1.79 # Data bus utilization in percentage 242system.physmem.busUtilRead 1.07 # Data bus utilization in percentage for reads 243system.physmem.busUtilWrite 0.72 # Data bus utilization in percentage for writes |
| 243system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing | 244system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| 244system.physmem.avgWrQLen 23.56 # Average write queue length when enqueuing 245system.physmem.readRowHits 112029 # Number of row buffer hits during reads 246system.physmem.writeRowHits 70027 # Number of row buffer hits during writes 247system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads 248system.physmem.writeRowHitRate 80.91 # Row buffer hit rate for writes 249system.physmem.avgGap 273172.45 # Average gap between requests 250system.physmem.pageHitRate 84.65 # Row buffer hit rate, read and write combined 251system.physmem_0.actEnergy 130599000 # Energy for activate commands per rank (pJ) 252system.physmem_0.preEnergy 71259375 # Energy for precharge commands per rank (pJ) 253system.physmem_0.readEnergy 511009200 # Energy for read commands per rank (pJ) 254system.physmem_0.writeEnergy 280655280 # Energy for write commands per rank (pJ) 255system.physmem_0.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) 256system.physmem_0.actBackEnergy 11237331690 # Energy for active background per rank (pJ) 257system.physmem_0.preBackEnergy 25391203500 # Energy for precharge background per rank (pJ) 258system.physmem_0.totalEnergy 41459143245 # Total energy per rank (pJ) 259system.physmem_0.averagePower 705.717335 # Core power per rank (mW) 260system.physmem_0.memoryStateTime::IDLE 42124223000 # Time in different power states 261system.physmem_0.memoryStateTime::REF 1961700000 # Time in different power states 262system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 263system.physmem_0.memoryStateTime::ACT 14661610750 # Time in different power states 264system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 265system.physmem_1.actEnergy 118555920 # Energy for activate commands per rank (pJ) 266system.physmem_1.preEnergy 64688250 # Energy for precharge commands per rank (pJ) 267system.physmem_1.readEnergy 491072400 # Energy for read commands per rank (pJ) 268system.physmem_1.writeEnergy 279819360 # Energy for write commands per rank (pJ) 269system.physmem_1.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) 270system.physmem_1.actBackEnergy 10919729115 # Energy for active background per rank (pJ) 271system.physmem_1.preBackEnergy 25669800000 # Energy for precharge background per rank (pJ) 272system.physmem_1.totalEnergy 41380750245 # Total energy per rank (pJ) 273system.physmem_1.averagePower 704.382975 # Core power per rank (mW) 274system.physmem_1.memoryStateTime::IDLE 42589738750 # Time in different power states 275system.physmem_1.memoryStateTime::REF 1961700000 # Time in different power states 276system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 277system.physmem_1.memoryStateTime::ACT 14196261750 # Time in different power states 278system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 279system.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 280system.cpu.branchPred.lookups 14827613 # Number of BP lookups 281system.cpu.branchPred.condPredicted 9922572 # Number of conditional branches predicted 282system.cpu.branchPred.condIncorrect 342024 # Number of conditional branches incorrect 283system.cpu.branchPred.BTBLookups 9662819 # Number of BTB lookups 284system.cpu.branchPred.BTBHits 6571830 # Number of BTB hits | 245system.physmem.avgWrQLen 23.60 # Average write queue length when enqueuing 246system.physmem.readRowHits 112228 # Number of row buffer hits during reads 247system.physmem.writeRowHits 69923 # Number of row buffer hits during writes 248system.physmem.readRowHitRate 87.33 # Row buffer hit rate for reads 249system.physmem.writeRowHitRate 80.79 # Row buffer hit rate for writes 250system.physmem.avgGap 279590.56 # Average gap between requests 251system.physmem.pageHitRate 84.70 # Row buffer hit rate, read and write combined 252system.physmem_0.actEnergy 123522000 # Energy for activate commands per rank (pJ) 253system.physmem_0.preEnergy 65634525 # Energy for precharge commands per rank (pJ) 254system.physmem_0.readEnergy 467912760 # Energy for read commands per rank (pJ) 255system.physmem_0.writeEnergy 226187820 # Energy for write commands per rank (pJ) 256system.physmem_0.refreshEnergy 2501584800.000000 # Energy for refresh commands per rank (pJ) 257system.physmem_0.actBackEnergy 2202428130 # Energy for active background per rank (pJ) 258system.physmem_0.preBackEnergy 166870080 # Energy for precharge background per rank (pJ) 259system.physmem_0.actPowerDownEnergy 5871636120 # Energy for active power-down per rank (pJ) 260system.physmem_0.prePowerDownEnergy 2984284320 # Energy for precharge power-down per rank (pJ) 261system.physmem_0.selfRefreshEnergy 8652824730 # Energy for self refresh per rank (pJ) 262system.physmem_0.totalEnergy 23263603845 # Total energy per rank (pJ) 263system.physmem_0.averagePower 386.883743 # Core power per rank (mW) 264system.physmem_0.totalIdleTime 54864406750 # Total Idle time Per DRAM Rank 265system.physmem_0.memoryStateTime::IDLE 285894000 # Time in different power states 266system.physmem_0.memoryStateTime::REF 1063168000 # Time in different power states 267system.physmem_0.memoryStateTime::SREF 34216733000 # Time in different power states 268system.physmem_0.memoryStateTime::PRE_PDN 7771569500 # Time in different power states 269system.physmem_0.memoryStateTime::ACT 3916970000 # Time in different power states 270system.physmem_0.memoryStateTime::ACT_PDN 12876400000 # Time in different power states 271system.physmem_1.actEnergy 111255480 # Energy for activate commands per rank (pJ) 272system.physmem_1.preEnergy 59114715 # Energy for precharge commands per rank (pJ) 273system.physmem_1.readEnergy 449648640 # Energy for read commands per rank (pJ) 274system.physmem_1.writeEnergy 225462240 # Energy for write commands per rank (pJ) 275system.physmem_1.refreshEnergy 2476999200.000000 # Energy for refresh commands per rank (pJ) 276system.physmem_1.actBackEnergy 2186718930 # Energy for active background per rank (pJ) 277system.physmem_1.preBackEnergy 154089120 # Energy for precharge background per rank (pJ) 278system.physmem_1.actPowerDownEnergy 5325084780 # Energy for active power-down per rank (pJ) 279system.physmem_1.prePowerDownEnergy 3204564480 # Energy for precharge power-down per rank (pJ) 280system.physmem_1.selfRefreshEnergy 8848391460 # Energy for self refresh per rank (pJ) 281system.physmem_1.totalEnergy 23042110905 # Total energy per rank (pJ) 282system.physmem_1.averagePower 383.200220 # Core power per rank (mW) 283system.physmem_1.totalIdleTime 54932244750 # Total Idle time Per DRAM Rank 284system.physmem_1.memoryStateTime::IDLE 256290500 # Time in different power states 285system.physmem_1.memoryStateTime::REF 1053008000 # Time in different power states 286system.physmem_1.memoryStateTime::SREF 34909248000 # Time in different power states 287system.physmem_1.memoryStateTime::PRE_PDN 8345212750 # Time in different power states 288system.physmem_1.memoryStateTime::ACT 3889130500 # Time in different power states 289system.physmem_1.memoryStateTime::ACT_PDN 11677844750 # Time in different power states 290system.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states 291system.cpu.branchPred.lookups 14827796 # Number of BP lookups 292system.cpu.branchPred.condPredicted 9922694 # Number of conditional branches predicted 293system.cpu.branchPred.condIncorrect 342031 # Number of conditional branches incorrect 294system.cpu.branchPred.BTBLookups 9662876 # Number of BTB lookups 295system.cpu.branchPred.BTBHits 6571901 # Number of BTB hits |
| 285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 296system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 286system.cpu.branchPred.BTBHitPct 68.011519 # BTB Hit Percentage 287system.cpu.branchPred.usedRAS 1720035 # Number of times the RAS was used to get a target. | 297system.cpu.branchPred.BTBHitPct 68.011853 # BTB Hit Percentage 298system.cpu.branchPred.usedRAS 1720083 # Number of times the RAS was used to get a target. |
| 288system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. | 299system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. |
| 289system.cpu.branchPred.indirectLookups 175655 # Number of indirect predictor lookups. 290system.cpu.branchPred.indirectHits 158613 # Number of indirect target hits. | 300system.cpu.branchPred.indirectLookups 175657 # Number of indirect predictor lookups. 301system.cpu.branchPred.indirectHits 158615 # Number of indirect target hits. |
| 291system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. 292system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. 293system.cpu_clk_domain.clock 500 # Clock period in ticks | 302system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. 303system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. 304system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 294system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 305system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 295system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 316system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 317system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 318system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 319system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 320system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 321system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 322system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 323system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 306system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 307system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 308system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 309system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 310system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 311system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 312system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 313system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 327system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 328system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 329system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 330system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 331system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 332system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 333system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 334system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 324system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 335system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 325system.cpu.dtb.walker.walks 0 # Table walker walks requested 326system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.dtb.read_accesses 0 # DTB read accesses 349system.cpu.dtb.write_accesses 0 # DTB write accesses 350system.cpu.dtb.inst_accesses 0 # ITB inst accesses 351system.cpu.dtb.hits 0 # DTB hits 352system.cpu.dtb.misses 0 # DTB misses 353system.cpu.dtb.accesses 0 # DTB accesses | 336system.cpu.dtb.walker.walks 0 # Table walker walks requested 337system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 338system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 339system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 340system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 341system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 342system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 343system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 357system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 358system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 359system.cpu.dtb.read_accesses 0 # DTB read accesses 360system.cpu.dtb.write_accesses 0 # DTB write accesses 361system.cpu.dtb.inst_accesses 0 # ITB inst accesses 362system.cpu.dtb.hits 0 # DTB hits 363system.cpu.dtb.misses 0 # DTB misses 364system.cpu.dtb.accesses 0 # DTB accesses |
| 354system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 365system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 355system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 376system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 379system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 380system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 381system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 382system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 383system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 366system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 367system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 368system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 369system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 370system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 371system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 372system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 373system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 387system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 388system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 389system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 390system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 391system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 392system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 393system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 394system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 384system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 395system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 385system.cpu.itb.walker.walks 0 # Table walker walks requested 386system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 407system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu.itb.read_accesses 0 # DTB read accesses 409system.cpu.itb.write_accesses 0 # DTB write accesses 410system.cpu.itb.inst_accesses 0 # ITB inst accesses 411system.cpu.itb.hits 0 # DTB hits 412system.cpu.itb.misses 0 # DTB misses 413system.cpu.itb.accesses 0 # DTB accesses 414system.cpu.workload.num_syscalls 1946 # Number of system calls | 396system.cpu.itb.walker.walks 0 # Table walker walks requested 397system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 398system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 399system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 400system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 401system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 402system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 403system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 418system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 419system.cpu.itb.read_accesses 0 # DTB read accesses 420system.cpu.itb.write_accesses 0 # DTB write accesses 421system.cpu.itb.inst_accesses 0 # ITB inst accesses 422system.cpu.itb.hits 0 # DTB hits 423system.cpu.itb.misses 0 # DTB misses 424system.cpu.itb.accesses 0 # DTB accesses 425system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 415system.cpu.pwrStateResidencyTicks::ON 58750410500 # Cumulative time (in ticks) in various power states 416system.cpu.numCycles 117500821 # number of cpu cycles simulated | 426system.cpu.pwrStateResidencyTicks::ON 60130734500 # Cumulative time (in ticks) in various power states 427system.cpu.numCycles 120261469 # number of cpu cycles simulated |
| 417system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 418system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 419system.cpu.committedInsts 70915150 # Number of instructions committed 420system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed | 428system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 429system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 430system.cpu.committedInsts 70915150 # Number of instructions committed 431system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed |
| 421system.cpu.discardedOps 1179078 # Number of ops (including micro ops) which were discarded before commit | 432system.cpu.discardedOps 1179235 # Number of ops (including micro ops) which were discarded before commit |
| 422system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 433system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 423system.cpu.cpi 1.656921 # CPI: cycles per instruction 424system.cpu.ipc 0.603529 # IPC: instructions per cycle | 434system.cpu.cpi 1.695850 # CPI: cycles per instruction 435system.cpu.ipc 0.589675 # IPC: instructions per cycle |
| 425system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 426system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction 427system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 428system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 429system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 430system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 431system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 432system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 452system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 453system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 454system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 455system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 456system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction 457system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 458system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 459system.cpu.op_class_0::total 90690106 # Class of committed instruction | 436system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 437system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction 438system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 439system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 440system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 441system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 442system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 443system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 463system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 464system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 465system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 466system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 467system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction 468system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 469system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 470system.cpu.op_class_0::total 90690106 # Class of committed instruction |
| 460system.cpu.tickCycles 97998947 # Number of cycles that the object actually ticked 461system.cpu.idleCycles 19501874 # Total number of cycles that the object has spent stopped 462system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 471system.cpu.tickCycles 98354903 # Number of cycles that the object actually ticked 472system.cpu.idleCycles 21906566 # Total number of cycles that the object has spent stopped 473system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 463system.cpu.dcache.tags.replacements 156451 # number of replacements | 474system.cpu.dcache.tags.replacements 156451 # number of replacements |
| 464system.cpu.dcache.tags.tagsinuse 4067.791520 # Cycle average of tags in use 465system.cpu.dcache.tags.total_refs 42637484 # Total number of references to valid blocks. | 475system.cpu.dcache.tags.tagsinuse 4067.127252 # Cycle average of tags in use 476system.cpu.dcache.tags.total_refs 42637295 # Total number of references to valid blocks. |
| 466system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. | 477system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. |
| 467system.cpu.dcache.tags.avg_refs 265.576336 # Average number of references to valid blocks. 468system.cpu.dcache.tags.warmup_cycle 830343500 # Cycle when the warmup percentage was hit. 469system.cpu.dcache.tags.occ_blocks::cpu.data 4067.791520 # Average occupied blocks per requestor 470system.cpu.dcache.tags.occ_percent::cpu.data 0.993113 # Average percentage of cache occupancy 471system.cpu.dcache.tags.occ_percent::total 0.993113 # Average percentage of cache occupancy | 478system.cpu.dcache.tags.avg_refs 265.575159 # Average number of references to valid blocks. 479system.cpu.dcache.tags.warmup_cycle 880684500 # Cycle when the warmup percentage was hit. 480system.cpu.dcache.tags.occ_blocks::cpu.data 4067.127252 # Average occupied blocks per requestor 481system.cpu.dcache.tags.occ_percent::cpu.data 0.992951 # Average percentage of cache occupancy 482system.cpu.dcache.tags.occ_percent::total 0.992951 # Average percentage of cache occupancy |
| 472system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id | 483system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| 473system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 474system.cpu.dcache.tags.age_task_id_blocks_1024::1 1054 # Occupied blocks per task id 475system.cpu.dcache.tags.age_task_id_blocks_1024::2 2998 # Occupied blocks per task id | 484system.cpu.dcache.tags.age_task_id_blocks_1024::0 43 # Occupied blocks per task id 485system.cpu.dcache.tags.age_task_id_blocks_1024::1 1009 # Occupied blocks per task id 486system.cpu.dcache.tags.age_task_id_blocks_1024::2 3044 # Occupied blocks per task id |
| 476system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 487system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 477system.cpu.dcache.tags.tag_accesses 86035297 # Number of tag accesses 478system.cpu.dcache.tags.data_accesses 86035297 # Number of data accesses 479system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 480system.cpu.dcache.ReadReq_hits::cpu.data 22880319 # number of ReadReq hits 481system.cpu.dcache.ReadReq_hits::total 22880319 # number of ReadReq hits 482system.cpu.dcache.WriteReq_hits::cpu.data 19642152 # number of WriteReq hits 483system.cpu.dcache.WriteReq_hits::total 19642152 # number of WriteReq hits 484system.cpu.dcache.SoftPFReq_hits::cpu.data 83175 # number of SoftPFReq hits 485system.cpu.dcache.SoftPFReq_hits::total 83175 # number of SoftPFReq hits | 488system.cpu.dcache.tags.tag_accesses 86034713 # Number of tag accesses 489system.cpu.dcache.tags.data_accesses 86034713 # Number of data accesses 490system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states 491system.cpu.dcache.ReadReq_hits::cpu.data 22880152 # number of ReadReq hits 492system.cpu.dcache.ReadReq_hits::total 22880152 # number of ReadReq hits 493system.cpu.dcache.WriteReq_hits::cpu.data 19642142 # number of WriteReq hits 494system.cpu.dcache.WriteReq_hits::total 19642142 # number of WriteReq hits 495system.cpu.dcache.SoftPFReq_hits::cpu.data 83163 # number of SoftPFReq hits 496system.cpu.dcache.SoftPFReq_hits::total 83163 # number of SoftPFReq hits |
| 486system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 487system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 488system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 489system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits | 497system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 498system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 499system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 500system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| 490system.cpu.dcache.demand_hits::cpu.data 42522471 # number of demand (read+write) hits 491system.cpu.dcache.demand_hits::total 42522471 # number of demand (read+write) hits 492system.cpu.dcache.overall_hits::cpu.data 42605646 # number of overall hits 493system.cpu.dcache.overall_hits::total 42605646 # number of overall hits 494system.cpu.dcache.ReadReq_misses::cpu.data 47369 # number of ReadReq misses 495system.cpu.dcache.ReadReq_misses::total 47369 # number of ReadReq misses 496system.cpu.dcache.WriteReq_misses::cpu.data 207749 # number of WriteReq misses 497system.cpu.dcache.WriteReq_misses::total 207749 # number of WriteReq misses 498system.cpu.dcache.SoftPFReq_misses::cpu.data 44773 # number of SoftPFReq misses 499system.cpu.dcache.SoftPFReq_misses::total 44773 # number of SoftPFReq misses 500system.cpu.dcache.demand_misses::cpu.data 255118 # number of demand (read+write) misses 501system.cpu.dcache.demand_misses::total 255118 # number of demand (read+write) misses 502system.cpu.dcache.overall_misses::cpu.data 299891 # number of overall misses 503system.cpu.dcache.overall_misses::total 299891 # number of overall misses 504system.cpu.dcache.ReadReq_miss_latency::cpu.data 1548941500 # number of ReadReq miss cycles 505system.cpu.dcache.ReadReq_miss_latency::total 1548941500 # number of ReadReq miss cycles 506system.cpu.dcache.WriteReq_miss_latency::cpu.data 16628210000 # number of WriteReq miss cycles 507system.cpu.dcache.WriteReq_miss_latency::total 16628210000 # number of WriteReq miss cycles 508system.cpu.dcache.demand_miss_latency::cpu.data 18177151500 # number of demand (read+write) miss cycles 509system.cpu.dcache.demand_miss_latency::total 18177151500 # number of demand (read+write) miss cycles 510system.cpu.dcache.overall_miss_latency::cpu.data 18177151500 # number of overall miss cycles 511system.cpu.dcache.overall_miss_latency::total 18177151500 # number of overall miss cycles 512system.cpu.dcache.ReadReq_accesses::cpu.data 22927688 # number of ReadReq accesses(hits+misses) 513system.cpu.dcache.ReadReq_accesses::total 22927688 # number of ReadReq accesses(hits+misses) | 501system.cpu.dcache.demand_hits::cpu.data 42522294 # number of demand (read+write) hits 502system.cpu.dcache.demand_hits::total 42522294 # number of demand (read+write) hits 503system.cpu.dcache.overall_hits::cpu.data 42605457 # number of overall hits 504system.cpu.dcache.overall_hits::total 42605457 # number of overall hits 505system.cpu.dcache.ReadReq_misses::cpu.data 47246 # number of ReadReq misses 506system.cpu.dcache.ReadReq_misses::total 47246 # number of ReadReq misses 507system.cpu.dcache.WriteReq_misses::cpu.data 207759 # number of WriteReq misses 508system.cpu.dcache.WriteReq_misses::total 207759 # number of WriteReq misses 509system.cpu.dcache.SoftPFReq_misses::cpu.data 44783 # number of SoftPFReq misses 510system.cpu.dcache.SoftPFReq_misses::total 44783 # number of SoftPFReq misses 511system.cpu.dcache.demand_misses::cpu.data 255005 # number of demand (read+write) misses 512system.cpu.dcache.demand_misses::total 255005 # number of demand (read+write) misses 513system.cpu.dcache.overall_misses::cpu.data 299788 # number of overall misses 514system.cpu.dcache.overall_misses::total 299788 # number of overall misses 515system.cpu.dcache.ReadReq_miss_latency::cpu.data 1839858000 # number of ReadReq miss cycles 516system.cpu.dcache.ReadReq_miss_latency::total 1839858000 # number of ReadReq miss cycles 517system.cpu.dcache.WriteReq_miss_latency::cpu.data 18545282000 # number of WriteReq miss cycles 518system.cpu.dcache.WriteReq_miss_latency::total 18545282000 # number of WriteReq miss cycles 519system.cpu.dcache.demand_miss_latency::cpu.data 20385140000 # number of demand (read+write) miss cycles 520system.cpu.dcache.demand_miss_latency::total 20385140000 # number of demand (read+write) miss cycles 521system.cpu.dcache.overall_miss_latency::cpu.data 20385140000 # number of overall miss cycles 522system.cpu.dcache.overall_miss_latency::total 20385140000 # number of overall miss cycles 523system.cpu.dcache.ReadReq_accesses::cpu.data 22927398 # number of ReadReq accesses(hits+misses) 524system.cpu.dcache.ReadReq_accesses::total 22927398 # number of ReadReq accesses(hits+misses) |
| 514system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 515system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) | 525system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 526system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| 516system.cpu.dcache.SoftPFReq_accesses::cpu.data 127948 # number of SoftPFReq accesses(hits+misses) 517system.cpu.dcache.SoftPFReq_accesses::total 127948 # number of SoftPFReq accesses(hits+misses) | 527system.cpu.dcache.SoftPFReq_accesses::cpu.data 127946 # number of SoftPFReq accesses(hits+misses) 528system.cpu.dcache.SoftPFReq_accesses::total 127946 # number of SoftPFReq accesses(hits+misses) |
| 518system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 519system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 520system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 521system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) | 529system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 530system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 531system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 532system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| 522system.cpu.dcache.demand_accesses::cpu.data 42777589 # number of demand (read+write) accesses 523system.cpu.dcache.demand_accesses::total 42777589 # number of demand (read+write) accesses 524system.cpu.dcache.overall_accesses::cpu.data 42905537 # number of overall (read+write) accesses 525system.cpu.dcache.overall_accesses::total 42905537 # number of overall (read+write) accesses 526system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002066 # miss rate for ReadReq accesses 527system.cpu.dcache.ReadReq_miss_rate::total 0.002066 # miss rate for ReadReq accesses 528system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses 529system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses 530system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349931 # miss rate for SoftPFReq accesses 531system.cpu.dcache.SoftPFReq_miss_rate::total 0.349931 # miss rate for SoftPFReq accesses 532system.cpu.dcache.demand_miss_rate::cpu.data 0.005964 # miss rate for demand accesses 533system.cpu.dcache.demand_miss_rate::total 0.005964 # miss rate for demand accesses 534system.cpu.dcache.overall_miss_rate::cpu.data 0.006990 # miss rate for overall accesses 535system.cpu.dcache.overall_miss_rate::total 0.006990 # miss rate for overall accesses 536system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32699.476451 # average ReadReq miss latency 537system.cpu.dcache.ReadReq_avg_miss_latency::total 32699.476451 # average ReadReq miss latency 538system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80039.903923 # average WriteReq miss latency 539system.cpu.dcache.WriteReq_avg_miss_latency::total 80039.903923 # average WriteReq miss latency 540system.cpu.dcache.demand_avg_miss_latency::cpu.data 71249.976481 # average overall miss latency 541system.cpu.dcache.demand_avg_miss_latency::total 71249.976481 # average overall miss latency 542system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552 # average overall miss latency 543system.cpu.dcache.overall_avg_miss_latency::total 60612.527552 # average overall miss latency 544system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 533system.cpu.dcache.demand_accesses::cpu.data 42777299 # number of demand (read+write) accesses 534system.cpu.dcache.demand_accesses::total 42777299 # number of demand (read+write) accesses 535system.cpu.dcache.overall_accesses::cpu.data 42905245 # number of overall (read+write) accesses 536system.cpu.dcache.overall_accesses::total 42905245 # number of overall (read+write) accesses 537system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002061 # miss rate for ReadReq accesses 538system.cpu.dcache.ReadReq_miss_rate::total 0.002061 # miss rate for ReadReq accesses 539system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010467 # miss rate for WriteReq accesses 540system.cpu.dcache.WriteReq_miss_rate::total 0.010467 # miss rate for WriteReq accesses 541system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.350015 # miss rate for SoftPFReq accesses 542system.cpu.dcache.SoftPFReq_miss_rate::total 0.350015 # miss rate for SoftPFReq accesses 543system.cpu.dcache.demand_miss_rate::cpu.data 0.005961 # miss rate for demand accesses 544system.cpu.dcache.demand_miss_rate::total 0.005961 # miss rate for demand accesses 545system.cpu.dcache.overall_miss_rate::cpu.data 0.006987 # miss rate for overall accesses 546system.cpu.dcache.overall_miss_rate::total 0.006987 # miss rate for overall accesses 547system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38942.090336 # average ReadReq miss latency 548system.cpu.dcache.ReadReq_avg_miss_latency::total 38942.090336 # average ReadReq miss latency 549system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 89263.435038 # average WriteReq miss latency 550system.cpu.dcache.WriteReq_avg_miss_latency::total 89263.435038 # average WriteReq miss latency 551system.cpu.dcache.demand_avg_miss_latency::cpu.data 79940.158036 # average overall miss latency 552system.cpu.dcache.demand_avg_miss_latency::total 79940.158036 # average overall miss latency 553system.cpu.dcache.overall_avg_miss_latency::cpu.data 67998.518953 # average overall miss latency 554system.cpu.dcache.overall_avg_miss_latency::total 67998.518953 # average overall miss latency 555system.cpu.dcache.blocked_cycles::no_mshrs 185 # number of cycles access was blocked |
| 545system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 556system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 546system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked | 557system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked |
| 547system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 558system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 548system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 559system.cpu.dcache.avg_blocked_cycles::no_mshrs 185 # average number of cycles each access was blocked |
| 549system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 550system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks 551system.cpu.dcache.writebacks::total 128145 # number of writebacks | 560system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 561system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks 562system.cpu.dcache.writebacks::total 128145 # number of writebacks |
| 552system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17840 # number of ReadReq MSHR hits 553system.cpu.dcache.ReadReq_mshr_hits::total 17840 # number of ReadReq MSHR hits 554system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100712 # number of WriteReq MSHR hits 555system.cpu.dcache.WriteReq_mshr_hits::total 100712 # number of WriteReq MSHR hits 556system.cpu.dcache.demand_mshr_hits::cpu.data 118552 # number of demand (read+write) MSHR hits 557system.cpu.dcache.demand_mshr_hits::total 118552 # number of demand (read+write) MSHR hits 558system.cpu.dcache.overall_mshr_hits::cpu.data 118552 # number of overall MSHR hits 559system.cpu.dcache.overall_mshr_hits::total 118552 # number of overall MSHR hits | 563system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17717 # number of ReadReq MSHR hits 564system.cpu.dcache.ReadReq_mshr_hits::total 17717 # number of ReadReq MSHR hits 565system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100722 # number of WriteReq MSHR hits 566system.cpu.dcache.WriteReq_mshr_hits::total 100722 # number of WriteReq MSHR hits 567system.cpu.dcache.demand_mshr_hits::cpu.data 118439 # number of demand (read+write) MSHR hits 568system.cpu.dcache.demand_mshr_hits::total 118439 # number of demand (read+write) MSHR hits 569system.cpu.dcache.overall_mshr_hits::cpu.data 118439 # number of overall MSHR hits 570system.cpu.dcache.overall_mshr_hits::total 118439 # number of overall MSHR hits |
| 560system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses 561system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses 562system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses 563system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses 564system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses 565system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses 566system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses 567system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses 568system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses 569system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses | 571system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses 572system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses 573system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses 574system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses 575system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses 576system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses 577system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses 578system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses 579system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses 580system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses |
| 570system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 586674000 # number of ReadReq MSHR miss cycles 571system.cpu.dcache.ReadReq_mshr_miss_latency::total 586674000 # number of ReadReq MSHR miss cycles 572system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401236500 # number of WriteReq MSHR miss cycles 573system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401236500 # number of WriteReq MSHR miss cycles 574system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788829000 # number of SoftPFReq MSHR miss cycles 575system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788829000 # number of SoftPFReq MSHR miss cycles 576system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910500 # number of demand (read+write) MSHR miss cycles 577system.cpu.dcache.demand_mshr_miss_latency::total 8987910500 # number of demand (read+write) MSHR miss cycles 578system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10776739500 # number of overall MSHR miss cycles 579system.cpu.dcache.overall_mshr_miss_latency::total 10776739500 # number of overall MSHR miss cycles | 581system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 773644500 # number of ReadReq MSHR miss cycles 582system.cpu.dcache.ReadReq_mshr_miss_latency::total 773644500 # number of ReadReq MSHR miss cycles 583system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9479497500 # number of WriteReq MSHR miss cycles 584system.cpu.dcache.WriteReq_mshr_miss_latency::total 9479497500 # number of WriteReq MSHR miss cycles 585system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1896776500 # number of SoftPFReq MSHR miss cycles 586system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1896776500 # number of SoftPFReq MSHR miss cycles 587system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10253142000 # number of demand (read+write) MSHR miss cycles 588system.cpu.dcache.demand_mshr_miss_latency::total 10253142000 # number of demand (read+write) MSHR miss cycles 589system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12149918500 # number of overall MSHR miss cycles 590system.cpu.dcache.overall_mshr_miss_latency::total 12149918500 # number of overall MSHR miss cycles |
| 580system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses 581system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses 582system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 583system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses | 591system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses 592system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses 593system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 594system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses |
| 584system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187428 # mshr miss rate for SoftPFReq accesses 585system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187428 # mshr miss rate for SoftPFReq accesses | 595system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187431 # mshr miss rate for SoftPFReq accesses 596system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187431 # mshr miss rate for SoftPFReq accesses |
| 586system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses 587system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses 588system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 589system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses | 597system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses 598system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses 599system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 600system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses |
| 590system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19867.723255 # average ReadReq mshr miss latency 591system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19867.723255 # average ReadReq mshr miss latency 592system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78489.087885 # average WriteReq mshr miss latency 593system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78489.087885 # average WriteReq mshr miss latency 594system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74593.594929 # average SoftPFReq mshr miss latency 595system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74593.594929 # average SoftPFReq mshr miss latency 596system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65813.676171 # average overall mshr miss latency 597system.cpu.dcache.demand_avg_mshr_miss_latency::total 65813.676171 # average overall mshr miss latency 598system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67125.137810 # average overall mshr miss latency 599system.cpu.dcache.overall_avg_mshr_miss_latency::total 67125.137810 # average overall mshr miss latency 600system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 601system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 26199.481865 # average ReadReq mshr miss latency 602system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 26199.481865 # average ReadReq mshr miss latency 603system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 88562.810056 # average WriteReq mshr miss latency 604system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 88562.810056 # average WriteReq mshr miss latency 605system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 79094.971019 # average SoftPFReq mshr miss latency 606system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 79094.971019 # average SoftPFReq mshr miss latency 607system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75078.291815 # average overall mshr miss latency 608system.cpu.dcache.demand_avg_mshr_miss_latency::total 75078.291815 # average overall mshr miss latency 609system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75678.265555 # average overall mshr miss latency 610system.cpu.dcache.overall_avg_mshr_miss_latency::total 75678.265555 # average overall mshr miss latency 611system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 601system.cpu.icache.tags.replacements 43545 # number of replacements | 612system.cpu.icache.tags.replacements 43545 # number of replacements |
| 602system.cpu.icache.tags.tagsinuse 1854.190293 # Cycle average of tags in use 603system.cpu.icache.tags.total_refs 25047618 # Total number of references to valid blocks. | 613system.cpu.icache.tags.tagsinuse 1852.001681 # Cycle average of tags in use 614system.cpu.icache.tags.total_refs 25048343 # Total number of references to valid blocks. |
| 604system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. | 615system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. |
| 605system.cpu.icache.tags.avg_refs 549.446509 # Average number of references to valid blocks. | 616system.cpu.icache.tags.avg_refs 549.462413 # Average number of references to valid blocks. |
| 606system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 617system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 607system.cpu.icache.tags.occ_blocks::cpu.inst 1854.190293 # Average occupied blocks per requestor 608system.cpu.icache.tags.occ_percent::cpu.inst 0.905366 # Average percentage of cache occupancy 609system.cpu.icache.tags.occ_percent::total 0.905366 # Average percentage of cache occupancy | 618system.cpu.icache.tags.occ_blocks::cpu.inst 1852.001681 # Average occupied blocks per requestor 619system.cpu.icache.tags.occ_percent::cpu.inst 0.904298 # Average percentage of cache occupancy 620system.cpu.icache.tags.occ_percent::total 0.904298 # Average percentage of cache occupancy |
| 610system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id | 621system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id |
| 611system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id | 622system.cpu.icache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id 623system.cpu.icache.tags.age_task_id_blocks_1024::1 54 # Occupied blocks per task id |
| 613system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id | 624system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id |
| 614system.cpu.icache.tags.age_task_id_blocks_1024::3 913 # Occupied blocks per task id 615system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id | 625system.cpu.icache.tags.age_task_id_blocks_1024::3 898 # Occupied blocks per task id 626system.cpu.icache.tags.age_task_id_blocks_1024::4 1021 # Occupied blocks per task id |
| 616system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id | 627system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id |
| 617system.cpu.icache.tags.tag_accesses 50231999 # Number of tag accesses 618system.cpu.icache.tags.data_accesses 50231999 # Number of data accesses 619system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 620system.cpu.icache.ReadReq_hits::cpu.inst 25047618 # number of ReadReq hits 621system.cpu.icache.ReadReq_hits::total 25047618 # number of ReadReq hits 622system.cpu.icache.demand_hits::cpu.inst 25047618 # number of demand (read+write) hits 623system.cpu.icache.demand_hits::total 25047618 # number of demand (read+write) hits 624system.cpu.icache.overall_hits::cpu.inst 25047618 # number of overall hits 625system.cpu.icache.overall_hits::total 25047618 # number of overall hits | 628system.cpu.icache.tags.tag_accesses 50233449 # Number of tag accesses 629system.cpu.icache.tags.data_accesses 50233449 # Number of data accesses 630system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states 631system.cpu.icache.ReadReq_hits::cpu.inst 25048343 # number of ReadReq hits 632system.cpu.icache.ReadReq_hits::total 25048343 # number of ReadReq hits 633system.cpu.icache.demand_hits::cpu.inst 25048343 # number of demand (read+write) hits 634system.cpu.icache.demand_hits::total 25048343 # number of demand (read+write) hits 635system.cpu.icache.overall_hits::cpu.inst 25048343 # number of overall hits 636system.cpu.icache.overall_hits::total 25048343 # number of overall hits |
| 626system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses 627system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses 628system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses 629system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses 630system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses 631system.cpu.icache.overall_misses::total 45588 # number of overall misses | 637system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses 638system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses 639system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses 640system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses 641system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses 642system.cpu.icache.overall_misses::total 45588 # number of overall misses |
| 632system.cpu.icache.ReadReq_miss_latency::cpu.inst 918433000 # number of ReadReq miss cycles 633system.cpu.icache.ReadReq_miss_latency::total 918433000 # number of ReadReq miss cycles 634system.cpu.icache.demand_miss_latency::cpu.inst 918433000 # number of demand (read+write) miss cycles 635system.cpu.icache.demand_miss_latency::total 918433000 # number of demand (read+write) miss cycles 636system.cpu.icache.overall_miss_latency::cpu.inst 918433000 # number of overall miss cycles 637system.cpu.icache.overall_miss_latency::total 918433000 # number of overall miss cycles 638system.cpu.icache.ReadReq_accesses::cpu.inst 25093206 # number of ReadReq accesses(hits+misses) 639system.cpu.icache.ReadReq_accesses::total 25093206 # number of ReadReq accesses(hits+misses) 640system.cpu.icache.demand_accesses::cpu.inst 25093206 # number of demand (read+write) accesses 641system.cpu.icache.demand_accesses::total 25093206 # number of demand (read+write) accesses 642system.cpu.icache.overall_accesses::cpu.inst 25093206 # number of overall (read+write) accesses 643system.cpu.icache.overall_accesses::total 25093206 # number of overall (read+write) accesses | 643system.cpu.icache.ReadReq_miss_latency::cpu.inst 1042270000 # number of ReadReq miss cycles 644system.cpu.icache.ReadReq_miss_latency::total 1042270000 # number of ReadReq miss cycles 645system.cpu.icache.demand_miss_latency::cpu.inst 1042270000 # number of demand (read+write) miss cycles 646system.cpu.icache.demand_miss_latency::total 1042270000 # number of demand (read+write) miss cycles 647system.cpu.icache.overall_miss_latency::cpu.inst 1042270000 # number of overall miss cycles 648system.cpu.icache.overall_miss_latency::total 1042270000 # number of overall miss cycles 649system.cpu.icache.ReadReq_accesses::cpu.inst 25093931 # number of ReadReq accesses(hits+misses) 650system.cpu.icache.ReadReq_accesses::total 25093931 # number of ReadReq accesses(hits+misses) 651system.cpu.icache.demand_accesses::cpu.inst 25093931 # number of demand (read+write) accesses 652system.cpu.icache.demand_accesses::total 25093931 # number of demand (read+write) accesses 653system.cpu.icache.overall_accesses::cpu.inst 25093931 # number of overall (read+write) accesses 654system.cpu.icache.overall_accesses::total 25093931 # number of overall (read+write) accesses |
| 644system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses 645system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses 646system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses 647system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses 648system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses 649system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses | 655system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses 656system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses 657system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses 658system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses 659system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses 660system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses |
| 650system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20146.376239 # average ReadReq miss latency 651system.cpu.icache.ReadReq_avg_miss_latency::total 20146.376239 # average ReadReq miss latency 652system.cpu.icache.demand_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency 653system.cpu.icache.demand_avg_miss_latency::total 20146.376239 # average overall miss latency 654system.cpu.icache.overall_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency 655system.cpu.icache.overall_avg_miss_latency::total 20146.376239 # average overall miss latency | 661system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22862.814776 # average ReadReq miss latency 662system.cpu.icache.ReadReq_avg_miss_latency::total 22862.814776 # average ReadReq miss latency 663system.cpu.icache.demand_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency 664system.cpu.icache.demand_avg_miss_latency::total 22862.814776 # average overall miss latency 665system.cpu.icache.overall_avg_miss_latency::cpu.inst 22862.814776 # average overall miss latency 666system.cpu.icache.overall_avg_miss_latency::total 22862.814776 # average overall miss latency |
| 656system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 657system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 659system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 660system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 661system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 662system.cpu.icache.writebacks::writebacks 43545 # number of writebacks 663system.cpu.icache.writebacks::total 43545 # number of writebacks 664system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45588 # number of ReadReq MSHR misses 665system.cpu.icache.ReadReq_mshr_misses::total 45588 # number of ReadReq MSHR misses 666system.cpu.icache.demand_mshr_misses::cpu.inst 45588 # number of demand (read+write) MSHR misses 667system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses 668system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses 669system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses | 667system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 668system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 669system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 670system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 671system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 672system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 673system.cpu.icache.writebacks::writebacks 43545 # number of writebacks 674system.cpu.icache.writebacks::total 43545 # number of writebacks 675system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45588 # number of ReadReq MSHR misses 676system.cpu.icache.ReadReq_mshr_misses::total 45588 # number of ReadReq MSHR misses 677system.cpu.icache.demand_mshr_misses::cpu.inst 45588 # number of demand (read+write) MSHR misses 678system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses 679system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses 680system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses |
| 670system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 872846000 # number of ReadReq MSHR miss cycles 671system.cpu.icache.ReadReq_mshr_miss_latency::total 872846000 # number of ReadReq MSHR miss cycles 672system.cpu.icache.demand_mshr_miss_latency::cpu.inst 872846000 # number of demand (read+write) MSHR miss cycles 673system.cpu.icache.demand_mshr_miss_latency::total 872846000 # number of demand (read+write) MSHR miss cycles 674system.cpu.icache.overall_mshr_miss_latency::cpu.inst 872846000 # number of overall MSHR miss cycles 675system.cpu.icache.overall_mshr_miss_latency::total 872846000 # number of overall MSHR miss cycles | 681system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 996683000 # number of ReadReq MSHR miss cycles 682system.cpu.icache.ReadReq_mshr_miss_latency::total 996683000 # number of ReadReq MSHR miss cycles 683system.cpu.icache.demand_mshr_miss_latency::cpu.inst 996683000 # number of demand (read+write) MSHR miss cycles 684system.cpu.icache.demand_mshr_miss_latency::total 996683000 # number of demand (read+write) MSHR miss cycles 685system.cpu.icache.overall_mshr_miss_latency::cpu.inst 996683000 # number of overall MSHR miss cycles 686system.cpu.icache.overall_mshr_miss_latency::total 996683000 # number of overall MSHR miss cycles |
| 676system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses 677system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses 678system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses 679system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses 680system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses 681system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses | 687system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses 688system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses 689system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses 690system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses 691system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses 692system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses |
| 682system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19146.398175 # average ReadReq mshr miss latency 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19146.398175 # average ReadReq mshr miss latency 684system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency 686system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency 688system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 693system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21862.836711 # average ReadReq mshr miss latency 694system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21862.836711 # average ReadReq mshr miss latency 695system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency 696system.cpu.icache.demand_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency 697system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21862.836711 # average overall mshr miss latency 698system.cpu.icache.overall_avg_mshr_miss_latency::total 21862.836711 # average overall mshr miss latency 699system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 689system.cpu.l2cache.tags.replacements 97176 # number of replacements | 700system.cpu.l2cache.tags.replacements 97176 # number of replacements |
| 690system.cpu.l2cache.tags.tagsinuse 31328.460689 # Cycle average of tags in use 691system.cpu.l2cache.tags.total_refs 268173 # Total number of references to valid blocks. | 701system.cpu.l2cache.tags.tagsinuse 31292.334990 # Cycle average of tags in use 702system.cpu.l2cache.tags.total_refs 268174 # Total number of references to valid blocks. |
| 692system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. | 703system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. |
| 693system.cpu.l2cache.tags.avg_refs 2.063758 # Average number of references to valid blocks. 694system.cpu.l2cache.tags.warmup_cycle 10596662000 # Cycle when the warmup percentage was hit. 695system.cpu.l2cache.tags.occ_blocks::writebacks 480.299456 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_blocks::cpu.inst 1381.968758 # Average occupied blocks per requestor 697system.cpu.l2cache.tags.occ_blocks::cpu.data 29466.192474 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_percent::writebacks 0.014658 # Average percentage of cache occupancy 699system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042174 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_percent::cpu.data 0.899237 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::total 0.956069 # Average percentage of cache occupancy | 704system.cpu.l2cache.tags.avg_refs 2.063766 # Average number of references to valid blocks. 705system.cpu.l2cache.tags.warmup_cycle 10980034000 # Cycle when the warmup percentage was hit. 706system.cpu.l2cache.tags.occ_blocks::writebacks 476.637646 # Average occupied blocks per requestor 707system.cpu.l2cache.tags.occ_blocks::cpu.inst 1378.081673 # Average occupied blocks per requestor 708system.cpu.l2cache.tags.occ_blocks::cpu.data 29437.615671 # Average occupied blocks per requestor 709system.cpu.l2cache.tags.occ_percent::writebacks 0.014546 # Average percentage of cache occupancy 710system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042056 # Average percentage of cache occupancy 711system.cpu.l2cache.tags.occ_percent::cpu.data 0.898365 # Average percentage of cache occupancy 712system.cpu.l2cache.tags.occ_percent::total 0.954966 # Average percentage of cache occupancy |
| 702system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id | 713system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id |
| 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1189 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13615 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17003 # Occupied blocks per task id | 714system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 715system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1141 # Occupied blocks per task id 716system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12834 # Occupied blocks per task id 717system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17840 # Occupied blocks per task id |
| 707system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id 708system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 709system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses 710system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses | 718system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id 719system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 720system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses 721system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses |
| 711system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 722system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 712system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits 713system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits 714system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits 715system.cpu.l2cache.WritebackClean_hits::total 39944 # number of WritebackClean hits 716system.cpu.l2cache.ReadExReq_hits::cpu.data 4720 # number of ReadExReq hits 717system.cpu.l2cache.ReadExReq_hits::total 4720 # number of ReadExReq hits | 723system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits 724system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits 725system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits 726system.cpu.l2cache.WritebackClean_hits::total 39944 # number of WritebackClean hits 727system.cpu.l2cache.ReadExReq_hits::cpu.data 4720 # number of ReadExReq hits 728system.cpu.l2cache.ReadExReq_hits::total 4720 # number of ReadExReq hits |
| 718system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41100 # number of ReadCleanReq hits 719system.cpu.l2cache.ReadCleanReq_hits::total 41100 # number of ReadCleanReq hits | 729system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41101 # number of ReadCleanReq hits 730system.cpu.l2cache.ReadCleanReq_hits::total 41101 # number of ReadCleanReq hits |
| 720system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31726 # number of ReadSharedReq hits 721system.cpu.l2cache.ReadSharedReq_hits::total 31726 # number of ReadSharedReq hits | 731system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31726 # number of ReadSharedReq hits 732system.cpu.l2cache.ReadSharedReq_hits::total 31726 # number of ReadSharedReq hits |
| 722system.cpu.l2cache.demand_hits::cpu.inst 41100 # number of demand (read+write) hits | 733system.cpu.l2cache.demand_hits::cpu.inst 41101 # number of demand (read+write) hits |
| 723system.cpu.l2cache.demand_hits::cpu.data 36446 # number of demand (read+write) hits | 734system.cpu.l2cache.demand_hits::cpu.data 36446 # number of demand (read+write) hits |
| 724system.cpu.l2cache.demand_hits::total 77546 # number of demand (read+write) hits 725system.cpu.l2cache.overall_hits::cpu.inst 41100 # number of overall hits | 735system.cpu.l2cache.demand_hits::total 77547 # number of demand (read+write) hits 736system.cpu.l2cache.overall_hits::cpu.inst 41101 # number of overall hits |
| 726system.cpu.l2cache.overall_hits::cpu.data 36446 # number of overall hits | 737system.cpu.l2cache.overall_hits::cpu.data 36446 # number of overall hits |
| 727system.cpu.l2cache.overall_hits::total 77546 # number of overall hits | 738system.cpu.l2cache.overall_hits::total 77547 # number of overall hits |
| 728system.cpu.l2cache.ReadExReq_misses::cpu.data 102317 # number of ReadExReq misses 729system.cpu.l2cache.ReadExReq_misses::total 102317 # number of ReadExReq misses | 739system.cpu.l2cache.ReadExReq_misses::cpu.data 102317 # number of ReadExReq misses 740system.cpu.l2cache.ReadExReq_misses::total 102317 # number of ReadExReq misses |
| 730system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4488 # number of ReadCleanReq misses 731system.cpu.l2cache.ReadCleanReq_misses::total 4488 # number of ReadCleanReq misses | 741system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4487 # number of ReadCleanReq misses 742system.cpu.l2cache.ReadCleanReq_misses::total 4487 # number of ReadCleanReq misses |
| 732system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21784 # number of ReadSharedReq misses 733system.cpu.l2cache.ReadSharedReq_misses::total 21784 # number of ReadSharedReq misses | 743system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21784 # number of ReadSharedReq misses 744system.cpu.l2cache.ReadSharedReq_misses::total 21784 # number of ReadSharedReq misses |
| 734system.cpu.l2cache.demand_misses::cpu.inst 4488 # number of demand (read+write) misses | 745system.cpu.l2cache.demand_misses::cpu.inst 4487 # number of demand (read+write) misses |
| 735system.cpu.l2cache.demand_misses::cpu.data 124101 # number of demand (read+write) misses | 746system.cpu.l2cache.demand_misses::cpu.data 124101 # number of demand (read+write) misses |
| 736system.cpu.l2cache.demand_misses::total 128589 # number of demand (read+write) misses 737system.cpu.l2cache.overall_misses::cpu.inst 4488 # number of overall misses | 747system.cpu.l2cache.demand_misses::total 128588 # number of demand (read+write) misses 748system.cpu.l2cache.overall_misses::cpu.inst 4487 # number of overall misses |
| 738system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses | 749system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses |
| 739system.cpu.l2cache.overall_misses::total 128589 # number of overall misses 740system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8191072500 # number of ReadExReq miss cycles 741system.cpu.l2cache.ReadExReq_miss_latency::total 8191072500 # number of ReadExReq miss cycles 742system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 369038000 # number of ReadCleanReq miss cycles 743system.cpu.l2cache.ReadCleanReq_miss_latency::total 369038000 # number of ReadCleanReq miss cycles 744system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1957896000 # number of ReadSharedReq miss cycles 745system.cpu.l2cache.ReadSharedReq_miss_latency::total 1957896000 # number of ReadSharedReq miss cycles 746system.cpu.l2cache.demand_miss_latency::cpu.inst 369038000 # number of demand (read+write) miss cycles 747system.cpu.l2cache.demand_miss_latency::cpu.data 10148968500 # number of demand (read+write) miss cycles 748system.cpu.l2cache.demand_miss_latency::total 10518006500 # number of demand (read+write) miss cycles 749system.cpu.l2cache.overall_miss_latency::cpu.inst 369038000 # number of overall miss cycles 750system.cpu.l2cache.overall_miss_latency::cpu.data 10148968500 # number of overall miss cycles 751system.cpu.l2cache.overall_miss_latency::total 10518006500 # number of overall miss cycles | 750system.cpu.l2cache.overall_misses::total 128588 # number of overall misses 751system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 9269336000 # number of ReadExReq miss cycles 752system.cpu.l2cache.ReadExReq_miss_latency::total 9269336000 # number of ReadExReq miss cycles 753system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 492869500 # number of ReadCleanReq miss cycles 754system.cpu.l2cache.ReadCleanReq_miss_latency::total 492869500 # number of ReadCleanReq miss cycles 755system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 2252818000 # number of ReadSharedReq miss cycles 756system.cpu.l2cache.ReadSharedReq_miss_latency::total 2252818000 # number of ReadSharedReq miss cycles 757system.cpu.l2cache.demand_miss_latency::cpu.inst 492869500 # number of demand (read+write) miss cycles 758system.cpu.l2cache.demand_miss_latency::cpu.data 11522154000 # number of demand (read+write) miss cycles 759system.cpu.l2cache.demand_miss_latency::total 12015023500 # number of demand (read+write) miss cycles 760system.cpu.l2cache.overall_miss_latency::cpu.inst 492869500 # number of overall miss cycles 761system.cpu.l2cache.overall_miss_latency::cpu.data 11522154000 # number of overall miss cycles 762system.cpu.l2cache.overall_miss_latency::total 12015023500 # number of overall miss cycles |
| 752system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses) 753system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses) 754system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses) 755system.cpu.l2cache.WritebackClean_accesses::total 39944 # number of WritebackClean accesses(hits+misses) 756system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses) 757system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses) 758system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45588 # number of ReadCleanReq accesses(hits+misses) 759system.cpu.l2cache.ReadCleanReq_accesses::total 45588 # number of ReadCleanReq accesses(hits+misses) 760system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses) 761system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses) 762system.cpu.l2cache.demand_accesses::cpu.inst 45588 # number of demand (read+write) accesses 763system.cpu.l2cache.demand_accesses::cpu.data 160547 # number of demand (read+write) accesses 764system.cpu.l2cache.demand_accesses::total 206135 # number of demand (read+write) accesses 765system.cpu.l2cache.overall_accesses::cpu.inst 45588 # number of overall (read+write) accesses 766system.cpu.l2cache.overall_accesses::cpu.data 160547 # number of overall (read+write) accesses 767system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses 768system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses 769system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses | 763system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses) 764system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses) 765system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses) 766system.cpu.l2cache.WritebackClean_accesses::total 39944 # number of WritebackClean accesses(hits+misses) 767system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses) 768system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses) 769system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45588 # number of ReadCleanReq accesses(hits+misses) 770system.cpu.l2cache.ReadCleanReq_accesses::total 45588 # number of ReadCleanReq accesses(hits+misses) 771system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses) 772system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses) 773system.cpu.l2cache.demand_accesses::cpu.inst 45588 # number of demand (read+write) accesses 774system.cpu.l2cache.demand_accesses::cpu.data 160547 # number of demand (read+write) accesses 775system.cpu.l2cache.demand_accesses::total 206135 # number of demand (read+write) accesses 776system.cpu.l2cache.overall_accesses::cpu.inst 45588 # number of overall (read+write) accesses 777system.cpu.l2cache.overall_accesses::cpu.data 160547 # number of overall (read+write) accesses 778system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses 779system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses 780system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses |
| 770system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098447 # miss rate for ReadCleanReq accesses 771system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098447 # miss rate for ReadCleanReq accesses | 781system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098425 # miss rate for ReadCleanReq accesses 782system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098425 # miss rate for ReadCleanReq accesses |
| 772system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses 773system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses | 783system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses 784system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses |
| 774system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098447 # miss rate for demand accesses | 785system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098425 # miss rate for demand accesses |
| 775system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses | 786system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses |
| 776system.cpu.l2cache.demand_miss_rate::total 0.623810 # miss rate for demand accesses 777system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098447 # miss rate for overall accesses | 787system.cpu.l2cache.demand_miss_rate::total 0.623805 # miss rate for demand accesses 788system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098425 # miss rate for overall accesses |
| 778system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses | 789system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses |
| 779system.cpu.l2cache.overall_miss_rate::total 0.623810 # miss rate for overall accesses 780system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80055.831387 # average ReadExReq miss latency 781system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80055.831387 # average ReadExReq miss latency 782system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82227.718360 # average ReadCleanReq miss latency 783system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82227.718360 # average ReadCleanReq miss latency 784system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89877.708410 # average ReadSharedReq miss latency 785system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89877.708410 # average ReadSharedReq miss latency 786system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency 787system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency 788system.cpu.l2cache.demand_avg_miss_latency::total 81795.538499 # average overall miss latency 789system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency 790system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency 791system.cpu.l2cache.overall_avg_miss_latency::total 81795.538499 # average overall miss latency | 790system.cpu.l2cache.overall_miss_rate::total 0.623805 # miss rate for overall accesses 791system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 90594.290294 # average ReadExReq miss latency 792system.cpu.l2cache.ReadExReq_avg_miss_latency::total 90594.290294 # average ReadExReq miss latency 793system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 109843.882327 # average ReadCleanReq miss latency 794system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 109843.882327 # average ReadCleanReq miss latency 795system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 103416.177011 # average ReadSharedReq miss latency 796system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 103416.177011 # average ReadSharedReq miss latency 797system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency 798system.cpu.l2cache.demand_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency 799system.cpu.l2cache.demand_avg_miss_latency::total 93438.139640 # average overall miss latency 800system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 109843.882327 # average overall miss latency 801system.cpu.l2cache.overall_avg_miss_latency::cpu.data 92844.973046 # average overall miss latency 802system.cpu.l2cache.overall_avg_miss_latency::total 93438.139640 # average overall miss latency |
| 792system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 793system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 794system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 795system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 796system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 797system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 798system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks 799system.cpu.l2cache.writebacks::total 86552 # number of writebacks | 803system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 804system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 805system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 806system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 807system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 808system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 809system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks 810system.cpu.l2cache.writebacks::total 86552 # number of writebacks |
| 800system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits 801system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits | 811system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits 812system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits |
| 802system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits 803system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits | 813system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits 814system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits |
| 804system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits | 815system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits |
| 805system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits | 816system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits |
| 806system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 807system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits | 817system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 818system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits |
| 808system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits | 819system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits |
| 809system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits | 820system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits |
| 810system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 811system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses 812system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses 813system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses 814system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses 815system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses 816system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses 817system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses 818system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses 819system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses 820system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses 821system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses 822system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses 823system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses | 821system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 822system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses 823system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses 824system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses 825system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses 826system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses 827system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses 828system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses 829system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses 830system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses 831system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses 832system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses 833system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses 834system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses |
| 824system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7167902500 # number of ReadExReq MSHR miss cycles 825system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7167902500 # number of ReadExReq MSHR miss cycles 826system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 323146000 # number of ReadCleanReq MSHR miss cycles 827system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 323146000 # number of ReadCleanReq MSHR miss cycles 828system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1736095500 # number of ReadSharedReq MSHR miss cycles 829system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1736095500 # number of ReadSharedReq MSHR miss cycles 830system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 323146000 # number of demand (read+write) MSHR miss cycles 831system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8903998000 # number of demand (read+write) MSHR miss cycles 832system.cpu.l2cache.demand_mshr_miss_latency::total 9227144000 # number of demand (read+write) MSHR miss cycles 833system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 323146000 # number of overall MSHR miss cycles 834system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8903998000 # number of overall MSHR miss cycles 835system.cpu.l2cache.overall_mshr_miss_latency::total 9227144000 # number of overall MSHR miss cycles | 835system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 8246166000 # number of ReadExReq MSHR miss cycles 836system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 8246166000 # number of ReadExReq MSHR miss cycles 837system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 446702000 # number of ReadCleanReq MSHR miss cycles 838system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 446702000 # number of ReadCleanReq MSHR miss cycles 839system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2029430500 # number of ReadSharedReq MSHR miss cycles 840system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2029430500 # number of ReadSharedReq MSHR miss cycles 841system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 446702000 # number of demand (read+write) MSHR miss cycles 842system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10275596500 # number of demand (read+write) MSHR miss cycles 843system.cpu.l2cache.demand_mshr_miss_latency::total 10722298500 # number of demand (read+write) MSHR miss cycles 844system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 446702000 # number of overall MSHR miss cycles 845system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10275596500 # number of overall MSHR miss cycles 846system.cpu.l2cache.overall_mshr_miss_latency::total 10722298500 # number of overall MSHR miss cycles |
| 836system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 837system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 838system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses 839system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses 840system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses 841system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses 842system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses 843system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses 844system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses 845system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses 846system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses 847system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses 848system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses 849system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses | 847system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 848system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 849system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses 850system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses 851system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses 852system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses 853system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses 854system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses 855system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses 856system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses 857system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses 858system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses 859system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses 860system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses |
| 850system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387 # average ReadExReq mshr miss latency 851system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387 # average ReadExReq mshr miss latency 852system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648 # average ReadCleanReq mshr miss latency 853system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648 # average ReadCleanReq mshr miss latency 854system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546 # average ReadSharedReq mshr miss latency 855system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546 # average ReadSharedReq mshr miss latency 856system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency 857system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency 858system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency 859system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency 860system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency 861system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency | 861system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80594.290294 # average ReadExReq mshr miss latency 862system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80594.290294 # average ReadExReq mshr miss latency 863system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 99821.675978 # average ReadCleanReq mshr miss latency 864system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 99821.675978 # average ReadCleanReq mshr miss latency 865system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 93418.822500 # average ReadSharedReq mshr miss latency 866system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 93418.822500 # average ReadSharedReq mshr miss latency 867system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency 868system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency 869system.cpu.l2cache.demand_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency 870system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 99821.675978 # average overall mshr miss latency 871system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82840.322958 # average overall mshr miss latency 872system.cpu.l2cache.overall_avg_mshr_miss_latency::total 83431.623300 # average overall mshr miss latency |
| 862system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. 863system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. 864system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 865system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. 866system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 867system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 873system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. 874system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. 875system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 876system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. 877system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 878system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 868system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 879system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 869system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution 870system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution 871system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution 875system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution 876system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution --- 13 unchanged lines hidden (view full) --- 890system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram 891system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram 892system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 893system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 894system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 895system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram 896system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) 897system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) | 880system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution 881system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution 882system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution 883system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution 884system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution 885system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution 886system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution 887system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution --- 13 unchanged lines hidden (view full) --- 901system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram 902system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram 903system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 904system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 905system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 906system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram 907system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) 908system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 898system.cpu.toL2Bus.respLayer0.occupancy 68396468 # Layer occupancy (ticks) | 909system.cpu.toL2Bus.respLayer0.occupancy 68395969 # Layer occupancy (ticks) |
| 899system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 900system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) 901system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 902system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter. 903system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data. 904system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 905system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 906system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 907system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 910system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 911system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) 912system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 913system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter. 914system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data. 915system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 916system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 917system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 918system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 908system.membus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states | 919system.membus.pwrStateResidencyTicks::UNDEFINED 60130734500 # Cumulative time (in ticks) in various power states |
| 909system.membus.trans_dist::ReadResp 26198 # Transaction distribution 910system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution 911system.membus.trans_dist::CleanEvict 7237 # Transaction distribution 912system.membus.trans_dist::ReadExReq 102317 # Transaction distribution 913system.membus.trans_dist::ReadExResp 102317 # Transaction distribution 914system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution 915system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes) 916system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 923system.membus.snoop_fanout::stdev 0 # Request fanout histogram 924system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 925system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram 926system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 927system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 928system.membus.snoop_fanout::min_value 0 # Request fanout histogram 929system.membus.snoop_fanout::max_value 0 # Request fanout histogram 930system.membus.snoop_fanout::total 128515 # Request fanout histogram | 920system.membus.trans_dist::ReadResp 26198 # Transaction distribution 921system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution 922system.membus.trans_dist::CleanEvict 7237 # Transaction distribution 923system.membus.trans_dist::ReadExReq 102317 # Transaction distribution 924system.membus.trans_dist::ReadExResp 102317 # Transaction distribution 925system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution 926system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes) 927system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes) --- 6 unchanged lines hidden (view full) --- 934system.membus.snoop_fanout::stdev 0 # Request fanout histogram 935system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 936system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram 937system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 938system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 939system.membus.snoop_fanout::min_value 0 # Request fanout histogram 940system.membus.snoop_fanout::max_value 0 # Request fanout histogram 941system.membus.snoop_fanout::total 128515 # Request fanout histogram |
| 931system.membus.reqLayer0.occupancy 587526000 # Layer occupancy (ticks) | 942system.membus.reqLayer0.occupancy 588253000 # Layer occupancy (ticks) |
| 932system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) | 943system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| 933system.membus.respLayer1.occupancy 677474000 # Layer occupancy (ticks) 934system.membus.respLayer1.utilization 1.2 # Layer utilization (%) | 944system.membus.respLayer1.occupancy 677385750 # Layer occupancy (ticks) 945system.membus.respLayer1.utilization 1.1 # Layer utilization (%) |
| 935 936---------- End Simulation Statistics ---------- | 946 947---------- End Simulation Statistics ---------- |