| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.058768 # Number of seconds simulated 4sim_ticks 58768125500 # Number of ticks simulated 5final_tick 58768125500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.058750 # Number of seconds simulated 4sim_ticks 58750410500 # Number of ticks simulated 5final_tick 58750410500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 140139 # Simulator instruction rate (inst/s) 8host_op_rate 179217 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 116134728 # Simulator tick rate (ticks/s) 10host_mem_usage 275656 # Number of bytes of host memory used 11host_seconds 506.03 # Real time elapsed on the host | 7host_inst_rate 179920 # Simulator instruction rate (inst/s) 8host_op_rate 230092 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 149057017 # Simulator tick rate (ticks/s) 10host_mem_usage 281832 # Number of bytes of host memory used 11host_seconds 394.15 # Real time elapsed on the host |
| 12sim_insts 70915150 # Number of instructions simulated 13sim_ops 90690106 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 70915150 # Number of instructions simulated 13sim_ops 90690106 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 285632 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8210304 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 285632 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 285632 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5517568 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5517568 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 4463 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 128286 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 86212 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 86212 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 4860322 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 134846431 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 139706753 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 4860322 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 4860322 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 93887085 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 93887085 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 93887085 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 4860322 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 134846431 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 233593838 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 128286 # Number of read requests accepted 41system.physmem.writeReqs 86212 # Number of write requests accepted 42system.physmem.readBursts 128286 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 86212 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 8209920 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue 46system.physmem.bytesWritten 5515840 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 8210304 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 5517568 # Total written bytes from the system interface side 49system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 286336 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7938624 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8224960 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 286336 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 286336 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5539328 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5539328 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 4474 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 124041 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 128515 # Number of read requests responded to by this memory 27system.physmem.num_writes::writebacks 86552 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 86552 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 4873770 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 135124571 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 139998341 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 4873770 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 4873770 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::writebacks 94285775 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 94285775 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::writebacks 94285775 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.inst 4873770 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::cpu.data 135124571 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.bw_total::total 234284116 # Total bandwidth to/from this memory (bytes/s) 40system.physmem.readReqs 128515 # Number of read requests accepted 41system.physmem.writeReqs 86552 # Number of write requests accepted 42system.physmem.readBursts 128515 # Number of DRAM read bursts, including those serviced by the write queue 43system.physmem.writeBursts 86552 # Number of DRAM write bursts, including those merged in the write queue 44system.physmem.bytesReadDRAM 8224512 # Total number of bytes read from DRAM 45system.physmem.bytesReadWrQ 448 # Total number of bytes read from write queue 46system.physmem.bytesWritten 5537600 # Total number of bytes written to DRAM 47system.physmem.bytesReadSys 8224960 # Total read bytes from the system interface side 48system.physmem.bytesWrittenSys 5539328 # Total written bytes from the system interface side 49system.physmem.servicedByWrQ 7 # Number of DRAM read bursts serviced by the write queue |
| 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 50system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 51system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 52system.physmem.perBankRdBursts::0 8065 # Per bank write bursts 53system.physmem.perBankRdBursts::1 8314 # Per bank write bursts 54system.physmem.perBankRdBursts::2 8239 # Per bank write bursts 55system.physmem.perBankRdBursts::3 8142 # Per bank write bursts 56system.physmem.perBankRdBursts::4 8284 # Per bank write bursts 57system.physmem.perBankRdBursts::5 8404 # Per bank write bursts 58system.physmem.perBankRdBursts::6 8054 # Per bank write bursts 59system.physmem.perBankRdBursts::7 7915 # Per bank write bursts 60system.physmem.perBankRdBursts::8 8035 # Per bank write bursts 61system.physmem.perBankRdBursts::9 7585 # Per bank write bursts 62system.physmem.perBankRdBursts::10 7763 # Per bank write bursts 63system.physmem.perBankRdBursts::11 7814 # Per bank write bursts 64system.physmem.perBankRdBursts::12 7871 # Per bank write bursts 65system.physmem.perBankRdBursts::13 7866 # Per bank write bursts 66system.physmem.perBankRdBursts::14 7967 # Per bank write bursts 67system.physmem.perBankRdBursts::15 7962 # Per bank write bursts 68system.physmem.perBankWrBursts::0 5395 # Per bank write bursts 69system.physmem.perBankWrBursts::1 5541 # Per bank write bursts 70system.physmem.perBankWrBursts::2 5468 # Per bank write bursts 71system.physmem.perBankWrBursts::3 5336 # Per bank write bursts 72system.physmem.perBankWrBursts::4 5363 # Per bank write bursts 73system.physmem.perBankWrBursts::5 5561 # Per bank write bursts 74system.physmem.perBankWrBursts::6 5259 # Per bank write bursts 75system.physmem.perBankWrBursts::7 5180 # Per bank write bursts 76system.physmem.perBankWrBursts::8 5154 # Per bank write bursts 77system.physmem.perBankWrBursts::9 5103 # Per bank write bursts 78system.physmem.perBankWrBursts::10 5293 # Per bank write bursts 79system.physmem.perBankWrBursts::11 5270 # Per bank write bursts 80system.physmem.perBankWrBursts::12 5531 # Per bank write bursts | 52system.physmem.perBankRdBursts::0 8086 # Per bank write bursts 53system.physmem.perBankRdBursts::1 8335 # Per bank write bursts 54system.physmem.perBankRdBursts::2 8257 # Per bank write bursts 55system.physmem.perBankRdBursts::3 8155 # Per bank write bursts 56system.physmem.perBankRdBursts::4 8301 # Per bank write bursts 57system.physmem.perBankRdBursts::5 8413 # Per bank write bursts 58system.physmem.perBankRdBursts::6 8070 # Per bank write bursts 59system.physmem.perBankRdBursts::7 7917 # Per bank write bursts 60system.physmem.perBankRdBursts::8 8053 # Per bank write bursts 61system.physmem.perBankRdBursts::9 7612 # Per bank write bursts 62system.physmem.perBankRdBursts::10 7771 # Per bank write bursts 63system.physmem.perBankRdBursts::11 7825 # Per bank write bursts 64system.physmem.perBankRdBursts::12 7888 # Per bank write bursts 65system.physmem.perBankRdBursts::13 7870 # Per bank write bursts 66system.physmem.perBankRdBursts::14 7981 # Per bank write bursts 67system.physmem.perBankRdBursts::15 7974 # Per bank write bursts 68system.physmem.perBankWrBursts::0 5399 # Per bank write bursts 69system.physmem.perBankWrBursts::1 5549 # Per bank write bursts 70system.physmem.perBankWrBursts::2 5476 # Per bank write bursts 71system.physmem.perBankWrBursts::3 5348 # Per bank write bursts 72system.physmem.perBankWrBursts::4 5387 # Per bank write bursts 73system.physmem.perBankWrBursts::5 5588 # Per bank write bursts 74system.physmem.perBankWrBursts::6 5325 # Per bank write bursts 75system.physmem.perBankWrBursts::7 5260 # Per bank write bursts 76system.physmem.perBankWrBursts::8 5187 # Per bank write bursts 77system.physmem.perBankWrBursts::9 5136 # Per bank write bursts 78system.physmem.perBankWrBursts::10 5306 # Per bank write bursts 79system.physmem.perBankWrBursts::11 5279 # Per bank write bursts 80system.physmem.perBankWrBursts::12 5541 # Per bank write bursts |
| 81system.physmem.perBankWrBursts::13 5597 # Per bank write bursts | 81system.physmem.perBankWrBursts::13 5597 # Per bank write bursts |
| 82system.physmem.perBankWrBursts::14 5703 # Per bank write bursts 83system.physmem.perBankWrBursts::15 5431 # Per bank write bursts | 82system.physmem.perBankWrBursts::14 5706 # Per bank write bursts 83system.physmem.perBankWrBursts::15 5441 # Per bank write bursts |
| 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 84system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 85system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 86system.physmem.totGap 58768094000 # Total gap between requests | 86system.physmem.totGap 58750379000 # Total gap between requests |
| 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) | 87system.physmem.readPktSize::0 0 # Read request sizes (log2) 88system.physmem.readPktSize::1 0 # Read request sizes (log2) 89system.physmem.readPktSize::2 0 # Read request sizes (log2) 90system.physmem.readPktSize::3 0 # Read request sizes (log2) 91system.physmem.readPktSize::4 0 # Read request sizes (log2) 92system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 93system.physmem.readPktSize::6 128286 # Read request sizes (log2) | 93system.physmem.readPktSize::6 128515 # Read request sizes (log2) |
| 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) | 94system.physmem.writePktSize::0 0 # Write request sizes (log2) 95system.physmem.writePktSize::1 0 # Write request sizes (log2) 96system.physmem.writePktSize::2 0 # Write request sizes (log2) 97system.physmem.writePktSize::3 0 # Write request sizes (log2) 98system.physmem.writePktSize::4 0 # Write request sizes (log2) 99system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| 100system.physmem.writePktSize::6 86212 # Write request sizes (log2) 101system.physmem.rdQLenPdf::0 116156 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 12104 # What read queue length does an incoming req see | 100system.physmem.writePktSize::6 86552 # Write request sizes (log2) 101system.physmem.rdQLenPdf::0 116239 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::1 12249 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see | 103system.physmem.rdQLenPdf::2 20 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see --- 29 unchanged lines hidden (view full) --- 140system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 148system.physmem.wrQLenPdf::15 628 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 4059 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 5180 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 5287 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 5319 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 5314 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 5316 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 5321 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 5334 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 5362 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 5346 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 5514 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 5445 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 5466 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 5870 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 5486 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 5303 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 9 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see | 148system.physmem.wrQLenPdf::15 470 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::16 477 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::17 4747 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::18 5340 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::19 5346 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::20 5349 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::21 5348 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::22 5355 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::23 5356 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::24 5371 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::25 5382 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::27 5490 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::28 5388 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::29 5469 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::30 5417 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::31 5499 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::32 5347 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::33 3 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see |
| 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 169system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see --- 12 unchanged lines hidden (view full) --- 189system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 196system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 197system.physmem.bytesPerActivate::samples 38803 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 353.665026 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 214.783131 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 335.990632 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 12260 31.60% 31.60% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 8290 21.36% 52.96% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 4146 10.68% 63.64% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 2807 7.23% 70.88% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 2540 6.55% 77.42% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 1701 4.38% 81.81% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 1262 3.25% 85.06% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 1176 3.03% 88.09% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 4621 11.91% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 38803 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 5298 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 24.212911 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::stdev 352.385643 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::0-1023 5295 99.94% 99.94% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes | 197system.physmem.bytesPerActivate::samples 32968 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::mean 417.384130 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::gmean 256.722785 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::stdev 362.908382 # Bytes accessed per row activation 201system.physmem.bytesPerActivate::0-127 8749 26.54% 26.54% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::128-255 6430 19.50% 46.04% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::256-383 3309 10.04% 56.08% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::384-511 2430 7.37% 63.45% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::512-639 2267 6.88% 70.33% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::640-767 1599 4.85% 75.18% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::768-895 1281 3.89% 79.06% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::896-1023 1267 3.84% 82.90% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::1024-1151 5636 17.10% 100.00% # Bytes accessed per row activation 210system.physmem.bytesPerActivate::total 32968 # Bytes accessed per row activation 211system.physmem.rdPerTurnAround::samples 5346 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::mean 24.036289 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::gmean 17.665302 # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::stdev 347.416280 # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::0-1023 5344 99.96% 99.96% # Reads before turning the bus around for writes |
| 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes | 216system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes |
| 218system.physmem.rdPerTurnAround::total 5298 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 5297 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.269398 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.253066 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.759205 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 4663 88.03% 88.03% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 7 0.13% 88.16% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 496 9.36% 97.53% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 106 2.00% 99.53% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 16 0.30% 99.83% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::21 8 0.15% 99.98% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::22 1 0.02% 100.00% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::total 5297 # Writes before turning the bus around for reads 231system.physmem.totQLat 1679255750 # Total ticks spent queuing 232system.physmem.totMemAccLat 4084505750 # Total ticks spent from burst creation until serviced by the DRAM 233system.physmem.totBusLat 641400000 # Total ticks spent in databus transfers 234system.physmem.avgQLat 13090.55 # Average queueing delay per DRAM burst | 218system.physmem.rdPerTurnAround::total 5346 # Reads before turning the bus around for writes 219system.physmem.wrPerTurnAround::samples 5346 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::mean 16.184998 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::gmean 16.174634 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::stdev 0.600598 # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::16 4870 91.10% 91.10% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::17 4 0.07% 91.17% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::18 438 8.19% 99.36% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::19 27 0.51% 99.87% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::20 7 0.13% 100.00% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::total 5346 # Writes before turning the bus around for reads 229system.physmem.totQLat 1552277750 # Total ticks spent queuing 230system.physmem.totMemAccLat 3961802750 # Total ticks spent from burst creation until serviced by the DRAM 231system.physmem.totBusLat 642540000 # Total ticks spent in databus transfers 232system.physmem.avgQLat 12079.23 # Average queueing delay per DRAM burst |
| 235system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 233system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 236system.physmem.avgMemAccLat 31840.55 # Average memory access latency per DRAM burst 237system.physmem.avgRdBW 139.70 # Average DRAM read bandwidth in MiByte/s 238system.physmem.avgWrBW 93.86 # Average achieved write bandwidth in MiByte/s 239system.physmem.avgRdBWSys 139.71 # Average system read bandwidth in MiByte/s 240system.physmem.avgWrBWSys 93.89 # Average system write bandwidth in MiByte/s | 234system.physmem.avgMemAccLat 30829.23 # Average memory access latency per DRAM burst 235system.physmem.avgRdBW 139.99 # Average DRAM read bandwidth in MiByte/s 236system.physmem.avgWrBW 94.26 # Average achieved write bandwidth in MiByte/s 237system.physmem.avgRdBWSys 140.00 # Average system read bandwidth in MiByte/s 238system.physmem.avgWrBWSys 94.29 # Average system write bandwidth in MiByte/s |
| 241system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 239system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 242system.physmem.busUtil 1.82 # Data bus utilization in percentage | 240system.physmem.busUtil 1.83 # Data bus utilization in percentage |
| 243system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads | 241system.physmem.busUtilRead 1.09 # Data bus utilization in percentage for reads |
| 244system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes | 242system.physmem.busUtilWrite 0.74 # Data bus utilization in percentage for writes |
| 245system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing | 243system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing |
| 246system.physmem.avgWrQLen 23.33 # Average write queue length when enqueuing 247system.physmem.readRowHits 111800 # Number of row buffer hits during reads 248system.physmem.writeRowHits 63851 # Number of row buffer hits during writes 249system.physmem.readRowHitRate 87.15 # Row buffer hit rate for reads 250system.physmem.writeRowHitRate 74.06 # Row buffer hit rate for writes 251system.physmem.avgGap 273979.68 # Average gap between requests 252system.physmem.pageHitRate 81.89 # Row buffer hit rate, read and write combined 253system.physmem_0.actEnergy 153014400 # Energy for activate commands per rank (pJ) 254system.physmem_0.preEnergy 83490000 # Energy for precharge commands per rank (pJ) 255system.physmem_0.readEnergy 509886000 # Energy for read commands per rank (pJ) 256system.physmem_0.writeEnergy 279190800 # Energy for write commands per rank (pJ) 257system.physmem_0.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) 258system.physmem_0.actBackEnergy 11659704255 # Energy for active background per rank (pJ) 259system.physmem_0.preBackEnergy 25030042500 # Energy for precharge background per rank (pJ) 260system.physmem_0.totalEnergy 41553430275 # Total energy per rank (pJ) 261system.physmem_0.averagePower 707.134890 # Core power per rank (mW) 262system.physmem_0.memoryStateTime::IDLE 41510709500 # Time in different power states 263system.physmem_0.memoryStateTime::REF 1962220000 # Time in different power states | 244system.physmem.avgWrQLen 23.56 # Average write queue length when enqueuing 245system.physmem.readRowHits 112029 # Number of row buffer hits during reads 246system.physmem.writeRowHits 70027 # Number of row buffer hits during writes 247system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads 248system.physmem.writeRowHitRate 80.91 # Row buffer hit rate for writes 249system.physmem.avgGap 273172.45 # Average gap between requests 250system.physmem.pageHitRate 84.65 # Row buffer hit rate, read and write combined 251system.physmem_0.actEnergy 130599000 # Energy for activate commands per rank (pJ) 252system.physmem_0.preEnergy 71259375 # Energy for precharge commands per rank (pJ) 253system.physmem_0.readEnergy 511009200 # Energy for read commands per rank (pJ) 254system.physmem_0.writeEnergy 280655280 # Energy for write commands per rank (pJ) 255system.physmem_0.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) 256system.physmem_0.actBackEnergy 11237331690 # Energy for active background per rank (pJ) 257system.physmem_0.preBackEnergy 25391203500 # Energy for precharge background per rank (pJ) 258system.physmem_0.totalEnergy 41459143245 # Total energy per rank (pJ) 259system.physmem_0.averagePower 705.717335 # Core power per rank (mW) 260system.physmem_0.memoryStateTime::IDLE 42124223000 # Time in different power states 261system.physmem_0.memoryStateTime::REF 1961700000 # Time in different power states |
| 264system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 262system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 265system.physmem_0.memoryStateTime::ACT 15290173000 # Time in different power states | 263system.physmem_0.memoryStateTime::ACT 14661610750 # Time in different power states |
| 266system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 264system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 267system.physmem_1.actEnergy 140215320 # Energy for activate commands per rank (pJ) 268system.physmem_1.preEnergy 76506375 # Energy for precharge commands per rank (pJ) 269system.physmem_1.readEnergy 490152000 # Energy for read commands per rank (pJ) 270system.physmem_1.writeEnergy 279145440 # Energy for write commands per rank (pJ) 271system.physmem_1.refreshEnergy 3838102320 # Energy for refresh commands per rank (pJ) 272system.physmem_1.actBackEnergy 11133864720 # Energy for active background per rank (pJ) 273system.physmem_1.preBackEnergy 25491305250 # Energy for precharge background per rank (pJ) 274system.physmem_1.totalEnergy 41449291425 # Total energy per rank (pJ) 275system.physmem_1.averagePower 705.362708 # Core power per rank (mW) 276system.physmem_1.memoryStateTime::IDLE 42280803500 # Time in different power states 277system.physmem_1.memoryStateTime::REF 1962220000 # Time in different power states | 265system.physmem_1.actEnergy 118555920 # Energy for activate commands per rank (pJ) 266system.physmem_1.preEnergy 64688250 # Energy for precharge commands per rank (pJ) 267system.physmem_1.readEnergy 491072400 # Energy for read commands per rank (pJ) 268system.physmem_1.writeEnergy 279819360 # Energy for write commands per rank (pJ) 269system.physmem_1.refreshEnergy 3837085200 # Energy for refresh commands per rank (pJ) 270system.physmem_1.actBackEnergy 10919729115 # Energy for active background per rank (pJ) 271system.physmem_1.preBackEnergy 25669800000 # Energy for precharge background per rank (pJ) 272system.physmem_1.totalEnergy 41380750245 # Total energy per rank (pJ) 273system.physmem_1.averagePower 704.382975 # Core power per rank (mW) 274system.physmem_1.memoryStateTime::IDLE 42589738750 # Time in different power states 275system.physmem_1.memoryStateTime::REF 1961700000 # Time in different power states |
| 278system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 276system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 279system.physmem_1.memoryStateTime::ACT 14520166000 # Time in different power states | 277system.physmem_1.memoryStateTime::ACT 14196261750 # Time in different power states |
| 280system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 278system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 281system.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states 282system.cpu.branchPred.lookups 14827521 # Number of BP lookups 283system.cpu.branchPred.condPredicted 9922528 # Number of conditional branches predicted 284system.cpu.branchPred.condIncorrect 342114 # Number of conditional branches incorrect 285system.cpu.branchPred.BTBLookups 9663077 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 6571727 # Number of BTB hits | 279system.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 280system.cpu.branchPred.lookups 14827613 # Number of BP lookups 281system.cpu.branchPred.condPredicted 9922572 # Number of conditional branches predicted 282system.cpu.branchPred.condIncorrect 342024 # Number of conditional branches incorrect 283system.cpu.branchPred.BTBLookups 9662819 # Number of BTB lookups 284system.cpu.branchPred.BTBHits 6571830 # Number of BTB hits |
| 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 285system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 288system.cpu.branchPred.BTBHitPct 68.008637 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 1719937 # Number of times the RAS was used to get a target. | 286system.cpu.branchPred.BTBHitPct 68.011519 # BTB Hit Percentage 287system.cpu.branchPred.usedRAS 1720035 # Number of times the RAS was used to get a target. |
| 290system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. | 288system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. |
| 291system.cpu.branchPred.indirectLookups 176106 # Number of indirect predictor lookups. 292system.cpu.branchPred.indirectHits 158425 # Number of indirect target hits. 293system.cpu.branchPred.indirectMisses 17681 # Number of indirect misses. 294system.cpu.branchPredindirectMispredicted 24889 # Number of mispredicted indirect branches. | 289system.cpu.branchPred.indirectLookups 175655 # Number of indirect predictor lookups. 290system.cpu.branchPred.indirectHits 158613 # Number of indirect target hits. 291system.cpu.branchPred.indirectMisses 17042 # Number of indirect misses. 292system.cpu.branchPredindirectMispredicted 24764 # Number of mispredicted indirect branches. |
| 295system.cpu_clk_domain.clock 500 # Clock period in ticks | 293system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 296system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states | 294system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states |
| 297system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 318system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 319system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 320system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 321system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 322system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 323system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 324system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 325system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 295system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 296system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 316system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 317system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 318system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 319system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 320system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 321system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 322system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 323system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 326system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states | 324system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states |
| 327system.cpu.dtb.walker.walks 0 # Table walker walks requested 328system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 348system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 349system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 350system.cpu.dtb.read_accesses 0 # DTB read accesses 351system.cpu.dtb.write_accesses 0 # DTB write accesses 352system.cpu.dtb.inst_accesses 0 # ITB inst accesses 353system.cpu.dtb.hits 0 # DTB hits 354system.cpu.dtb.misses 0 # DTB misses 355system.cpu.dtb.accesses 0 # DTB accesses | 325system.cpu.dtb.walker.walks 0 # Table walker walks requested 326system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.dtb.read_accesses 0 # DTB read accesses 349system.cpu.dtb.write_accesses 0 # DTB write accesses 350system.cpu.dtb.inst_accesses 0 # ITB inst accesses 351system.cpu.dtb.hits 0 # DTB hits 352system.cpu.dtb.misses 0 # DTB misses 353system.cpu.dtb.accesses 0 # DTB accesses |
| 356system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states | 354system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states |
| 357system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 378system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 379system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 380system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 381system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 382system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 383system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 384system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 385system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 355system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 376system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 377system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 378system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 379system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 380system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 381system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 382system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 383system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 386system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states | 384system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states |
| 387system.cpu.itb.walker.walks 0 # Table walker walks requested 388system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 409system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 410system.cpu.itb.read_accesses 0 # DTB read accesses 411system.cpu.itb.write_accesses 0 # DTB write accesses 412system.cpu.itb.inst_accesses 0 # ITB inst accesses 413system.cpu.itb.hits 0 # DTB hits 414system.cpu.itb.misses 0 # DTB misses 415system.cpu.itb.accesses 0 # DTB accesses 416system.cpu.workload.num_syscalls 1946 # Number of system calls | 385system.cpu.itb.walker.walks 0 # Table walker walks requested 386system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 407system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 408system.cpu.itb.read_accesses 0 # DTB read accesses 409system.cpu.itb.write_accesses 0 # DTB write accesses 410system.cpu.itb.inst_accesses 0 # ITB inst accesses 411system.cpu.itb.hits 0 # DTB hits 412system.cpu.itb.misses 0 # DTB misses 413system.cpu.itb.accesses 0 # DTB accesses 414system.cpu.workload.num_syscalls 1946 # Number of system calls |
| 417system.cpu.pwrStateResidencyTicks::ON 58768125500 # Cumulative time (in ticks) in various power states 418system.cpu.numCycles 117536251 # number of cpu cycles simulated | 415system.cpu.pwrStateResidencyTicks::ON 58750410500 # Cumulative time (in ticks) in various power states 416system.cpu.numCycles 117500821 # number of cpu cycles simulated |
| 419system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 420system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 421system.cpu.committedInsts 70915150 # Number of instructions committed 422system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed | 417system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 418system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 419system.cpu.committedInsts 70915150 # Number of instructions committed 420system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed |
| 423system.cpu.discardedOps 1179302 # Number of ops (including micro ops) which were discarded before commit | 421system.cpu.discardedOps 1179078 # Number of ops (including micro ops) which were discarded before commit |
| 424system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching | 422system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| 425system.cpu.cpi 1.657421 # CPI: cycles per instruction 426system.cpu.ipc 0.603347 # IPC: instructions per cycle | 423system.cpu.cpi 1.656921 # CPI: cycles per instruction 424system.cpu.ipc 0.603529 # IPC: instructions per cycle |
| 427system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 428system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction 429system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 430system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 431system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 432system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 433system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 434system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 454system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 455system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 456system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 457system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 458system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction 459system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 460system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 461system.cpu.op_class_0::total 90690106 # Class of committed instruction | 425system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 426system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction 427system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 428system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 429system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 430system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 431system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 432system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction --- 19 unchanged lines hidden (view full) --- 452system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 453system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 454system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 455system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 456system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction 457system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 458system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 459system.cpu.op_class_0::total 90690106 # Class of committed instruction |
| 462system.cpu.tickCycles 97988256 # Number of cycles that the object actually ticked 463system.cpu.idleCycles 19547995 # Total number of cycles that the object has spent stopped 464system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states 465system.cpu.dcache.tags.replacements 156444 # number of replacements 466system.cpu.dcache.tags.tagsinuse 4068.129500 # Cycle average of tags in use 467system.cpu.dcache.tags.total_refs 42637241 # Total number of references to valid blocks. 468system.cpu.dcache.tags.sampled_refs 160540 # Sample count of references to valid blocks. 469system.cpu.dcache.tags.avg_refs 265.586402 # Average number of references to valid blocks. 470system.cpu.dcache.tags.warmup_cycle 821026500 # Cycle when the warmup percentage was hit. 471system.cpu.dcache.tags.occ_blocks::cpu.data 4068.129500 # Average occupied blocks per requestor 472system.cpu.dcache.tags.occ_percent::cpu.data 0.993196 # Average percentage of cache occupancy 473system.cpu.dcache.tags.occ_percent::total 0.993196 # Average percentage of cache occupancy | 460system.cpu.tickCycles 97998947 # Number of cycles that the object actually ticked 461system.cpu.idleCycles 19501874 # Total number of cycles that the object has spent stopped 462system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 463system.cpu.dcache.tags.replacements 156451 # number of replacements 464system.cpu.dcache.tags.tagsinuse 4067.791520 # Cycle average of tags in use 465system.cpu.dcache.tags.total_refs 42637484 # Total number of references to valid blocks. 466system.cpu.dcache.tags.sampled_refs 160547 # Sample count of references to valid blocks. 467system.cpu.dcache.tags.avg_refs 265.576336 # Average number of references to valid blocks. 468system.cpu.dcache.tags.warmup_cycle 830343500 # Cycle when the warmup percentage was hit. 469system.cpu.dcache.tags.occ_blocks::cpu.data 4067.791520 # Average occupied blocks per requestor 470system.cpu.dcache.tags.occ_percent::cpu.data 0.993113 # Average percentage of cache occupancy 471system.cpu.dcache.tags.occ_percent::total 0.993113 # Average percentage of cache occupancy |
| 474system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 475system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id | 472system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 473system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id |
| 476system.cpu.dcache.tags.age_task_id_blocks_1024::1 1100 # Occupied blocks per task id 477system.cpu.dcache.tags.age_task_id_blocks_1024::2 2952 # Occupied blocks per task id | 474system.cpu.dcache.tags.age_task_id_blocks_1024::1 1054 # Occupied blocks per task id 475system.cpu.dcache.tags.age_task_id_blocks_1024::2 2998 # Occupied blocks per task id |
| 478system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id | 476system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| 479system.cpu.dcache.tags.tag_accesses 86035236 # Number of tag accesses 480system.cpu.dcache.tags.data_accesses 86035236 # Number of data accesses 481system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states 482system.cpu.dcache.ReadReq_hits::cpu.data 22879875 # number of ReadReq hits 483system.cpu.dcache.ReadReq_hits::total 22879875 # number of ReadReq hits 484system.cpu.dcache.WriteReq_hits::cpu.data 19642158 # number of WriteReq hits 485system.cpu.dcache.WriteReq_hits::total 19642158 # number of WriteReq hits 486system.cpu.dcache.SoftPFReq_hits::cpu.data 83370 # number of SoftPFReq hits 487system.cpu.dcache.SoftPFReq_hits::total 83370 # number of SoftPFReq hits | 477system.cpu.dcache.tags.tag_accesses 86035297 # Number of tag accesses 478system.cpu.dcache.tags.data_accesses 86035297 # Number of data accesses 479system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 480system.cpu.dcache.ReadReq_hits::cpu.data 22880319 # number of ReadReq hits 481system.cpu.dcache.ReadReq_hits::total 22880319 # number of ReadReq hits 482system.cpu.dcache.WriteReq_hits::cpu.data 19642152 # number of WriteReq hits 483system.cpu.dcache.WriteReq_hits::total 19642152 # number of WriteReq hits 484system.cpu.dcache.SoftPFReq_hits::cpu.data 83175 # number of SoftPFReq hits 485system.cpu.dcache.SoftPFReq_hits::total 83175 # number of SoftPFReq hits |
| 488system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 489system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 490system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 491system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits | 486system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 487system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 488system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 489system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits |
| 492system.cpu.dcache.demand_hits::cpu.data 42522033 # number of demand (read+write) hits 493system.cpu.dcache.demand_hits::total 42522033 # number of demand (read+write) hits 494system.cpu.dcache.overall_hits::cpu.data 42605403 # number of overall hits 495system.cpu.dcache.overall_hits::total 42605403 # number of overall hits 496system.cpu.dcache.ReadReq_misses::cpu.data 47768 # number of ReadReq misses 497system.cpu.dcache.ReadReq_misses::total 47768 # number of ReadReq misses 498system.cpu.dcache.WriteReq_misses::cpu.data 207743 # number of WriteReq misses 499system.cpu.dcache.WriteReq_misses::total 207743 # number of WriteReq misses 500system.cpu.dcache.SoftPFReq_misses::cpu.data 44596 # number of SoftPFReq misses 501system.cpu.dcache.SoftPFReq_misses::total 44596 # number of SoftPFReq misses 502system.cpu.dcache.demand_misses::cpu.data 255511 # number of demand (read+write) misses 503system.cpu.dcache.demand_misses::total 255511 # number of demand (read+write) misses 504system.cpu.dcache.overall_misses::cpu.data 300107 # number of overall misses 505system.cpu.dcache.overall_misses::total 300107 # number of overall misses 506system.cpu.dcache.ReadReq_miss_latency::cpu.data 1443300500 # number of ReadReq miss cycles 507system.cpu.dcache.ReadReq_miss_latency::total 1443300500 # number of ReadReq miss cycles 508system.cpu.dcache.WriteReq_miss_latency::cpu.data 16810663000 # number of WriteReq miss cycles 509system.cpu.dcache.WriteReq_miss_latency::total 16810663000 # number of WriteReq miss cycles 510system.cpu.dcache.demand_miss_latency::cpu.data 18253963500 # number of demand (read+write) miss cycles 511system.cpu.dcache.demand_miss_latency::total 18253963500 # number of demand (read+write) miss cycles 512system.cpu.dcache.overall_miss_latency::cpu.data 18253963500 # number of overall miss cycles 513system.cpu.dcache.overall_miss_latency::total 18253963500 # number of overall miss cycles 514system.cpu.dcache.ReadReq_accesses::cpu.data 22927643 # number of ReadReq accesses(hits+misses) 515system.cpu.dcache.ReadReq_accesses::total 22927643 # number of ReadReq accesses(hits+misses) | 490system.cpu.dcache.demand_hits::cpu.data 42522471 # number of demand (read+write) hits 491system.cpu.dcache.demand_hits::total 42522471 # number of demand (read+write) hits 492system.cpu.dcache.overall_hits::cpu.data 42605646 # number of overall hits 493system.cpu.dcache.overall_hits::total 42605646 # number of overall hits 494system.cpu.dcache.ReadReq_misses::cpu.data 47369 # number of ReadReq misses 495system.cpu.dcache.ReadReq_misses::total 47369 # number of ReadReq misses 496system.cpu.dcache.WriteReq_misses::cpu.data 207749 # number of WriteReq misses 497system.cpu.dcache.WriteReq_misses::total 207749 # number of WriteReq misses 498system.cpu.dcache.SoftPFReq_misses::cpu.data 44773 # number of SoftPFReq misses 499system.cpu.dcache.SoftPFReq_misses::total 44773 # number of SoftPFReq misses 500system.cpu.dcache.demand_misses::cpu.data 255118 # number of demand (read+write) misses 501system.cpu.dcache.demand_misses::total 255118 # number of demand (read+write) misses 502system.cpu.dcache.overall_misses::cpu.data 299891 # number of overall misses 503system.cpu.dcache.overall_misses::total 299891 # number of overall misses 504system.cpu.dcache.ReadReq_miss_latency::cpu.data 1548941500 # number of ReadReq miss cycles 505system.cpu.dcache.ReadReq_miss_latency::total 1548941500 # number of ReadReq miss cycles 506system.cpu.dcache.WriteReq_miss_latency::cpu.data 16628210000 # number of WriteReq miss cycles 507system.cpu.dcache.WriteReq_miss_latency::total 16628210000 # number of WriteReq miss cycles 508system.cpu.dcache.demand_miss_latency::cpu.data 18177151500 # number of demand (read+write) miss cycles 509system.cpu.dcache.demand_miss_latency::total 18177151500 # number of demand (read+write) miss cycles 510system.cpu.dcache.overall_miss_latency::cpu.data 18177151500 # number of overall miss cycles 511system.cpu.dcache.overall_miss_latency::total 18177151500 # number of overall miss cycles 512system.cpu.dcache.ReadReq_accesses::cpu.data 22927688 # number of ReadReq accesses(hits+misses) 513system.cpu.dcache.ReadReq_accesses::total 22927688 # number of ReadReq accesses(hits+misses) |
| 516system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 517system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) | 514system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 515system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) |
| 518system.cpu.dcache.SoftPFReq_accesses::cpu.data 127966 # number of SoftPFReq accesses(hits+misses) 519system.cpu.dcache.SoftPFReq_accesses::total 127966 # number of SoftPFReq accesses(hits+misses) | 516system.cpu.dcache.SoftPFReq_accesses::cpu.data 127948 # number of SoftPFReq accesses(hits+misses) 517system.cpu.dcache.SoftPFReq_accesses::total 127948 # number of SoftPFReq accesses(hits+misses) |
| 520system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 521system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 522system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 523system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) | 518system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 519system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 520system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 521system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) |
| 524system.cpu.dcache.demand_accesses::cpu.data 42777544 # number of demand (read+write) accesses 525system.cpu.dcache.demand_accesses::total 42777544 # number of demand (read+write) accesses 526system.cpu.dcache.overall_accesses::cpu.data 42905510 # number of overall (read+write) accesses 527system.cpu.dcache.overall_accesses::total 42905510 # number of overall (read+write) accesses 528system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002083 # miss rate for ReadReq accesses 529system.cpu.dcache.ReadReq_miss_rate::total 0.002083 # miss rate for ReadReq accesses | 522system.cpu.dcache.demand_accesses::cpu.data 42777589 # number of demand (read+write) accesses 523system.cpu.dcache.demand_accesses::total 42777589 # number of demand (read+write) accesses 524system.cpu.dcache.overall_accesses::cpu.data 42905537 # number of overall (read+write) accesses 525system.cpu.dcache.overall_accesses::total 42905537 # number of overall (read+write) accesses 526system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002066 # miss rate for ReadReq accesses 527system.cpu.dcache.ReadReq_miss_rate::total 0.002066 # miss rate for ReadReq accesses |
| 530system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses 531system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses | 528system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010466 # miss rate for WriteReq accesses 529system.cpu.dcache.WriteReq_miss_rate::total 0.010466 # miss rate for WriteReq accesses |
| 532system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348499 # miss rate for SoftPFReq accesses 533system.cpu.dcache.SoftPFReq_miss_rate::total 0.348499 # miss rate for SoftPFReq accesses 534system.cpu.dcache.demand_miss_rate::cpu.data 0.005973 # miss rate for demand accesses 535system.cpu.dcache.demand_miss_rate::total 0.005973 # miss rate for demand accesses 536system.cpu.dcache.overall_miss_rate::cpu.data 0.006995 # miss rate for overall accesses 537system.cpu.dcache.overall_miss_rate::total 0.006995 # miss rate for overall accesses 538system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30214.798610 # average ReadReq miss latency 539system.cpu.dcache.ReadReq_avg_miss_latency::total 30214.798610 # average ReadReq miss latency 540system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80920.478668 # average WriteReq miss latency 541system.cpu.dcache.WriteReq_avg_miss_latency::total 80920.478668 # average WriteReq miss latency 542system.cpu.dcache.demand_avg_miss_latency::cpu.data 71441.008411 # average overall miss latency 543system.cpu.dcache.demand_avg_miss_latency::total 71441.008411 # average overall miss latency 544system.cpu.dcache.overall_avg_miss_latency::cpu.data 60824.850803 # average overall miss latency 545system.cpu.dcache.overall_avg_miss_latency::total 60824.850803 # average overall miss latency | 530system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.349931 # miss rate for SoftPFReq accesses 531system.cpu.dcache.SoftPFReq_miss_rate::total 0.349931 # miss rate for SoftPFReq accesses 532system.cpu.dcache.demand_miss_rate::cpu.data 0.005964 # miss rate for demand accesses 533system.cpu.dcache.demand_miss_rate::total 0.005964 # miss rate for demand accesses 534system.cpu.dcache.overall_miss_rate::cpu.data 0.006990 # miss rate for overall accesses 535system.cpu.dcache.overall_miss_rate::total 0.006990 # miss rate for overall accesses 536system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32699.476451 # average ReadReq miss latency 537system.cpu.dcache.ReadReq_avg_miss_latency::total 32699.476451 # average ReadReq miss latency 538system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80039.903923 # average WriteReq miss latency 539system.cpu.dcache.WriteReq_avg_miss_latency::total 80039.903923 # average WriteReq miss latency 540system.cpu.dcache.demand_avg_miss_latency::cpu.data 71249.976481 # average overall miss latency 541system.cpu.dcache.demand_avg_miss_latency::total 71249.976481 # average overall miss latency 542system.cpu.dcache.overall_avg_miss_latency::cpu.data 60612.527552 # average overall miss latency 543system.cpu.dcache.overall_avg_miss_latency::total 60612.527552 # average overall miss latency |
| 546system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 547system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 548system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 549system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 550system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 551system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 544system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 545system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 546system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 547system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 548system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 549system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 552system.cpu.dcache.writebacks::writebacks 128383 # number of writebacks 553system.cpu.dcache.writebacks::total 128383 # number of writebacks 554system.cpu.dcache.ReadReq_mshr_hits::cpu.data 18246 # number of ReadReq MSHR hits 555system.cpu.dcache.ReadReq_mshr_hits::total 18246 # number of ReadReq MSHR hits 556system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100706 # number of WriteReq MSHR hits 557system.cpu.dcache.WriteReq_mshr_hits::total 100706 # number of WriteReq MSHR hits 558system.cpu.dcache.demand_mshr_hits::cpu.data 118952 # number of demand (read+write) MSHR hits 559system.cpu.dcache.demand_mshr_hits::total 118952 # number of demand (read+write) MSHR hits 560system.cpu.dcache.overall_mshr_hits::cpu.data 118952 # number of overall MSHR hits 561system.cpu.dcache.overall_mshr_hits::total 118952 # number of overall MSHR hits 562system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29522 # number of ReadReq MSHR misses 563system.cpu.dcache.ReadReq_mshr_misses::total 29522 # number of ReadReq MSHR misses | 550system.cpu.dcache.writebacks::writebacks 128145 # number of writebacks 551system.cpu.dcache.writebacks::total 128145 # number of writebacks 552system.cpu.dcache.ReadReq_mshr_hits::cpu.data 17840 # number of ReadReq MSHR hits 553system.cpu.dcache.ReadReq_mshr_hits::total 17840 # number of ReadReq MSHR hits 554system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100712 # number of WriteReq MSHR hits 555system.cpu.dcache.WriteReq_mshr_hits::total 100712 # number of WriteReq MSHR hits 556system.cpu.dcache.demand_mshr_hits::cpu.data 118552 # number of demand (read+write) MSHR hits 557system.cpu.dcache.demand_mshr_hits::total 118552 # number of demand (read+write) MSHR hits 558system.cpu.dcache.overall_mshr_hits::cpu.data 118552 # number of overall MSHR hits 559system.cpu.dcache.overall_mshr_hits::total 118552 # number of overall MSHR hits 560system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29529 # number of ReadReq MSHR misses 561system.cpu.dcache.ReadReq_mshr_misses::total 29529 # number of ReadReq MSHR misses |
| 564system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses 565system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses 566system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses 567system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses | 562system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107037 # number of WriteReq MSHR misses 563system.cpu.dcache.WriteReq_mshr_misses::total 107037 # number of WriteReq MSHR misses 564system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23981 # number of SoftPFReq MSHR misses 565system.cpu.dcache.SoftPFReq_mshr_misses::total 23981 # number of SoftPFReq MSHR misses |
| 568system.cpu.dcache.demand_mshr_misses::cpu.data 136559 # number of demand (read+write) MSHR misses 569system.cpu.dcache.demand_mshr_misses::total 136559 # number of demand (read+write) MSHR misses 570system.cpu.dcache.overall_mshr_misses::cpu.data 160540 # number of overall MSHR misses 571system.cpu.dcache.overall_mshr_misses::total 160540 # number of overall MSHR misses 572system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 576668000 # number of ReadReq MSHR miss cycles 573system.cpu.dcache.ReadReq_mshr_miss_latency::total 576668000 # number of ReadReq MSHR miss cycles 574system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8488003000 # number of WriteReq MSHR miss cycles 575system.cpu.dcache.WriteReq_mshr_miss_latency::total 8488003000 # number of WriteReq MSHR miss cycles 576system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1709526500 # number of SoftPFReq MSHR miss cycles 577system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1709526500 # number of SoftPFReq MSHR miss cycles 578system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9064671000 # number of demand (read+write) MSHR miss cycles 579system.cpu.dcache.demand_mshr_miss_latency::total 9064671000 # number of demand (read+write) MSHR miss cycles 580system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10774197500 # number of overall MSHR miss cycles 581system.cpu.dcache.overall_mshr_miss_latency::total 10774197500 # number of overall MSHR miss cycles | 566system.cpu.dcache.demand_mshr_misses::cpu.data 136566 # number of demand (read+write) MSHR misses 567system.cpu.dcache.demand_mshr_misses::total 136566 # number of demand (read+write) MSHR misses 568system.cpu.dcache.overall_mshr_misses::cpu.data 160547 # number of overall MSHR misses 569system.cpu.dcache.overall_mshr_misses::total 160547 # number of overall MSHR misses 570system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 586674000 # number of ReadReq MSHR miss cycles 571system.cpu.dcache.ReadReq_mshr_miss_latency::total 586674000 # number of ReadReq MSHR miss cycles 572system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8401236500 # number of WriteReq MSHR miss cycles 573system.cpu.dcache.WriteReq_mshr_miss_latency::total 8401236500 # number of WriteReq MSHR miss cycles 574system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1788829000 # number of SoftPFReq MSHR miss cycles 575system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1788829000 # number of SoftPFReq MSHR miss cycles 576system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8987910500 # number of demand (read+write) MSHR miss cycles 577system.cpu.dcache.demand_mshr_miss_latency::total 8987910500 # number of demand (read+write) MSHR miss cycles 578system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10776739500 # number of overall MSHR miss cycles 579system.cpu.dcache.overall_mshr_miss_latency::total 10776739500 # number of overall MSHR miss cycles |
| 582system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses 583system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses 584system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 585system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses | 580system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses 581system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses 582system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 583system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses |
| 586system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187401 # mshr miss rate for SoftPFReq accesses 587system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187401 # mshr miss rate for SoftPFReq accesses | 584system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187428 # mshr miss rate for SoftPFReq accesses 585system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187428 # mshr miss rate for SoftPFReq accesses |
| 588system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses 589system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses 590system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 591system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses | 586system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses 587system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses 588system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses 589system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses |
| 592system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19533.500440 # average ReadReq mshr miss latency 593system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19533.500440 # average ReadReq mshr miss latency 594system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79299.709446 # average WriteReq mshr miss latency 595system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79299.709446 # average WriteReq mshr miss latency 596system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71286.706142 # average SoftPFReq mshr miss latency 597system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71286.706142 # average SoftPFReq mshr miss latency 598system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66379.154798 # average overall mshr miss latency 599system.cpu.dcache.demand_avg_mshr_miss_latency::total 66379.154798 # average overall mshr miss latency 600system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67112.230597 # average overall mshr miss latency 601system.cpu.dcache.overall_avg_mshr_miss_latency::total 67112.230597 # average overall mshr miss latency 602system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states 603system.cpu.icache.tags.replacements 43538 # number of replacements 604system.cpu.icache.tags.tagsinuse 1854.967198 # Cycle average of tags in use 605system.cpu.icache.tags.total_refs 25047260 # Total number of references to valid blocks. 606system.cpu.icache.tags.sampled_refs 45580 # Sample count of references to valid blocks. 607system.cpu.icache.tags.avg_refs 549.523036 # Average number of references to valid blocks. | 590system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19867.723255 # average ReadReq mshr miss latency 591system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19867.723255 # average ReadReq mshr miss latency 592system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78489.087885 # average WriteReq mshr miss latency 593system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78489.087885 # average WriteReq mshr miss latency 594system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 74593.594929 # average SoftPFReq mshr miss latency 595system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 74593.594929 # average SoftPFReq mshr miss latency 596system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65813.676171 # average overall mshr miss latency 597system.cpu.dcache.demand_avg_mshr_miss_latency::total 65813.676171 # average overall mshr miss latency 598system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67125.137810 # average overall mshr miss latency 599system.cpu.dcache.overall_avg_mshr_miss_latency::total 67125.137810 # average overall mshr miss latency 600system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 601system.cpu.icache.tags.replacements 43545 # number of replacements 602system.cpu.icache.tags.tagsinuse 1854.190293 # Cycle average of tags in use 603system.cpu.icache.tags.total_refs 25047618 # Total number of references to valid blocks. 604system.cpu.icache.tags.sampled_refs 45587 # Sample count of references to valid blocks. 605system.cpu.icache.tags.avg_refs 549.446509 # Average number of references to valid blocks. |
| 608system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 606system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 609system.cpu.icache.tags.occ_blocks::cpu.inst 1854.967198 # Average occupied blocks per requestor 610system.cpu.icache.tags.occ_percent::cpu.inst 0.905746 # Average percentage of cache occupancy 611system.cpu.icache.tags.occ_percent::total 0.905746 # Average percentage of cache occupancy | 607system.cpu.icache.tags.occ_blocks::cpu.inst 1854.190293 # Average occupied blocks per requestor 608system.cpu.icache.tags.occ_percent::cpu.inst 0.905366 # Average percentage of cache occupancy 609system.cpu.icache.tags.occ_percent::total 0.905366 # Average percentage of cache occupancy |
| 612system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id | 610system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id |
| 613system.cpu.icache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id 614system.cpu.icache.tags.age_task_id_blocks_1024::1 45 # Occupied blocks per task id | 611system.cpu.icache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::1 50 # Occupied blocks per task id |
| 615system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id | 613system.cpu.icache.tags.age_task_id_blocks_1024::2 1 # Occupied blocks per task id |
| 616system.cpu.icache.tags.age_task_id_blocks_1024::3 907 # Occupied blocks per task id 617system.cpu.icache.tags.age_task_id_blocks_1024::4 1012 # Occupied blocks per task id | 614system.cpu.icache.tags.age_task_id_blocks_1024::3 913 # Occupied blocks per task id 615system.cpu.icache.tags.age_task_id_blocks_1024::4 1006 # Occupied blocks per task id |
| 618system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id | 616system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id |
| 619system.cpu.icache.tags.tag_accesses 50231262 # Number of tag accesses 620system.cpu.icache.tags.data_accesses 50231262 # Number of data accesses 621system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states 622system.cpu.icache.ReadReq_hits::cpu.inst 25047260 # number of ReadReq hits 623system.cpu.icache.ReadReq_hits::total 25047260 # number of ReadReq hits 624system.cpu.icache.demand_hits::cpu.inst 25047260 # number of demand (read+write) hits 625system.cpu.icache.demand_hits::total 25047260 # number of demand (read+write) hits 626system.cpu.icache.overall_hits::cpu.inst 25047260 # number of overall hits 627system.cpu.icache.overall_hits::total 25047260 # number of overall hits 628system.cpu.icache.ReadReq_misses::cpu.inst 45581 # number of ReadReq misses 629system.cpu.icache.ReadReq_misses::total 45581 # number of ReadReq misses 630system.cpu.icache.demand_misses::cpu.inst 45581 # number of demand (read+write) misses 631system.cpu.icache.demand_misses::total 45581 # number of demand (read+write) misses 632system.cpu.icache.overall_misses::cpu.inst 45581 # number of overall misses 633system.cpu.icache.overall_misses::total 45581 # number of overall misses 634system.cpu.icache.ReadReq_miss_latency::cpu.inst 906370500 # number of ReadReq miss cycles 635system.cpu.icache.ReadReq_miss_latency::total 906370500 # number of ReadReq miss cycles 636system.cpu.icache.demand_miss_latency::cpu.inst 906370500 # number of demand (read+write) miss cycles 637system.cpu.icache.demand_miss_latency::total 906370500 # number of demand (read+write) miss cycles 638system.cpu.icache.overall_miss_latency::cpu.inst 906370500 # number of overall miss cycles 639system.cpu.icache.overall_miss_latency::total 906370500 # number of overall miss cycles 640system.cpu.icache.ReadReq_accesses::cpu.inst 25092841 # number of ReadReq accesses(hits+misses) 641system.cpu.icache.ReadReq_accesses::total 25092841 # number of ReadReq accesses(hits+misses) 642system.cpu.icache.demand_accesses::cpu.inst 25092841 # number of demand (read+write) accesses 643system.cpu.icache.demand_accesses::total 25092841 # number of demand (read+write) accesses 644system.cpu.icache.overall_accesses::cpu.inst 25092841 # number of overall (read+write) accesses 645system.cpu.icache.overall_accesses::total 25092841 # number of overall (read+write) accesses 646system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001816 # miss rate for ReadReq accesses 647system.cpu.icache.ReadReq_miss_rate::total 0.001816 # miss rate for ReadReq accesses 648system.cpu.icache.demand_miss_rate::cpu.inst 0.001816 # miss rate for demand accesses 649system.cpu.icache.demand_miss_rate::total 0.001816 # miss rate for demand accesses 650system.cpu.icache.overall_miss_rate::cpu.inst 0.001816 # miss rate for overall accesses 651system.cpu.icache.overall_miss_rate::total 0.001816 # miss rate for overall accesses 652system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19884.831399 # average ReadReq miss latency 653system.cpu.icache.ReadReq_avg_miss_latency::total 19884.831399 # average ReadReq miss latency 654system.cpu.icache.demand_avg_miss_latency::cpu.inst 19884.831399 # average overall miss latency 655system.cpu.icache.demand_avg_miss_latency::total 19884.831399 # average overall miss latency 656system.cpu.icache.overall_avg_miss_latency::cpu.inst 19884.831399 # average overall miss latency 657system.cpu.icache.overall_avg_miss_latency::total 19884.831399 # average overall miss latency | 617system.cpu.icache.tags.tag_accesses 50231999 # Number of tag accesses 618system.cpu.icache.tags.data_accesses 50231999 # Number of data accesses 619system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 620system.cpu.icache.ReadReq_hits::cpu.inst 25047618 # number of ReadReq hits 621system.cpu.icache.ReadReq_hits::total 25047618 # number of ReadReq hits 622system.cpu.icache.demand_hits::cpu.inst 25047618 # number of demand (read+write) hits 623system.cpu.icache.demand_hits::total 25047618 # number of demand (read+write) hits 624system.cpu.icache.overall_hits::cpu.inst 25047618 # number of overall hits 625system.cpu.icache.overall_hits::total 25047618 # number of overall hits 626system.cpu.icache.ReadReq_misses::cpu.inst 45588 # number of ReadReq misses 627system.cpu.icache.ReadReq_misses::total 45588 # number of ReadReq misses 628system.cpu.icache.demand_misses::cpu.inst 45588 # number of demand (read+write) misses 629system.cpu.icache.demand_misses::total 45588 # number of demand (read+write) misses 630system.cpu.icache.overall_misses::cpu.inst 45588 # number of overall misses 631system.cpu.icache.overall_misses::total 45588 # number of overall misses 632system.cpu.icache.ReadReq_miss_latency::cpu.inst 918433000 # number of ReadReq miss cycles 633system.cpu.icache.ReadReq_miss_latency::total 918433000 # number of ReadReq miss cycles 634system.cpu.icache.demand_miss_latency::cpu.inst 918433000 # number of demand (read+write) miss cycles 635system.cpu.icache.demand_miss_latency::total 918433000 # number of demand (read+write) miss cycles 636system.cpu.icache.overall_miss_latency::cpu.inst 918433000 # number of overall miss cycles 637system.cpu.icache.overall_miss_latency::total 918433000 # number of overall miss cycles 638system.cpu.icache.ReadReq_accesses::cpu.inst 25093206 # number of ReadReq accesses(hits+misses) 639system.cpu.icache.ReadReq_accesses::total 25093206 # number of ReadReq accesses(hits+misses) 640system.cpu.icache.demand_accesses::cpu.inst 25093206 # number of demand (read+write) accesses 641system.cpu.icache.demand_accesses::total 25093206 # number of demand (read+write) accesses 642system.cpu.icache.overall_accesses::cpu.inst 25093206 # number of overall (read+write) accesses 643system.cpu.icache.overall_accesses::total 25093206 # number of overall (read+write) accesses 644system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001817 # miss rate for ReadReq accesses 645system.cpu.icache.ReadReq_miss_rate::total 0.001817 # miss rate for ReadReq accesses 646system.cpu.icache.demand_miss_rate::cpu.inst 0.001817 # miss rate for demand accesses 647system.cpu.icache.demand_miss_rate::total 0.001817 # miss rate for demand accesses 648system.cpu.icache.overall_miss_rate::cpu.inst 0.001817 # miss rate for overall accesses 649system.cpu.icache.overall_miss_rate::total 0.001817 # miss rate for overall accesses 650system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20146.376239 # average ReadReq miss latency 651system.cpu.icache.ReadReq_avg_miss_latency::total 20146.376239 # average ReadReq miss latency 652system.cpu.icache.demand_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency 653system.cpu.icache.demand_avg_miss_latency::total 20146.376239 # average overall miss latency 654system.cpu.icache.overall_avg_miss_latency::cpu.inst 20146.376239 # average overall miss latency 655system.cpu.icache.overall_avg_miss_latency::total 20146.376239 # average overall miss latency |
| 658system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 659system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 660system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 661system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 662system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 663system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 656system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 657system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 658system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 659system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 660system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 661system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 664system.cpu.icache.writebacks::writebacks 43538 # number of writebacks 665system.cpu.icache.writebacks::total 43538 # number of writebacks 666system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45581 # number of ReadReq MSHR misses 667system.cpu.icache.ReadReq_mshr_misses::total 45581 # number of ReadReq MSHR misses 668system.cpu.icache.demand_mshr_misses::cpu.inst 45581 # number of demand (read+write) MSHR misses 669system.cpu.icache.demand_mshr_misses::total 45581 # number of demand (read+write) MSHR misses 670system.cpu.icache.overall_mshr_misses::cpu.inst 45581 # number of overall MSHR misses 671system.cpu.icache.overall_mshr_misses::total 45581 # number of overall MSHR misses 672system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 860790500 # number of ReadReq MSHR miss cycles 673system.cpu.icache.ReadReq_mshr_miss_latency::total 860790500 # number of ReadReq MSHR miss cycles 674system.cpu.icache.demand_mshr_miss_latency::cpu.inst 860790500 # number of demand (read+write) MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::total 860790500 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.overall_mshr_miss_latency::cpu.inst 860790500 # number of overall MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::total 860790500 # number of overall MSHR miss cycles 678system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001816 # mshr miss rate for ReadReq accesses 679system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001816 # mshr miss rate for ReadReq accesses 680system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001816 # mshr miss rate for demand accesses 681system.cpu.icache.demand_mshr_miss_rate::total 0.001816 # mshr miss rate for demand accesses 682system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001816 # mshr miss rate for overall accesses 683system.cpu.icache.overall_mshr_miss_rate::total 0.001816 # mshr miss rate for overall accesses 684system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18884.853338 # average ReadReq mshr miss latency 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18884.853338 # average ReadReq mshr miss latency 686system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18884.853338 # average overall mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::total 18884.853338 # average overall mshr miss latency 688system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18884.853338 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::total 18884.853338 # average overall mshr miss latency 690system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states 691system.cpu.l2cache.tags.replacements 96393 # number of replacements 692system.cpu.l2cache.tags.tagsinuse 29915.680999 # Cycle average of tags in use 693system.cpu.l2cache.tags.total_refs 163475 # Total number of references to valid blocks. 694system.cpu.l2cache.tags.sampled_refs 127546 # Sample count of references to valid blocks. 695system.cpu.l2cache.tags.avg_refs 1.281694 # Average number of references to valid blocks. 696system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 697system.cpu.l2cache.tags.occ_blocks::writebacks 26835.960013 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_blocks::cpu.inst 1436.225853 # Average occupied blocks per requestor 699system.cpu.l2cache.tags.occ_blocks::cpu.data 1643.495133 # Average occupied blocks per requestor 700system.cpu.l2cache.tags.occ_percent::writebacks 0.818969 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043830 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_percent::cpu.data 0.050155 # Average percentage of cache occupancy 703system.cpu.l2cache.tags.occ_percent::total 0.912954 # Average percentage of cache occupancy 704system.cpu.l2cache.tags.occ_task_id_blocks::1024 31153 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12744 # Occupied blocks per task id 708system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15761 # Occupied blocks per task id 709system.cpu.l2cache.tags.age_task_id_blocks_1024::4 596 # Occupied blocks per task id 710system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950714 # Percentage of cache occupancy per task id 711system.cpu.l2cache.tags.tag_accesses 3420655 # Number of tag accesses 712system.cpu.l2cache.tags.data_accesses 3420655 # Number of data accesses 713system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states 714system.cpu.l2cache.WritebackDirty_hits::writebacks 128383 # number of WritebackDirty hits 715system.cpu.l2cache.WritebackDirty_hits::total 128383 # number of WritebackDirty hits 716system.cpu.l2cache.WritebackClean_hits::writebacks 39935 # number of WritebackClean hits 717system.cpu.l2cache.WritebackClean_hits::total 39935 # number of WritebackClean hits 718system.cpu.l2cache.ReadExReq_hits::cpu.data 4757 # number of ReadExReq hits 719system.cpu.l2cache.ReadExReq_hits::total 4757 # number of ReadExReq hits 720system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41105 # number of ReadCleanReq hits 721system.cpu.l2cache.ReadCleanReq_hits::total 41105 # number of ReadCleanReq hits 722system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31900 # number of ReadSharedReq hits 723system.cpu.l2cache.ReadSharedReq_hits::total 31900 # number of ReadSharedReq hits 724system.cpu.l2cache.demand_hits::cpu.inst 41105 # number of demand (read+write) hits 725system.cpu.l2cache.demand_hits::cpu.data 36657 # number of demand (read+write) hits 726system.cpu.l2cache.demand_hits::total 77762 # number of demand (read+write) hits 727system.cpu.l2cache.overall_hits::cpu.inst 41105 # number of overall hits 728system.cpu.l2cache.overall_hits::cpu.data 36657 # number of overall hits 729system.cpu.l2cache.overall_hits::total 77762 # number of overall hits 730system.cpu.l2cache.ReadExReq_misses::cpu.data 102280 # number of ReadExReq misses 731system.cpu.l2cache.ReadExReq_misses::total 102280 # number of ReadExReq misses 732system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4476 # number of ReadCleanReq misses 733system.cpu.l2cache.ReadCleanReq_misses::total 4476 # number of ReadCleanReq misses 734system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21603 # number of ReadSharedReq misses 735system.cpu.l2cache.ReadSharedReq_misses::total 21603 # number of ReadSharedReq misses 736system.cpu.l2cache.demand_misses::cpu.inst 4476 # number of demand (read+write) misses 737system.cpu.l2cache.demand_misses::cpu.data 123883 # number of demand (read+write) misses 738system.cpu.l2cache.demand_misses::total 128359 # number of demand (read+write) misses 739system.cpu.l2cache.overall_misses::cpu.inst 4476 # number of overall misses 740system.cpu.l2cache.overall_misses::cpu.data 123883 # number of overall misses 741system.cpu.l2cache.overall_misses::total 128359 # number of overall misses 742system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8277452000 # number of ReadExReq miss cycles 743system.cpu.l2cache.ReadExReq_miss_latency::total 8277452000 # number of ReadExReq miss cycles 744system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356943000 # number of ReadCleanReq miss cycles 745system.cpu.l2cache.ReadCleanReq_miss_latency::total 356943000 # number of ReadCleanReq miss cycles 746system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1866770000 # number of ReadSharedReq miss cycles 747system.cpu.l2cache.ReadSharedReq_miss_latency::total 1866770000 # number of ReadSharedReq miss cycles 748system.cpu.l2cache.demand_miss_latency::cpu.inst 356943000 # number of demand (read+write) miss cycles 749system.cpu.l2cache.demand_miss_latency::cpu.data 10144222000 # number of demand (read+write) miss cycles 750system.cpu.l2cache.demand_miss_latency::total 10501165000 # number of demand (read+write) miss cycles 751system.cpu.l2cache.overall_miss_latency::cpu.inst 356943000 # number of overall miss cycles 752system.cpu.l2cache.overall_miss_latency::cpu.data 10144222000 # number of overall miss cycles 753system.cpu.l2cache.overall_miss_latency::total 10501165000 # number of overall miss cycles 754system.cpu.l2cache.WritebackDirty_accesses::writebacks 128383 # number of WritebackDirty accesses(hits+misses) 755system.cpu.l2cache.WritebackDirty_accesses::total 128383 # number of WritebackDirty accesses(hits+misses) 756system.cpu.l2cache.WritebackClean_accesses::writebacks 39935 # number of WritebackClean accesses(hits+misses) 757system.cpu.l2cache.WritebackClean_accesses::total 39935 # number of WritebackClean accesses(hits+misses) | 662system.cpu.icache.writebacks::writebacks 43545 # number of writebacks 663system.cpu.icache.writebacks::total 43545 # number of writebacks 664system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45588 # number of ReadReq MSHR misses 665system.cpu.icache.ReadReq_mshr_misses::total 45588 # number of ReadReq MSHR misses 666system.cpu.icache.demand_mshr_misses::cpu.inst 45588 # number of demand (read+write) MSHR misses 667system.cpu.icache.demand_mshr_misses::total 45588 # number of demand (read+write) MSHR misses 668system.cpu.icache.overall_mshr_misses::cpu.inst 45588 # number of overall MSHR misses 669system.cpu.icache.overall_mshr_misses::total 45588 # number of overall MSHR misses 670system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 872846000 # number of ReadReq MSHR miss cycles 671system.cpu.icache.ReadReq_mshr_miss_latency::total 872846000 # number of ReadReq MSHR miss cycles 672system.cpu.icache.demand_mshr_miss_latency::cpu.inst 872846000 # number of demand (read+write) MSHR miss cycles 673system.cpu.icache.demand_mshr_miss_latency::total 872846000 # number of demand (read+write) MSHR miss cycles 674system.cpu.icache.overall_mshr_miss_latency::cpu.inst 872846000 # number of overall MSHR miss cycles 675system.cpu.icache.overall_mshr_miss_latency::total 872846000 # number of overall MSHR miss cycles 676system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for ReadReq accesses 677system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001817 # mshr miss rate for ReadReq accesses 678system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for demand accesses 679system.cpu.icache.demand_mshr_miss_rate::total 0.001817 # mshr miss rate for demand accesses 680system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001817 # mshr miss rate for overall accesses 681system.cpu.icache.overall_mshr_miss_rate::total 0.001817 # mshr miss rate for overall accesses 682system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19146.398175 # average ReadReq mshr miss latency 683system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19146.398175 # average ReadReq mshr miss latency 684system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency 685system.cpu.icache.demand_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency 686system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19146.398175 # average overall mshr miss latency 687system.cpu.icache.overall_avg_mshr_miss_latency::total 19146.398175 # average overall mshr miss latency 688system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 689system.cpu.l2cache.tags.replacements 97176 # number of replacements 690system.cpu.l2cache.tags.tagsinuse 31328.460689 # Cycle average of tags in use 691system.cpu.l2cache.tags.total_refs 268173 # Total number of references to valid blocks. 692system.cpu.l2cache.tags.sampled_refs 129944 # Sample count of references to valid blocks. 693system.cpu.l2cache.tags.avg_refs 2.063758 # Average number of references to valid blocks. 694system.cpu.l2cache.tags.warmup_cycle 10596662000 # Cycle when the warmup percentage was hit. 695system.cpu.l2cache.tags.occ_blocks::writebacks 480.299456 # Average occupied blocks per requestor 696system.cpu.l2cache.tags.occ_blocks::cpu.inst 1381.968758 # Average occupied blocks per requestor 697system.cpu.l2cache.tags.occ_blocks::cpu.data 29466.192474 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_percent::writebacks 0.014658 # Average percentage of cache occupancy 699system.cpu.l2cache.tags.occ_percent::cpu.inst 0.042174 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_percent::cpu.data 0.899237 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::total 0.956069 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 179 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1189 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::2 13615 # Occupied blocks per task id 706system.cpu.l2cache.tags.age_task_id_blocks_1024::3 17003 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::4 782 # Occupied blocks per task id 708system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 709system.cpu.l2cache.tags.tag_accesses 3316240 # Number of tag accesses 710system.cpu.l2cache.tags.data_accesses 3316240 # Number of data accesses 711system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 712system.cpu.l2cache.WritebackDirty_hits::writebacks 128145 # number of WritebackDirty hits 713system.cpu.l2cache.WritebackDirty_hits::total 128145 # number of WritebackDirty hits 714system.cpu.l2cache.WritebackClean_hits::writebacks 39944 # number of WritebackClean hits 715system.cpu.l2cache.WritebackClean_hits::total 39944 # number of WritebackClean hits 716system.cpu.l2cache.ReadExReq_hits::cpu.data 4720 # number of ReadExReq hits 717system.cpu.l2cache.ReadExReq_hits::total 4720 # number of ReadExReq hits 718system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41100 # number of ReadCleanReq hits 719system.cpu.l2cache.ReadCleanReq_hits::total 41100 # number of ReadCleanReq hits 720system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31726 # number of ReadSharedReq hits 721system.cpu.l2cache.ReadSharedReq_hits::total 31726 # number of ReadSharedReq hits 722system.cpu.l2cache.demand_hits::cpu.inst 41100 # number of demand (read+write) hits 723system.cpu.l2cache.demand_hits::cpu.data 36446 # number of demand (read+write) hits 724system.cpu.l2cache.demand_hits::total 77546 # number of demand (read+write) hits 725system.cpu.l2cache.overall_hits::cpu.inst 41100 # number of overall hits 726system.cpu.l2cache.overall_hits::cpu.data 36446 # number of overall hits 727system.cpu.l2cache.overall_hits::total 77546 # number of overall hits 728system.cpu.l2cache.ReadExReq_misses::cpu.data 102317 # number of ReadExReq misses 729system.cpu.l2cache.ReadExReq_misses::total 102317 # number of ReadExReq misses 730system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4488 # number of ReadCleanReq misses 731system.cpu.l2cache.ReadCleanReq_misses::total 4488 # number of ReadCleanReq misses 732system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21784 # number of ReadSharedReq misses 733system.cpu.l2cache.ReadSharedReq_misses::total 21784 # number of ReadSharedReq misses 734system.cpu.l2cache.demand_misses::cpu.inst 4488 # number of demand (read+write) misses 735system.cpu.l2cache.demand_misses::cpu.data 124101 # number of demand (read+write) misses 736system.cpu.l2cache.demand_misses::total 128589 # number of demand (read+write) misses 737system.cpu.l2cache.overall_misses::cpu.inst 4488 # number of overall misses 738system.cpu.l2cache.overall_misses::cpu.data 124101 # number of overall misses 739system.cpu.l2cache.overall_misses::total 128589 # number of overall misses 740system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8191072500 # number of ReadExReq miss cycles 741system.cpu.l2cache.ReadExReq_miss_latency::total 8191072500 # number of ReadExReq miss cycles 742system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 369038000 # number of ReadCleanReq miss cycles 743system.cpu.l2cache.ReadCleanReq_miss_latency::total 369038000 # number of ReadCleanReq miss cycles 744system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1957896000 # number of ReadSharedReq miss cycles 745system.cpu.l2cache.ReadSharedReq_miss_latency::total 1957896000 # number of ReadSharedReq miss cycles 746system.cpu.l2cache.demand_miss_latency::cpu.inst 369038000 # number of demand (read+write) miss cycles 747system.cpu.l2cache.demand_miss_latency::cpu.data 10148968500 # number of demand (read+write) miss cycles 748system.cpu.l2cache.demand_miss_latency::total 10518006500 # number of demand (read+write) miss cycles 749system.cpu.l2cache.overall_miss_latency::cpu.inst 369038000 # number of overall miss cycles 750system.cpu.l2cache.overall_miss_latency::cpu.data 10148968500 # number of overall miss cycles 751system.cpu.l2cache.overall_miss_latency::total 10518006500 # number of overall miss cycles 752system.cpu.l2cache.WritebackDirty_accesses::writebacks 128145 # number of WritebackDirty accesses(hits+misses) 753system.cpu.l2cache.WritebackDirty_accesses::total 128145 # number of WritebackDirty accesses(hits+misses) 754system.cpu.l2cache.WritebackClean_accesses::writebacks 39944 # number of WritebackClean accesses(hits+misses) 755system.cpu.l2cache.WritebackClean_accesses::total 39944 # number of WritebackClean accesses(hits+misses) |
| 758system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses) 759system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses) | 756system.cpu.l2cache.ReadExReq_accesses::cpu.data 107037 # number of ReadExReq accesses(hits+misses) 757system.cpu.l2cache.ReadExReq_accesses::total 107037 # number of ReadExReq accesses(hits+misses) |
| 760system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45581 # number of ReadCleanReq accesses(hits+misses) 761system.cpu.l2cache.ReadCleanReq_accesses::total 45581 # number of ReadCleanReq accesses(hits+misses) 762system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53503 # number of ReadSharedReq accesses(hits+misses) 763system.cpu.l2cache.ReadSharedReq_accesses::total 53503 # number of ReadSharedReq accesses(hits+misses) 764system.cpu.l2cache.demand_accesses::cpu.inst 45581 # number of demand (read+write) accesses 765system.cpu.l2cache.demand_accesses::cpu.data 160540 # number of demand (read+write) accesses 766system.cpu.l2cache.demand_accesses::total 206121 # number of demand (read+write) accesses 767system.cpu.l2cache.overall_accesses::cpu.inst 45581 # number of overall (read+write) accesses 768system.cpu.l2cache.overall_accesses::cpu.data 160540 # number of overall (read+write) accesses 769system.cpu.l2cache.overall_accesses::total 206121 # number of overall (read+write) accesses 770system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955557 # miss rate for ReadExReq accesses 771system.cpu.l2cache.ReadExReq_miss_rate::total 0.955557 # miss rate for ReadExReq accesses 772system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098199 # miss rate for ReadCleanReq accesses 773system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098199 # miss rate for ReadCleanReq accesses 774system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403772 # miss rate for ReadSharedReq accesses 775system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403772 # miss rate for ReadSharedReq accesses 776system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098199 # miss rate for demand accesses 777system.cpu.l2cache.demand_miss_rate::cpu.data 0.771664 # miss rate for demand accesses 778system.cpu.l2cache.demand_miss_rate::total 0.622736 # miss rate for demand accesses 779system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098199 # miss rate for overall accesses 780system.cpu.l2cache.overall_miss_rate::cpu.data 0.771664 # miss rate for overall accesses 781system.cpu.l2cache.overall_miss_rate::total 0.622736 # miss rate for overall accesses 782system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80929.331248 # average ReadExReq miss latency 783system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80929.331248 # average ReadExReq miss latency 784system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79745.978552 # average ReadCleanReq miss latency 785system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79745.978552 # average ReadCleanReq miss latency 786system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86412.535296 # average ReadSharedReq miss latency 787system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86412.535296 # average ReadSharedReq miss latency 788system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79745.978552 # average overall miss latency 789system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81885.504872 # average overall miss latency 790system.cpu.l2cache.demand_avg_miss_latency::total 81810.897561 # average overall miss latency 791system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79745.978552 # average overall miss latency 792system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81885.504872 # average overall miss latency 793system.cpu.l2cache.overall_avg_miss_latency::total 81810.897561 # average overall miss latency | 758system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45588 # number of ReadCleanReq accesses(hits+misses) 759system.cpu.l2cache.ReadCleanReq_accesses::total 45588 # number of ReadCleanReq accesses(hits+misses) 760system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses) 761system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses) 762system.cpu.l2cache.demand_accesses::cpu.inst 45588 # number of demand (read+write) accesses 763system.cpu.l2cache.demand_accesses::cpu.data 160547 # number of demand (read+write) accesses 764system.cpu.l2cache.demand_accesses::total 206135 # number of demand (read+write) accesses 765system.cpu.l2cache.overall_accesses::cpu.inst 45588 # number of overall (read+write) accesses 766system.cpu.l2cache.overall_accesses::cpu.data 160547 # number of overall (read+write) accesses 767system.cpu.l2cache.overall_accesses::total 206135 # number of overall (read+write) accesses 768system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955903 # miss rate for ReadExReq accesses 769system.cpu.l2cache.ReadExReq_miss_rate::total 0.955903 # miss rate for ReadExReq accesses 770system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098447 # miss rate for ReadCleanReq accesses 771system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098447 # miss rate for ReadCleanReq accesses 772system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.407101 # miss rate for ReadSharedReq accesses 773system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.407101 # miss rate for ReadSharedReq accesses 774system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098447 # miss rate for demand accesses 775system.cpu.l2cache.demand_miss_rate::cpu.data 0.772989 # miss rate for demand accesses 776system.cpu.l2cache.demand_miss_rate::total 0.623810 # miss rate for demand accesses 777system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098447 # miss rate for overall accesses 778system.cpu.l2cache.overall_miss_rate::cpu.data 0.772989 # miss rate for overall accesses 779system.cpu.l2cache.overall_miss_rate::total 0.623810 # miss rate for overall accesses 780system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80055.831387 # average ReadExReq miss latency 781system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80055.831387 # average ReadExReq miss latency 782system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82227.718360 # average ReadCleanReq miss latency 783system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82227.718360 # average ReadCleanReq miss latency 784system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 89877.708410 # average ReadSharedReq miss latency 785system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 89877.708410 # average ReadSharedReq miss latency 786system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency 787system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency 788system.cpu.l2cache.demand_avg_miss_latency::total 81795.538499 # average overall miss latency 789system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82227.718360 # average overall miss latency 790system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81779.909106 # average overall miss latency 791system.cpu.l2cache.overall_avg_miss_latency::total 81795.538499 # average overall miss latency |
| 794system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 795system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 796system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 797system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 798system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 799system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 792system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 793system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 794system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 795system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 796system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 797system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 800system.cpu.l2cache.writebacks::writebacks 86212 # number of writebacks 801system.cpu.l2cache.writebacks::total 86212 # number of writebacks 802system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 12 # number of ReadCleanReq MSHR hits 803system.cpu.l2cache.ReadCleanReq_mshr_hits::total 12 # number of ReadCleanReq MSHR hits | 798system.cpu.l2cache.writebacks::writebacks 86552 # number of writebacks 799system.cpu.l2cache.writebacks::total 86552 # number of writebacks 800system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits 801system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits |
| 804system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits 805system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits | 802system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 60 # number of ReadSharedReq MSHR hits 803system.cpu.l2cache.ReadSharedReq_mshr_hits::total 60 # number of ReadSharedReq MSHR hits |
| 806system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits | 804system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits |
| 807system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits | 805system.cpu.l2cache.demand_mshr_hits::cpu.data 60 # number of demand (read+write) MSHR hits |
| 808system.cpu.l2cache.demand_mshr_hits::total 72 # number of demand (read+write) MSHR hits 809system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits | 806system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 807system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits |
| 810system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits | 808system.cpu.l2cache.overall_mshr_hits::cpu.data 60 # number of overall MSHR hits |
| 811system.cpu.l2cache.overall_mshr_hits::total 72 # number of overall MSHR hits | 809system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits |
| 812system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 813system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses | 810system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 811system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses |
| 814system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102280 # number of ReadExReq MSHR misses 815system.cpu.l2cache.ReadExReq_mshr_misses::total 102280 # number of ReadExReq MSHR misses 816system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4464 # number of ReadCleanReq MSHR misses 817system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4464 # number of ReadCleanReq MSHR misses 818system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21543 # number of ReadSharedReq MSHR misses 819system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21543 # number of ReadSharedReq MSHR misses 820system.cpu.l2cache.demand_mshr_misses::cpu.inst 4464 # number of demand (read+write) MSHR misses 821system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses 822system.cpu.l2cache.demand_mshr_misses::total 128287 # number of demand (read+write) MSHR misses 823system.cpu.l2cache.overall_mshr_misses::cpu.inst 4464 # number of overall MSHR misses 824system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses 825system.cpu.l2cache.overall_mshr_misses::total 128287 # number of overall MSHR misses 826system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7254652000 # number of ReadExReq MSHR miss cycles 827system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7254652000 # number of ReadExReq MSHR miss cycles 828system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 311353500 # number of ReadCleanReq MSHR miss cycles 829system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 311353500 # number of ReadCleanReq MSHR miss cycles 830system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1646809500 # number of ReadSharedReq MSHR miss cycles 831system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1646809500 # number of ReadSharedReq MSHR miss cycles 832system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 311353500 # number of demand (read+write) MSHR miss cycles 833system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8901461500 # number of demand (read+write) MSHR miss cycles 834system.cpu.l2cache.demand_mshr_miss_latency::total 9212815000 # number of demand (read+write) MSHR miss cycles 835system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 311353500 # number of overall MSHR miss cycles 836system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8901461500 # number of overall MSHR miss cycles 837system.cpu.l2cache.overall_mshr_miss_latency::total 9212815000 # number of overall MSHR miss cycles | 812system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102317 # number of ReadExReq MSHR misses 813system.cpu.l2cache.ReadExReq_mshr_misses::total 102317 # number of ReadExReq MSHR misses 814system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4475 # number of ReadCleanReq MSHR misses 815system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4475 # number of ReadCleanReq MSHR misses 816system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21724 # number of ReadSharedReq MSHR misses 817system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21724 # number of ReadSharedReq MSHR misses 818system.cpu.l2cache.demand_mshr_misses::cpu.inst 4475 # number of demand (read+write) MSHR misses 819system.cpu.l2cache.demand_mshr_misses::cpu.data 124041 # number of demand (read+write) MSHR misses 820system.cpu.l2cache.demand_mshr_misses::total 128516 # number of demand (read+write) MSHR misses 821system.cpu.l2cache.overall_mshr_misses::cpu.inst 4475 # number of overall MSHR misses 822system.cpu.l2cache.overall_mshr_misses::cpu.data 124041 # number of overall MSHR misses 823system.cpu.l2cache.overall_mshr_misses::total 128516 # number of overall MSHR misses 824system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7167902500 # number of ReadExReq MSHR miss cycles 825system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7167902500 # number of ReadExReq MSHR miss cycles 826system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 323146000 # number of ReadCleanReq MSHR miss cycles 827system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 323146000 # number of ReadCleanReq MSHR miss cycles 828system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1736095500 # number of ReadSharedReq MSHR miss cycles 829system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1736095500 # number of ReadSharedReq MSHR miss cycles 830system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 323146000 # number of demand (read+write) MSHR miss cycles 831system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8903998000 # number of demand (read+write) MSHR miss cycles 832system.cpu.l2cache.demand_mshr_miss_latency::total 9227144000 # number of demand (read+write) MSHR miss cycles 833system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 323146000 # number of overall MSHR miss cycles 834system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8903998000 # number of overall MSHR miss cycles 835system.cpu.l2cache.overall_mshr_miss_latency::total 9227144000 # number of overall MSHR miss cycles |
| 838system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 839system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses | 836system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 837system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses |
| 840system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955557 # mshr miss rate for ReadExReq accesses 841system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955557 # mshr miss rate for ReadExReq accesses 842system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for ReadCleanReq accesses 843system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097936 # mshr miss rate for ReadCleanReq accesses 844system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402650 # mshr miss rate for ReadSharedReq accesses 845system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402650 # mshr miss rate for ReadSharedReq accesses 846system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for demand accesses 847system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771291 # mshr miss rate for demand accesses 848system.cpu.l2cache.demand_mshr_miss_rate::total 0.622387 # mshr miss rate for demand accesses 849system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097936 # mshr miss rate for overall accesses 850system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771291 # mshr miss rate for overall accesses 851system.cpu.l2cache.overall_mshr_miss_rate::total 0.622387 # mshr miss rate for overall accesses 852system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70929.331248 # average ReadExReq mshr miss latency 853system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70929.331248 # average ReadExReq mshr miss latency 854system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69747.647849 # average ReadCleanReq mshr miss latency 855system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69747.647849 # average ReadCleanReq mshr miss latency 856system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76442.904888 # average ReadSharedReq mshr miss latency 857system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76442.904888 # average ReadSharedReq mshr miss latency 858system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency 859system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency 860system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency 861system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69747.647849 # average overall mshr miss latency 862system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71888.595011 # average overall mshr miss latency 863system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71814.096518 # average overall mshr miss latency 864system.cpu.toL2Bus.snoop_filter.tot_requests 406103 # Total number of requests made to the snoop filter. 865system.cpu.toL2Bus.snoop_filter.hit_single_requests 200020 # Number of requests hitting in the snoop filter with a single holder of the requested data. | 838system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955903 # mshr miss rate for ReadExReq accesses 839system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955903 # mshr miss rate for ReadExReq accesses 840system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for ReadCleanReq accesses 841system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.098162 # mshr miss rate for ReadCleanReq accesses 842system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.405980 # mshr miss rate for ReadSharedReq accesses 843system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.405980 # mshr miss rate for ReadSharedReq accesses 844system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for demand accesses 845system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for demand accesses 846system.cpu.l2cache.demand_mshr_miss_rate::total 0.623456 # mshr miss rate for demand accesses 847system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.098162 # mshr miss rate for overall accesses 848system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.772615 # mshr miss rate for overall accesses 849system.cpu.l2cache.overall_mshr_miss_rate::total 0.623456 # mshr miss rate for overall accesses 850system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70055.831387 # average ReadExReq mshr miss latency 851system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70055.831387 # average ReadExReq mshr miss latency 852system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72211.396648 # average ReadCleanReq mshr miss latency 853system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72211.396648 # average ReadCleanReq mshr miss latency 854system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 79916.014546 # average ReadSharedReq mshr miss latency 855system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 79916.014546 # average ReadSharedReq mshr miss latency 856system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency 857system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency 858system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency 859system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72211.396648 # average overall mshr miss latency 860system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71782.700881 # average overall mshr miss latency 861system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71797.628311 # average overall mshr miss latency 862system.cpu.toL2Bus.snoop_filter.tot_requests 406131 # Total number of requests made to the snoop filter. 863system.cpu.toL2Bus.snoop_filter.hit_single_requests 200034 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| 866system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 864system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7844 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 867system.cpu.toL2Bus.snoop_filter.tot_snoops 3360 # Total number of snoops made to the snoop filter. 868system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3331 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 869system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 870system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states 871system.cpu.toL2Bus.trans_dist::ReadResp 99083 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::WritebackDirty 214595 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::WritebackClean 43538 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::CleanEvict 38242 # Transaction distribution | 865system.cpu.toL2Bus.snoop_filter.tot_snoops 3482 # Total number of snoops made to the snoop filter. 866system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3452 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 867system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 30 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 868system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 869system.cpu.toL2Bus.trans_dist::ReadResp 99097 # Transaction distribution 870system.cpu.toL2Bus.trans_dist::WritebackDirty 214697 # Transaction distribution 871system.cpu.toL2Bus.trans_dist::WritebackClean 43545 # Transaction distribution 872system.cpu.toL2Bus.trans_dist::CleanEvict 38930 # Transaction distribution |
| 875system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution 876system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution | 873system.cpu.toL2Bus.trans_dist::ReadExReq 107037 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::ReadExResp 107037 # Transaction distribution |
| 877system.cpu.toL2Bus.trans_dist::ReadCleanReq 45581 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::ReadSharedReq 53503 # Transaction distribution 879system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134699 # Packet count per connected master and slave (bytes) 880system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477524 # Packet count per connected master and slave (bytes) 881system.cpu.toL2Bus.pkt_count::total 612223 # Packet count per connected master and slave (bytes) 882system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5703552 # Cumulative packet size per connected master and slave (bytes) 883system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491072 # Cumulative packet size per connected master and slave (bytes) 884system.cpu.toL2Bus.pkt_size::total 24194624 # Cumulative packet size per connected master and slave (bytes) 885system.cpu.toL2Bus.snoops 96393 # Total snoops (count) 886system.cpu.toL2Bus.snoopTraffic 5517568 # Total snoop traffic (bytes) 887system.cpu.toL2Bus.snoop_fanout::samples 302514 # Request fanout histogram 888system.cpu.toL2Bus.snoop_fanout::mean 0.037258 # Request fanout histogram 889system.cpu.toL2Bus.snoop_fanout::stdev 0.189899 # Request fanout histogram | 875system.cpu.toL2Bus.trans_dist::ReadCleanReq 45588 # Transaction distribution 876system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution 877system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134720 # Packet count per connected master and slave (bytes) 878system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477545 # Packet count per connected master and slave (bytes) 879system.cpu.toL2Bus.pkt_count::total 612265 # Packet count per connected master and slave (bytes) 880system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5704448 # Cumulative packet size per connected master and slave (bytes) 881system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18476288 # Cumulative packet size per connected master and slave (bytes) 882system.cpu.toL2Bus.pkt_size::total 24180736 # Cumulative packet size per connected master and slave (bytes) 883system.cpu.toL2Bus.snoops 97176 # Total snoops (count) 884system.cpu.toL2Bus.snoopTraffic 5539328 # Total snoop traffic (bytes) 885system.cpu.toL2Bus.snoop_fanout::samples 303311 # Request fanout histogram 886system.cpu.toL2Bus.snoop_fanout::mean 0.037565 # Request fanout histogram 887system.cpu.toL2Bus.snoop_fanout::stdev 0.190662 # Request fanout histogram |
| 890system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 888system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 891system.cpu.toL2Bus.snoop_fanout::0 291272 96.28% 96.28% # Request fanout histogram 892system.cpu.toL2Bus.snoop_fanout::1 11213 3.71% 99.99% # Request fanout histogram 893system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram | 889system.cpu.toL2Bus.snoop_fanout::0 291947 96.25% 96.25% # Request fanout histogram 890system.cpu.toL2Bus.snoop_fanout::1 11334 3.74% 99.99% # Request fanout histogram 891system.cpu.toL2Bus.snoop_fanout::2 30 0.01% 100.00% # Request fanout histogram |
| 894system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 895system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 896system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 892system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 893system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 894system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 897system.cpu.toL2Bus.snoop_fanout::total 302514 # Request fanout histogram 898system.cpu.toL2Bus.reqLayer0.occupancy 374972500 # Layer occupancy (ticks) | 895system.cpu.toL2Bus.snoop_fanout::total 303311 # Request fanout histogram 896system.cpu.toL2Bus.reqLayer0.occupancy 374755500 # Layer occupancy (ticks) |
| 899system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) | 897system.cpu.toL2Bus.reqLayer0.utilization 0.6 # Layer utilization (%) |
| 900system.cpu.toL2Bus.respLayer0.occupancy 68384970 # Layer occupancy (ticks) | 898system.cpu.toL2Bus.respLayer0.occupancy 68396468 # Layer occupancy (ticks) |
| 901system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) | 899system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) |
| 902system.cpu.toL2Bus.respLayer1.occupancy 240842435 # Layer occupancy (ticks) | 900system.cpu.toL2Bus.respLayer1.occupancy 240852935 # Layer occupancy (ticks) |
| 903system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) | 901system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) |
| 904system.membus.pwrStateResidencyTicks::UNDEFINED 58768125500 # Cumulative time (in ticks) in various power states 905system.membus.trans_dist::ReadResp 26006 # Transaction distribution 906system.membus.trans_dist::WritebackDirty 86212 # Transaction distribution 907system.membus.trans_dist::CleanEvict 6916 # Transaction distribution 908system.membus.trans_dist::ReadExReq 102280 # Transaction distribution 909system.membus.trans_dist::ReadExResp 102280 # Transaction distribution 910system.membus.trans_dist::ReadSharedReq 26006 # Transaction distribution 911system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349700 # Packet count per connected master and slave (bytes) 912system.membus.pkt_count::total 349700 # Packet count per connected master and slave (bytes) 913system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727872 # Cumulative packet size per connected master and slave (bytes) 914system.membus.pkt_size::total 13727872 # Cumulative packet size per connected master and slave (bytes) | 902system.membus.snoop_filter.tot_requests 222304 # Total number of requests made to the snoop filter. 903system.membus.snoop_filter.hit_single_requests 93865 # Number of requests hitting in the snoop filter with a single holder of the requested data. 904system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 905system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 906system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 907system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 908system.membus.pwrStateResidencyTicks::UNDEFINED 58750410500 # Cumulative time (in ticks) in various power states 909system.membus.trans_dist::ReadResp 26198 # Transaction distribution 910system.membus.trans_dist::WritebackDirty 86552 # Transaction distribution 911system.membus.trans_dist::CleanEvict 7237 # Transaction distribution 912system.membus.trans_dist::ReadExReq 102317 # Transaction distribution 913system.membus.trans_dist::ReadExResp 102317 # Transaction distribution 914system.membus.trans_dist::ReadSharedReq 26198 # Transaction distribution 915system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 350819 # Packet count per connected master and slave (bytes) 916system.membus.pkt_count::total 350819 # Packet count per connected master and slave (bytes) 917system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13764288 # Cumulative packet size per connected master and slave (bytes) 918system.membus.pkt_size::total 13764288 # Cumulative packet size per connected master and slave (bytes) |
| 915system.membus.snoops 0 # Total snoops (count) 916system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 919system.membus.snoops 0 # Total snoops (count) 920system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 917system.membus.snoop_fanout::samples 221414 # Request fanout histogram | 921system.membus.snoop_fanout::samples 128515 # Request fanout histogram |
| 918system.membus.snoop_fanout::mean 0 # Request fanout histogram 919system.membus.snoop_fanout::stdev 0 # Request fanout histogram 920system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 922system.membus.snoop_fanout::mean 0 # Request fanout histogram 923system.membus.snoop_fanout::stdev 0 # Request fanout histogram 924system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 921system.membus.snoop_fanout::0 221414 100.00% 100.00% # Request fanout histogram | 925system.membus.snoop_fanout::0 128515 100.00% 100.00% # Request fanout histogram |
| 922system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 923system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 924system.membus.snoop_fanout::min_value 0 # Request fanout histogram 925system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 926system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 927system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 928system.membus.snoop_fanout::min_value 0 # Request fanout histogram 929system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 926system.membus.snoop_fanout::total 221414 # Request fanout histogram 927system.membus.reqLayer0.occupancy 586752500 # Layer occupancy (ticks) | 930system.membus.snoop_fanout::total 128515 # Request fanout histogram 931system.membus.reqLayer0.occupancy 587526000 # Layer occupancy (ticks) |
| 928system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) | 932system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) |
| 929system.membus.respLayer1.occupancy 676437000 # Layer occupancy (ticks) | 933system.membus.respLayer1.occupancy 677474000 # Layer occupancy (ticks) |
| 930system.membus.respLayer1.utilization 1.2 # Layer utilization (%) 931 932---------- End Simulation Statistics ---------- | 934system.membus.respLayer1.utilization 1.2 # Layer utilization (%) 935 936---------- End Simulation Statistics ---------- |