Cross Reference: /gem5/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt

stats.txt (11507:be6065c1d8d2)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.056803 # Number of seconds simulated 4sim_ticks 56802974500 # Number of ticks simulated 5final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.056803 # Number of seconds simulated 4sim_ticks 56802974500 # Number of ticks simulated 5final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 132517 # Simulator instruction rate (inst/s) 8host_op_rate 169470 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 106146312 # Simulator tick rate (ticks/s) 10host_mem_usage 275700 # Number of bytes of host memory used 11host_seconds 535.14 # Real time elapsed on the host	7host_inst_rate 307576 # Simulator instruction rate (inst/s) 8host_op_rate 393344 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 246367888 # Simulator tick rate (ticks/s) 10host_mem_usage 323312 # Number of bytes of host memory used 11host_seconds 230.56 # Real time elapsed on the host
12sim_insts 70915150 # Number of instructions simulated 13sim_ops 90690106 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	12sim_insts 70915150 # Number of instructions simulated 13sim_ops 90690106 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 285504 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5517760 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5517760 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4461 # Number of read requests responded to by this memory --- 250 unchanged lines hidden (view full) --- 274system.physmem_1.preBackEnergy 24426384750 # Energy for precharge background per rank (pJ) 275system.physmem_1.totalEnergy 40129152600 # Total energy per rank (pJ) 276system.physmem_1.averagePower 706.487303 # Core power per rank (mW) 277system.physmem_1.memoryStateTime::IDLE 40510168000 # Time in different power states 278system.physmem_1.memoryStateTime::REF 1896700000 # Time in different power states 279system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 280system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states 281system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states	17system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory 19system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 285504 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::writebacks 5517760 # Number of bytes written to this memory 23system.physmem.bytes_written::total 5517760 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 4461 # Number of read requests responded to by this memory --- 250 unchanged lines hidden (view full) --- 275system.physmem_1.preBackEnergy 24426384750 # Energy for precharge background per rank (pJ) 276system.physmem_1.totalEnergy 40129152600 # Total energy per rank (pJ) 277system.physmem_1.averagePower 706.487303 # Core power per rank (mW) 278system.physmem_1.memoryStateTime::IDLE 40510168000 # Time in different power states 279system.physmem_1.memoryStateTime::REF 1896700000 # Time in different power states 280system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 281system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states 282system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
	283system.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
282system.cpu.branchPred.lookups 14774616 # Number of BP lookups 283system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted 284system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect 285system.cpu.branchPred.BTBLookups 9548677 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 6547888 # Number of BTB hits 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 288system.cpu.branchPred.BTBHitPct 68.573772 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 1714315 # Number of times the RAS was used to get a target. 290system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 291system.cpu.branchPred.indirectLookups 174550 # Number of indirect predictor lookups. 292system.cpu.branchPred.indirectHits 157999 # Number of indirect target hits. 293system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses. 294system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches. 295system.cpu_clk_domain.clock 500 # Clock period in ticks	284system.cpu.branchPred.lookups 14774616 # Number of BP lookups 285system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted 286system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect 287system.cpu.branchPred.BTBLookups 9548677 # Number of BTB lookups 288system.cpu.branchPred.BTBHits 6547888 # Number of BTB hits 289system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 290system.cpu.branchPred.BTBHitPct 68.573772 # BTB Hit Percentage 291system.cpu.branchPred.usedRAS 1714315 # Number of times the RAS was used to get a target. 292system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 293system.cpu.branchPred.indirectLookups 174550 # Number of indirect predictor lookups. 294system.cpu.branchPred.indirectHits 157999 # Number of indirect target hits. 295system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses. 296system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches. 297system.cpu_clk_domain.clock 500 # Clock period in ticks
	298system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
296system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 317system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 320system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 321system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 322system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 323system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 324system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	299system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 320system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 321system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 322system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 323system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 324system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 325system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 326system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 327system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	328system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
325system.cpu.dtb.walker.walks 0 # Table walker walks requested 326system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.dtb.read_accesses 0 # DTB read accesses 349system.cpu.dtb.write_accesses 0 # DTB write accesses 350system.cpu.dtb.inst_accesses 0 # ITB inst accesses 351system.cpu.dtb.hits 0 # DTB hits 352system.cpu.dtb.misses 0 # DTB misses 353system.cpu.dtb.accesses 0 # DTB accesses	329system.cpu.dtb.walker.walks 0 # Table walker walks requested 330system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 336system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 350system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 351system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 352system.cpu.dtb.read_accesses 0 # DTB read accesses 353system.cpu.dtb.write_accesses 0 # DTB write accesses 354system.cpu.dtb.inst_accesses 0 # ITB inst accesses 355system.cpu.dtb.hits 0 # DTB hits 356system.cpu.dtb.misses 0 # DTB misses 357system.cpu.dtb.accesses 0 # DTB accesses
	358system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
354system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 375system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 378system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 379system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 380system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 381system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 382system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	359system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 380system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 381system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 382system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 383system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 384system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 385system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 386system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 387system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	388system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
383system.cpu.itb.walker.walks 0 # Table walker walks requested 384system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 405system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu.itb.read_accesses 0 # DTB read accesses 407system.cpu.itb.write_accesses 0 # DTB write accesses 408system.cpu.itb.inst_accesses 0 # ITB inst accesses 409system.cpu.itb.hits 0 # DTB hits 410system.cpu.itb.misses 0 # DTB misses 411system.cpu.itb.accesses 0 # DTB accesses 412system.cpu.workload.num_syscalls 1946 # Number of system calls	389system.cpu.itb.walker.walks 0 # Table walker walks requested 390system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 392system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 393system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 394system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 395system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 396system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 411system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 412system.cpu.itb.read_accesses 0 # DTB read accesses 413system.cpu.itb.write_accesses 0 # DTB write accesses 414system.cpu.itb.inst_accesses 0 # ITB inst accesses 415system.cpu.itb.hits 0 # DTB hits 416system.cpu.itb.misses 0 # DTB misses 417system.cpu.itb.accesses 0 # DTB accesses 418system.cpu.workload.num_syscalls 1946 # Number of system calls
	419system.cpu.pwrStateResidencyTicks::ON 56802974500 # Cumulative time (in ticks) in various power states
413system.cpu.numCycles 113605949 # number of cpu cycles simulated 414system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 415system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 416system.cpu.committedInsts 70915150 # Number of instructions committed 417system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed 418system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit 419system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 420system.cpu.cpi 1.601998 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 451system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 452system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 453system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction 454system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 455system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 456system.cpu.op_class_0::total 90690106 # Class of committed instruction 457system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked 458system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped	420system.cpu.numCycles 113605949 # number of cpu cycles simulated 421system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 422system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 423system.cpu.committedInsts 70915150 # Number of instructions committed 424system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed 425system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit 426system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 427system.cpu.cpi 1.601998 # CPI: cycles per instruction --- 30 unchanged lines hidden (view full) --- 458system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 459system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 460system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction 461system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 462system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 463system.cpu.op_class_0::total 90690106 # Class of committed instruction 464system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked 465system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped
	466system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
459system.cpu.dcache.tags.replacements 156448 # number of replacements 460system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use 461system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks. 462system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks. 463system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks. 464system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit. 465system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor 466system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy 467system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy 468system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 469system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 470system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id 471system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id 472system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 473system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses 474system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses	467system.cpu.dcache.tags.replacements 156448 # number of replacements 468system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use 469system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks. 470system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks. 471system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks. 472system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit. 473system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor 474system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy 475system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy 476system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 477system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 478system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id 479system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id 480system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 481system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses 482system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses
	483system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
475system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits 476system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits 477system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits 478system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits 479system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits 480system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits 481system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 482system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 587system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency 588system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency 589system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency 590system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency 591system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency 592system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency 593system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency 594system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency	484system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits 485system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits 486system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits 487system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits 488system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits 489system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits 490system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 491system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits --- 104 unchanged lines hidden (view full) --- 596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency 597system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency 598system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency 599system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency 600system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency 601system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency 602system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency 603system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency
	604system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
595system.cpu.icache.tags.replacements 43497 # number of replacements 596system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use 597system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks. 598system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks. 599system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks. 600system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 601system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor 602system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy 603system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy 604system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id 605system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 606system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 607system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id 608system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id 609system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id 610system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses 611system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses	605system.cpu.icache.tags.replacements 43497 # number of replacements 606system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use 607system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks. 608system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks. 609system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks. 610system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 611system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor 612system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy 613system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy 614system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id 615system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 616system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 617system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id 618system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id 619system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id 620system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses 621system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses
	622system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
612system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits 613system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits 614system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits 615system.cpu.icache.demand_hits::total 24844377 # number of demand (read+write) hits 616system.cpu.icache.overall_hits::cpu.inst 24844377 # number of overall hits 617system.cpu.icache.overall_hits::total 24844377 # number of overall hits 618system.cpu.icache.ReadReq_misses::cpu.inst 45540 # number of ReadReq misses 619system.cpu.icache.ReadReq_misses::total 45540 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 672system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses 673system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency 675system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency 677system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency 679system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency	623system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits 624system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits 625system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits 626system.cpu.icache.demand_hits::total 24844377 # number of demand (read+write) hits 627system.cpu.icache.overall_hits::cpu.inst 24844377 # number of overall hits 628system.cpu.icache.overall_hits::total 24844377 # number of overall hits 629system.cpu.icache.ReadReq_misses::cpu.inst 45540 # number of ReadReq misses 630system.cpu.icache.ReadReq_misses::total 45540 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses 684system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
	691system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
680system.cpu.l2cache.tags.replacements 96391 # number of replacements 681system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use 682system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks. 683system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks. 684system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks. 685system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 686system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor 687system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 694system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 695system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id 696system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12725 # Occupied blocks per task id 697system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15781 # Occupied blocks per task id 698system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 # Occupied blocks per task id 699system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id 700system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses 701system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses	692system.cpu.l2cache.tags.replacements 96391 # number of replacements 693system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use 694system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks. 695system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks. 696system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks. 697system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 698system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor 699system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor --- 6 unchanged lines hidden (view full) --- 706system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 707system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id 708system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12725 # Occupied blocks per task id 709system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15781 # Occupied blocks per task id 710system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 # Occupied blocks per task id 711system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id 712system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses 713system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses
	714system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
702system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits 703system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits 704system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits 705system.cpu.l2cache.WritebackClean_hits::total 39908 # number of WritebackClean hits 706system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits 707system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits 708system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41065 # number of ReadCleanReq hits 709system.cpu.l2cache.ReadCleanReq_hits::total 41065 # number of ReadCleanReq hits --- 140 unchanged lines hidden (view full) --- 850system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency 851system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency 852system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter. 853system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data. 854system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 855system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter. 856system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 857system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	715system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits 716system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits 717system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits 718system.cpu.l2cache.WritebackClean_hits::total 39908 # number of WritebackClean hits 719system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits 720system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits 721system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41065 # number of ReadCleanReq hits 722system.cpu.l2cache.ReadCleanReq_hits::total 41065 # number of ReadCleanReq hits --- 140 unchanged lines hidden (view full) --- 863system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency 864system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency 865system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter. 866system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data. 867system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 868system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter. 869system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 870system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	871system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
858system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution 859system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution 860system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution 861system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution 862system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 882system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 883system.cpu.toL2Bus.snoop_fanout::total 302475 # Request fanout histogram 884system.cpu.toL2Bus.reqLayer0.occupancy 374900500 # Layer occupancy (ticks) 885system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 886system.cpu.toL2Bus.respLayer0.occupancy 68328959 # Layer occupancy (ticks) 887system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 888system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks) 889system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)	872system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution 873system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution 874system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution 875system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution 876system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution 877system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution 878system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution 879system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 896system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 897system.cpu.toL2Bus.snoop_fanout::total 302475 # Request fanout histogram 898system.cpu.toL2Bus.reqLayer0.occupancy 374900500 # Layer occupancy (ticks) 899system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 900system.cpu.toL2Bus.respLayer0.occupancy 68328959 # Layer occupancy (ticks) 901system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 902system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks) 903system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
	904system.membus.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states
890system.membus.trans_dist::ReadResp 26002 # Transaction distribution 891system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution 892system.membus.trans_dist::CleanEvict 6912 # Transaction distribution 893system.membus.trans_dist::ReadExReq 102282 # Transaction distribution 894system.membus.trans_dist::ReadExResp 102282 # Transaction distribution 895system.membus.trans_dist::ReadSharedReq 26002 # Transaction distribution 896system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349695 # Packet count per connected master and slave (bytes) 897system.membus.pkt_count::total 349695 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden ---	905system.membus.trans_dist::ReadResp 26002 # Transaction distribution 906system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution 907system.membus.trans_dist::CleanEvict 6912 # Transaction distribution 908system.membus.trans_dist::ReadExReq 102282 # Transaction distribution 909system.membus.trans_dist::ReadExResp 102282 # Transaction distribution 910system.membus.trans_dist::ReadSharedReq 26002 # Transaction distribution 911system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349695 # Packet count per connected master and slave (bytes) 912system.membus.pkt_count::total 349695 # Packet count per connected master and slave (bytes) --- 19 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.056803 # Number of seconds simulated
4sim_ticks 56802974500 # Number of ticks simulated
5final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 132517 # Simulator instruction rate (inst/s)
8host_op_rate 169470 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 106146312 # Simulator tick rate (ticks/s)
10host_mem_usage 275700 # Number of bytes of host memory used
11host_seconds 535.14 # Real time elapsed on the host

7host_inst_rate 307576 # Simulator instruction rate (inst/s)
8host_op_rate 393344 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 246367888 # Simulator tick rate (ticks/s)
10host_mem_usage 323312 # Number of bytes of host memory used
11host_seconds 230.56 # Real time elapsed on the host

12sim_insts 70915150 # Number of instructions simulated
13sim_ops 90690106 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory
18system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 285504 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 5517760 # Number of bytes written to this memory
22system.physmem.bytes_written::total 5517760 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 4461 # Number of read requests responded to by this memory

--- 250 unchanged lines hidden (view full) ---

274system.physmem_1.preBackEnergy 24426384750 # Energy for precharge background per rank (pJ)
275system.physmem_1.totalEnergy 40129152600 # Total energy per rank (pJ)
276system.physmem_1.averagePower 706.487303 # Core power per rank (mW)
277system.physmem_1.memoryStateTime::IDLE 40510168000 # Time in different power states
278system.physmem_1.memoryStateTime::REF 1896700000 # Time in different power states
279system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
280system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states
281system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

17system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory
19system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 285504 # Number of instructions bytes read from this memory
22system.physmem.bytes_written::writebacks 5517760 # Number of bytes written to this memory
23system.physmem.bytes_written::total 5517760 # Number of bytes written to this memory
24system.physmem.num_reads::cpu.inst 4461 # Number of read requests responded to by this memory

--- 250 unchanged lines hidden (view full) ---

275system.physmem_1.preBackEnergy 24426384750 # Energy for precharge background per rank (pJ)
276system.physmem_1.totalEnergy 40129152600 # Total energy per rank (pJ)
277system.physmem_1.averagePower 706.487303 # Core power per rank (mW)
278system.physmem_1.memoryStateTime::IDLE 40510168000 # Time in different power states
279system.physmem_1.memoryStateTime::REF 1896700000 # Time in different power states
280system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
281system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states
282system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states

283system.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

282system.cpu.branchPred.lookups 14774616 # Number of BP lookups
283system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted
284system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect
285system.cpu.branchPred.BTBLookups 9548677 # Number of BTB lookups
286system.cpu.branchPred.BTBHits 6547888 # Number of BTB hits
287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
288system.cpu.branchPred.BTBHitPct 68.573772 # BTB Hit Percentage
289system.cpu.branchPred.usedRAS 1714315 # Number of times the RAS was used to get a target.
290system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
291system.cpu.branchPred.indirectLookups 174550 # Number of indirect predictor lookups.
292system.cpu.branchPred.indirectHits 157999 # Number of indirect target hits.
293system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses.
294system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches.
295system.cpu_clk_domain.clock 500 # Clock period in ticks

284system.cpu.branchPred.lookups 14774616 # Number of BP lookups
285system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted
286system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect
287system.cpu.branchPred.BTBLookups 9548677 # Number of BTB lookups
288system.cpu.branchPred.BTBHits 6547888 # Number of BTB hits
289system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
290system.cpu.branchPred.BTBHitPct 68.573772 # BTB Hit Percentage
291system.cpu.branchPred.usedRAS 1714315 # Number of times the RAS was used to get a target.
292system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
293system.cpu.branchPred.indirectLookups 174550 # Number of indirect predictor lookups.
294system.cpu.branchPred.indirectHits 157999 # Number of indirect target hits.
295system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses.
296system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches.
297system.cpu_clk_domain.clock 500 # Clock period in ticks

298system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

296system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

317system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
318system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
319system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
320system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
321system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
322system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
323system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
324system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

299system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
304system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
305system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
306system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

320system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
321system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
322system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
323system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
324system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
325system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
326system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
327system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

328system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

325system.cpu.dtb.walker.walks 0 # Table walker walks requested
326system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
327system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
328system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
329system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
330system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
331system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
332system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
347system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
348system.cpu.dtb.read_accesses 0 # DTB read accesses
349system.cpu.dtb.write_accesses 0 # DTB write accesses
350system.cpu.dtb.inst_accesses 0 # ITB inst accesses
351system.cpu.dtb.hits 0 # DTB hits
352system.cpu.dtb.misses 0 # DTB misses
353system.cpu.dtb.accesses 0 # DTB accesses

329system.cpu.dtb.walker.walks 0 # Table walker walks requested
330system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
331system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
332system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
333system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
334system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
335system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
336system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

350system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
351system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
352system.cpu.dtb.read_accesses 0 # DTB read accesses
353system.cpu.dtb.write_accesses 0 # DTB write accesses
354system.cpu.dtb.inst_accesses 0 # ITB inst accesses
355system.cpu.dtb.hits 0 # DTB hits
356system.cpu.dtb.misses 0 # DTB misses
357system.cpu.dtb.accesses 0 # DTB accesses

358system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

354system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

375system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
376system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
377system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
378system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
379system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
380system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
381system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
382system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

359system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
362system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
363system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
364system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
365system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
366system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

380system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
381system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
382system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
383system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
384system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
385system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
386system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
387system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

388system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

383system.cpu.itb.walker.walks 0 # Table walker walks requested
384system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
385system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
386system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
387system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
388system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
389system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
390system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

405system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
406system.cpu.itb.read_accesses 0 # DTB read accesses
407system.cpu.itb.write_accesses 0 # DTB write accesses
408system.cpu.itb.inst_accesses 0 # ITB inst accesses
409system.cpu.itb.hits 0 # DTB hits
410system.cpu.itb.misses 0 # DTB misses
411system.cpu.itb.accesses 0 # DTB accesses
412system.cpu.workload.num_syscalls 1946 # Number of system calls

389system.cpu.itb.walker.walks 0 # Table walker walks requested
390system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
391system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
392system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
393system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
394system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
395system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
396system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

411system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
412system.cpu.itb.read_accesses 0 # DTB read accesses
413system.cpu.itb.write_accesses 0 # DTB write accesses
414system.cpu.itb.inst_accesses 0 # ITB inst accesses
415system.cpu.itb.hits 0 # DTB hits
416system.cpu.itb.misses 0 # DTB misses
417system.cpu.itb.accesses 0 # DTB accesses
418system.cpu.workload.num_syscalls 1946 # Number of system calls

419system.cpu.pwrStateResidencyTicks::ON 56802974500 # Cumulative time (in ticks) in various power states

413system.cpu.numCycles 113605949 # number of cpu cycles simulated
414system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
415system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
416system.cpu.committedInsts 70915150 # Number of instructions committed
417system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
418system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit
419system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
420system.cpu.cpi 1.601998 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

451system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
452system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction
453system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction
454system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
455system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
456system.cpu.op_class_0::total 90690106 # Class of committed instruction
457system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked
458system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped

420system.cpu.numCycles 113605949 # number of cpu cycles simulated
421system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
422system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
423system.cpu.committedInsts 70915150 # Number of instructions committed
424system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
425system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit
426system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
427system.cpu.cpi 1.601998 # CPI: cycles per instruction

--- 30 unchanged lines hidden (view full) ---

458system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
459system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction
460system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction
461system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
462system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
463system.cpu.op_class_0::total 90690106 # Class of committed instruction
464system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked
465system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped

466system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

459system.cpu.dcache.tags.replacements 156448 # number of replacements
460system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use
461system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks.
462system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks.
463system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks.
464system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit.
465system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor
466system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy
467system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy
468system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
469system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
470system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id
471system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id
472system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
473system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses
474system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses

467system.cpu.dcache.tags.replacements 156448 # number of replacements
468system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use
469system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks.
470system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks.
471system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks.
472system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit.
473system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor
474system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy
475system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy
476system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
477system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
478system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id
479system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id
480system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
481system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses
482system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses

483system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

475system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits
476system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits
477system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits
478system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits
479system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits
480system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits
481system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
482system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

587system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency
588system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency
589system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency
590system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency
591system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency
592system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency
593system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency
594system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency

484system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits
485system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits
486system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits
487system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits
488system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits
489system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits
490system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
491system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits

--- 104 unchanged lines hidden (view full) ---

596system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency
597system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency
598system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency
599system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency
600system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency
601system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency
602system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency
603system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency

604system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

595system.cpu.icache.tags.replacements 43497 # number of replacements
596system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use
597system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks.
598system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks.
599system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks.
600system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
601system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor
602system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy
603system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy
604system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
605system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
606system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
607system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id
608system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id
609system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
610system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses
611system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses

605system.cpu.icache.tags.replacements 43497 # number of replacements
606system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use
607system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks.
608system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks.
609system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks.
610system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
611system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor
612system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy
613system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy
614system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
615system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
616system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
617system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id
618system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id
619system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
620system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses
621system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses

622system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

612system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits
613system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits
614system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits
615system.cpu.icache.demand_hits::total 24844377 # number of demand (read+write) hits
616system.cpu.icache.overall_hits::cpu.inst 24844377 # number of overall hits
617system.cpu.icache.overall_hits::total 24844377 # number of overall hits
618system.cpu.icache.ReadReq_misses::cpu.inst 45540 # number of ReadReq misses
619system.cpu.icache.ReadReq_misses::total 45540 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

672system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses
673system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses
674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency
675system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency
676system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
677system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
678system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
679system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency

623system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits
624system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits
625system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits
626system.cpu.icache.demand_hits::total 24844377 # number of demand (read+write) hits
627system.cpu.icache.overall_hits::cpu.inst 24844377 # number of overall hits
628system.cpu.icache.overall_hits::total 24844377 # number of overall hits
629system.cpu.icache.ReadReq_misses::cpu.inst 45540 # number of ReadReq misses
630system.cpu.icache.ReadReq_misses::total 45540 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses
684system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses
685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency
686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency
687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
688system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
690system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency

691system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

680system.cpu.l2cache.tags.replacements 96391 # number of replacements
681system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use
682system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks.
683system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks.
684system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks.
685system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
686system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor
687system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor

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694system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
695system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id
696system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12725 # Occupied blocks per task id
697system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15781 # Occupied blocks per task id
698system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 # Occupied blocks per task id
699system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id
700system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses
701system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses

692system.cpu.l2cache.tags.replacements 96391 # number of replacements
693system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use
694system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks.
695system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks.
696system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks.
697system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
698system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor
699system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor

--- 6 unchanged lines hidden (view full) ---

706system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
707system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id
708system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12725 # Occupied blocks per task id
709system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15781 # Occupied blocks per task id
710system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 # Occupied blocks per task id
711system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id
712system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses
713system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses

714system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

702system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits
703system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits
704system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits
705system.cpu.l2cache.WritebackClean_hits::total 39908 # number of WritebackClean hits
706system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits
707system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits
708system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41065 # number of ReadCleanReq hits
709system.cpu.l2cache.ReadCleanReq_hits::total 41065 # number of ReadCleanReq hits

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850system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
851system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
852system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter.
853system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data.
854system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
855system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter.
856system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
857system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

715system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits
716system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits
717system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits
718system.cpu.l2cache.WritebackClean_hits::total 39908 # number of WritebackClean hits
719system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits
720system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits
721system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41065 # number of ReadCleanReq hits
722system.cpu.l2cache.ReadCleanReq_hits::total 41065 # number of ReadCleanReq hits

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863system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
864system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
865system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter.
866system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data.
867system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
868system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter.
869system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
870system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

871system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states

858system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution
859system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution
860system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution
861system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution
862system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
863system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
864system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution
865system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution

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882system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
883system.cpu.toL2Bus.snoop_fanout::total 302475 # Request fanout histogram
884system.cpu.toL2Bus.reqLayer0.occupancy 374900500 # Layer occupancy (ticks)
885system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
886system.cpu.toL2Bus.respLayer0.occupancy 68328959 # Layer occupancy (ticks)
887system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
888system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks)
889system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)

872system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution
873system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution
874system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution
875system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution
876system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
877system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
878system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution
879system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution

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896system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
897system.cpu.toL2Bus.snoop_fanout::total 302475 # Request fanout histogram
898system.cpu.toL2Bus.reqLayer0.occupancy 374900500 # Layer occupancy (ticks)
899system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
900system.cpu.toL2Bus.respLayer0.occupancy 68328959 # Layer occupancy (ticks)
901system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
902system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks)
903system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)

904system.membus.pwrStateResidencyTicks::UNDEFINED 56802974500 # Cumulative time (in ticks) in various power states