Cross Reference: /gem5/tests/long/se/50.vortex/ref/arm/linux/minor-timing/stats.txt

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stats.txt (11456:c0fb4435b80f)	stats.txt (11502:e273e86a873d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.056803 # Number of seconds simulated 4sim_ticks 56802974500 # Number of ticks simulated 5final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 222036 # Simulator instruction rate (inst/s) 8host_op_rate 283951 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 177850276 # Simulator tick rate (ticks/s) 10host_mem_usage 280068 # Number of bytes of host memory used 11host_seconds 319.39 # Real time elapsed on the host 12sim_insts 70915150 # Number of instructions simulated 13sim_ops 90690106 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 285504 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::writebacks 5517760 # Number of bytes written to this memory 22system.physmem.bytes_written::total 5517760 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4461 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 128284 # Number of read requests responded to by this memory 26system.physmem.num_writes::writebacks 86215 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 86215 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 5026216 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 139511567 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 144537783 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 5026216 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 5026216 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::writebacks 97138575 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 97138575 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::writebacks 97138575 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 5026216 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 139511567 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 241676358 # Total bandwidth to/from this memory (bytes/s) 39system.physmem.readReqs 128284 # Number of read requests accepted 40system.physmem.writeReqs 86215 # Number of write requests accepted 41system.physmem.readBursts 128284 # Number of DRAM read bursts, including those serviced by the write queue 42system.physmem.writeBursts 86215 # Number of DRAM write bursts, including those merged in the write queue 43system.physmem.bytesReadDRAM 8209792 # Total number of bytes read from DRAM 44system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue 45system.physmem.bytesWritten 5515904 # Total number of bytes written to DRAM 46system.physmem.bytesReadSys 8210176 # Total read bytes from the system interface side 47system.physmem.bytesWrittenSys 5517760 # Total written bytes from the system interface side 48system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue 49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 51system.physmem.perBankRdBursts::0 8062 # Per bank write bursts 52system.physmem.perBankRdBursts::1 8315 # Per bank write bursts 53system.physmem.perBankRdBursts::2 8233 # Per bank write bursts 54system.physmem.perBankRdBursts::3 8142 # Per bank write bursts 55system.physmem.perBankRdBursts::4 8284 # Per bank write bursts 56system.physmem.perBankRdBursts::5 8403 # Per bank write bursts 57system.physmem.perBankRdBursts::6 8055 # Per bank write bursts 58system.physmem.perBankRdBursts::7 7916 # Per bank write bursts 59system.physmem.perBankRdBursts::8 8035 # Per bank write bursts 60system.physmem.perBankRdBursts::9 7587 # Per bank write bursts 61system.physmem.perBankRdBursts::10 7763 # Per bank write bursts 62system.physmem.perBankRdBursts::11 7815 # Per bank write bursts 63system.physmem.perBankRdBursts::12 7871 # Per bank write bursts 64system.physmem.perBankRdBursts::13 7867 # Per bank write bursts 65system.physmem.perBankRdBursts::14 7968 # Per bank write bursts 66system.physmem.perBankRdBursts::15 7962 # Per bank write bursts 67system.physmem.perBankWrBursts::0 5395 # Per bank write bursts 68system.physmem.perBankWrBursts::1 5541 # Per bank write bursts 69system.physmem.perBankWrBursts::2 5468 # Per bank write bursts 70system.physmem.perBankWrBursts::3 5336 # Per bank write bursts 71system.physmem.perBankWrBursts::4 5366 # Per bank write bursts 72system.physmem.perBankWrBursts::5 5560 # Per bank write bursts 73system.physmem.perBankWrBursts::6 5257 # Per bank write bursts 74system.physmem.perBankWrBursts::7 5179 # Per bank write bursts 75system.physmem.perBankWrBursts::8 5154 # Per bank write bursts 76system.physmem.perBankWrBursts::9 5105 # Per bank write bursts 77system.physmem.perBankWrBursts::10 5292 # Per bank write bursts 78system.physmem.perBankWrBursts::11 5270 # Per bank write bursts 79system.physmem.perBankWrBursts::12 5531 # Per bank write bursts 80system.physmem.perBankWrBursts::13 5597 # Per bank write bursts 81system.physmem.perBankWrBursts::14 5703 # Per bank write bursts 82system.physmem.perBankWrBursts::15 5432 # Per bank write bursts 83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 85system.physmem.totGap 56802942500 # Total gap between requests 86system.physmem.readPktSize::0 0 # Read request sizes (log2) 87system.physmem.readPktSize::1 0 # Read request sizes (log2) 88system.physmem.readPktSize::2 0 # Read request sizes (log2) 89system.physmem.readPktSize::3 0 # Read request sizes (log2) 90system.physmem.readPktSize::4 0 # Read request sizes (log2) 91system.physmem.readPktSize::5 0 # Read request sizes (log2) 92system.physmem.readPktSize::6 128284 # Read request sizes (log2) 93system.physmem.writePktSize::0 0 # Write request sizes (log2) 94system.physmem.writePktSize::1 0 # Write request sizes (log2) 95system.physmem.writePktSize::2 0 # Write request sizes (log2) 96system.physmem.writePktSize::3 0 # Write request sizes (log2) 97system.physmem.writePktSize::4 0 # Write request sizes (log2) 98system.physmem.writePktSize::5 0 # Write request sizes (log2) 99system.physmem.writePktSize::6 86215 # Write request sizes (log2) 100system.physmem.rdQLenPdf::0 116125 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::1 12132 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::15 631 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::16 643 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::17 4122 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::18 5183 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::19 5277 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::20 5318 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::21 5309 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::22 5314 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::24 5321 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::25 5353 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::27 5464 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::28 5436 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::29 5495 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::31 5447 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::32 5305 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 196system.physmem.bytesPerActivate::samples 38880 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::mean 352.990947 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::gmean 214.489872 # Bytes accessed per row activation 199system.physmem.bytesPerActivate::stdev 335.589979 # Bytes accessed per row activation 200system.physmem.bytesPerActivate::0-127 12269 31.56% 31.56% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::128-255 8336 21.44% 53.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::256-383 4191 10.78% 63.78% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::384-511 2845 7.32% 71.09% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::512-639 2490 6.40% 77.50% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::640-767 1681 4.32% 81.82% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::768-895 1302 3.35% 85.17% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::896-1023 1149 2.96% 88.12% # Bytes accessed per row activation 208system.physmem.bytesPerActivate::1024-1151 4617 11.88% 100.00% # Bytes accessed per row activation 209system.physmem.bytesPerActivate::total 38880 # Bytes accessed per row activation 210system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes 211system.physmem.rdPerTurnAround::mean 24.227616 # Reads before turning the bus around for writes 212system.physmem.rdPerTurnAround::stdev 352.423208 # Reads before turning the bus around for writes 213system.physmem.rdPerTurnAround::0-1023 5291 99.94% 99.94% # Reads before turning the bus around for writes 214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes 215system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes 216system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes 217system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes 218system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads 219system.physmem.wrPerTurnAround::mean 16.279940 # Writes before turning the bus around for reads 220system.physmem.wrPerTurnAround::gmean 16.260845 # Writes before turning the bus around for reads 221system.physmem.wrPerTurnAround::stdev 0.856304 # Writes before turning the bus around for reads 222system.physmem.wrPerTurnAround::16 4659 88.01% 88.01% # Writes before turning the bus around for reads 223system.physmem.wrPerTurnAround::17 4 0.08% 88.08% # Writes before turning the bus around for reads 224system.physmem.wrPerTurnAround::18 483 9.12% 97.20% # Writes before turning the bus around for reads 225system.physmem.wrPerTurnAround::19 119 2.25% 99.45% # Writes before turning the bus around for reads 226system.physmem.wrPerTurnAround::20 16 0.30% 99.75% # Writes before turning the bus around for reads 227system.physmem.wrPerTurnAround::21 8 0.15% 99.91% # Writes before turning the bus around for reads 228system.physmem.wrPerTurnAround::22 3 0.06% 99.96% # Writes before turning the bus around for reads 229system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads 230system.physmem.wrPerTurnAround::42 1 0.02% 100.00% # Writes before turning the bus around for reads 231system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads 232system.physmem.totQLat 1681541750 # Total ticks spent queuing 233system.physmem.totMemAccLat 4086754250 # Total ticks spent from burst creation until serviced by the DRAM 234system.physmem.totBusLat 641390000 # Total ticks spent in databus transfers 235system.physmem.avgQLat 13108.57 # Average queueing delay per DRAM burst 236system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 237system.physmem.avgMemAccLat 31858.57 # Average memory access latency per DRAM burst 238system.physmem.avgRdBW 144.53 # Average DRAM read bandwidth in MiByte/s 239system.physmem.avgWrBW 97.11 # Average achieved write bandwidth in MiByte/s 240system.physmem.avgRdBWSys 144.54 # Average system read bandwidth in MiByte/s 241system.physmem.avgWrBWSys 97.14 # Average system write bandwidth in MiByte/s 242system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 243system.physmem.busUtil 1.89 # Data bus utilization in percentage 244system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads 245system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes 246system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing 247system.physmem.avgWrQLen 23.24 # Average write queue length when enqueuing 248system.physmem.readRowHits 111837 # Number of row buffer hits during reads 249system.physmem.writeRowHits 63741 # Number of row buffer hits during writes 250system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads 251system.physmem.writeRowHitRate 73.93 # Row buffer hit rate for writes 252system.physmem.avgGap 264816.82 # Average gap between requests 253system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined 254system.physmem_0.actEnergy 153127800 # Energy for activate commands per rank (pJ) 255system.physmem_0.preEnergy 83551875 # Energy for precharge commands per rank (pJ) 256system.physmem_0.readEnergy 510073200 # Energy for read commands per rank (pJ) 257system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ) 258system.physmem_0.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ) 259system.physmem_0.actBackEnergy 11545672905 # Energy for active background per rank (pJ) 260system.physmem_0.preBackEnergy 23952789000 # Energy for precharge background per rank (pJ) 261system.physmem_0.totalEnergy 40234383180 # Total energy per rank (pJ) 262system.physmem_0.averagePower 708.339923 # Core power per rank (mW) 263system.physmem_0.memoryStateTime::IDLE 39720213500 # Time in different power states 264system.physmem_0.memoryStateTime::REF 1896700000 # Time in different power states 265system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 266system.physmem_0.memoryStateTime::ACT 15184054000 # Time in different power states 267system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 268system.physmem_1.actEnergy 140767200 # Energy for activate commands per rank (pJ) 269system.physmem_1.preEnergy 76807500 # Energy for precharge commands per rank (pJ) 270system.physmem_1.readEnergy 490315800 # Energy for read commands per rank (pJ) 271system.physmem_1.writeEnergy 279158400 # Energy for write commands per rank (pJ) 272system.physmem_1.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ) 273system.physmem_1.actBackEnergy 11005773750 # Energy for active background per rank (pJ) 274system.physmem_1.preBackEnergy 24426384750 # Energy for precharge background per rank (pJ) 275system.physmem_1.totalEnergy 40129152600 # Total energy per rank (pJ) 276system.physmem_1.averagePower 706.487303 # Core power per rank (mW) 277system.physmem_1.memoryStateTime::IDLE 40510168000 # Time in different power states 278system.physmem_1.memoryStateTime::REF 1896700000 # Time in different power states 279system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 280system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states 281system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 282system.cpu.branchPred.lookups 14774616 # Number of BP lookups 283system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted 284system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect 285system.cpu.branchPred.BTBLookups 9548677 # Number of BTB lookups 286system.cpu.branchPred.BTBHits 6547888 # Number of BTB hits 287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 288system.cpu.branchPred.BTBHitPct 68.573772 # BTB Hit Percentage 289system.cpu.branchPred.usedRAS 1714315 # Number of times the RAS was used to get a target. 290system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. 291system.cpu.branchPred.indirectLookups 174550 # Number of indirect predictor lookups. 292system.cpu.branchPred.indirectHits 157999 # Number of indirect target hits. 293system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses. 294system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches. 295system.cpu_clk_domain.clock 500 # Clock period in ticks 296system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 305system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 306system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 307system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 308system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 309system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 310system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 314system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 315system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 316system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 317system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 320system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 321system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 322system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 323system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 324system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 325system.cpu.dtb.walker.walks 0 # Table walker walks requested 326system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 333system.cpu.dtb.inst_hits 0 # ITB inst hits 334system.cpu.dtb.inst_misses 0 # ITB inst misses 335system.cpu.dtb.read_hits 0 # DTB read hits 336system.cpu.dtb.read_misses 0 # DTB read misses 337system.cpu.dtb.write_hits 0 # DTB write hits 338system.cpu.dtb.write_misses 0 # DTB write misses 339system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 341system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 342system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 343system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 344system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 345system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.dtb.read_accesses 0 # DTB read accesses 349system.cpu.dtb.write_accesses 0 # DTB write accesses 350system.cpu.dtb.inst_accesses 0 # ITB inst accesses 351system.cpu.dtb.hits 0 # DTB hits 352system.cpu.dtb.misses 0 # DTB misses 353system.cpu.dtb.accesses 0 # DTB accesses 354system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 362system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 363system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 364system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 365system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 366system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 367system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 368system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 372system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 373system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 374system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 375system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 376system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 378system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 379system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 380system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 381system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 382system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 383system.cpu.itb.walker.walks 0 # Table walker walks requested 384system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 385system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 386system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 387system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 388system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 389system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 390system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 391system.cpu.itb.inst_hits 0 # ITB inst hits 392system.cpu.itb.inst_misses 0 # ITB inst misses 393system.cpu.itb.read_hits 0 # DTB read hits 394system.cpu.itb.read_misses 0 # DTB read misses 395system.cpu.itb.write_hits 0 # DTB write hits 396system.cpu.itb.write_misses 0 # DTB write misses 397system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 398system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 399system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 400system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 401system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 402system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 403system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 404system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 405system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 406system.cpu.itb.read_accesses 0 # DTB read accesses 407system.cpu.itb.write_accesses 0 # DTB write accesses 408system.cpu.itb.inst_accesses 0 # ITB inst accesses 409system.cpu.itb.hits 0 # DTB hits 410system.cpu.itb.misses 0 # DTB misses 411system.cpu.itb.accesses 0 # DTB accesses 412system.cpu.workload.num_syscalls 1946 # Number of system calls 413system.cpu.numCycles 113605949 # number of cpu cycles simulated 414system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 415system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 416system.cpu.committedInsts 70915150 # Number of instructions committed 417system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed 418system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit 419system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching 420system.cpu.cpi 1.601998 # CPI: cycles per instruction 421system.cpu.ipc 0.624220 # IPC: instructions per cycle 422system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 423system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction 424system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction 425system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction 426system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction 427system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction 428system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction 429system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction 430system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction 431system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction 432system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction 433system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction 434system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction 435system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction 436system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction 437system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction 438system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction 439system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction 440system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction 441system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction 442system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction 443system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction 444system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction 445system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction 446system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction 447system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction 448system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction 449system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction 450system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction 451system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction 452system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction 453system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction 454system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 455system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 456system.cpu.op_class_0::total 90690106 # Class of committed instruction 457system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked 458system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped 459system.cpu.dcache.tags.replacements 156448 # number of replacements 460system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use 461system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks. 462system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks. 463system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks. 464system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit. 465system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor 466system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy 467system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy 468system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id 469system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id 470system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id 471system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id 472system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id 473system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses 474system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses 475system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits 476system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits 477system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits 478system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits 479system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits 480system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits 481system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits 482system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits 483system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits 484system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits 485system.cpu.dcache.demand_hits::cpu.data 42505075 # number of demand (read+write) hits 486system.cpu.dcache.demand_hits::total 42505075 # number of demand (read+write) hits 487system.cpu.dcache.overall_hits::cpu.data 42588476 # number of overall hits 488system.cpu.dcache.overall_hits::total 42588476 # number of overall hits 489system.cpu.dcache.ReadReq_misses::cpu.data 51661 # number of ReadReq misses 490system.cpu.dcache.ReadReq_misses::total 51661 # number of ReadReq misses 491system.cpu.dcache.WriteReq_misses::cpu.data 207729 # number of WriteReq misses 492system.cpu.dcache.WriteReq_misses::total 207729 # number of WriteReq misses 493system.cpu.dcache.SoftPFReq_misses::cpu.data 44584 # number of SoftPFReq misses 494system.cpu.dcache.SoftPFReq_misses::total 44584 # number of SoftPFReq misses 495system.cpu.dcache.demand_misses::cpu.data 259390 # number of demand (read+write) misses 496system.cpu.dcache.demand_misses::total 259390 # number of demand (read+write) misses 497system.cpu.dcache.overall_misses::cpu.data 303974 # number of overall misses 498system.cpu.dcache.overall_misses::total 303974 # number of overall misses 499system.cpu.dcache.ReadReq_miss_latency::cpu.data 1490194000 # number of ReadReq miss cycles 500system.cpu.dcache.ReadReq_miss_latency::total 1490194000 # number of ReadReq miss cycles 501system.cpu.dcache.WriteReq_miss_latency::cpu.data 16811157000 # number of WriteReq miss cycles 502system.cpu.dcache.WriteReq_miss_latency::total 16811157000 # number of WriteReq miss cycles 503system.cpu.dcache.demand_miss_latency::cpu.data 18301351000 # number of demand (read+write) miss cycles 504system.cpu.dcache.demand_miss_latency::total 18301351000 # number of demand (read+write) miss cycles 505system.cpu.dcache.overall_miss_latency::cpu.data 18301351000 # number of overall miss cycles 506system.cpu.dcache.overall_miss_latency::total 18301351000 # number of overall miss cycles 507system.cpu.dcache.ReadReq_accesses::cpu.data 22914564 # number of ReadReq accesses(hits+misses) 508system.cpu.dcache.ReadReq_accesses::total 22914564 # number of ReadReq accesses(hits+misses) 509system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses) 510system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses) 511system.cpu.dcache.SoftPFReq_accesses::cpu.data 127985 # number of SoftPFReq accesses(hits+misses) 512system.cpu.dcache.SoftPFReq_accesses::total 127985 # number of SoftPFReq accesses(hits+misses) 513system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses) 514system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses) 515system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses) 516system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses) 517system.cpu.dcache.demand_accesses::cpu.data 42764465 # number of demand (read+write) accesses 518system.cpu.dcache.demand_accesses::total 42764465 # number of demand (read+write) accesses 519system.cpu.dcache.overall_accesses::cpu.data 42892450 # number of overall (read+write) accesses 520system.cpu.dcache.overall_accesses::total 42892450 # number of overall (read+write) accesses 521system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002255 # miss rate for ReadReq accesses 522system.cpu.dcache.ReadReq_miss_rate::total 0.002255 # miss rate for ReadReq accesses 523system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses 524system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses 525system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348353 # miss rate for SoftPFReq accesses 526system.cpu.dcache.SoftPFReq_miss_rate::total 0.348353 # miss rate for SoftPFReq accesses 527system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses 528system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses 529system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses 530system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses 531system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28845.628230 # average ReadReq miss latency 532system.cpu.dcache.ReadReq_avg_miss_latency::total 28845.628230 # average ReadReq miss latency 533system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80928.310443 # average WriteReq miss latency 534system.cpu.dcache.WriteReq_avg_miss_latency::total 80928.310443 # average WriteReq miss latency 535system.cpu.dcache.demand_avg_miss_latency::cpu.data 70555.345233 # average overall miss latency 536system.cpu.dcache.demand_avg_miss_latency::total 70555.345233 # average overall miss latency 537system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780 # average overall miss latency 538system.cpu.dcache.overall_avg_miss_latency::total 60206.961780 # average overall miss latency 539system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 540system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 541system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 542system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 543system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 544system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 545system.cpu.dcache.writebacks::writebacks 128389 # number of writebacks 546system.cpu.dcache.writebacks::total 128389 # number of writebacks 547system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22138 # number of ReadReq MSHR hits 548system.cpu.dcache.ReadReq_mshr_hits::total 22138 # number of ReadReq MSHR hits 549system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100695 # number of WriteReq MSHR hits 550system.cpu.dcache.WriteReq_mshr_hits::total 100695 # number of WriteReq MSHR hits 551system.cpu.dcache.demand_mshr_hits::cpu.data 122833 # number of demand (read+write) MSHR hits 552system.cpu.dcache.demand_mshr_hits::total 122833 # number of demand (read+write) MSHR hits 553system.cpu.dcache.overall_mshr_hits::cpu.data 122833 # number of overall MSHR hits 554system.cpu.dcache.overall_mshr_hits::total 122833 # number of overall MSHR hits 555system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29523 # number of ReadReq MSHR misses 556system.cpu.dcache.ReadReq_mshr_misses::total 29523 # number of ReadReq MSHR misses 557system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses 558system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses 559system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23987 # number of SoftPFReq MSHR misses 560system.cpu.dcache.SoftPFReq_mshr_misses::total 23987 # number of SoftPFReq MSHR misses 561system.cpu.dcache.demand_mshr_misses::cpu.data 136557 # number of demand (read+write) MSHR misses 562system.cpu.dcache.demand_mshr_misses::total 136557 # number of demand (read+write) MSHR misses 563system.cpu.dcache.overall_mshr_misses::cpu.data 160544 # number of overall MSHR misses 564system.cpu.dcache.overall_mshr_misses::total 160544 # number of overall MSHR misses 565system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578329500 # number of ReadReq MSHR miss cycles 566system.cpu.dcache.ReadReq_mshr_miss_latency::total 578329500 # number of ReadReq MSHR miss cycles 567system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8490118500 # number of WriteReq MSHR miss cycles 568system.cpu.dcache.WriteReq_mshr_miss_latency::total 8490118500 # number of WriteReq MSHR miss cycles 569system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713467500 # number of SoftPFReq MSHR miss cycles 570system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713467500 # number of SoftPFReq MSHR miss cycles 571system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9068448000 # number of demand (read+write) MSHR miss cycles 572system.cpu.dcache.demand_mshr_miss_latency::total 9068448000 # number of demand (read+write) MSHR miss cycles 573system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10781915500 # number of overall MSHR miss cycles 574system.cpu.dcache.overall_mshr_miss_latency::total 10781915500 # number of overall MSHR miss cycles 575system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses 576system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses 577system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses 578system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses 579system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187420 # mshr miss rate for SoftPFReq accesses 580system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187420 # mshr miss rate for SoftPFReq accesses 581system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses 582system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses 583system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003743 # mshr miss rate for overall accesses 584system.cpu.dcache.overall_mshr_miss_rate::total 0.003743 # mshr miss rate for overall accesses 585system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19589.116960 # average ReadReq mshr miss latency 586system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19589.116960 # average ReadReq mshr miss latency 587system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency 588system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency 589system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency 590system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency 591system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency 592system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency 593system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency 594system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency 595system.cpu.icache.tags.replacements 43497 # number of replacements 596system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use 597system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks. 598system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks. 599system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks. 600system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 601system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor 602system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy 603system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy 604system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id 605system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id 606system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id 607system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id 608system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id 609system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id 610system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses 611system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses 612system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits 613system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits 614system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits 615system.cpu.icache.demand_hits::total 24844377 # number of demand (read+write) hits 616system.cpu.icache.overall_hits::cpu.inst 24844377 # number of overall hits 617system.cpu.icache.overall_hits::total 24844377 # number of overall hits 618system.cpu.icache.ReadReq_misses::cpu.inst 45540 # number of ReadReq misses 619system.cpu.icache.ReadReq_misses::total 45540 # number of ReadReq misses 620system.cpu.icache.demand_misses::cpu.inst 45540 # number of demand (read+write) misses 621system.cpu.icache.demand_misses::total 45540 # number of demand (read+write) misses 622system.cpu.icache.overall_misses::cpu.inst 45540 # number of overall misses 623system.cpu.icache.overall_misses::total 45540 # number of overall misses 624system.cpu.icache.ReadReq_miss_latency::cpu.inst 905103000 # number of ReadReq miss cycles 625system.cpu.icache.ReadReq_miss_latency::total 905103000 # number of ReadReq miss cycles 626system.cpu.icache.demand_miss_latency::cpu.inst 905103000 # number of demand (read+write) miss cycles 627system.cpu.icache.demand_miss_latency::total 905103000 # number of demand (read+write) miss cycles 628system.cpu.icache.overall_miss_latency::cpu.inst 905103000 # number of overall miss cycles 629system.cpu.icache.overall_miss_latency::total 905103000 # number of overall miss cycles 630system.cpu.icache.ReadReq_accesses::cpu.inst 24889917 # number of ReadReq accesses(hits+misses) 631system.cpu.icache.ReadReq_accesses::total 24889917 # number of ReadReq accesses(hits+misses) 632system.cpu.icache.demand_accesses::cpu.inst 24889917 # number of demand (read+write) accesses 633system.cpu.icache.demand_accesses::total 24889917 # number of demand (read+write) accesses 634system.cpu.icache.overall_accesses::cpu.inst 24889917 # number of overall (read+write) accesses 635system.cpu.icache.overall_accesses::total 24889917 # number of overall (read+write) accesses 636system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001830 # miss rate for ReadReq accesses 637system.cpu.icache.ReadReq_miss_rate::total 0.001830 # miss rate for ReadReq accesses 638system.cpu.icache.demand_miss_rate::cpu.inst 0.001830 # miss rate for demand accesses 639system.cpu.icache.demand_miss_rate::total 0.001830 # miss rate for demand accesses 640system.cpu.icache.overall_miss_rate::cpu.inst 0.001830 # miss rate for overall accesses 641system.cpu.icache.overall_miss_rate::total 0.001830 # miss rate for overall accesses 642system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19874.901186 # average ReadReq miss latency 643system.cpu.icache.ReadReq_avg_miss_latency::total 19874.901186 # average ReadReq miss latency 644system.cpu.icache.demand_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency 645system.cpu.icache.demand_avg_miss_latency::total 19874.901186 # average overall miss latency 646system.cpu.icache.overall_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency 647system.cpu.icache.overall_avg_miss_latency::total 19874.901186 # average overall miss latency 648system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 649system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 650system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 651system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 652system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 653system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 654system.cpu.icache.writebacks::writebacks 43497 # number of writebacks 655system.cpu.icache.writebacks::total 43497 # number of writebacks 656system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45540 # number of ReadReq MSHR misses 657system.cpu.icache.ReadReq_mshr_misses::total 45540 # number of ReadReq MSHR misses 658system.cpu.icache.demand_mshr_misses::cpu.inst 45540 # number of demand (read+write) MSHR misses 659system.cpu.icache.demand_mshr_misses::total 45540 # number of demand (read+write) MSHR misses 660system.cpu.icache.overall_mshr_misses::cpu.inst 45540 # number of overall MSHR misses 661system.cpu.icache.overall_mshr_misses::total 45540 # number of overall MSHR misses 662system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 859564000 # number of ReadReq MSHR miss cycles 663system.cpu.icache.ReadReq_mshr_miss_latency::total 859564000 # number of ReadReq MSHR miss cycles 664system.cpu.icache.demand_mshr_miss_latency::cpu.inst 859564000 # number of demand (read+write) MSHR miss cycles 665system.cpu.icache.demand_mshr_miss_latency::total 859564000 # number of demand (read+write) MSHR miss cycles 666system.cpu.icache.overall_mshr_miss_latency::cpu.inst 859564000 # number of overall MSHR miss cycles 667system.cpu.icache.overall_mshr_miss_latency::total 859564000 # number of overall MSHR miss cycles 668system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for ReadReq accesses 669system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001830 # mshr miss rate for ReadReq accesses 670system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for demand accesses 671system.cpu.icache.demand_mshr_miss_rate::total 0.001830 # mshr miss rate for demand accesses 672system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses 673system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency 675system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency 677system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency 679system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency 680system.cpu.l2cache.tags.replacements 96391 # number of replacements 681system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use 682system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks. 683system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks. 684system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks. 685system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 686system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor 687system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor 688system.cpu.l2cache.tags.occ_blocks::cpu.data 1656.072920 # Average occupied blocks per requestor 689system.cpu.l2cache.tags.occ_percent::writebacks 0.817316 # Average percentage of cache occupancy 690system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043735 # Average percentage of cache occupancy 691system.cpu.l2cache.tags.occ_percent::cpu.data 0.050539 # Average percentage of cache occupancy 692system.cpu.l2cache.tags.occ_percent::total 0.911590 # Average percentage of cache occupancy 693system.cpu.l2cache.tags.occ_task_id_blocks::1024 31151 # Occupied blocks per task id 694system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id 695system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id 696system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12725 # Occupied blocks per task id 697system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15781 # Occupied blocks per task id 698system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 # Occupied blocks per task id 699system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id 700system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses 701system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses 702system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits 703system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits 704system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits 705system.cpu.l2cache.WritebackClean_hits::total 39908 # number of WritebackClean hits 706system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits 707system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits 708system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41065 # number of ReadCleanReq hits 709system.cpu.l2cache.ReadCleanReq_hits::total 41065 # number of ReadCleanReq hits 710system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31907 # number of ReadSharedReq hits 711system.cpu.l2cache.ReadSharedReq_hits::total 31907 # number of ReadSharedReq hits 712system.cpu.l2cache.demand_hits::cpu.inst 41065 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits 714system.cpu.l2cache.demand_hits::total 77724 # number of demand (read+write) hits 715system.cpu.l2cache.overall_hits::cpu.inst 41065 # number of overall hits 716system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits 717system.cpu.l2cache.overall_hits::total 77724 # number of overall hits 718system.cpu.l2cache.ReadExReq_misses::cpu.data 102282 # number of ReadExReq misses 719system.cpu.l2cache.ReadExReq_misses::total 102282 # number of ReadExReq misses 720system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4475 # number of ReadCleanReq misses 721system.cpu.l2cache.ReadCleanReq_misses::total 4475 # number of ReadCleanReq misses 722system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21603 # number of ReadSharedReq misses 723system.cpu.l2cache.ReadSharedReq_misses::total 21603 # number of ReadSharedReq misses 724system.cpu.l2cache.demand_misses::cpu.inst 4475 # number of demand (read+write) misses 725system.cpu.l2cache.demand_misses::cpu.data 123885 # number of demand (read+write) misses 726system.cpu.l2cache.demand_misses::total 128360 # number of demand (read+write) misses 727system.cpu.l2cache.overall_misses::cpu.inst 4475 # number of overall misses 728system.cpu.l2cache.overall_misses::cpu.data 123885 # number of overall misses 729system.cpu.l2cache.overall_misses::total 128360 # number of overall misses 730system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8279623500 # number of ReadExReq miss cycles 731system.cpu.l2cache.ReadExReq_miss_latency::total 8279623500 # number of ReadExReq miss cycles 732system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356201500 # number of ReadCleanReq miss cycles 733system.cpu.l2cache.ReadCleanReq_miss_latency::total 356201500 # number of ReadCleanReq miss cycles 734system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1872087500 # number of ReadSharedReq miss cycles 735system.cpu.l2cache.ReadSharedReq_miss_latency::total 1872087500 # number of ReadSharedReq miss cycles 736system.cpu.l2cache.demand_miss_latency::cpu.inst 356201500 # number of demand (read+write) miss cycles 737system.cpu.l2cache.demand_miss_latency::cpu.data 10151711000 # number of demand (read+write) miss cycles 738system.cpu.l2cache.demand_miss_latency::total 10507912500 # number of demand (read+write) miss cycles 739system.cpu.l2cache.overall_miss_latency::cpu.inst 356201500 # number of overall miss cycles 740system.cpu.l2cache.overall_miss_latency::cpu.data 10151711000 # number of overall miss cycles 741system.cpu.l2cache.overall_miss_latency::total 10507912500 # number of overall miss cycles 742system.cpu.l2cache.WritebackDirty_accesses::writebacks 128389 # number of WritebackDirty accesses(hits+misses) 743system.cpu.l2cache.WritebackDirty_accesses::total 128389 # number of WritebackDirty accesses(hits+misses) 744system.cpu.l2cache.WritebackClean_accesses::writebacks 39908 # number of WritebackClean accesses(hits+misses) 745system.cpu.l2cache.WritebackClean_accesses::total 39908 # number of WritebackClean accesses(hits+misses) 746system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses) 747system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses) 748system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45540 # number of ReadCleanReq accesses(hits+misses) 749system.cpu.l2cache.ReadCleanReq_accesses::total 45540 # number of ReadCleanReq accesses(hits+misses) 750system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses) 751system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses) 752system.cpu.l2cache.demand_accesses::cpu.inst 45540 # number of demand (read+write) accesses 753system.cpu.l2cache.demand_accesses::cpu.data 160544 # number of demand (read+write) accesses 754system.cpu.l2cache.demand_accesses::total 206084 # number of demand (read+write) accesses 755system.cpu.l2cache.overall_accesses::cpu.inst 45540 # number of overall (read+write) accesses 756system.cpu.l2cache.overall_accesses::cpu.data 160544 # number of overall (read+write) accesses 757system.cpu.l2cache.overall_accesses::total 206084 # number of overall (read+write) accesses 758system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955603 # miss rate for ReadExReq accesses 759system.cpu.l2cache.ReadExReq_miss_rate::total 0.955603 # miss rate for ReadExReq accesses 760system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098265 # miss rate for ReadCleanReq accesses 761system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098265 # miss rate for ReadCleanReq accesses 762system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403719 # miss rate for ReadSharedReq accesses 763system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403719 # miss rate for ReadSharedReq accesses 764system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098265 # miss rate for demand accesses 765system.cpu.l2cache.demand_miss_rate::cpu.data 0.771658 # miss rate for demand accesses 766system.cpu.l2cache.demand_miss_rate::total 0.622853 # miss rate for demand accesses 767system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098265 # miss rate for overall accesses 768system.cpu.l2cache.overall_miss_rate::cpu.data 0.771658 # miss rate for overall accesses 769system.cpu.l2cache.overall_miss_rate::total 0.622853 # miss rate for overall accesses 770system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80948.979293 # average ReadExReq miss latency 771system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80948.979293 # average ReadExReq miss latency 772system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79598.100559 # average ReadCleanReq miss latency 773system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79598.100559 # average ReadCleanReq miss latency 774system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86658.681665 # average ReadSharedReq miss latency 775system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86658.681665 # average ReadSharedReq miss latency 776system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency 777system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency 778system.cpu.l2cache.demand_avg_miss_latency::total 81862.827205 # average overall miss latency 779system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency 780system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency 781system.cpu.l2cache.overall_avg_miss_latency::total 81862.827205 # average overall miss latency 782system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 785system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 786system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 787system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 788system.cpu.l2cache.writebacks::writebacks 86215 # number of writebacks 789system.cpu.l2cache.writebacks::total 86215 # number of writebacks 790system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits 791system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 792system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits 793system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits 794system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits 795system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits 796system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits 797system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits 798system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits 799system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits 800system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses 801system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses 802system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102282 # number of ReadExReq MSHR misses 803system.cpu.l2cache.ReadExReq_mshr_misses::total 102282 # number of ReadExReq MSHR misses 804system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4462 # number of ReadCleanReq MSHR misses 805system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4462 # number of ReadCleanReq MSHR misses 806system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21541 # number of ReadSharedReq MSHR misses 807system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21541 # number of ReadSharedReq MSHR misses 808system.cpu.l2cache.demand_mshr_misses::cpu.inst 4462 # number of demand (read+write) MSHR misses 809system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses 810system.cpu.l2cache.demand_mshr_misses::total 128285 # number of demand (read+write) MSHR misses 811system.cpu.l2cache.overall_mshr_misses::cpu.inst 4462 # number of overall MSHR misses 812system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses 813system.cpu.l2cache.overall_mshr_misses::total 128285 # number of overall MSHR misses 814system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7256803500 # number of ReadExReq MSHR miss cycles 815system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7256803500 # number of ReadExReq MSHR miss cycles 816system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310457000 # number of ReadCleanReq MSHR miss cycles 817system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310457000 # number of ReadCleanReq MSHR miss cycles 818system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1652012000 # number of ReadSharedReq MSHR miss cycles 819system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1652012000 # number of ReadSharedReq MSHR miss cycles 820system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310457000 # number of demand (read+write) MSHR miss cycles 821system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8908815500 # number of demand (read+write) MSHR miss cycles 822system.cpu.l2cache.demand_mshr_miss_latency::total 9219272500 # number of demand (read+write) MSHR miss cycles 823system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310457000 # number of overall MSHR miss cycles 824system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8908815500 # number of overall MSHR miss cycles 825system.cpu.l2cache.overall_mshr_miss_latency::total 9219272500 # number of overall MSHR miss cycles 826system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses 827system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses 828system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955603 # mshr miss rate for ReadExReq accesses 829system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955603 # mshr miss rate for ReadExReq accesses 830system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for ReadCleanReq accesses 831system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097980 # mshr miss rate for ReadCleanReq accesses 832system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402560 # mshr miss rate for ReadSharedReq accesses 833system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402560 # mshr miss rate for ReadSharedReq accesses 834system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for demand accesses 835system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for demand accesses 836system.cpu.l2cache.demand_mshr_miss_rate::total 0.622489 # mshr miss rate for demand accesses 837system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for overall accesses 838system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for overall accesses 839system.cpu.l2cache.overall_mshr_miss_rate::total 0.622489 # mshr miss rate for overall accesses 840system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70948.979293 # average ReadExReq mshr miss latency 841system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70948.979293 # average ReadExReq mshr miss latency 842system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69577.991932 # average ReadCleanReq mshr miss latency 843system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69577.991932 # average ReadCleanReq mshr miss latency 844system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76691.518500 # average ReadSharedReq mshr miss latency 845system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76691.518500 # average ReadSharedReq mshr miss latency 846system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency 847system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency 848system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency 849system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency 850system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency 851system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency 852system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter. 853system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data. 854system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 855system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter. 856system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 857system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 858system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution 859system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution 860system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution 861system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution 862system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution 863system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution 864system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution 865system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution 866system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134576 # Packet count per connected master and slave (bytes) 867system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes) 868system.cpu.toL2Bus.pkt_count::total 612112 # Packet count per connected master and slave (bytes) 869system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5698304 # Cumulative packet size per connected master and slave (bytes) 870system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491712 # Cumulative packet size per connected master and slave (bytes) 871system.cpu.toL2Bus.pkt_size::total 24190016 # Cumulative packet size per connected master and slave (bytes) 872system.cpu.toL2Bus.snoops 96391 # Total snoops (count) 873system.cpu.toL2Bus.snoop_fanout::samples 302475 # Request fanout histogram 874system.cpu.toL2Bus.snoop_fanout::mean 0.037210 # Request fanout histogram 875system.cpu.toL2Bus.snoop_fanout::stdev 0.189781 # Request fanout histogram 876system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 877system.cpu.toL2Bus.snoop_fanout::0 291249 96.29% 96.29% # Request fanout histogram 878system.cpu.toL2Bus.snoop_fanout::1 11197 3.70% 99.99% # Request fanout histogram 879system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram 880system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 881system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 882system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 883system.cpu.toL2Bus.snoop_fanout::total 302475 # Request fanout histogram 884system.cpu.toL2Bus.reqLayer0.occupancy 374900500 # Layer occupancy (ticks) 885system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 886system.cpu.toL2Bus.respLayer0.occupancy 68328959 # Layer occupancy (ticks) 887system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) 888system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks) 889system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%) 890system.membus.trans_dist::ReadResp 26002 # Transaction distribution 891system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution 892system.membus.trans_dist::CleanEvict 6912 # Transaction distribution 893system.membus.trans_dist::ReadExReq 102282 # Transaction distribution 894system.membus.trans_dist::ReadExResp 102282 # Transaction distribution 895system.membus.trans_dist::ReadSharedReq 26002 # Transaction distribution 896system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349695 # Packet count per connected master and slave (bytes) 897system.membus.pkt_count::total 349695 # Packet count per connected master and slave (bytes) 898system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727936 # Cumulative packet size per connected master and slave (bytes) 899system.membus.pkt_size::total 13727936 # Cumulative packet size per connected master and slave (bytes) 900system.membus.snoops 0 # Total snoops (count) 901system.membus.snoop_fanout::samples 221411 # Request fanout histogram 902system.membus.snoop_fanout::mean 0 # Request fanout histogram 903system.membus.snoop_fanout::stdev 0 # Request fanout histogram 904system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 905system.membus.snoop_fanout::0 221411 100.00% 100.00% # Request fanout histogram 906system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 907system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 908system.membus.snoop_fanout::min_value 0 # Request fanout histogram 909system.membus.snoop_fanout::max_value 0 # Request fanout histogram 910system.membus.snoop_fanout::total 221411 # Request fanout histogram 911system.membus.reqLayer0.occupancy 590704500 # Layer occupancy (ticks) 912system.membus.reqLayer0.utilization 1.0 # Layer utilization (%) 913system.membus.respLayer1.occupancy 676958000 # Layer occupancy (ticks) 914system.membus.respLayer1.utilization 1.2 # Layer utilization (%) 915 916---------- End Simulation Statistics ----------

stats.txt (11456:c0fb4435b80f)

stats.txt (11502:e273e86a873d)

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.056803 # Number of seconds simulated
4sim_ticks 56802974500 # Number of ticks simulated
5final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 222036 # Simulator instruction rate (inst/s)
8host_op_rate 283951 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 177850276 # Simulator tick rate (ticks/s)
10host_mem_usage 280068 # Number of bytes of host memory used
11host_seconds 319.39 # Real time elapsed on the host
12sim_insts 70915150 # Number of instructions simulated
13sim_ops 90690106 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory
18system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 285504 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::writebacks 5517760 # Number of bytes written to this memory
22system.physmem.bytes_written::total 5517760 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 4461 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 123823 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 128284 # Number of read requests responded to by this memory
26system.physmem.num_writes::writebacks 86215 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 86215 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 5026216 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 139511567 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 144537783 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 5026216 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 5026216 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::writebacks 97138575 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 97138575 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::writebacks 97138575 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.inst 5026216 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::cpu.data 139511567 # Total bandwidth to/from this memory (bytes/s)
38system.physmem.bw_total::total 241676358 # Total bandwidth to/from this memory (bytes/s)
39system.physmem.readReqs 128284 # Number of read requests accepted
40system.physmem.writeReqs 86215 # Number of write requests accepted
41system.physmem.readBursts 128284 # Number of DRAM read bursts, including those serviced by the write queue
42system.physmem.writeBursts 86215 # Number of DRAM write bursts, including those merged in the write queue
43system.physmem.bytesReadDRAM 8209792 # Total number of bytes read from DRAM
44system.physmem.bytesReadWrQ 384 # Total number of bytes read from write queue
45system.physmem.bytesWritten 5515904 # Total number of bytes written to DRAM
46system.physmem.bytesReadSys 8210176 # Total read bytes from the system interface side
47system.physmem.bytesWrittenSys 5517760 # Total written bytes from the system interface side
48system.physmem.servicedByWrQ 6 # Number of DRAM read bursts serviced by the write queue
49system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
50system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
51system.physmem.perBankRdBursts::0 8062 # Per bank write bursts
52system.physmem.perBankRdBursts::1 8315 # Per bank write bursts
53system.physmem.perBankRdBursts::2 8233 # Per bank write bursts
54system.physmem.perBankRdBursts::3 8142 # Per bank write bursts
55system.physmem.perBankRdBursts::4 8284 # Per bank write bursts
56system.physmem.perBankRdBursts::5 8403 # Per bank write bursts
57system.physmem.perBankRdBursts::6 8055 # Per bank write bursts
58system.physmem.perBankRdBursts::7 7916 # Per bank write bursts
59system.physmem.perBankRdBursts::8 8035 # Per bank write bursts
60system.physmem.perBankRdBursts::9 7587 # Per bank write bursts
61system.physmem.perBankRdBursts::10 7763 # Per bank write bursts
62system.physmem.perBankRdBursts::11 7815 # Per bank write bursts
63system.physmem.perBankRdBursts::12 7871 # Per bank write bursts
64system.physmem.perBankRdBursts::13 7867 # Per bank write bursts
65system.physmem.perBankRdBursts::14 7968 # Per bank write bursts
66system.physmem.perBankRdBursts::15 7962 # Per bank write bursts
67system.physmem.perBankWrBursts::0 5395 # Per bank write bursts
68system.physmem.perBankWrBursts::1 5541 # Per bank write bursts
69system.physmem.perBankWrBursts::2 5468 # Per bank write bursts
70system.physmem.perBankWrBursts::3 5336 # Per bank write bursts
71system.physmem.perBankWrBursts::4 5366 # Per bank write bursts
72system.physmem.perBankWrBursts::5 5560 # Per bank write bursts
73system.physmem.perBankWrBursts::6 5257 # Per bank write bursts
74system.physmem.perBankWrBursts::7 5179 # Per bank write bursts
75system.physmem.perBankWrBursts::8 5154 # Per bank write bursts
76system.physmem.perBankWrBursts::9 5105 # Per bank write bursts
77system.physmem.perBankWrBursts::10 5292 # Per bank write bursts
78system.physmem.perBankWrBursts::11 5270 # Per bank write bursts
79system.physmem.perBankWrBursts::12 5531 # Per bank write bursts
80system.physmem.perBankWrBursts::13 5597 # Per bank write bursts
81system.physmem.perBankWrBursts::14 5703 # Per bank write bursts
82system.physmem.perBankWrBursts::15 5432 # Per bank write bursts
83system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
84system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
85system.physmem.totGap 56802942500 # Total gap between requests
86system.physmem.readPktSize::0 0 # Read request sizes (log2)
87system.physmem.readPktSize::1 0 # Read request sizes (log2)
88system.physmem.readPktSize::2 0 # Read request sizes (log2)
89system.physmem.readPktSize::3 0 # Read request sizes (log2)
90system.physmem.readPktSize::4 0 # Read request sizes (log2)
91system.physmem.readPktSize::5 0 # Read request sizes (log2)
92system.physmem.readPktSize::6 128284 # Read request sizes (log2)
93system.physmem.writePktSize::0 0 # Write request sizes (log2)
94system.physmem.writePktSize::1 0 # Write request sizes (log2)
95system.physmem.writePktSize::2 0 # Write request sizes (log2)
96system.physmem.writePktSize::3 0 # Write request sizes (log2)
97system.physmem.writePktSize::4 0 # Write request sizes (log2)
98system.physmem.writePktSize::5 0 # Write request sizes (log2)
99system.physmem.writePktSize::6 86215 # Write request sizes (log2)
100system.physmem.rdQLenPdf::0 116125 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::1 12132 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
125system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
126system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
127system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
128system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
129system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
130system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
131system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
132system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::15 631 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::16 643 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::17 4122 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::18 5183 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::19 5277 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::20 5318 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::21 5309 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::22 5314 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::23 5323 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::24 5321 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::25 5353 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::26 5383 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::27 5464 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::28 5436 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::29 5495 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::30 5851 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::31 5447 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::32 5305 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::33 15 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::34 2 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::35 1 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::36 1 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::37 1 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::38 1 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::41 1 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::42 1 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
189system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
190system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
191system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
192system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
193system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
194system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
195system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
196system.physmem.bytesPerActivate::samples 38880 # Bytes accessed per row activation
197system.physmem.bytesPerActivate::mean 352.990947 # Bytes accessed per row activation
198system.physmem.bytesPerActivate::gmean 214.489872 # Bytes accessed per row activation
199system.physmem.bytesPerActivate::stdev 335.589979 # Bytes accessed per row activation
200system.physmem.bytesPerActivate::0-127 12269 31.56% 31.56% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::128-255 8336 21.44% 53.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::256-383 4191 10.78% 63.78% # Bytes accessed per row activation
203system.physmem.bytesPerActivate::384-511 2845 7.32% 71.09% # Bytes accessed per row activation
204system.physmem.bytesPerActivate::512-639 2490 6.40% 77.50% # Bytes accessed per row activation
205system.physmem.bytesPerActivate::640-767 1681 4.32% 81.82% # Bytes accessed per row activation
206system.physmem.bytesPerActivate::768-895 1302 3.35% 85.17% # Bytes accessed per row activation
207system.physmem.bytesPerActivate::896-1023 1149 2.96% 88.12% # Bytes accessed per row activation
208system.physmem.bytesPerActivate::1024-1151 4617 11.88% 100.00% # Bytes accessed per row activation
209system.physmem.bytesPerActivate::total 38880 # Bytes accessed per row activation
210system.physmem.rdPerTurnAround::samples 5294 # Reads before turning the bus around for writes
211system.physmem.rdPerTurnAround::mean 24.227616 # Reads before turning the bus around for writes
212system.physmem.rdPerTurnAround::stdev 352.423208 # Reads before turning the bus around for writes
213system.physmem.rdPerTurnAround::0-1023 5291 99.94% 99.94% # Reads before turning the bus around for writes
214system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
215system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes
216system.physmem.rdPerTurnAround::24576-25599 1 0.02% 100.00% # Reads before turning the bus around for writes
217system.physmem.rdPerTurnAround::total 5294 # Reads before turning the bus around for writes
218system.physmem.wrPerTurnAround::samples 5294 # Writes before turning the bus around for reads
219system.physmem.wrPerTurnAround::mean 16.279940 # Writes before turning the bus around for reads
220system.physmem.wrPerTurnAround::gmean 16.260845 # Writes before turning the bus around for reads
221system.physmem.wrPerTurnAround::stdev 0.856304 # Writes before turning the bus around for reads
222system.physmem.wrPerTurnAround::16 4659 88.01% 88.01% # Writes before turning the bus around for reads
223system.physmem.wrPerTurnAround::17 4 0.08% 88.08% # Writes before turning the bus around for reads
224system.physmem.wrPerTurnAround::18 483 9.12% 97.20% # Writes before turning the bus around for reads
225system.physmem.wrPerTurnAround::19 119 2.25% 99.45% # Writes before turning the bus around for reads
226system.physmem.wrPerTurnAround::20 16 0.30% 99.75% # Writes before turning the bus around for reads
227system.physmem.wrPerTurnAround::21 8 0.15% 99.91% # Writes before turning the bus around for reads
228system.physmem.wrPerTurnAround::22 3 0.06% 99.96% # Writes before turning the bus around for reads
229system.physmem.wrPerTurnAround::23 1 0.02% 99.98% # Writes before turning the bus around for reads
230system.physmem.wrPerTurnAround::42 1 0.02% 100.00% # Writes before turning the bus around for reads
231system.physmem.wrPerTurnAround::total 5294 # Writes before turning the bus around for reads
232system.physmem.totQLat 1681541750 # Total ticks spent queuing
233system.physmem.totMemAccLat 4086754250 # Total ticks spent from burst creation until serviced by the DRAM
234system.physmem.totBusLat 641390000 # Total ticks spent in databus transfers
235system.physmem.avgQLat 13108.57 # Average queueing delay per DRAM burst
236system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
237system.physmem.avgMemAccLat 31858.57 # Average memory access latency per DRAM burst
238system.physmem.avgRdBW 144.53 # Average DRAM read bandwidth in MiByte/s
239system.physmem.avgWrBW 97.11 # Average achieved write bandwidth in MiByte/s
240system.physmem.avgRdBWSys 144.54 # Average system read bandwidth in MiByte/s
241system.physmem.avgWrBWSys 97.14 # Average system write bandwidth in MiByte/s
242system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
243system.physmem.busUtil 1.89 # Data bus utilization in percentage
244system.physmem.busUtilRead 1.13 # Data bus utilization in percentage for reads
245system.physmem.busUtilWrite 0.76 # Data bus utilization in percentage for writes
246system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
247system.physmem.avgWrQLen 23.24 # Average write queue length when enqueuing
248system.physmem.readRowHits 111837 # Number of row buffer hits during reads
249system.physmem.writeRowHits 63741 # Number of row buffer hits during writes
250system.physmem.readRowHitRate 87.18 # Row buffer hit rate for reads
251system.physmem.writeRowHitRate 73.93 # Row buffer hit rate for writes
252system.physmem.avgGap 264816.82 # Average gap between requests
253system.physmem.pageHitRate 81.86 # Row buffer hit rate, read and write combined
254system.physmem_0.actEnergy 153127800 # Energy for activate commands per rank (pJ)
255system.physmem_0.preEnergy 83551875 # Energy for precharge commands per rank (pJ)
256system.physmem_0.readEnergy 510073200 # Energy for read commands per rank (pJ)
257system.physmem_0.writeEnergy 279223200 # Energy for write commands per rank (pJ)
258system.physmem_0.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ)
259system.physmem_0.actBackEnergy 11545672905 # Energy for active background per rank (pJ)
260system.physmem_0.preBackEnergy 23952789000 # Energy for precharge background per rank (pJ)
261system.physmem_0.totalEnergy 40234383180 # Total energy per rank (pJ)
262system.physmem_0.averagePower 708.339923 # Core power per rank (mW)
263system.physmem_0.memoryStateTime::IDLE 39720213500 # Time in different power states
264system.physmem_0.memoryStateTime::REF 1896700000 # Time in different power states
265system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
266system.physmem_0.memoryStateTime::ACT 15184054000 # Time in different power states
267system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
268system.physmem_1.actEnergy 140767200 # Energy for activate commands per rank (pJ)
269system.physmem_1.preEnergy 76807500 # Energy for precharge commands per rank (pJ)
270system.physmem_1.readEnergy 490315800 # Energy for read commands per rank (pJ)
271system.physmem_1.writeEnergy 279158400 # Energy for write commands per rank (pJ)
272system.physmem_1.refreshEnergy 3709945200 # Energy for refresh commands per rank (pJ)
273system.physmem_1.actBackEnergy 11005773750 # Energy for active background per rank (pJ)
274system.physmem_1.preBackEnergy 24426384750 # Energy for precharge background per rank (pJ)
275system.physmem_1.totalEnergy 40129152600 # Total energy per rank (pJ)
276system.physmem_1.averagePower 706.487303 # Core power per rank (mW)
277system.physmem_1.memoryStateTime::IDLE 40510168000 # Time in different power states
278system.physmem_1.memoryStateTime::REF 1896700000 # Time in different power states
279system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
280system.physmem_1.memoryStateTime::ACT 14394586000 # Time in different power states
281system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
282system.cpu.branchPred.lookups 14774616 # Number of BP lookups
283system.cpu.branchPred.condPredicted 9890616 # Number of conditional branches predicted
284system.cpu.branchPred.condIncorrect 339334 # Number of conditional branches incorrect
285system.cpu.branchPred.BTBLookups 9548677 # Number of BTB lookups
286system.cpu.branchPred.BTBHits 6547888 # Number of BTB hits
287system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
288system.cpu.branchPred.BTBHitPct 68.573772 # BTB Hit Percentage
289system.cpu.branchPred.usedRAS 1714315 # Number of times the RAS was used to get a target.
290system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions.
291system.cpu.branchPred.indirectLookups 174550 # Number of indirect predictor lookups.
292system.cpu.branchPred.indirectHits 157999 # Number of indirect target hits.
293system.cpu.branchPred.indirectMisses 16551 # Number of indirect misses.
294system.cpu.branchPredindirectMispredicted 24800 # Number of mispredicted indirect branches.
295system.cpu_clk_domain.clock 500 # Clock period in ticks
296system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
297system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
298system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
299system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
300system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
301system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
302system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
303system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
304system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
305system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
306system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
307system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
308system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
309system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
310system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
311system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
312system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
313system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
314system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
315system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
316system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
317system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
318system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
319system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
320system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
321system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
322system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
323system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
324system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
325system.cpu.dtb.walker.walks 0 # Table walker walks requested
326system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
327system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
328system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
329system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
330system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
331system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
332system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
333system.cpu.dtb.inst_hits 0 # ITB inst hits
334system.cpu.dtb.inst_misses 0 # ITB inst misses
335system.cpu.dtb.read_hits 0 # DTB read hits
336system.cpu.dtb.read_misses 0 # DTB read misses
337system.cpu.dtb.write_hits 0 # DTB write hits
338system.cpu.dtb.write_misses 0 # DTB write misses
339system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
340system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
341system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
342system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
343system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
344system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
345system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
346system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
347system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
348system.cpu.dtb.read_accesses 0 # DTB read accesses
349system.cpu.dtb.write_accesses 0 # DTB write accesses
350system.cpu.dtb.inst_accesses 0 # ITB inst accesses
351system.cpu.dtb.hits 0 # DTB hits
352system.cpu.dtb.misses 0 # DTB misses
353system.cpu.dtb.accesses 0 # DTB accesses
354system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
355system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
356system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
357system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
358system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
359system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
360system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
361system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
362system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
363system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
364system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
365system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
366system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
367system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
368system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
369system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
370system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
371system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
372system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
373system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
374system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
375system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
376system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
377system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
378system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
379system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
380system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
381system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
382system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
383system.cpu.itb.walker.walks 0 # Table walker walks requested
384system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
385system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
386system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
387system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
388system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
389system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
390system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
391system.cpu.itb.inst_hits 0 # ITB inst hits
392system.cpu.itb.inst_misses 0 # ITB inst misses
393system.cpu.itb.read_hits 0 # DTB read hits
394system.cpu.itb.read_misses 0 # DTB read misses
395system.cpu.itb.write_hits 0 # DTB write hits
396system.cpu.itb.write_misses 0 # DTB write misses
397system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
398system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
399system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
400system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
401system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
402system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
403system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
404system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
405system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
406system.cpu.itb.read_accesses 0 # DTB read accesses
407system.cpu.itb.write_accesses 0 # DTB write accesses
408system.cpu.itb.inst_accesses 0 # ITB inst accesses
409system.cpu.itb.hits 0 # DTB hits
410system.cpu.itb.misses 0 # DTB misses
411system.cpu.itb.accesses 0 # DTB accesses
412system.cpu.workload.num_syscalls 1946 # Number of system calls
413system.cpu.numCycles 113605949 # number of cpu cycles simulated
414system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
415system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
416system.cpu.committedInsts 70915150 # Number of instructions committed
417system.cpu.committedOps 90690106 # Number of ops (including micro ops) committed
418system.cpu.discardedOps 1137741 # Number of ops (including micro ops) which were discarded before commit
419system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
420system.cpu.cpi 1.601998 # CPI: cycles per instruction
421system.cpu.ipc 0.624220 # IPC: instructions per cycle
422system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
423system.cpu.op_class_0::IntAlu 47187979 52.03% 52.03% # Class of committed instruction
424system.cpu.op_class_0::IntMult 80119 0.09% 52.12% # Class of committed instruction
425system.cpu.op_class_0::IntDiv 0 0.00% 52.12% # Class of committed instruction
426system.cpu.op_class_0::FloatAdd 0 0.00% 52.12% # Class of committed instruction
427system.cpu.op_class_0::FloatCmp 0 0.00% 52.12% # Class of committed instruction
428system.cpu.op_class_0::FloatCvt 0 0.00% 52.12% # Class of committed instruction
429system.cpu.op_class_0::FloatMult 0 0.00% 52.12% # Class of committed instruction
430system.cpu.op_class_0::FloatDiv 0 0.00% 52.12% # Class of committed instruction
431system.cpu.op_class_0::FloatSqrt 0 0.00% 52.12% # Class of committed instruction
432system.cpu.op_class_0::SimdAdd 0 0.00% 52.12% # Class of committed instruction
433system.cpu.op_class_0::SimdAddAcc 0 0.00% 52.12% # Class of committed instruction
434system.cpu.op_class_0::SimdAlu 0 0.00% 52.12% # Class of committed instruction
435system.cpu.op_class_0::SimdCmp 0 0.00% 52.12% # Class of committed instruction
436system.cpu.op_class_0::SimdCvt 0 0.00% 52.12% # Class of committed instruction
437system.cpu.op_class_0::SimdMisc 0 0.00% 52.12% # Class of committed instruction
438system.cpu.op_class_0::SimdMult 0 0.00% 52.12% # Class of committed instruction
439system.cpu.op_class_0::SimdMultAcc 0 0.00% 52.12% # Class of committed instruction
440system.cpu.op_class_0::SimdShift 0 0.00% 52.12% # Class of committed instruction
441system.cpu.op_class_0::SimdShiftAcc 0 0.00% 52.12% # Class of committed instruction
442system.cpu.op_class_0::SimdSqrt 0 0.00% 52.12% # Class of committed instruction
443system.cpu.op_class_0::SimdFloatAdd 0 0.00% 52.12% # Class of committed instruction
444system.cpu.op_class_0::SimdFloatAlu 0 0.00% 52.12% # Class of committed instruction
445system.cpu.op_class_0::SimdFloatCmp 0 0.00% 52.12% # Class of committed instruction
446system.cpu.op_class_0::SimdFloatCvt 0 0.00% 52.12% # Class of committed instruction
447system.cpu.op_class_0::SimdFloatDiv 0 0.00% 52.12% # Class of committed instruction
448system.cpu.op_class_0::SimdFloatMisc 7 0.00% 52.12% # Class of committed instruction
449system.cpu.op_class_0::SimdFloatMult 0 0.00% 52.12% # Class of committed instruction
450system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 52.12% # Class of committed instruction
451system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 52.12% # Class of committed instruction
452system.cpu.op_class_0::MemRead 22866262 25.21% 77.33% # Class of committed instruction
453system.cpu.op_class_0::MemWrite 20555739 22.67% 100.00% # Class of committed instruction
454system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
455system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
456system.cpu.op_class_0::total 90690106 # Class of committed instruction
457system.cpu.tickCycles 95311103 # Number of cycles that the object actually ticked
458system.cpu.idleCycles 18294846 # Total number of cycles that the object has spent stopped
459system.cpu.dcache.tags.replacements 156448 # number of replacements
460system.cpu.dcache.tags.tagsinuse 4067.225830 # Cycle average of tags in use
461system.cpu.dcache.tags.total_refs 42620314 # Total number of references to valid blocks.
462system.cpu.dcache.tags.sampled_refs 160544 # Sample count of references to valid blocks.
463system.cpu.dcache.tags.avg_refs 265.474350 # Average number of references to valid blocks.
464system.cpu.dcache.tags.warmup_cycle 820768500 # Cycle when the warmup percentage was hit.
465system.cpu.dcache.tags.occ_blocks::cpu.data 4067.225830 # Average occupied blocks per requestor
466system.cpu.dcache.tags.occ_percent::cpu.data 0.992975 # Average percentage of cache occupancy
467system.cpu.dcache.tags.occ_percent::total 0.992975 # Average percentage of cache occupancy
468system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
469system.cpu.dcache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id
470system.cpu.dcache.tags.age_task_id_blocks_1024::1 1099 # Occupied blocks per task id
471system.cpu.dcache.tags.age_task_id_blocks_1024::2 2953 # Occupied blocks per task id
472system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
473system.cpu.dcache.tags.tag_accesses 86009120 # Number of tag accesses
474system.cpu.dcache.tags.data_accesses 86009120 # Number of data accesses
475system.cpu.dcache.ReadReq_hits::cpu.data 22862903 # number of ReadReq hits
476system.cpu.dcache.ReadReq_hits::total 22862903 # number of ReadReq hits
477system.cpu.dcache.WriteReq_hits::cpu.data 19642172 # number of WriteReq hits
478system.cpu.dcache.WriteReq_hits::total 19642172 # number of WriteReq hits
479system.cpu.dcache.SoftPFReq_hits::cpu.data 83401 # number of SoftPFReq hits
480system.cpu.dcache.SoftPFReq_hits::total 83401 # number of SoftPFReq hits
481system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
482system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
483system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
484system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
485system.cpu.dcache.demand_hits::cpu.data 42505075 # number of demand (read+write) hits
486system.cpu.dcache.demand_hits::total 42505075 # number of demand (read+write) hits
487system.cpu.dcache.overall_hits::cpu.data 42588476 # number of overall hits
488system.cpu.dcache.overall_hits::total 42588476 # number of overall hits
489system.cpu.dcache.ReadReq_misses::cpu.data 51661 # number of ReadReq misses
490system.cpu.dcache.ReadReq_misses::total 51661 # number of ReadReq misses
491system.cpu.dcache.WriteReq_misses::cpu.data 207729 # number of WriteReq misses
492system.cpu.dcache.WriteReq_misses::total 207729 # number of WriteReq misses
493system.cpu.dcache.SoftPFReq_misses::cpu.data 44584 # number of SoftPFReq misses
494system.cpu.dcache.SoftPFReq_misses::total 44584 # number of SoftPFReq misses
495system.cpu.dcache.demand_misses::cpu.data 259390 # number of demand (read+write) misses
496system.cpu.dcache.demand_misses::total 259390 # number of demand (read+write) misses
497system.cpu.dcache.overall_misses::cpu.data 303974 # number of overall misses
498system.cpu.dcache.overall_misses::total 303974 # number of overall misses
499system.cpu.dcache.ReadReq_miss_latency::cpu.data 1490194000 # number of ReadReq miss cycles
500system.cpu.dcache.ReadReq_miss_latency::total 1490194000 # number of ReadReq miss cycles
501system.cpu.dcache.WriteReq_miss_latency::cpu.data 16811157000 # number of WriteReq miss cycles
502system.cpu.dcache.WriteReq_miss_latency::total 16811157000 # number of WriteReq miss cycles
503system.cpu.dcache.demand_miss_latency::cpu.data 18301351000 # number of demand (read+write) miss cycles
504system.cpu.dcache.demand_miss_latency::total 18301351000 # number of demand (read+write) miss cycles
505system.cpu.dcache.overall_miss_latency::cpu.data 18301351000 # number of overall miss cycles
506system.cpu.dcache.overall_miss_latency::total 18301351000 # number of overall miss cycles
507system.cpu.dcache.ReadReq_accesses::cpu.data 22914564 # number of ReadReq accesses(hits+misses)
508system.cpu.dcache.ReadReq_accesses::total 22914564 # number of ReadReq accesses(hits+misses)
509system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
510system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
511system.cpu.dcache.SoftPFReq_accesses::cpu.data 127985 # number of SoftPFReq accesses(hits+misses)
512system.cpu.dcache.SoftPFReq_accesses::total 127985 # number of SoftPFReq accesses(hits+misses)
513system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
514system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
515system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
516system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
517system.cpu.dcache.demand_accesses::cpu.data 42764465 # number of demand (read+write) accesses
518system.cpu.dcache.demand_accesses::total 42764465 # number of demand (read+write) accesses
519system.cpu.dcache.overall_accesses::cpu.data 42892450 # number of overall (read+write) accesses
520system.cpu.dcache.overall_accesses::total 42892450 # number of overall (read+write) accesses
521system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002255 # miss rate for ReadReq accesses
522system.cpu.dcache.ReadReq_miss_rate::total 0.002255 # miss rate for ReadReq accesses
523system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010465 # miss rate for WriteReq accesses
524system.cpu.dcache.WriteReq_miss_rate::total 0.010465 # miss rate for WriteReq accesses
525system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.348353 # miss rate for SoftPFReq accesses
526system.cpu.dcache.SoftPFReq_miss_rate::total 0.348353 # miss rate for SoftPFReq accesses
527system.cpu.dcache.demand_miss_rate::cpu.data 0.006066 # miss rate for demand accesses
528system.cpu.dcache.demand_miss_rate::total 0.006066 # miss rate for demand accesses
529system.cpu.dcache.overall_miss_rate::cpu.data 0.007087 # miss rate for overall accesses
530system.cpu.dcache.overall_miss_rate::total 0.007087 # miss rate for overall accesses
531system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28845.628230 # average ReadReq miss latency
532system.cpu.dcache.ReadReq_avg_miss_latency::total 28845.628230 # average ReadReq miss latency
533system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 80928.310443 # average WriteReq miss latency
534system.cpu.dcache.WriteReq_avg_miss_latency::total 80928.310443 # average WriteReq miss latency
535system.cpu.dcache.demand_avg_miss_latency::cpu.data 70555.345233 # average overall miss latency
536system.cpu.dcache.demand_avg_miss_latency::total 70555.345233 # average overall miss latency
537system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780 # average overall miss latency
538system.cpu.dcache.overall_avg_miss_latency::total 60206.961780 # average overall miss latency
539system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
540system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
541system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
542system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
543system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
544system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
545system.cpu.dcache.writebacks::writebacks 128389 # number of writebacks
546system.cpu.dcache.writebacks::total 128389 # number of writebacks
547system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22138 # number of ReadReq MSHR hits
548system.cpu.dcache.ReadReq_mshr_hits::total 22138 # number of ReadReq MSHR hits
549system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100695 # number of WriteReq MSHR hits
550system.cpu.dcache.WriteReq_mshr_hits::total 100695 # number of WriteReq MSHR hits
551system.cpu.dcache.demand_mshr_hits::cpu.data 122833 # number of demand (read+write) MSHR hits
552system.cpu.dcache.demand_mshr_hits::total 122833 # number of demand (read+write) MSHR hits
553system.cpu.dcache.overall_mshr_hits::cpu.data 122833 # number of overall MSHR hits
554system.cpu.dcache.overall_mshr_hits::total 122833 # number of overall MSHR hits
555system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29523 # number of ReadReq MSHR misses
556system.cpu.dcache.ReadReq_mshr_misses::total 29523 # number of ReadReq MSHR misses
557system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107034 # number of WriteReq MSHR misses
558system.cpu.dcache.WriteReq_mshr_misses::total 107034 # number of WriteReq MSHR misses
559system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23987 # number of SoftPFReq MSHR misses
560system.cpu.dcache.SoftPFReq_mshr_misses::total 23987 # number of SoftPFReq MSHR misses
561system.cpu.dcache.demand_mshr_misses::cpu.data 136557 # number of demand (read+write) MSHR misses
562system.cpu.dcache.demand_mshr_misses::total 136557 # number of demand (read+write) MSHR misses
563system.cpu.dcache.overall_mshr_misses::cpu.data 160544 # number of overall MSHR misses
564system.cpu.dcache.overall_mshr_misses::total 160544 # number of overall MSHR misses
565system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 578329500 # number of ReadReq MSHR miss cycles
566system.cpu.dcache.ReadReq_mshr_miss_latency::total 578329500 # number of ReadReq MSHR miss cycles
567system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8490118500 # number of WriteReq MSHR miss cycles
568system.cpu.dcache.WriteReq_mshr_miss_latency::total 8490118500 # number of WriteReq MSHR miss cycles
569system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1713467500 # number of SoftPFReq MSHR miss cycles
570system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1713467500 # number of SoftPFReq MSHR miss cycles
571system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9068448000 # number of demand (read+write) MSHR miss cycles
572system.cpu.dcache.demand_mshr_miss_latency::total 9068448000 # number of demand (read+write) MSHR miss cycles
573system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10781915500 # number of overall MSHR miss cycles
574system.cpu.dcache.overall_mshr_miss_latency::total 10781915500 # number of overall MSHR miss cycles
575system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001288 # mshr miss rate for ReadReq accesses
576system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001288 # mshr miss rate for ReadReq accesses
577system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
578system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
579system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187420 # mshr miss rate for SoftPFReq accesses
580system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187420 # mshr miss rate for SoftPFReq accesses
581system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003193 # mshr miss rate for demand accesses
582system.cpu.dcache.demand_mshr_miss_rate::total 0.003193 # mshr miss rate for demand accesses
583system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003743 # mshr miss rate for overall accesses
584system.cpu.dcache.overall_mshr_miss_rate::total 0.003743 # mshr miss rate for overall accesses
585system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19589.116960 # average ReadReq mshr miss latency
586system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 19589.116960 # average ReadReq mshr miss latency
587system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency
588system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency
589system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency
590system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency
591system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency
592system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency
593system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency
594system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency
595system.cpu.icache.tags.replacements 43497 # number of replacements
596system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use
597system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks.
598system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks.
599system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks.
600system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
601system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor
602system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy
603system.cpu.icache.tags.occ_percent::total 0.904627 # Average percentage of cache occupancy
604system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
605system.cpu.icache.tags.age_task_id_blocks_1024::0 76 # Occupied blocks per task id
606system.cpu.icache.tags.age_task_id_blocks_1024::1 46 # Occupied blocks per task id
607system.cpu.icache.tags.age_task_id_blocks_1024::3 915 # Occupied blocks per task id
608system.cpu.icache.tags.age_task_id_blocks_1024::4 1005 # Occupied blocks per task id
609system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
610system.cpu.icache.tags.tag_accesses 49825373 # Number of tag accesses
611system.cpu.icache.tags.data_accesses 49825373 # Number of data accesses
612system.cpu.icache.ReadReq_hits::cpu.inst 24844377 # number of ReadReq hits
613system.cpu.icache.ReadReq_hits::total 24844377 # number of ReadReq hits
614system.cpu.icache.demand_hits::cpu.inst 24844377 # number of demand (read+write) hits
615system.cpu.icache.demand_hits::total 24844377 # number of demand (read+write) hits
616system.cpu.icache.overall_hits::cpu.inst 24844377 # number of overall hits
617system.cpu.icache.overall_hits::total 24844377 # number of overall hits
618system.cpu.icache.ReadReq_misses::cpu.inst 45540 # number of ReadReq misses
619system.cpu.icache.ReadReq_misses::total 45540 # number of ReadReq misses
620system.cpu.icache.demand_misses::cpu.inst 45540 # number of demand (read+write) misses
621system.cpu.icache.demand_misses::total 45540 # number of demand (read+write) misses
622system.cpu.icache.overall_misses::cpu.inst 45540 # number of overall misses
623system.cpu.icache.overall_misses::total 45540 # number of overall misses
624system.cpu.icache.ReadReq_miss_latency::cpu.inst 905103000 # number of ReadReq miss cycles
625system.cpu.icache.ReadReq_miss_latency::total 905103000 # number of ReadReq miss cycles
626system.cpu.icache.demand_miss_latency::cpu.inst 905103000 # number of demand (read+write) miss cycles
627system.cpu.icache.demand_miss_latency::total 905103000 # number of demand (read+write) miss cycles
628system.cpu.icache.overall_miss_latency::cpu.inst 905103000 # number of overall miss cycles
629system.cpu.icache.overall_miss_latency::total 905103000 # number of overall miss cycles
630system.cpu.icache.ReadReq_accesses::cpu.inst 24889917 # number of ReadReq accesses(hits+misses)
631system.cpu.icache.ReadReq_accesses::total 24889917 # number of ReadReq accesses(hits+misses)
632system.cpu.icache.demand_accesses::cpu.inst 24889917 # number of demand (read+write) accesses
633system.cpu.icache.demand_accesses::total 24889917 # number of demand (read+write) accesses
634system.cpu.icache.overall_accesses::cpu.inst 24889917 # number of overall (read+write) accesses
635system.cpu.icache.overall_accesses::total 24889917 # number of overall (read+write) accesses
636system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001830 # miss rate for ReadReq accesses
637system.cpu.icache.ReadReq_miss_rate::total 0.001830 # miss rate for ReadReq accesses
638system.cpu.icache.demand_miss_rate::cpu.inst 0.001830 # miss rate for demand accesses
639system.cpu.icache.demand_miss_rate::total 0.001830 # miss rate for demand accesses
640system.cpu.icache.overall_miss_rate::cpu.inst 0.001830 # miss rate for overall accesses
641system.cpu.icache.overall_miss_rate::total 0.001830 # miss rate for overall accesses
642system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 19874.901186 # average ReadReq miss latency
643system.cpu.icache.ReadReq_avg_miss_latency::total 19874.901186 # average ReadReq miss latency
644system.cpu.icache.demand_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency
645system.cpu.icache.demand_avg_miss_latency::total 19874.901186 # average overall miss latency
646system.cpu.icache.overall_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency
647system.cpu.icache.overall_avg_miss_latency::total 19874.901186 # average overall miss latency
648system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
649system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
650system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
651system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
652system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
653system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
654system.cpu.icache.writebacks::writebacks 43497 # number of writebacks
655system.cpu.icache.writebacks::total 43497 # number of writebacks
656system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45540 # number of ReadReq MSHR misses
657system.cpu.icache.ReadReq_mshr_misses::total 45540 # number of ReadReq MSHR misses
658system.cpu.icache.demand_mshr_misses::cpu.inst 45540 # number of demand (read+write) MSHR misses
659system.cpu.icache.demand_mshr_misses::total 45540 # number of demand (read+write) MSHR misses
660system.cpu.icache.overall_mshr_misses::cpu.inst 45540 # number of overall MSHR misses
661system.cpu.icache.overall_mshr_misses::total 45540 # number of overall MSHR misses
662system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 859564000 # number of ReadReq MSHR miss cycles
663system.cpu.icache.ReadReq_mshr_miss_latency::total 859564000 # number of ReadReq MSHR miss cycles
664system.cpu.icache.demand_mshr_miss_latency::cpu.inst 859564000 # number of demand (read+write) MSHR miss cycles
665system.cpu.icache.demand_mshr_miss_latency::total 859564000 # number of demand (read+write) MSHR miss cycles
666system.cpu.icache.overall_mshr_miss_latency::cpu.inst 859564000 # number of overall MSHR miss cycles
667system.cpu.icache.overall_mshr_miss_latency::total 859564000 # number of overall MSHR miss cycles
668system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for ReadReq accesses
669system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001830 # mshr miss rate for ReadReq accesses
670system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for demand accesses
671system.cpu.icache.demand_mshr_miss_rate::total 0.001830 # mshr miss rate for demand accesses
672system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses
673system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses
674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency
675system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency
676system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
677system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
678system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency
679system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency
680system.cpu.l2cache.tags.replacements 96391 # number of replacements
681system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use
682system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks.
683system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks.
684system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks.
685system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
686system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor
687system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor
688system.cpu.l2cache.tags.occ_blocks::cpu.data 1656.072920 # Average occupied blocks per requestor
689system.cpu.l2cache.tags.occ_percent::writebacks 0.817316 # Average percentage of cache occupancy
690system.cpu.l2cache.tags.occ_percent::cpu.inst 0.043735 # Average percentage of cache occupancy
691system.cpu.l2cache.tags.occ_percent::cpu.data 0.050539 # Average percentage of cache occupancy
692system.cpu.l2cache.tags.occ_percent::total 0.911590 # Average percentage of cache occupancy
693system.cpu.l2cache.tags.occ_task_id_blocks::1024 31151 # Occupied blocks per task id
694system.cpu.l2cache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id
695system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1859 # Occupied blocks per task id
696system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12725 # Occupied blocks per task id
697system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15781 # Occupied blocks per task id
698system.cpu.l2cache.tags.age_task_id_blocks_1024::4 595 # Occupied blocks per task id
699system.cpu.l2cache.tags.occ_task_id_percent::1024 0.950653 # Percentage of cache occupancy per task id
700system.cpu.l2cache.tags.tag_accesses 3420152 # Number of tag accesses
701system.cpu.l2cache.tags.data_accesses 3420152 # Number of data accesses
702system.cpu.l2cache.WritebackDirty_hits::writebacks 128389 # number of WritebackDirty hits
703system.cpu.l2cache.WritebackDirty_hits::total 128389 # number of WritebackDirty hits
704system.cpu.l2cache.WritebackClean_hits::writebacks 39908 # number of WritebackClean hits
705system.cpu.l2cache.WritebackClean_hits::total 39908 # number of WritebackClean hits
706system.cpu.l2cache.ReadExReq_hits::cpu.data 4752 # number of ReadExReq hits
707system.cpu.l2cache.ReadExReq_hits::total 4752 # number of ReadExReq hits
708system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 41065 # number of ReadCleanReq hits
709system.cpu.l2cache.ReadCleanReq_hits::total 41065 # number of ReadCleanReq hits
710system.cpu.l2cache.ReadSharedReq_hits::cpu.data 31907 # number of ReadSharedReq hits
711system.cpu.l2cache.ReadSharedReq_hits::total 31907 # number of ReadSharedReq hits
712system.cpu.l2cache.demand_hits::cpu.inst 41065 # number of demand (read+write) hits
713system.cpu.l2cache.demand_hits::cpu.data 36659 # number of demand (read+write) hits
714system.cpu.l2cache.demand_hits::total 77724 # number of demand (read+write) hits
715system.cpu.l2cache.overall_hits::cpu.inst 41065 # number of overall hits
716system.cpu.l2cache.overall_hits::cpu.data 36659 # number of overall hits
717system.cpu.l2cache.overall_hits::total 77724 # number of overall hits
718system.cpu.l2cache.ReadExReq_misses::cpu.data 102282 # number of ReadExReq misses
719system.cpu.l2cache.ReadExReq_misses::total 102282 # number of ReadExReq misses
720system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 4475 # number of ReadCleanReq misses
721system.cpu.l2cache.ReadCleanReq_misses::total 4475 # number of ReadCleanReq misses
722system.cpu.l2cache.ReadSharedReq_misses::cpu.data 21603 # number of ReadSharedReq misses
723system.cpu.l2cache.ReadSharedReq_misses::total 21603 # number of ReadSharedReq misses
724system.cpu.l2cache.demand_misses::cpu.inst 4475 # number of demand (read+write) misses
725system.cpu.l2cache.demand_misses::cpu.data 123885 # number of demand (read+write) misses
726system.cpu.l2cache.demand_misses::total 128360 # number of demand (read+write) misses
727system.cpu.l2cache.overall_misses::cpu.inst 4475 # number of overall misses
728system.cpu.l2cache.overall_misses::cpu.data 123885 # number of overall misses
729system.cpu.l2cache.overall_misses::total 128360 # number of overall misses
730system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8279623500 # number of ReadExReq miss cycles
731system.cpu.l2cache.ReadExReq_miss_latency::total 8279623500 # number of ReadExReq miss cycles
732system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 356201500 # number of ReadCleanReq miss cycles
733system.cpu.l2cache.ReadCleanReq_miss_latency::total 356201500 # number of ReadCleanReq miss cycles
734system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1872087500 # number of ReadSharedReq miss cycles
735system.cpu.l2cache.ReadSharedReq_miss_latency::total 1872087500 # number of ReadSharedReq miss cycles
736system.cpu.l2cache.demand_miss_latency::cpu.inst 356201500 # number of demand (read+write) miss cycles
737system.cpu.l2cache.demand_miss_latency::cpu.data 10151711000 # number of demand (read+write) miss cycles
738system.cpu.l2cache.demand_miss_latency::total 10507912500 # number of demand (read+write) miss cycles
739system.cpu.l2cache.overall_miss_latency::cpu.inst 356201500 # number of overall miss cycles
740system.cpu.l2cache.overall_miss_latency::cpu.data 10151711000 # number of overall miss cycles
741system.cpu.l2cache.overall_miss_latency::total 10507912500 # number of overall miss cycles
742system.cpu.l2cache.WritebackDirty_accesses::writebacks 128389 # number of WritebackDirty accesses(hits+misses)
743system.cpu.l2cache.WritebackDirty_accesses::total 128389 # number of WritebackDirty accesses(hits+misses)
744system.cpu.l2cache.WritebackClean_accesses::writebacks 39908 # number of WritebackClean accesses(hits+misses)
745system.cpu.l2cache.WritebackClean_accesses::total 39908 # number of WritebackClean accesses(hits+misses)
746system.cpu.l2cache.ReadExReq_accesses::cpu.data 107034 # number of ReadExReq accesses(hits+misses)
747system.cpu.l2cache.ReadExReq_accesses::total 107034 # number of ReadExReq accesses(hits+misses)
748system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 45540 # number of ReadCleanReq accesses(hits+misses)
749system.cpu.l2cache.ReadCleanReq_accesses::total 45540 # number of ReadCleanReq accesses(hits+misses)
750system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53510 # number of ReadSharedReq accesses(hits+misses)
751system.cpu.l2cache.ReadSharedReq_accesses::total 53510 # number of ReadSharedReq accesses(hits+misses)
752system.cpu.l2cache.demand_accesses::cpu.inst 45540 # number of demand (read+write) accesses
753system.cpu.l2cache.demand_accesses::cpu.data 160544 # number of demand (read+write) accesses
754system.cpu.l2cache.demand_accesses::total 206084 # number of demand (read+write) accesses
755system.cpu.l2cache.overall_accesses::cpu.inst 45540 # number of overall (read+write) accesses
756system.cpu.l2cache.overall_accesses::cpu.data 160544 # number of overall (read+write) accesses
757system.cpu.l2cache.overall_accesses::total 206084 # number of overall (read+write) accesses
758system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955603 # miss rate for ReadExReq accesses
759system.cpu.l2cache.ReadExReq_miss_rate::total 0.955603 # miss rate for ReadExReq accesses
760system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.098265 # miss rate for ReadCleanReq accesses
761system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.098265 # miss rate for ReadCleanReq accesses
762system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.403719 # miss rate for ReadSharedReq accesses
763system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.403719 # miss rate for ReadSharedReq accesses
764system.cpu.l2cache.demand_miss_rate::cpu.inst 0.098265 # miss rate for demand accesses
765system.cpu.l2cache.demand_miss_rate::cpu.data 0.771658 # miss rate for demand accesses
766system.cpu.l2cache.demand_miss_rate::total 0.622853 # miss rate for demand accesses
767system.cpu.l2cache.overall_miss_rate::cpu.inst 0.098265 # miss rate for overall accesses
768system.cpu.l2cache.overall_miss_rate::cpu.data 0.771658 # miss rate for overall accesses
769system.cpu.l2cache.overall_miss_rate::total 0.622853 # miss rate for overall accesses
770system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80948.979293 # average ReadExReq miss latency
771system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80948.979293 # average ReadExReq miss latency
772system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 79598.100559 # average ReadCleanReq miss latency
773system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 79598.100559 # average ReadCleanReq miss latency
774system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86658.681665 # average ReadSharedReq miss latency
775system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86658.681665 # average ReadSharedReq miss latency
776system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency
777system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency
778system.cpu.l2cache.demand_avg_miss_latency::total 81862.827205 # average overall miss latency
779system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79598.100559 # average overall miss latency
780system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency
781system.cpu.l2cache.overall_avg_miss_latency::total 81862.827205 # average overall miss latency
782system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
783system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
784system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
785system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
786system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
787system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
788system.cpu.l2cache.writebacks::writebacks 86215 # number of writebacks
789system.cpu.l2cache.writebacks::total 86215 # number of writebacks
790system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits
791system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits
792system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits
793system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits
794system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits
795system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits
796system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits
797system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits
798system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits
799system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits
800system.cpu.l2cache.CleanEvict_mshr_misses::writebacks 96 # number of CleanEvict MSHR misses
801system.cpu.l2cache.CleanEvict_mshr_misses::total 96 # number of CleanEvict MSHR misses
802system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102282 # number of ReadExReq MSHR misses
803system.cpu.l2cache.ReadExReq_mshr_misses::total 102282 # number of ReadExReq MSHR misses
804system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 4462 # number of ReadCleanReq MSHR misses
805system.cpu.l2cache.ReadCleanReq_mshr_misses::total 4462 # number of ReadCleanReq MSHR misses
806system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 21541 # number of ReadSharedReq MSHR misses
807system.cpu.l2cache.ReadSharedReq_mshr_misses::total 21541 # number of ReadSharedReq MSHR misses
808system.cpu.l2cache.demand_mshr_misses::cpu.inst 4462 # number of demand (read+write) MSHR misses
809system.cpu.l2cache.demand_mshr_misses::cpu.data 123823 # number of demand (read+write) MSHR misses
810system.cpu.l2cache.demand_mshr_misses::total 128285 # number of demand (read+write) MSHR misses
811system.cpu.l2cache.overall_mshr_misses::cpu.inst 4462 # number of overall MSHR misses
812system.cpu.l2cache.overall_mshr_misses::cpu.data 123823 # number of overall MSHR misses
813system.cpu.l2cache.overall_mshr_misses::total 128285 # number of overall MSHR misses
814system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7256803500 # number of ReadExReq MSHR miss cycles
815system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7256803500 # number of ReadExReq MSHR miss cycles
816system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 310457000 # number of ReadCleanReq MSHR miss cycles
817system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 310457000 # number of ReadCleanReq MSHR miss cycles
818system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1652012000 # number of ReadSharedReq MSHR miss cycles
819system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1652012000 # number of ReadSharedReq MSHR miss cycles
820system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 310457000 # number of demand (read+write) MSHR miss cycles
821system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8908815500 # number of demand (read+write) MSHR miss cycles
822system.cpu.l2cache.demand_mshr_miss_latency::total 9219272500 # number of demand (read+write) MSHR miss cycles
823system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 310457000 # number of overall MSHR miss cycles
824system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8908815500 # number of overall MSHR miss cycles
825system.cpu.l2cache.overall_mshr_miss_latency::total 9219272500 # number of overall MSHR miss cycles
826system.cpu.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses
827system.cpu.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses
828system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955603 # mshr miss rate for ReadExReq accesses
829system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955603 # mshr miss rate for ReadExReq accesses
830system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for ReadCleanReq accesses
831system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.097980 # mshr miss rate for ReadCleanReq accesses
832system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.402560 # mshr miss rate for ReadSharedReq accesses
833system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.402560 # mshr miss rate for ReadSharedReq accesses
834system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for demand accesses
835system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for demand accesses
836system.cpu.l2cache.demand_mshr_miss_rate::total 0.622489 # mshr miss rate for demand accesses
837system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.097980 # mshr miss rate for overall accesses
838system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771271 # mshr miss rate for overall accesses
839system.cpu.l2cache.overall_mshr_miss_rate::total 0.622489 # mshr miss rate for overall accesses
840system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70948.979293 # average ReadExReq mshr miss latency
841system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70948.979293 # average ReadExReq mshr miss latency
842system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69577.991932 # average ReadCleanReq mshr miss latency
843system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69577.991932 # average ReadCleanReq mshr miss latency
844system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76691.518500 # average ReadSharedReq mshr miss latency
845system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76691.518500 # average ReadSharedReq mshr miss latency
846system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency
847system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
848system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
849system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency
850system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency
851system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency
852system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter.
853system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data.
854system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
855system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter.
856system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
857system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
858system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution
859system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution
860system.cpu.toL2Bus.trans_dist::WritebackClean 43497 # Transaction distribution
861system.cpu.toL2Bus.trans_dist::CleanEvict 38235 # Transaction distribution
862system.cpu.toL2Bus.trans_dist::ReadExReq 107034 # Transaction distribution
863system.cpu.toL2Bus.trans_dist::ReadExResp 107034 # Transaction distribution
864system.cpu.toL2Bus.trans_dist::ReadCleanReq 45540 # Transaction distribution
865system.cpu.toL2Bus.trans_dist::ReadSharedReq 53510 # Transaction distribution
866system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 134576 # Packet count per connected master and slave (bytes)
867system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 477536 # Packet count per connected master and slave (bytes)
868system.cpu.toL2Bus.pkt_count::total 612112 # Packet count per connected master and slave (bytes)
869system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5698304 # Cumulative packet size per connected master and slave (bytes)
870system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18491712 # Cumulative packet size per connected master and slave (bytes)
871system.cpu.toL2Bus.pkt_size::total 24190016 # Cumulative packet size per connected master and slave (bytes)
872system.cpu.toL2Bus.snoops 96391 # Total snoops (count)
873system.cpu.toL2Bus.snoop_fanout::samples 302475 # Request fanout histogram
874system.cpu.toL2Bus.snoop_fanout::mean 0.037210 # Request fanout histogram
875system.cpu.toL2Bus.snoop_fanout::stdev 0.189781 # Request fanout histogram
876system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
877system.cpu.toL2Bus.snoop_fanout::0 291249 96.29% 96.29% # Request fanout histogram
878system.cpu.toL2Bus.snoop_fanout::1 11197 3.70% 99.99% # Request fanout histogram
879system.cpu.toL2Bus.snoop_fanout::2 29 0.01% 100.00% # Request fanout histogram
880system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
881system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
882system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram
883system.cpu.toL2Bus.snoop_fanout::total 302475 # Request fanout histogram
884system.cpu.toL2Bus.reqLayer0.occupancy 374900500 # Layer occupancy (ticks)
885system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
886system.cpu.toL2Bus.respLayer0.occupancy 68328959 # Layer occupancy (ticks)
887system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
888system.cpu.toL2Bus.respLayer1.occupancy 240850431 # Layer occupancy (ticks)
889system.cpu.toL2Bus.respLayer1.utilization 0.4 # Layer utilization (%)
890system.membus.trans_dist::ReadResp 26002 # Transaction distribution
891system.membus.trans_dist::WritebackDirty 86215 # Transaction distribution
892system.membus.trans_dist::CleanEvict 6912 # Transaction distribution
893system.membus.trans_dist::ReadExReq 102282 # Transaction distribution
894system.membus.trans_dist::ReadExResp 102282 # Transaction distribution
895system.membus.trans_dist::ReadSharedReq 26002 # Transaction distribution
896system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 349695 # Packet count per connected master and slave (bytes)
897system.membus.pkt_count::total 349695 # Packet count per connected master and slave (bytes)
898system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13727936 # Cumulative packet size per connected master and slave (bytes)
899system.membus.pkt_size::total 13727936 # Cumulative packet size per connected master and slave (bytes)
900system.membus.snoops 0 # Total snoops (count)
901system.membus.snoop_fanout::samples 221411 # Request fanout histogram
902system.membus.snoop_fanout::mean 0 # Request fanout histogram
903system.membus.snoop_fanout::stdev 0 # Request fanout histogram
904system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
905system.membus.snoop_fanout::0 221411 100.00% 100.00% # Request fanout histogram
906system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
907system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
908system.membus.snoop_fanout::min_value 0 # Request fanout histogram
909system.membus.snoop_fanout::max_value 0 # Request fanout histogram
910system.membus.snoop_fanout::total 221411 # Request fanout histogram
911system.membus.reqLayer0.occupancy 590704500 # Layer occupancy (ticks)
912system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
913system.membus.respLayer1.occupancy 676958000 # Layer occupancy (ticks)
914system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
915
916---------- End Simulation Statistics ----------