| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.056803 # Number of seconds simulated 4sim_ticks 56802974500 # Number of ticks simulated 5final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.056803 # Number of seconds simulated 4sim_ticks 56802974500 # Number of ticks simulated 5final_tick 56802974500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 208655 # Simulator instruction rate (inst/s) 8host_op_rate 266840 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 167132713 # Simulator tick rate (ticks/s) 10host_mem_usage 280072 # Number of bytes of host memory used 11host_seconds 339.87 # Real time elapsed on the host | 7host_inst_rate 222036 # Simulator instruction rate (inst/s) 8host_op_rate 283951 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 177850276 # Simulator tick rate (ticks/s) 10host_mem_usage 280068 # Number of bytes of host memory used 11host_seconds 319.39 # Real time elapsed on the host |
| 12sim_insts 70915150 # Number of instructions simulated 13sim_ops 90690106 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory --- 517 unchanged lines hidden (view full) --- 537system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780 # average overall miss latency 538system.cpu.dcache.overall_avg_miss_latency::total 60206.961780 # average overall miss latency 539system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 540system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 541system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 542system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 543system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 544system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 70915150 # Number of instructions simulated 13sim_ops 90690106 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 285504 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7924672 # Number of bytes read from this memory 18system.physmem.bytes_read::total 8210176 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 285504 # Number of instructions bytes read from this memory --- 517 unchanged lines hidden (view full) --- 537system.cpu.dcache.overall_avg_miss_latency::cpu.data 60206.961780 # average overall miss latency 538system.cpu.dcache.overall_avg_miss_latency::total 60206.961780 # average overall miss latency 539system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 540system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 541system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 542system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 543system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 544system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 545system.cpu.dcache.fast_writes 0 # number of fast writes performed 546system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 547system.cpu.dcache.writebacks::writebacks 128389 # number of writebacks 548system.cpu.dcache.writebacks::total 128389 # number of writebacks 549system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22138 # number of ReadReq MSHR hits 550system.cpu.dcache.ReadReq_mshr_hits::total 22138 # number of ReadReq MSHR hits 551system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100695 # number of WriteReq MSHR hits 552system.cpu.dcache.WriteReq_mshr_hits::total 100695 # number of WriteReq MSHR hits 553system.cpu.dcache.demand_mshr_hits::cpu.data 122833 # number of demand (read+write) MSHR hits 554system.cpu.dcache.demand_mshr_hits::total 122833 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 589system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency 590system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency 591system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency 592system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency 593system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency 594system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency 595system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency 596system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency | 545system.cpu.dcache.writebacks::writebacks 128389 # number of writebacks 546system.cpu.dcache.writebacks::total 128389 # number of writebacks 547system.cpu.dcache.ReadReq_mshr_hits::cpu.data 22138 # number of ReadReq MSHR hits 548system.cpu.dcache.ReadReq_mshr_hits::total 22138 # number of ReadReq MSHR hits 549system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100695 # number of WriteReq MSHR hits 550system.cpu.dcache.WriteReq_mshr_hits::total 100695 # number of WriteReq MSHR hits 551system.cpu.dcache.demand_mshr_hits::cpu.data 122833 # number of demand (read+write) MSHR hits 552system.cpu.dcache.demand_mshr_hits::total 122833 # number of demand (read+write) MSHR hits --- 34 unchanged lines hidden (view full) --- 587system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79321.696844 # average WriteReq mshr miss latency 588system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79321.696844 # average WriteReq mshr miss latency 589system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 71433.172135 # average SoftPFReq mshr miss latency 590system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71433.172135 # average SoftPFReq mshr miss latency 591system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66407.785760 # average overall mshr miss latency 592system.cpu.dcache.demand_avg_mshr_miss_latency::total 66407.785760 # average overall mshr miss latency 593system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 67158.632524 # average overall mshr miss latency 594system.cpu.dcache.overall_avg_mshr_miss_latency::total 67158.632524 # average overall mshr miss latency |
| 597system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 598system.cpu.icache.tags.replacements 43497 # number of replacements 599system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use 600system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks. 601system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks. 602system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks. 603system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 604system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor 605system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 649system.cpu.icache.overall_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency 650system.cpu.icache.overall_avg_miss_latency::total 19874.901186 # average overall miss latency 651system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 652system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 653system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 654system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 656system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 595system.cpu.icache.tags.replacements 43497 # number of replacements 596system.cpu.icache.tags.tagsinuse 1852.676989 # Cycle average of tags in use 597system.cpu.icache.tags.total_refs 24844377 # Total number of references to valid blocks. 598system.cpu.icache.tags.sampled_refs 45539 # Sample count of references to valid blocks. 599system.cpu.icache.tags.avg_refs 545.562639 # Average number of references to valid blocks. 600system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 601system.cpu.icache.tags.occ_blocks::cpu.inst 1852.676989 # Average occupied blocks per requestor 602system.cpu.icache.tags.occ_percent::cpu.inst 0.904627 # Average percentage of cache occupancy --- 43 unchanged lines hidden (view full) --- 646system.cpu.icache.overall_avg_miss_latency::cpu.inst 19874.901186 # average overall miss latency 647system.cpu.icache.overall_avg_miss_latency::total 19874.901186 # average overall miss latency 648system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 649system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 650system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 651system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 652system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 653system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 657system.cpu.icache.fast_writes 0 # number of fast writes performed 658system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 659system.cpu.icache.writebacks::writebacks 43497 # number of writebacks 660system.cpu.icache.writebacks::total 43497 # number of writebacks 661system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45540 # number of ReadReq MSHR misses 662system.cpu.icache.ReadReq_mshr_misses::total 45540 # number of ReadReq MSHR misses 663system.cpu.icache.demand_mshr_misses::cpu.inst 45540 # number of demand (read+write) MSHR misses 664system.cpu.icache.demand_mshr_misses::total 45540 # number of demand (read+write) MSHR misses 665system.cpu.icache.overall_mshr_misses::cpu.inst 45540 # number of overall MSHR misses 666system.cpu.icache.overall_mshr_misses::total 45540 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 677system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses 678system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses 679system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency 680system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency 681system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency 682system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency 683system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency 684system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency | 654system.cpu.icache.writebacks::writebacks 43497 # number of writebacks 655system.cpu.icache.writebacks::total 43497 # number of writebacks 656system.cpu.icache.ReadReq_mshr_misses::cpu.inst 45540 # number of ReadReq MSHR misses 657system.cpu.icache.ReadReq_mshr_misses::total 45540 # number of ReadReq MSHR misses 658system.cpu.icache.demand_mshr_misses::cpu.inst 45540 # number of demand (read+write) MSHR misses 659system.cpu.icache.demand_mshr_misses::total 45540 # number of demand (read+write) MSHR misses 660system.cpu.icache.overall_mshr_misses::cpu.inst 45540 # number of overall MSHR misses 661system.cpu.icache.overall_mshr_misses::total 45540 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 672system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001830 # mshr miss rate for overall accesses 673system.cpu.icache.overall_mshr_miss_rate::total 0.001830 # mshr miss rate for overall accesses 674system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18874.923144 # average ReadReq mshr miss latency 675system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 18874.923144 # average ReadReq mshr miss latency 676system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency 677system.cpu.icache.demand_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency 678system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18874.923144 # average overall mshr miss latency 679system.cpu.icache.overall_avg_mshr_miss_latency::total 18874.923144 # average overall mshr miss latency |
| 685system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 686system.cpu.l2cache.tags.replacements 96391 # number of replacements 687system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use 688system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks. 689system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks. 690system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks. 691system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 692system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor 693system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 786system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency 787system.cpu.l2cache.overall_avg_miss_latency::total 81862.827205 # average overall miss latency 788system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 789system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 790system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 791system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 792system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 793system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 680system.cpu.l2cache.tags.replacements 96391 # number of replacements 681system.cpu.l2cache.tags.tagsinuse 29870.997301 # Cycle average of tags in use 682system.cpu.l2cache.tags.total_refs 163417 # Total number of references to valid blocks. 683system.cpu.l2cache.tags.sampled_refs 127542 # Sample count of references to valid blocks. 684system.cpu.l2cache.tags.avg_refs 1.281280 # Average number of references to valid blocks. 685system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 686system.cpu.l2cache.tags.occ_blocks::writebacks 26781.820547 # Average occupied blocks per requestor 687system.cpu.l2cache.tags.occ_blocks::cpu.inst 1433.103835 # Average occupied blocks per requestor --- 92 unchanged lines hidden (view full) --- 780system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81944.634136 # average overall miss latency 781system.cpu.l2cache.overall_avg_miss_latency::total 81862.827205 # average overall miss latency 782system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 784system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 785system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 786system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 787system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 794system.cpu.l2cache.fast_writes 0 # number of fast writes performed 795system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 796system.cpu.l2cache.writebacks::writebacks 86215 # number of writebacks 797system.cpu.l2cache.writebacks::total 86215 # number of writebacks 798system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits 799system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 800system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits 801system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits 802system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits 803system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits --- 48 unchanged lines hidden (view full) --- 852system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76691.518500 # average ReadSharedReq mshr miss latency 853system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76691.518500 # average ReadSharedReq mshr miss latency 854system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency 855system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency 856system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency 857system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency 858system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency 859system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency | 788system.cpu.l2cache.writebacks::writebacks 86215 # number of writebacks 789system.cpu.l2cache.writebacks::total 86215 # number of writebacks 790system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 13 # number of ReadCleanReq MSHR hits 791system.cpu.l2cache.ReadCleanReq_mshr_hits::total 13 # number of ReadCleanReq MSHR hits 792system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 62 # number of ReadSharedReq MSHR hits 793system.cpu.l2cache.ReadSharedReq_mshr_hits::total 62 # number of ReadSharedReq MSHR hits 794system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits 795system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits --- 48 unchanged lines hidden (view full) --- 844system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76691.518500 # average ReadSharedReq mshr miss latency 845system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76691.518500 # average ReadSharedReq mshr miss latency 846system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency 847system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency 848system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency 849system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69577.991932 # average overall mshr miss latency 850system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71947.986238 # average overall mshr miss latency 851system.cpu.l2cache.overall_avg_mshr_miss_latency::total 71865.553260 # average overall mshr miss latency |
| 860system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 861system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter. 862system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data. 863system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 864system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter. 865system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 866system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 867system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution 868system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution --- 57 unchanged lines hidden --- | 852system.cpu.toL2Bus.snoop_filter.tot_requests 406029 # Total number of requests made to the snoop filter. 853system.cpu.toL2Bus.snoop_filter.hit_single_requests 199980 # Number of requests hitting in the snoop filter with a single holder of the requested data. 854system.cpu.toL2Bus.snoop_filter.hit_multi_requests 7832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 855system.cpu.toL2Bus.snoop_filter.tot_snoops 3359 # Total number of snoops made to the snoop filter. 856system.cpu.toL2Bus.snoop_filter.hit_single_snoops 3330 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 857system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 29 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 858system.cpu.toL2Bus.trans_dist::ReadResp 99049 # Transaction distribution 859system.cpu.toL2Bus.trans_dist::WritebackDirty 214604 # Transaction distribution --- 57 unchanged lines hidden --- |